Microcontrollers Lab Manual
Microcontrollers Lab Manual
SEMESTER : IV
Ms .PRIYANKA.T.V, ASST.PROF,RLJIT
NAME
USN
Batch
Sem
Branch
Vision:
Mission:
M1: To craft the students with novel and intellectual skills to capability in the field of
Data science.
PEO1: Graduates will have Prospective careers in the field of Data Science.
PEO2: Graduates will have good Leadership Qualities, Self Learning abilities and Zeal
PEO3: Graduates will follow Ethical Practices and exhibit high level of Professionalism
PSO 1: Students will able to solve the real life problems faced in the society, industry
PSO 2: Students will have the knowledge of Software, Hardware, Algorithms, Modelling
PSO 3: Students will have the ability to develop computational knowledge and project
Sl.No. Experiments
Module – 1
1 Using Keil software, observe the various Registers, Dump, CPSR, with a simple Assembly
Language Programs (ALP).
Module – 2
2 Develop and simulate ARM ALP for Data Transfer, Arithmetic and Logical operations
(Demonstrate with the help of a suitable program).
6 Develop an ALP to count the number of ones and zeros in two consecutive memory
locations.
Module – 3
7 Simulate a program in C for ARM microcontroller using KEIL to sort the numbers in
ascending/descending order using bubble sort.
Module – 4 and 5
11 Demonstrate the handling of divide by zero, Invalid Operation and Overflow exceptions in
ARM.
INDEX
CO2 3 3 3 1 3 - - - - - - - 3 2 1
CO3 3 3 3 1 3 - - - - - - - 3 2 1
CO4 3 3 3 1 3 - - - - - - - 3 2 1
CO5 3 3 3 1 3 - - - - - - - 3 2 1
1) Using Keil software, observe the various Registers, Dump, CPSR, with
a simple Assembly Language Programs (ALP).
START
MOV R0, #10
MOV R1, #20
ADD R2, R0, R1
END
OUTPUT:
2)Develop and simulate ARM ALP for Data Transfer, Arithmetic and
Logical operations
(Demonstrate with the help of a suitable program).
AREA PRG6, CODE, READONLY
ENTRY
LDR R0, =5
LDR R1, =3
ADD R2, R0, R1
SUB R3, R0, R1
MUL R4, R0, R1
AND R5, R0, R1
ORR R6, R0, R1
EOR R7, R0, R1
END
OUTPUT:
HERE B HERE
END
OUTPUT:
AREA SUM,CODE,READONLY
ENTRY
MOV R1,#10
MOV R2,#0
LOOP ADD R2,R2,R1
SUBS R2,#0X01
BNE LOOP
HERE B HERE
END
OUTPUT:
AREA LARGE,CODE,READONLY
ENTRY
MOV R5,#5
LDR R1,=ARRAY
R2,[R1],#4
LOOP LDR R4,[R1],#4
MOV R2,R4
NEXT SUBS R5,R5,#1
LOOP
STOP B STOP
ARRAY DCD 0X23,0X45,0X65,0X76,0X12,0X99
END
OUTPUT:
OUTPUT:
#define ARRAY_SIZE 10
int main() {
int arr[ARRAY_SIZE] = {64, 34, 25, 12, 22, 11, 90, 32, 45, 70};
int i;
bubbleSort(arr, ARRAY_SIZE);
return 0;
}
OUTPUT:
Original array:
64 34 25 12 22 11 90 32 45 70
Array sorted in ascending order:
11 12 22 25 32 34 45 64 70 90
int main()
{
int num;
printf("Enter an integer: ");
scanf("%d", &num);
if (num < 0)
{
printf("Error! Factorial of a negative number doesn't exist.\n");
} else
{
unsigned long long fact = factorial(num); printf("Factorial of %d = %llu\n",
num, fact);
}
return 0;
}
#include <stdio.h>
int main() {
char str1[] = "Hello World!";
char str2[] = "HeLLo WorLD!";
toLowercase(str1);
printf("String in lowercase: %s\n", str1);
toUppercase(str2);
printf("String in uppercase: %s\n", str2);
return 0;
}
OUTPUT:
String in lowercase: hello world!
String in uppercase: HELLO WORLD!
DISABLE_INTERRUPT MACRO
LDR r0, =INTERRUPT_DISABLE
LDR r1, [r0]
ORR r1, r1, #(1 << INTERRUPT_BIT_POSITION) ;
STR r1, [r0]
ENDM
START
ENABLE_INTERRUPT
DISABLE_INTERRUPT
END
explanation:
In this code, we define memory-mapped addresses for the Interrupt Enable Register
(INTERRUPT_ENABLE) and the Interrupt Disable Register (INTERRUPT_DISABLE). These registers
control the enabling and disabling of interrupts in ARM microcontrollers.
We also define a bit position (INTERRUPT_BIT_POSITION) corresponding to the specific interrupt we
want to enable or disable. This allows us to manipulate individual interrupts.
Two macros are defined: ENABLE_INTERRUPT and DISABLE_INTERRUPT. These macros use
assembly instructions to modify the values of the Interrupt Enable and Disable Registers to enable or
disable the specific interrupt.
In the example usage within the START section, we first enable interrupts using the
ENABLE_INTERRUPT macro, then execute the interrupt service routine or main program code, and
finally disable interrupts using the DISABLE_INTERRUPT macro to prevent further interrupts from being
serviced.
DCD ExceptionHandler
DCD ExceptionHandler
DCD ExceptionHandler
MRS R0, CPSR
TST R0, #0x1F
BNE HandlerNotARM
BX LR
END
Explanation:
In this code, we define memory-mapped addresses for the Current Program Status Register (CPSR) and
the Vector Base Register (VICBASE), which are used for exception handling.
We define an exception vector table with entries for each type of exception: divide by zero, invalid
operation, overflow, etc.
Each entry in the exception vector table points to the ExceptionHandler label, where the actual exception
handling code resides.
In the ExceptionHandler, we check if the processor is in ARM state and interrupts are enabled. If not, we
handle the exception accordingly.
If the processor is in ARM state and interrupts are enabled, we set the appropriate vector base address for
each exception using the Vector Base Register.
After setting up the exception handling, you can add your custom exception handling code where indicated.