202 IEEE ELECTRON DEVICE LETTERS, VOL. 17, NO.

5 , MAY 1996

The Impact of Device Scaling and Power

Supply Change on CMOS Gate Performance
Kai Chen, H. Clement Wann, Ping K. KO, Senior Member, IEEE, and Chenming Hu, Fellow, IEEE

Abstract-Based a new empirical mobility model that’s solely 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
dependent on IbS. and To, and a corresponding saturation 5 5 0 , 1 . , . 1 . 1 . 1 . 1 . 1 . 1 . 1 . , . 1 ~
drain current ( I d s a t ) model, the impact of device scaling and
power supply voltage change on CMOS inverter’s performance is
investigated in this paper. It shows that the To, which maximizes
1
inverter’s speed may be thicker than reliability consideration 450-
requires. In addition, very high speed can be achieved even at h

low I& (for low power applications) if 1; can be lowered. 0 400-

0)
t
n
N$ 350-
I. INTRODUCTION E
0
v 300-
ECENT research in MOSFET carrier mobility has re-
sulted in the new empirical mobility models solely de- 250-
pendent on l&, V,, and To, for NMOS electrons and PMOS
holes, respectively, as follows (see Fig. 1) [l]: 200-
L
.-L
a,
150-
540
s 1M)-

50-
540 ,.~
om I I I I , . 1 * , - 1 I I . , I 1 . 1 ‘ I I

0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0

cm2 \ 185 ,E, = (Vg,+Vt-a)/6Tox(MV/cm)

Fig. 1. The new empirical mobility model solely dependent on Vt , V,, , and
T,, for both NMOSFET electrons and PMOS holes (a = 0 and 2.3 for the
surface and buried channel PMOSFET’s, respectively) fit the measurement
data well for the wide range of T o z .I%, and N s u b .

where Idsao is the saturation current for R,9= 0 131:

where a = 0 for the p+poly PMOSFET (or surface channel
PMOSFET) and UI = 2.3 for the n+poly PMOSFET (the
so-called “buried channel” PMOSFET) 111. Here E , f f is
in the unit of MVIcm. The corresponding accurate Idsat
model including velocity saturation, usat, mobility degrada-
“.
tion, p e f f which is expressed by (1) or (2) for N-MOSFET Ppf f
and P-MOSFET, respectively, and the source and drain series The experimental data and (3) are illustrated in Fig. 2.
resistance, €2, = R d , can be shown to be 121: Based on (1)-(4)>this paper investigates the impact of To,,
L,ff, and V d d scaling on CMOS inverter’s performance.

11. RESULTSAND DISCUSSIONS

The total load capacitance of a CMOS inverter, C L ,can be
Manuscript received September 29, 1995; revised February 6, 1996. This modeled by two components as follows:
work was supported by SRC contract 94-DC-324, the Joint Services Electron-
ics Program, F49620-94-C-0038, and AFOSR F49620-94- 1-0464.
The authors are with the Department of Electrical Engineering and Com-
CL = c
1 + CLoz
puter Science, University of California, Berkeley, CA 94720-1772 USA.
Publisher Item Identifier S 0741-3106(96)03728-7. 1 ox

0741-3106/96$05.00 0 1996 IEEE

CHEN et al.: IMPACT OF DEVICE SCALING AND POWER SUPPLY CHANGE !03

0.80 . I . l , , . I . I . I . l . I . I .
140 - ---L~O.5um, V,=0.6V
4,,,-0.25urn, V,=O.SV
130
- --r-L&O.lPurn, Vt=0.4V

120 -
h
110 -
E
v
100 -
8
c.

690
0.55 - F?
Y

K
.-0
L
m0 7
m
P
P
a

0.351'"' a I " ' I z 1 * I - I m I * I

0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2

Fig. 2. The corresponding semi-empirical I d s a t model employing the new

mobility equations (1) and (2) fit well with measurement data for three
different technologies. The devices shown in this figure are NMOSFET's.
Fig. 4. Minimum t p d may be reached at a thicker To, than that allowed
by reliability requirement represented by the dashed contour of E,, = 5
MV/cm in the figure. C1/1.I' = 3.5 fF/pm determined from Fig. 3 has been
used for this plot.

1
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3

Le, (urn)
Fig. 3 . Symbols are Cr, and C1,ox per unit width W = (Wn VVp) +
(fF/pm) extracted from the measured t , d and other related data published
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
in literature for the past fourteen years. C1/ W remains roughly constant at
3.5 (fF/pm). ,v (v)
Fig. 5. Power supply is less sensitive for scaled devices. To achieve high
where CLos represents all To, related capacitance (i.e., gate speed at low power V d d , L2 can be lowered in proportion to V d d if higher
off-state current is not a limiting factor.
and part of overlap capacitance) and C1 represents the junction
and interconnect capacitances which are not related to To,, W,
and W, are the widths of N- and P-MOSFET, respectively. and channel charge partition, parameter "a" in (5) is not unity
Because of the multitude of devices in an inverter. Miller effect but approximately 2.4 as determined by SPICE simulation. CL
204 IEEE ELECTRON DEVICE LETTERS, VOL. 17, NO. 5, MAY 1996

for different technologies can be extracted from the CMOS shown by Fig. 3 with Cl/W = 3.5 fF/pm). For the more
inverter t p d using the following (4), when To,.
Vdd, Iddsatn. practical case of larger interconnect loading (e.g., Cl/W =
I d s a t p W,,, W,, and t p d are known: 10 fF/pm), t p d minimum would occur at smaller To,’%Fig. 5
shows that in order to maintain high speed at low V d d , one
would like to reduce vt
in proportion to V d d if higher off-
state current is not a limiting factor. Trading speed for low
The results of CL and CLOXper unit width W = (W, W,) + power applications via choice of V d d and V, is discussed in [SI.
extracted from fifteen different technologies covering from Short channel devices’ weaker sensitivity of t p d with respect
L , f f = 1.2pm to 0.05 p m for the past fourteen years to Vdd scaling is resulted from its more linear Idsat - V,,
are shown in Fig. 3. It shows that CL and ( 3 ~ per 0 ~unit
~ characteristics, comparing to long channel devices’ square law.
total width, that is C L / W and C L O X / W have. decreased
111. CONCLUSIONS
slightly with the technology scaling. But C l / W = ( C L -
C L , ~ ) / Whave remained roughly constant at 3.5 fFlpm or A new I d s a t model including velocity saturation, mobility
85.1 f F for W p / W n= 14pm/10 pm. The ratio of To,related degradation and LDD source/drain series resistances is used
capacitance to the total load capacitance, G L O ~ ~ /= C 4L 0 7 ~ ~in projecting circuit performance or prediction for current
is a reasonable number. Wp/Wn = 14km/lO pm is used and future submicron technology. It is shown that the To,
in this paper because it can easily be shown that for given which maximizes gate speed may be thicker than reliability
+
the total area of an inverter, i.e., given (W, W p ) .t p d is consideration requires. Very high speed can be achieved even
minimized when the ratio Wp/WrL =d m = 1.4, where at low V d d (for low power) if Vt can be lowered.
J, and J p are the saturation current per unit width for N- and
P-MOSFET, respectively. REFERENCES
Now substitute To, dependent ( 3 ) and ( 5 ) into (6). the [ 11 K. Chen, J. Duster, H. C. Wann, T. Tanaka, M. Yoshida, P. K. KO, and C.
CMOS inverter propagation delay, t p d ; is now an explicit Hu; “Universal MOSFET carrier mobility model explicitly based on ‘Ut,
function of To,, V d d ? V,, W,,, W,, and L. as illustrated v g . and and its application in device modeling and optimization,” in
Proc. 1995 Int. Semicondact. Dev. Res. Con$, Virginia, Dec. 6-8, 1995,
in Fig. 4. It shows that there exists certain T,, such that pp. 607-610.
t p d is minimized. The physical interpretation is that when [2] K. Chen, H. C. Wann, J. Duster, D. Pramanik, S. Nariani, P. K. KO, and
C. Hu, “An accurate semi-empirical saturation drain current model for
To, is reduced to too small a value, the increase in channel N-MOSFET,“ IEEE Electron Device Lett., vol. 17, no. 3, pp. 145-147,
charge, Qi,,, K E,, /To,, is insufficient to compensate for the Mar. 1996.
decrease in mobility and the increase in ( 3 ~ 0 If ~
we~assume
. [3] K. Y. Toh, P. K. KO, and R. G. Meyer, “An engineering model for
short-channel mos devices,” ZEEE J. Solid State Circuits, vol. 23, pp.
that the oxide reliability limit is E,, < 5 MVlcm (Fig. 4).it 950-958. Aug. 1988.
can be seen that minimum t p d may be reached at a thicker [4] C. Hu. .‘Future CMOS scaling and reliability,” Proc. IEEE, (invited
To, than reliability allows. Fig. 4 is for the case of minimum paper). vol. 81. no. 5, May 1993.
[5] D. Liu and C. Svensson, “Trading speed for low power by choice of
interconnect capacitance (i.e., the so-called “unloaded” ring supply and threshold voltages,” IEEE J. Solid State Circuits, vol. 28,
oscillators where small interconnect loading is present, as no. 1. Jan. 1993.