UNIT:8

Advanced Microprocessors
Outline:
8086 logical block diagram, segmentation, Pin

functions, Minimum and maximum mode,

80286/80386: Overview and architecture,

Programming model, Data types and instruction set,

segments and its types,

segment descriptor, descriptor table and selectors

Introduction to 8086
8086 is a 16-bit processor, which implies that 16-bit data bus ,16-bit ALU,16-bit
registers.
8086 has a 20-bit address bus can access up to 220 memory locations. (220=1048576
bytes =1 MB) It can support up to 64K I/O ports. (216 I/O ports:216=65536)
8086 has 256 vectored interrupt.
8086 contains powerful instruction set, that also supports multiply and divide operation.
8086 can operate in two modes: Minimum mode: A system with only one processor
i.e.8086 Maximum mode: A system with multiple processors.
8086 uses memory segmentation. Segmentation means dividing memory into logical
components.
In 8086 memory is divided into 16 segments of capacity 216 bytes each and used as
code, stack, data and extra segment respectively.
8086 Architecture Block
Diagram
 In 8086 CPU is divided into two independent functional units:
1. BIU (Bus Interface Unit)
2. EU (Execution Unit)
Task of (Bus Interface Unit) :
Fetch instructions from memory.
Read/write instructions to/from the memory.
Input/output of data to/from peripheral ports.
Address generation for memory reference.
Queuing instructions.
Thus, BIU handles all transfer of data and address.
Task of EU (Execution Unit) :
Decodes the instruction.
Executes decoded instructions.
Tells BIU from where to fetch the instruction.
EU takes care of performing operation on the data.
EU is also known as execution heart of the processor.
8086 Registers
The 8086 microprocessor has a total of fourteen registers that are accessible to the
programmer as follows:-
General Purpose Register :
AX: - Accumulator register consists of two 8-bit registers AL and AH, which can be
combined together and used as a 16-bit register AX.
BX: - Base register consists of two 8-bit registers BL and BH, which can be combined
together and used as a 16-bit register BX.
CX: - Count register consists of two 8-bit registers CL and CH, which can be combined
together and used as a 16-bit register CX. Count register can be used in Loop,
shift/rotate instructions and as a counter in string manipulation.
DX: - Data register can be used together with AX register to execute MUL and DIV
instruction. Data register can be used as a port number in I/O operations.
Segment Register : Types of Segment registers are as follows:-
Code Segment (CS): The CS register is used for addressing a memory location in the Code
Segment of the memory, where the executable program is stored.
Data Segment (DS): The DS contains most data used by program. Data are accessed in the
Data Segment by an offset address or the content of other register that holds the offset
address.
Stack Segment (SS): SS defined the area of memory used for the stack.
Extra Segment (ES): ES is additional data segment that is used by some of the string to
hold the destination data .
Pointer Registers :
The pointers IP, BP, SP usually contain offsets within the code, data and stack segments
respectively.
Stack Pointer (SP): SP is a 16-bit register pointing to program stack in stack segment.
Base Pointer (BP): BP is a 16-bit register pointing to data in stack segment. BP register is
usually used for based, based indexed or register indirect addressing.
Instruction Pointer (IP): IP is a 16-bit register pointing to next instruction to be executed.
Segmentation in 8086
Segmentation is the process in which the main memory of the computer is logically divided into
different segments and each segment has its own base address.
It is basically used to enhance the speed of execution of the computer system, so that the processor is
able to fetch and execute the data from the memory easily and fast.
Need for Segmentation – The Bus Interface Unit (BIU) contains four 16 bit special purpose registers
(mentioned below) called as Segment Registers.
Code segment register (CS): is used for addressing memory location in the code segment of the
memory, where the executable program is stored.
Data segment register (DS): points to the data segment of the memory where the data is stored.
Extra Segment Register (ES): also refers to a segment in the memory which is another data segment
in the memory.
Stack Segment Register (SS): is used for addressing stack segment of the memory. The stack
segment is that segment of memory which is used to store stack data.
8086 pin diagram
Address and Data pins AD0-AD15 (bidirectional) :
These lines are multiplexed bidirectional address/data bus.
AD0-AD7 carry lower order byte of data and AD8-AD15 carry higher order byte of data.
When ALE=1, then Address bus gets enabled, else Data bus will get enabled.
A16/S3- A19/S6 (unidirectional) :
These lines are multiplexed and unidirectional address and status bus.
During T1, they carry higher order 4-bit address.
In the remaining clock cycles, they carry status signals.
S5 gives the status of Interrupt Flag (IF)
S6 goes low, when 8086 controls the shared system bus.
S3 and S4 indicates the segment register
BHE/S7
BHE stands for Bus High Enable.
Active low output signal.
BHE signal is used to indicate the transfer of data over higher order data bus (D8 – D15).
8-bit I/O devices use this signal.
S7 is reserved for future development.
 Interrupt Related pins
1. NMI
It is an active high input signal
It is a non-mask able interrupt signal.
2. INTR
It is an active high input signal
It is an interrupt request signal.
3. INTA
It is an active low output signal.
This is an interrupt acknowledge signal.
When microprocessor receives INTR signal, it acknowledges the interrupt by generating this
signal.
Clock Related pins
1. CLK
Generates clock signals that synchronize the operation of processor.
2. RESET: Active high input signal
When high, microprocessor enters into reset state and Terminates activity of processor
Processor requires 4 clock cycle to reset. Thus RESET signal must be 1 for at least 4 clock
cycles
3. READY: Active high input signal
This is an acknowledgement signal from I/O devices or memory.
When READY= high; it indicates that the device is ready to transfer data.
When READY=low; microprocessor is in wait state.
LOCK
It is an active low output signal.
This signal indicates that other processors should not ask CPU (8086) to hand over the system
bus.
This pin is activated by using LOCK prefix on any instruction.
̄WR
It is an active low output signal.
It is used to write data in memory or output signal, depending on status of M/IO signal.
HOLD
It is an active high input signal.
When DMA controller needs to use address/data bus, it sends a request to the CPU through this
pin.
When microprocessor receives HOLD signal, it issues HLDA signal to the DMA controller.
HLDA
It is an active high output signal.
It is a Hold Acknowledge signal.
It is issued after receiving the HOLD signal.
RQ/GT0 and RQ/GT1
These are Request/Grant bi-directional pins.
Other processors request the CPU through these lines to release the system bus.
After receiving the request, CPU sends acknowledge signal on the same lines.
RQ/GT0 has higher priority than RQ/GT1
80286 Architecture
The Intel 80286 had a 24-bit address bus and was able to address up to 16 MB of RAM
compared to 1 MB of its predecessor (8086).

It was designed for multi-user systems with multitasking applications, including

communications and real-time process control.

80286 is the advanced microprocessors with memory management and protection abilities.

80286 have two operating modes namely real address mode and virtual address mode.

In real address mode, it can address up to 1MB of physical memory address like 8086.

In virtual address mode, it can address up to 16 MB of physical memory address space and 1
GB of virtual memory address space.

The performance of 80286 is five times faster than 8086.

80286 Architecture:
80286 Architecture: Bus Unit
(BU)
Components:

1. Address Latches & Drivers

2. Bus Control

3. Instruction Pre-fetcher

4. Processor Extension Interface

5. Data Transceivers

6. 6-byte Instruction Queue

80286 Architecture: Instruction
Unit (IU)
Components:

3 decoded instruction queue

Instruction decoder

Functions :

It fully decodes up to 3 pre-fetched instructions and holds

them in a queue, so that Execution Unit (EU) can access them.

It helps processor to speed up by pipelining the instructions.

80286 Architecture: Execution
Unit (EU)
Components:
It includes ALU, registers and control unit.

Registers are general purpose, index, pointer, flag registers and

Machine Status Word (MSW).

Functions:
To sequentially execute instructions received from the instruction
unit.

ALU result is either stored in registers or sent back over data bus.
80286 Architecture: Address
Unit
Components:
1. Segment Bases
2. Segment Limit Checker
3. Segment Size
4. Offset address
5. Physical address adder
Functions:
1. It computes physical address that will be sent out to the memory
or I/O by Bus Unit (BU).
2. 80286 operate in two different modes
3. 1. Real address mode
4. 2. Protected Virtual Address Mode.
Register Organization of
80286
Eight 16-bit general purpose registers (AX, BX, CX, DX, SP, BP, SI, DI).
Four 16-bit segment registers (CS, SS, DS,ES).
16-bit Instruction Pointer (IP).
16-bit Flag Register.
Additionally, one new 16-bit Machine Status Word (MSW) register.
Segment Descriptor: PVAM
Descriptor
This smaller segments or pages have been associated with data structure called a
Descriptor.
It contains information of program segment or pages.
The data structure Descriptor is essentially one such identifier of particular program or
segment.
The set of such descriptor arranged in a proper sequence describes the complete
program.
Descriptor Table GDT & LDT
What is Descriptor Table?
The descriptor is a block of contiguous memory location containing information of a
segment, like :
1. Segment base address

2. Segment limit

3. Segment type

4. Privilege level – prevents unauthorized access

5. Segment availability in physical memory

6. Descriptor type

7. Segment use by another task

Descriptor Table: GDT &
LDT
A segment cannot be accessed, if its descriptor does not exist in either LDT (Local
Descriptor Table) or GDT (Global Descriptor Table).

Set of descriptor arranged in a proper sequence describes the complete program.

Each Descriptor is 8-byte long.

The GDT contains information about segments that are global in nature, that is, available
to all programs and normally used most heavily by the operating system.

The LDT contains descriptors that are application specific.

A global descriptor is also known as System Descriptor, and local descriptor is know as
Application Descriptor.

The global descriptor table’s base address is stored in GDTR.

The local descriptor table’s base address is stored in LDTR.

Descriptor Table: GDT &
LDT
80386: Introduction
80386 is 32-bit microprocessor.
Address Bus: 32-bit
Data Bus: 32-bit
Physical memory : 4GB
Virtual memory : 64TB
80386 supports variety of operating clock frequency, which are 16 MHz, 20 MHz, 25 MHz and 33
MHz.
80386 supports 3 operating modes: real, protected and virtual real mode.
Key characteristics: Multitasking and protection capability.
80386 has an internal dedicated hardware that permits multitasking.
3 stage pipeline: fetch, decode and execute.
it supports simultaneous fetching, decoding and execution inside the system.
80386 Architecture
Bus Interface Unit :
The Bus Interface Unit connects 80386 with memory and I/O.
Based on internal requests for fetching instructions and transferring data from the code pre-fetch unit, 80386
generates the address, data and control signals for the current bus cycles.

Code Pre-fetch Unit :

The code pre-fetch unit pre-fetches instructions when the bus interface unit is not executing the bus cycles.
It then stores them in a 16-byte instruction queue for decoding by the instruction decode unit.

Instruction Decoder Unit :

The Instruction Decoder Unit translates instructions from the pre-fetch queue into micro-codes.
The decoded instructions are then stored in an instruction queue (FIFO) for processing by the execution unit.

Execution unit :
Execution unit has 8 General purpose registers which are either used for handling data or calculating offset
addresses.
The execution unit processes the instructions from the instruction queue.
It contains a control unit, a data unit and a protection test unit.
The barrel shifter increases the speed of all shift and rotate operations.
Register organization of
80386
General Purpose Register :
Registers EAX, EBX, ECX, EDX, EBP, EDI and ESI are regarded as general purpose or multipurpose registers.
EAX (ACCUMULATOR): The accumulator is used for instructions such as multiplication, division and some of
the adjustment instructions. In 80386 and above, the EAX register may also hold the offset address of a
location in memory system.
EBX (BASE INDEX): This can hold the offset address of a location in the memory system in all version of the
microprocessor. It the 80386 and above EBX also can address memory data.
ECX (count): This acts as a counter for various instructions.
EDX (data): EDX is a general-purpose registers that holds a part of the result for multiplication or part of the
division. In the 80386 and above this register can also address memory data.
Pointer and Index Register
EBP (Base Pointer): EBP points to a memory location in all version of the microprocessor for memory data
transfers.
ESP (Stack Pointer): ESP addresses an area of memory called the stack. The stack memory is a data LIFO data
structure. The register is referred to as SP if used in 16 bit mode and ESP if referred to as a 32 bit register.
EDI (Destination index): EDI often addresses string destination data for the string instruction. It also functions
as either a 32-bit (EDI) or 16-bit (DI) general-purpose register.
THANK YOU