Faculty of Information and Communication Technology (FICT)

Mechanical Age
UCCE2043 Basic Microprocessor

Charles Babbage was the pioneer of mechanical
computing machinery
Architecture of  Analytical Engine in 1832

Assisted by Augusta Ada King
Microprocessor
Steam powered, 50 000
components

Input via punch cards,
H Y Lee control unit, memory unit
[email protected]
to calculate a series of numerical
values and automatically print the results.

1 2

Electrical Age Modern Computers

• There are three widely recognized
Supercomputers
generations of electrical-based, digital
Mainframes
computers:
Minicomputers (workstations, servers)
• First:

Microcomputers (PCs)
• Vacuum tubes
• Second:
Microcontrollers (Intel MCS-51 families,
• Transistors Zilog, HCS-12 Motorola etc.)
• Third:
• Integrated circuits (ICs)
Jack Kilby examines a wafer filled with chips. 3 4
Photo: Texas Instruments
 Date of
Processor Transistor count Manufacturer Process Area
introduction
Intel 4004 2,300 1971 Intel 10 µm 12 mm²
Intel 8008 3,500 1972 Intel 10 µm 14 mm²

MOS Technology 6502 3,510 1975 MOS Technology 21 mm²

Motorola 6800 4,100 1974 Motorola 16 mm²

6 μm
Microprocessor
Intel 8080 4,500 1974 Intel 20 mm²
RCA 1802 5,000 1974 RCA 5 μm 27 mm²
Intel 8085 6,500 1976 Intel 3 μm 20 mm²

1971 to 2010 Zilog Z80

Motorola 6809
8,500
9,000
1976
1978
Zilog
Motorola
4 μm
5 μm
18 mm²
21 mm²
Intel 8086 29,000 1978 Intel 3 μm 33 mm²
Intel 8088 29,000 1979 Intel 3 μm 33 mm²

Intel 80186 55,000 1982 Intel

230 million transistors, 206

Motorola 68000 68,000 1979 Motorola 4 μm 44 mm²
mm2 die size
Intel 80286 134,000 1982 Intel 1.5 µm

Intel 80386 275,000 1985 Intel 1.5 µm 104 mm²

Intel 80486 1,180,000 1989 Intel 1 µm

5 6

Date of Date of
Processor Transistor count Manufacturer Process Area Processor Transistor count Manufacturer Process Area
introduction introduction

Pentium 3,100,000 1993 Intel 0.8 µm Itanium 2 220,000,000 2003 Intel 130 nm

AMD K5 4,300,000 1996 AMD 0.5 µm Cell 241,000,000 2006 Sony/IBM/Toshiba 90 nm

Pentium II 7,500,000 1997 Intel 0.35 µm Core 2 Duo 291,000,000 2006 Intel 65 nm

AMD K6 8,800,000 1997 AMD 0.35 µm AMD K10 463,000,000 2007 AMD 65 nm

Pentium III 9,500,000 1999 Intel 0.25 µm AMD K10 758,000,000 2008 AMD 45 nm

AMD K6-III 21,300,000 1999 AMD 0.25 µm Itanium 2 with 9MB cache 592,000,000 2004 Intel 130 nm

Core i7 (Quad) 731,000,000 2008 Intel 45 nm 263 mm²

AMD K7 22,000,000 1999 AMD 0.25 µm
POWER6 789,000,000 2007 IBM 65 nm 341 mm²

Pentium 4 42,000,000 2000 Intel 180 nm Six-Core Opteron 2400 904,000,000 2009 AMD 45 nm

Atom 47,000,000 2008 Intel 45 nm Six-Core Core i7 1,170,000,000 2010 Intel 32 nm

POWER7 1,200,000,000 2010 IBM 45 nm 567 mm²

Barton 54,300,000 2003 AMD 130 nm
z196 1,400,000,000 2010 IBM 45 nm 512 mm²

AMD K8 105,900,000 2003 AMD 130 nm Dual-Core Itanium 2 1,700,000,000[3] 2006 Intel 90 nm 596 mm²
7 8
 Date of
Processor Transistor count Manufacturer Process Area
introduction

Six-Core Xeon 7400 1,900,000,000 2008 Intel 45 nm Moore’s Law

Quad-Core Itanium Tukwila 2,000,000,000 2010 Intel 65 nm

Made known by Intel’s co-founder Gordon

8-Core Xeon Nehalem-EX 2,300,000,000 2010 Intel 45 nm
Moore

Describes a long-term trend in the history of
computing hardware.

States that the number of transistors on a chip
will double about every two years.

 Intel has kept that pace for over 40 years, providing

more functions on a chip at significantly lower cost per
function.

9 10

11 12
 Integration example: Processors
Power consumption
Power Density Off Chip Cache:
(W/cm2) Sun’s Surface 82395 DX
10,000

Rocket Nozzle
1,000

Nuclear Reactor
100 387
Math Coprocessor

8086 Hot Plate Pentium®

10 Processors
8008 8085
386
1985 1989
286
4004 8080 486 Intel386™ Processor Intel486™ Processor
1
1970 1980 1990 2000 2010
Borrowed from Pat Gelsinger, CTO of Intel
13
Today > 2.3 billion transistors 14

Integration example: Networking Integration example: Optical Networking

1994 1997 2001 2003

Fast Ethernet Card: 10 chips 1 chip 100’s of chips 10+ Chips
15 16
 Processor Specifications –
The System Bus
System Bus

Data I/O Bus

Collection of wires on which electrical  data that can carry in a time –8, 16, 32 or 64 bits, larger
enables greater throughput
signals pass between components in the
Address bus
system.  memory location to which the data being read or write.
More wires (digits), greater the maximum amount of RAM
a chip can address.

3 major busses: the address bus, the data

Control bus
bus, and the control bus.  eclectic collection of signals that control how the processor
communicates with the rest of the system

These busses vary from processor to  Carries timing signals (and more) to synchronize CPU to
external circuitry
processor.  R/W

17 18

Processor Specifications –
The Address Bus
Architectures -I

Harvard architecture - separate data and
instruction busses, allowing transfers to be
performed simultaneously on both busses.

Von Neumann architecture - only one bus
which is used for both data transfers and
instruction fetches, and therefore data transfers
and instruction fetches must be scheduled - they
can not be performed at the same time

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 Architectures -II Block diagram of a Computer
System
Address Bus

I/O
MAIN
DEVICES
MEMORY
(Ports)

MPU
Data Bus

Control Lines (Bus)

21 22

External Address Bus

Memory Addr Reg

General
Registers
MPU vs MCU
DETAIL Program Counter

Stack Pointer

Micro-processor (MPU, μP)
OVERVIEW  CPU alone
may contain some memory
External Data Bus

Internal Data Bus 

Instruction
 classified by data path width 4, 8, 16, 32 or 64 bits
Register
Accumulator Temp Reg

Instruction
Decoder

Micro-controller (MCU)
C
Z
 microprocessor plus peripherals on a single chip
N  one chip computer system
ALU
RESET  additional peripherals may be interfaced separately
Clock
Control Unit
 Ex: 8051

IOR# IOW# MEMR# MEMW# INTR INTA# MPU

23 24
The 8086 vs 8088 Microprocessor (1) The 8086 vs 8088 Microprocessor (2)

Similarities
Differences

Architecture of the 8088 = 8086:
16-bit external data bus in 8086, 8-bit external data
 16-bit registers, 16-bit internal data bus and 20-bit address bus in 8088
bus, (address up to 1 MB of memory).

instruction queue size (8088 - 4 bytes long 8086-6
 8088 had the same segmented memory addressing as the
8086: the processor could address 64 KB of memory directly,
bytes) and prefetching algorithms were changed
and to address more than 64 KB of memory one of special  8088 used two consecutive bus cycles to write or read
segment registers had to be updated. 16 bit data instead of one cycle for the 8086.
 run slower, but on the hardware changes in the 8088
CPU made it compatible with 8080/8085 peripherals.

25 26

Fetch-Decode-Execute Fetch
Address Bus Address Bus Address Bus
Address
111
111 110
Instruction Pointer
Memory
Program Program Program
MPU MPU MPU
Memory Memory Memory Control

CPU Data
Data Bus Data Bus Data Bus
64
Instruction Register

Address (IP) is sent to Op Code is read into

the IR register via Instruction is executed 7 I/O
memory via the address the data bus for Accumulator
bus decoding

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 8088 CPU Functional Block (Courtesy Intel Corporation)
Decode-Execute
Address
111 111
Instruction Pointer
Memory

Control

CPU Data
Increment
64
Accumulator
Instruction Register

7
8 I/O
Accumulator

29 30

The Sequence
BIU outputs the contents of the IP into the address bus,
causing the selected byte or word to be read into the BIU.
Functions of BIU

Interface to the external world

Responsible for all external bus operations.
IP +1 to prepare for the next instruction fetch
Instruction fetching (reading) from primary memory.

R/W of data operand from/to primary memory.

I/O of data from/to peripheral ports.
Inside BIU, the instruction is passed to the queue

Address generation for memory reference (Or formation of a 20-bits RAM
address from the contents of a segment base registers and offset register,
later).
Assuming that the queue is initially empty, the EU
Prefetch instructions for the instructions stream queue. It is called
immediately draws this instruction from the queue and pipelined architecture.
begins execution

Contents of BIU
While the EU is executing this instruction, the BIU proceeds
4-segment registers (CS, DS, SS and ES) - to be discussed later
to fetch a new instruction.
An instruction pointer register (IP).

Address generation and bus control.

Instruction queue (FIFO)-pipeline.

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 Functions of EU Simple operation (1)

Responsible for decoding and execution of the Simple CPUs perform one action at a time.
instructions.

Accesses data from the general purpose register Example instruction sequence
Write to memory

Check and update control flags - to be discussed later Register operation

Commands BIU for memory & I/O operations Read from memory

Has the following units: CPU:

ALU. Fetch Execute Write Fetch Execute Fetch Execute Read

Status and control flags.

General purpose registers (AX, BX, CX, DX, etc).
Bus:
Busy Busy Busy Busy Busy

Temporary operand registers.

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Simple Operation (2) 8086/8088 Pre-fetching architecture

Fetching from EXTERNAL MEMORY is Bus-Interface

Execution unit
SLOW unit
(BIU)
Fetches Opcode (EU)

The 8086/8 used an instruction queue to Reads Operand
speed up performance Writes Data
Queue

While the processor is decoding and (Pipeline)
-FIFO
executing an instruction, its bus interface
can be reading new instructions, since at
that time the bus is not actually in use.
System Bus

35 36
 8086/8088 Pre-fetching No pipeline vs pipeline
The 8086/8088 has a pipelined architecture.
BIU – accesses memory and peripherals
EU – executes fetched instructions
BIU:
Fetch Fetch Write Fetch Fetch Read
6 cycles instead
EU: of 8
Idle Execute Execute Idle Execute Wait
Bus is more
Bus: efficient
Busy Busy Busy Busy Busy Busy

BIU pre-fetches instructions bytes whenever EU is not using the bus and stores them
in the queue.
37 38

8088/8086 address generation

Physical and Logical Addresses
1 Mbyte physical space
15 0 15 0

• Physical Address
• The 20-bit value that uniquely identifies each byte location in
the memory
16 bits
• Logical Address 15 0

16 bits offset
• Allows code to be developed without prior knowledge of where
the code is to be located in memory + Segment 0
• Facilitates dynamic management of memory resources 20 bits

• Consists of a segment base value and offset value Physical

Data
• 7000:1234 (Logical Address) 19 0

• = 8234h (Physical Address) offset

Segment
base (20 bits)
WRONG
39 40
 Restriction value to segment as base
Segmentation
It must reside on a 16-byte address boundary.
 0000:0000 = 00000
FFFFF
16 bytes
 0001:0000 = 00010 or 0000:0010
F0000
E0000 7000:FFFF  0002:0000 = 00020 or 0000:0020 16 bytes
D0000 16-bit Segment Base Address 70000h
C0000 16-bit Offset Address + 1234h
Segments can be set up to be contiguous,
B0000
A0000
20-bit Physical /Linear Address 71234h adjacent, disjoined or overlapping
WRONG
90000
80000
70000
60000
7000:1234
50000
40000 1234

30000
•Segmentation
20000 Protects tasks from
10000 interfering with each other
00000 (e.g. prevents them from
writing into each others
memory areas)
41 42

Segmentation: Pros and cons Question…

One program can work on several different sets of
What linear address corresponds to the segment/offset
data. This is done by reloading register DS to a new address 05AF:003A?
value.

Programs that reference logical addresses can be
loaded and run anywhere in the memory: relocatable 05AF0 + 003A = 05B2A

Segmented memory introduces extra complexity in
both hardware in that memory addresses require two What segment addresses correspond to the linear address
registers. 68F50h?

They also require complexity in software in that
programs are limited to the segment size
Many different segment-offset addresses can produce the

Programs greater than 64 KB can be run on 8086 but linear address 68F50h. For example:
the software needed is more complex as it must
switch to a new segment. 68F0:0050, 68F5:0000, 68B0:0450, . . .

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 Storage organization
Little Endian, Big Endian
All memory in 8086/88 systems are byte-addressable.
Store 12H, 34H, 56H, and 78H in locations 10000H to 10003H.
Little Endian
10003H 78H  The ‘little end’ of the number is stored in the
10002H 56H least significant byte.
10001H 34H
10000H 12H
Big Endian
 The ‘big end’ of the number is stored in the
In MPU world there are two categories--- Little endian and Big endian
most significant byte.
Store 1234H and 5678H in locations 10000H to 10003H.

10003H
10002H
78H
56H
10003H
10002H
56H
78H

8086/8088 uses little endian
Big Endian 10001H 34H 10001H 12H Little Endian
Motorola family uses big endian
10000H 12H 10000H 34H

45 46

Segment Registers
8088/86 Registers
Four 16-bit registers containing address of 64 KB segment
16-bits  Code segment (CS)

contains processor instructions (assembly).
 Stack segment (SS)

For temporary storage of data. By default, the processor assumes that
all data referenced by the stack pointer (SP) and base pointer (BP)
registers is located in the stack segment.
 Data segment (DS)

To store data that needs to processed. By default, the processor
assumes that all data referenced by general registers (AX, BX, CX, DX)
and index register (SI, DI) is located in the data segment.
 Extra segment (ES)

Secondary general purpose data area. Defines the area of memory
used by some of the string instructions to hold destination data.

 Note : Only one segment of each type can be activated at any

given time
47 48
 QUIZ… General Purpose Registers

Four general purpose registers with two 8-bit
registers (high and low)
What is the total memory that can be activated simultaneously?  Accumulator register (AL & AH= AX).

Used for I/O operations and string manipulation.
 Base register (BL & BH=BX).

Usually contains a data pointer used for based, based indexed
4*64KB=256KB or register indirect addressing.
 Count register (CL & CH= CX).

Used as a counter in string manipulation and shift/rotate
instructions.
 Data register (DL & DH= DX).

Used as a port number in I/O operations. In integer 32-bit
multiply and divide instruction the DX register contains high-
order word of the initial or resulting number.

49 50

String Index Registers

General Register : Summary

Source Index (SI) - 16-bit register.
 Used with data segment (DS:SI) and refer to offset locations within
Register Operation DS
Word Multiply, word Divide word input SI hold the offset address of a data operand to be READ from DS.
AX output

 used for indexed, based indexed and register indirect addressing,
byte Multiply, byte Divide byte input as well as a source data address in string manipulation instructions.
AL output, translate, decimal arithmetic
Destination Index (DI) -16-bit register.
byte Multiply, byte Divide,
AH  Used with data segment (DS:DI)
Store address information  DI holds the offset address of a data operand to be WRITTEN in
BX DS
CX String operations, loops  used for indexed, based indexed and register indirect addressing,
as well as a destination data address in string manipulation
Variable shift and rotate instructions.
CL
Word multiply, word divide, indirect IO
DX
51 52
 Stack & Base Pointers More on stack

Stack Pointer (SP)
 16-bit
register pointing to program stack.
 Used with SS (SS:SP) register

Used as temporary storage
 Always points to the top of the stack.
Used with instructions PUSH & POP

LIFO

Base Pointer (BP)
 16-bit register pointing to data in stack segment.
PUSH  SP-2 POPSP+2
 Used with SS (SS:BP) register

All, except the segment registers & SP ,
 BP register is usually used for based, based indexed
or register indirect addressing - discuss later can be pushed and popped
 Commonly used to access parameters that are passed
to a subroutine.

53 54

PUSH POP

Assume SP=1230H, AX=2107H, DI=1235H, DX=2345H
Assume SP=1230H, AX=2107H, DI=1235H, DX=2345H
Show the contents of the stack as each of the following instructions is Show the contents of the stack as each of the following instructions is
executed: executed:
PUSH AX PUSH DI PUSH DX PUSH AX PUSH DI PUSH DX

Show the contents of the stack as each of the following instructions is

executed
POP AX POP DI POP DX

55 56
 Offset Registers for Various Segments
IP & Flags

Instruction Pointer (IP)
 16-bit register which points to next instruction Note : Segments may be override !
to be executed.
 Contains the offset of the next instructions to Segment Override Examples
be fetched from the CS instead of the actual
address
 Every fetch operation, the value IP increment
by 2

57 58

Control flags (2)

Control Flags (1)
Flags is a 16-bit register containing nine 1-bit flags:
FlagsH FlagsL
Overflow Flag (OF) - set if the result is too large positive number, or is
too small negative number to fit into destination operand.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Direction Flag (DF) - if set then string manipulation instructions will
X X X X OF DF IF TF SF ZF X AF X PF X CF auto-decrement index registers. If cleared then the index registers will
be auto-incremented.

Interrupt-enable Flag (IF) - setting this bit enables maskable interrupts.
CF Carry Flag high-order bit carry or borrow
Single-step Flag (TF) - if set then single-step interrupt will occur after
PF Parity Flag low-order 8 bits contain even number of 1’s the next instruction.
AF Auxiliary Carry low-order 4 bits carry or borrow of AL
Sign Flag (SF) - set if the most significant bit of the result is set.
ZF Zero Flag result is zero
Zero Flag (ZF) - set if the result is zero.
SF Sign Flag equal to high-order bit
Auxiliary carry Flag (AF) - set if there was a carry from or borrow to bits
0-3 in the AL register.
TF Single-step Flag if set, single-step interrupt occurs

Parity Flag (PF) - set if parity (the number of "1" bits) in the low-order
control IF Interrupt-enable if set, maskable interrupts enabled byte of the result is even.
DF Direction Flag if set, auto-decrement for string instructions
Carry Flag (CF) - set if there was a carry from or borrow to the most
OF Overflow Flag signed result too large for destination significant bit during last result calculation.

59 60
 Example 1
mov BH,38H ; (BH) 38H
Find the contents of flag add BH,2FH ;ADD 2F to (BH) ,now
(BH) 67
register for the following
example!!! 38+2F=67 00111000
00101111
01100111

61 62

Example 2 Example 3
MOV AL,9CH ; (AL) 9CH MOV AX,34F5H ; AX=34F5
MOV DH,64H ; (DH) 64H ADD AX,95EBH ; now AX=CAE0
ADD AL,DH ; ADD DH to AL ,now 35F5+95EB=CAE0
AL=0
0011010111110101
9C+64=100 10011100 1001010111101011
01100100 1100101011100000
00000000

63 64
 Example 4 Example 5
Add the two signed numbers +96 ,+70
MOV BX,AAAAH ; BX=AAAAH
MOV AL,60H ; AL=0110 0000 (+96)
ADD BX,55 56H ; now BX=CAE0H
MOV BL,46H ; BL=0100 0110 (+60)
AAAA+5556=100000000
ADD AL,BL
0110 0000
1010101010101010
0100 0110
0101010101010110
1010 0110
0000000000000000

65 66

Understanding time!!! Answer - B

Q.1
The number of lines in the address bus is
Let said a 16-bits data bus. How many independent of the number of lines in the
electrical lines are there in the address data bus.
bus?

A. 16
B. Unknown

67 68
Q.2 Answer – B (56F)
What is 101011011112 in hex?

Break it up like this: 101 0110 1111
A. AD716
So hexadecimal is 56F
B. 56F16

69 70

Q.3 Answer – A (32767)

What is the largest value for a 16-bit
16-bit signed binary number
signed binary number? 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Sign bit Magnitude bits

A. + 32 767 0 = +ve
1 = -ve
B. + 32 768
215 variations = 32768 numbers

Positive range: 0 – 32 767

Negative range: -1 – -32 768

71 72
Q.4 Answer – A (1MB)
How much memory can be addressed if
a computer has an address bus with 20
The number of addressable units of
lines? memory is 220 = 1 048 576.

The standard addressable unit is a byte.

A. 1 MB
1 048 576 bytes is 1 MB

B. 4 KB

73 74

Answer - B
Q. 5
ROM is_________
Read Only Memory is non-volatile.

Non-volatile means that the contents of
A. volatile
the memory are not lost when power is
B. non-volatile
removed.

75 76
Q.6 Answer - A
A data bus is 32-bits wide. How many
memory banks are needed?
4 memory banks, if each one stores data
as 8 bits units, are needed for a 32-bit
A. 4 data bus.
 Not all memory banks are 8 bits wide!
B. 2

77 78

Q.7 Answer - B
A computer stores its instructions and
data in separate memory units. This
Computers with a Harvard architecture
architecture is called________. store instructions and data in separate
memory units.
 Most often used with Digital Signal
A. von Neumann
Processing (DSP) microprocessors, and
B. Harvard microcontrollers (MCUs)

79 80