Lab # 4

DATA FLOW MODELLING, MUX AND ADDERS

DATAFLOW MODELLING
For small circuits, the gate-level modeling approach works very well because the number of gates
is limited and the designer can instantiate and connect every gate individually. Also, gate-level
modeling is very intuitive to a designer with a basic knowledge of digital logic design. However,
in complex designs the number of gates is very large. Thus, designers can design more effectively
if they concentrate on implementing the function at a level of abstraction higher than gate level.
Dataflow modeling provides a powerful way to implement a design. Verilog allows a circuit to be
designed in terms of the data flow between registers and how a design processes data rather than
instantiation of individual gates.
importance. No longer can companies devote engineering resources to handcrafting entire designs
with gates. Currently, automated tools are used to create a gate-level circuit from a dataflow design
description. This process is called logic synthesis. Dataflow modeling has become a popular design
approach as logic synthesis tools have become sophisticated. This approach allows the designer to
concentrate on optimizing the circuit in terms of data flow. For maximum flexibility in the design
process, designers typically use a Verilog description style that combines the concepts of gate-
level, data flow, and behavioral design. In the digital design community, the term RTL (Register
Transfer Level) design is commonly used for a combination of dataflow modeling and behavioral
modeling.

Continuous Assignment
A continuous assignment is the most basic statement in dataflow modeling, used to drive a value
onto a net. This assignment replaces gates in the description of the circuit and describes the circuit
at a higher level of abstraction. The assignment statement starts with the keyword assign.
Continuous assignments have the following characteristics:
1. The left hand side of an assignment must always be a scalar or vector net or a concatenation of
scalar and vector nets. It cannot be a scalar or vector register.
2. Continuous assignments are always active. The assignment expression is evaluated as soon as
one of the right-hand-side operands changes and the value is assigned to the left-hand-side net.
3. The operands on the right-hand side can be registers or nets or function calls. Registers or nets
can be scalars or vectors.
4. Delay values can be specified for assignments in terms of time units. Delay values are used to
control the time when a net is assigned the evaluated value. This feature is similar to specifying
delays for gates. It is very useful in modelling timing behavior in real circuits.
Example-1: Examples of Continuous Assignment

Regular Assignment Delay

The first method is to assign a delay value in a continuous assignment statement. The delay value
is specified after the keyword assign. Any change in values of in1 or in2 will result in a delay of
10 time units before recomputation of the expression in1 & in2, and the result will be assigned to
out. If in1 or in2 changes value again before 10 time units when the result propagates to out, the
values of in1 and in2 at the time of recomputation are considered. This property is called inertial
delay.

Figure-1 Delays

Expressions, Operators and Operands

Dataflow modeling describes the design in terms of expressions instead of primitive gates.
Expressions, operators, and operands form the basis of dataflow modeling.

Expressions
Expressions are constructs that combine operators and operands to produce a result.

Operands
Some constructs will take only certain types of operands. Operands can be constants, integers, real
numbers, nets, registers, times, bit-select (one bit of vector net or a vector register), part-select
(selected bits of the vector net or register vector), and memories
Operators
Operators act on the operands to produce desired results. Verilog provides various types of
operators.

Operator Types
Verilog provides many different operator types. Operators can be arithmetic, logical, relational,
equality, bitwise, reduction, shift, concatenation, or conditional. Some of these operators are
similar to the operators used in the C programming language. Each operator type is denoted by a
symbol. Table -1 shows the complete listing of operator symbols classified by category.

Table - 1
Arithmetic Operators
There are two types of arithmetic operators: binary and unary.

Binary operators
Binary arithmetic operators are multiply (*), divide (/), add (+), subtract (-), power (**), and
modulus (%). Binary operators take two operands.
Negative numbers are represented as 2's complement internally in Verilog. It is advisable to use
negative numbers only of the type integer or real in expressions. Designers should avoid negative
numbers of the type <sss> '<base> <nnn> in expressions because they are converted to unsigned
2's complement numbers and hence yield unexpected results.

Logical Operators:
Logical operators are logical-and (&&), logical-or (||) and logical-not (!). Operators && and || are
binary operators. Operator ! is a unary operator. Logical operators follow these conditions:

1. Logical operators always evaluate to a 1-bit value, 0 (false), 1 (true), or x (ambiguous).

2. If an operand is not equal to zero, it is equivalent to a logical 1 (true condition). If it is 01equal
to zero, it is equivalent to a logical 0 (false condition). If any operand bit is x or z, it is equivalent
to x (ambiguous condition) and is normally treated by simulators as a false condition.
3. Logical operators take variables or expressions as operands.
Use of parentheses to group logical operations is highly recommended to improve readability.
Also, the user does not have to remember the precedence of operators.
Relational Operators:

Equality Operators:

filling if the operands are of unequal length. Table – 2 lists the operators.

Table – 2 Equality Operators

Bitwise Operators:
Bitwise operators are negation (~), and(&), or (|), xor (^), xnor (^~, ~^). Bitwise operators perform
a bit-by-bit operation on two operands. They take each bit in one operand and perform the
operation with the corresponding bit in the other operand. If one operand is shorter than the other,
it will be bit-extended with zeros to match the length of the longer operand. Logic tables for the
bit-by-bit computation are shown in Table -3. A z is treated as an x in a bitwise operation. The
exception is the unary negation operator (~), which takes only one operand and operates on the
bits of the single operand.

Figure – 2 Truth Tables for Bitwise Operators

It is important to distinguish bitwise operators ~, &, and | from logical operators !, &&, ||. Logical
operators always yield a logical value 0, 1, x, whereas bitwise operators yield a bit-by-bit value.
Logical operators perform a logical operation, not a bit-by-bit operation.
Reduction Operators:

Shift Operators:

Concatenation Operators:
Replication Operators:

Conditional Operator
The conditional operator(?:) takes three operands.

Usage: condition_expr ? true_expr : false_expr ;

The condition expression (condition_expr) is first evaluated. If the result is true (logical 1), then
the true_expr is evaluated. If the result is false (logical 0), then the false_expr is evaluated. If the
result is x (ambiguous), then both true_expr and false_expr are evaluated and their results are
compared, bit by bit, to return for each bit position an x if the bits are different and the value of
the bits if they are the same.

Conditional operators are frequently used in dataflow modeling to model conditional assignments.
The conditional expression acts as a switching control.

Conditional operations can be nested. Each true_expr or false_expr can itself be a conditional
operation. In the example that follows, convince yourself that (A==3) and control are the two select
signals of 4-to-1 multiplexer with n, m, y, x as the inputs and out as the output signal.

EXAMPLE 1: 4-to-1 line Multiplexer

We will implement 4-to-1 line multiplexer, using dataflow statements. Compare it with the gate-
level description.
Method 1: logic equation
We can use assignment statements instead of gates to model the logic equations of the multiplexer.
Notice that everything is same as the gate-level Verilog description except that computation of out
is done by specifying one logic equation by using operators instead of individual gate
instantiations. I/O ports remain the same. This is important so that the interface with the
environment does not change. Only the internals of the module change. Notice how concise the
description is compared to the gate-level description.

Example 4-to-1 Multiplexer, Using Logic Equation

There is a more concise way to specify the 4-to-1 multiplexers. In this we will use this conditional
operator to write a 4-to-1 multiplexer.

Example 4-to-1 Multiplexer, Using Conditional Operators

EXAMPLE 2: 4-bit Full Adder using data flow Operator

Method 1: dataflow operators

Below a concise description of the adder is defined with the + and { } operators.

EXAMPLE 4-bit Full Adder using data flow Operator

If we substitute the gate-level 4-bit full adder with the dataflow 4-bit full adder, the rest of the
modules will not change. The simulation results will be identical.

EXAMPLE 3: 4 – Bit Ripple Carry Counter

Now we design a 4-bit ripple counter by using negative edge-triggered flip flop. We design it using
Verilog dataflow statements and test it with a stimulus module. The diagrams for the 4-bit ripple
carry counter modules are shown below. Fallowing figure shows the counter being built with four
T-flipflops.
Figure – 3 4 Bit Ripple Carry Counter

As the T- FF is built with D- FF:

Dataflow code:
Verilog Code for T-flipflop

Finally, we define the lowest level module D_FF (edge_dff ), using dataflow statement.

Verilog Code for Edge-Triggered D-flipflop

The design block is now ready. Now we must instantiate the design block inside the stimulus block
to test the design. The clock has a time period of 20 with a 50% duty cycle.
NOTE: $finish statement is used whenever forever loop or always block is used, otherwise the
loop will keep on running indefinitely; it serves the useful purpose of suspending all initial blocks.
Also note that forever loop is normally used in conjunction with initial statement block, whereas
always can be used as a standalone block. All initial statements are executed concurrently at time
t =0 and the delays of one initial block do not affect the other initial block. On the other hand the
delays in one initial block containing begin and end are added.

Output:
The output of the simulation is shown below. Note that the clear signal resets the count to zero.

The waveforms are also shown below:

HOME TASKS:
1. Implement 8-bit 4x1 MUX using Data flow modelling.
2. Implement 4-bit 2x1 MUX using Data flow modelling.
Verify your design using display directive.
3. Implement 8-bit Ripple Carry Counter