High-Level State Machine Behavior

Inputs: B; Outputs: X
• Register-transfer level (RTL) design X=0

ECE 274 – Digital Logic captures desired system behavior using

high-level state machine B
Off B'

Verilog – Earlier example – 3 cycles high, used FSM X=1 X=1 X=1
– What if 512 cycles high? 512-state FSM? On1 On2 On3
– Better solution – High-level state machine
Verilog for Digital Design (Vahid, Lysecky): Ch. 5 that uses register to count cycles 3 cycles with X=1
• Declare explicit register Cnt (2 bits for 3-
cycles high) Inputs: B; Outputs: X; Register: Cnt(2)
• Initialize Cnt to 2 (2, 1, 0 Æ 3 counts) X=0
• "On" state Cnt=2
– Sets X=1
– Configures Cnt for decrement on next cycle Off B'
– Transitions to Off when Cnt is 0 Cnt=0
– Note that transition conditions use current B X=1
value of Cnt, not next (decremented) value Cnt=Cnt-1
• For 512 cycles high, just initialize Cnt to 511 On
(Cnt=0)'

Verilog for Digital Design Verilog for Digital Design

Copyright © 2007 Copyright © 2007 3 cycles with X=1 2
Frank Vahid and Roman Lysecky Frank Vahid and Roman Lysecky

High-Level State Machine Behavior High-Level State Machine Behavior

...
• CombLogic process reg [0:0] State, StateNext;
• Module ports same as FSM `timescale 1 ns/1 ns
– Describes actions and transitions reg [1:0] Cnt, CntNext;
• Same two-procedure approach module LaserTimer(B, X, Clk, Rst);
as FSM Inputs: B; Outputs: X; Register: Cnt(2)
// CombLogic
always @(State, Cnt, B) begin
– One for combinational logic, input B; X=0 case (State)
one for registers output reg X; Cnt=2 S_Off: begin
input Clk, Rst;
– Registers now include explicit Off B'
X <= 0;
registers (Cnt) parameter S_Off = 0,
CntNext <= 2;
Note: Writes
• Two reg variables per explicit Cnt=0 if (B == 0)
S_On = 1; B are to "next"
register (current and next), just X=1 StateNext <= S_Off;
like for state register Cnt=Cnt-1 else
reg [0:0] State, StateNext; variable, reads
StateNext <= S_On;
reg [1:0] Cnt, CntNext; On end are from
(Cnt=0)'
S_On: begin "current"
// CombLogic X <= 1;
always @(State, Cnt, B) begin variable. See
HLSM
inputs

outputs

outputs
inputs

HLSM
inputs

outputs
CntNext <= Cnt - 1;
HLSM
FSM

bB x X HLSM
FSM

B X
Combinational
Combinational
...
Combinational if (Cnt == 0) target
end
logic logic logic StateNext <= S_Off; architecture to
else
State
State Cnt // Regs State Cnt StateNext <= S_On;
understand
always @(posedge Clk) begin end why.
Clk
clk Stateregister
State register Cnt register ... Clk State register Cnt register endcase
end end
StateNext CntNext StateNext CntNext
StateNext endmodule ...

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Copyright © 2007 vldd_ch5_LaserTimerHLSM.v 3 Copyright © 2007 vldd_ch5_LaserTimerHLSM.v 4
Frank Vahid and Roman Lysecky Frank Vahid and Roman Lysecky

High-Level State Machine Behavior

Simulating the HLSM
• Regs process • Use same testbench as in Chapter 3
– Updates registers on rising clock
• Waveforms below also show Cnt and State
Inputs: B; Outputs: X; Register: Cnt(2)
variables, even though not a port on the
X=0 LaserTime module Inputs: B; Outputs: X; Register: Cnt(2)
Cnt=2 ... – Simulators allow one to zoom into modules to X=0
// Regs select internal variables/nets to show Cnt=2
Off B'
always @(posedge Clk) begin
Cnt=0 • Note reset behavior Off B'
if (Rst == 1 ) begin
B X=1 Cnt=0
Cnt=Cnt-1
State <= S_Off; – Until Rst=1 and rising clock, Cnt and State
Cnt <= 0; B X=1
undefined Cnt=Cnt-1
On end
(Cnt=0)' else begin – Upon Rst=1 and rising clock, Cnt set to 0, and
On
State <= StateNext; State set to S_Off (which is defined as 0) (Cnt=0)'
Cnt <= CntNext;
• Note how system enters S_On on first rising
HLSM
inputs

outputs

end
HLSM

B X
Combinational end clock after B becomes 1, causing Cnt to be 1 for 3 cycles
logic ...
initialized to 2 B
State Cnt
– Cnt is decremented in S_On x
X
Clk State register Cnt register – Cnt wrapped from 0 to 3, but the 3 was never
used Clk
StateNext CntNext
Rst
Cnt X
Verilog for Digital Design Verilog for Digital Design
Copyright © 2007 vldd_ch5_LaserTimerHLSM.v 5 Copyright © 2007 State X
6
Frank Vahid and Roman Lysecky Frank Vahid and Roman Lysecky

1
 Top-Down Design: HLSM to Controller and Datapath Top-Down Design: HLSM to Controller and Datapath
Inputs: B; Outputs: X; Register: Cnt(2)
• Recall from Chapters 2 & 3 • Recall from Chapters 2 & 3 X=0
– Top-down design – Top-down design Cnt=2
K_s
• Capture behavior, and simulate Capture P_s • Capture behavior, and simulate Off B'
Simulate
• Capture structure (circuit), behavior S_s
• Capture structure (circuit),
W_s Cnt=0
simulate again Should be simulate again B X=1
the same Cnt=Cnt-1
• Gets behavior right first, K_s • Gets behavior right first,
Capture P_s
unfettered by complexity of Simulate S_s unfettered by complexity of On
structure (Cnt=0)'
creating structure W_s creating structure
• At RTL level
– Capture behavior Æ HLSM
– Capture structure: Controller and
datapath Controller Datapath

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Frank Vahid and Roman Lysecky Frank Vahid and Roman Lysecky

Top-Down Design: HLSM to Controller and Datapath Top-Down Design: HLSM to Controller and Datapath
Inputs: B; Outputs: X; Register: Cnt(2)
X=0
• Deriving a Inputs: B; Outputs: X; Register: Cnt(2)
• Deriving a controller Cnt=2
datapath from X=0
– Replace HLSM by Off B'
the HLSM Cnt=2 FSM that uses the
datapath Cnt=0
Off B' B X=1
Cnt=Cnt-1
Cnt=0
B X=1 On
Cnt=Cnt-1 (Cnt=0)'

On
(Cnt=0)' Datapath
Inputs: B, Cnt_Eq_0; Outputs: X, Cnt_Sel, Cnt_Ld;
Datapath
X=0 "10"
Cnt_Sel=1, Cnt_Ld=1 Cnt_Sel
"10"
Cnt_Sel S 1 2x1 0
Off B' Cnt_Eq_0
="00" -1
="00" S 1 2x1 0 -1 Cnt_Eq_0
Cnt_Eq_0
B X=1 Cnt_Ld
Cnt_Sel=0, Cnt_Ld=1 Ld
Cnt_Ld Cnt
Ld Clk
Cnt On
Clk (Cnt_Eq_0)' Controller

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Frank Vahid and Roman Lysecky Frank Vahid and Roman Lysecky

Describing a Datapath
Top-Down Design: HLSM to Controller and Datapath
Behaviorally ...
// Shared variables
• Describe controller and datapath in VHDL • Two procedures reg Cnt_Eq_0, Cnt_Sel, Cnt_Ld;
// Controller variables
– One option: structural datapath, behavioral (FSM) controller – Combinational part and reg [0:0] State, StateNext;
// Datapath variables
– Let's instead describe both behaviorally register part reg [1:0] Cnt, CntNext;
– Current and next signals // ------ Datapath Procedures ------ //
shared between the two parts // DP CombLogic
always @(Cnt_Sel, Cnt) begin
– Just like for FSM behavior if (Cnt_Sel==1)
Inputs: B, Cnt_Eq_0; Outputs: X, Cnt_Sel, Cnt_Ld;
Datapath CntNext <= 2;
Datapath else
X=0 "10" CntNext <= Cnt - 1;
Cnt_Sel=1, Cnt_Ld=1 Cnt_Sel DpCombLogic
"10" Cnt_Eq_0 <= (Cnt==0)?1:0;
S 1 2x1 0 Cnt_Sel
Off B' Cnt_Eq_0
="00" -1 end
="00" S 1 2x1 0 -1
Cnt_Eq_0 Cnt_Eq_0 // DP Regs
B X=1 Cnt_Ld always @(posedge Clk) begin
Cnt_Sel=0, Cnt_Ld=1 Ld CntNext Cnt if (Rst == 1 )
Cnt Cnt_Ld Cnt <= 0;
Clk Ld
On Cnt else if (Cnt_Ld==1)
(Cnt_Eq_0)'Controller Clk Cnt <= CntNext;
DpRegs end
...

Verilog for Digital Design Verilog for Digital Design Note use of previously-introduced conditional operator
Copyright © 2007 11 Copyright © 2007 vldd_ch5_LaserTimerCtrlDpBeh.v 12
Frank Vahid and Roman Lysecky Frank Vahid and Roman Lysecky

2
 ...

Describing the Controller Controller and Datapath

module LaserTimer(B, X, Clk, Rst);
... ...
// ------ Controller Procedures ------ //

Behaviorally Behavior
// Ctrl CombLogic parameter S_Off = 0,
always @(State, Cnt_Eq_0, B) begin S_On = 1;
case (State)
• Standard approach for S_Off: begin • Result is one module with four // Shared variables
describing FSM X <= 0; Cnt_Sel <= 1; Cnt_Ld <= 1; procedures reg Cnt_Eq_0, Cnt_Sel, Cnt_Ld;
if (B == 0) // Controller variables
– Two procedures StateNext <= S_Off; – Datapath procedures (2) reg [0:0] State, StateNext;
else • Combinational logic // Datapath variables
StateNext <= S_On; reg [1:0] Cnt, CntNext;
• Registers
end
Inputs: B, Cnt_Eq_0; Outputs: X, Cnt_Sel, Cnt_Ld; S_On: begin – Controller procedures (2) // ------ Datapath Procedures ------ //
X <= 1; Cnt_Sel <= 0; Cnt_Ld <= 1; • Combinational logic // DP CombLogic
X=0 if (Cnt_Eq_0 == 1)
• Registers always @(Cnt_Sel, Cnt) begin
Cnt_Sel=1, Cnt_Ld=1 StateNext <= S_Off; ...
else end
Off B' StateNext <= S_On;
end // DP Regs
Cnt_Eq_0 endcase always @(posedge Clk) begin
B X=1 end Inputs: B, Cnt_Eq_0; Outputs: X, Cnt_Sel, Cnt_Ld;
Datapath
...
Cnt_Sel=0, Cnt_Ld=1 X=0 end
Cnt_Sel=1, Cnt_Ld=1 Cnt_Sel "10"
// Ctrl Regs
On always @(posedge Clk) begin Off B' Cnt_Eq_0
="00" S 1 2x1 0
-1 // ------ Controller Procedures ------ //
(Cnt_Eq_0)'Controller if (Rst == 1 ) begin Cnt_Eq_0 // Ctrl CombLogic
State <= S_Off; B X=1
Cnt_Sel=0, Cnt_Ld=1
Cnt_Ld
Ld
always @(State, Cnt_Eq_0, B) begin
end Cnt
Clk ...
else begin On
(Cnt_Eq_0)' Controller end
State <= StateNext;
end // Ctrl Regs
end always @(posedge Clk) begin
Verilog for Digital Design ... Verilog for Digital Design ...
Copyright © 2007 vldd_ch5_LaserTimerCtrlDpBeh.v 13 Copyright © 2007 end 14
Frank Vahid and Roman Lysecky Frank Vahid and Roman Lysecky endmodule vldd_ch5_LaserTimerCtrlDpBeh.v

One-Procedure State ...

module LaserTimer(B, X, Clk, Rst);

One-Procedure State Machine Description

...

Machine Description parameter S_Off = 0,

S_On = 1;
...
module LaserTimer(B, X, Clk, Rst); reg [0:0] State;
• Previously described HLSM ... • Procedure sensitive to clock only reg [1:0] Cnt;
using two procedures reg [0:0] State, StateNext; • If not reset, then executes current state's always @(posedge Clk) begin
reg [1:0] Cnt, CntNext;
actions, and assigns next value of state if (Rst == 1 ) begin
– One for combinational logic, // CombLogic State <= S_Off;
one for registers always @(State, Cnt, B) begin
• Why didn't we describe with one procedure Cnt <= 0;
... before? end
– Required "current" and end – Main reason – Procedure synchronous to else begin
"next" signals for each clock only Æ Inputs become synchronous case (State)
// Regs S_Off: begin
register always @(posedge Clk) begin • Changes the state machine's timing X <= 0;
... • e.g., In state S_off, and B changes to 1 in Cnt <= 2;
• A one-procedure description end vldd_ch5_LaserTimerHLSM.v middle of clock cycle if (B == 0)
is possible too endmodule • Previous two procedure model State <= S_Off;
else
– Change in b immediately noticed by
– One procedure per HLSM ... combinational logic procedure, which
State <= S_On;
configures next state to be S_On. State end
module LaserTimer(B, X, Clk, Rst);
– One variable per register ... changes to S_On on next rising clock. S_On: begin
X <= 1;
– Simpler code with clear reg [0:0] State; • One procedure model Cnt <= Cnt - 1;
reg [1:0] Cnt; – Change in b not noticed until next rising clock,
grouping of functionality if (Cnt == 0)
so next state still S_Off. After rising clock,
State <= S_Off;
always @(posedge Clk) begin procedure configures next state to be S_On.
– But may change timing end State changes to S_On on the next rising clock else
endmodule vhdd_ch5_LaserTimerHLSMOneProc.v – or two rising clocks after b changed State <= S_On;
end
• See next slide for timing diagrams endcase
Verilog for Digital Design Verilog for Digital Design vldd_ch5_LaserTimerHLSMOneProc.v
end
Copyright © 2007 15 Copyright © 2007 end 16
Frank Vahid and Roman Lysecky Frank Vahid and Roman Lysecky endmodule

Timing Differences Between Two and One Procedure One Procedure FSM Description
Descriptions
• Previous two procedure description
B
– Change in B immediately noticed by • Likewise, can describe FSM using one procedure rather than two
combinational logic procedure, X
– Same approach
which configures next state to be Clk
S_On. State changes to S_On (1) • One variable for state (rather than two)
Rst
on next rising clock (setting X=1). • One procedure, sensitive to clock only
State
• One procedure description – Same issues as with HLSM
– Change in B not noticed until next • Simpler, cleaner code: one procedure per FSM
rising clock, so next state still S_Off • Timing may change: makes inputs synchronous, may introduce extra cycles
(0). After rising clock, procedure B
configures next state to be S_On X
(1). State changes to S_On on the Clk
next rising clock (setting X=1) – two
Rst
rising clocks after b changed
State
• Likewise, initial reset also delayed

Synchronization of input can delay impact of input changes

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Frank Vahid and Roman Lysecky Frank Vahid and Roman Lysecky

3
 Improving Timing Realism Delay Control on Right Side of Assignment Statements
• Real components have delays • Delays can be described by including delay `timescale 1 ns/1 ns
control in assignment statement
• Suppose comparator has 7 ns delay – variablename <= # delay_value expression module LaserTimer(B, X, Clk, Rst);
...
• # delay_value –Time units into the future at
// DP CombLogic
which variable update should occur always @(Cnt_Sel, Cnt) begin
Suppose has 7 ns delay – Example gives comparator 7 time units of delay if (Cnt_Sel==1)
– And a time unit equals 1 ns, so 7 ns delay CntNext <= 2;
Datapath – Should also include delay for mux and subtractor else
Inputs: B, Cnt_Eq_0; Outputs: X, Cnt_Sel, Cnt_Ld; parts CntNext <= Cnt - 1;

X=0 • Previously saw delay control prepended to

"10" statement Cnt_Eq_0 <= #7 (Cnt==0)?1:0;
Cnt_Sel=1, Cnt_Ld=1 Cnt_Sel
end
– e.g., #10 Y <= 0; ...
Off ="00" S 1 2x1 0 -1 – Prepended form delays execution of next
B' Cnt_Eq_0
statement by 10 time units
Cnt_Eq_0 – Right side form executes statement immediately,
B X=1 Cnt_Ld but schedule update of Y for 10 time units later
Cnt_Sel=0, Cnt_Ld=1 Ld • Delays might be estimated from real component
Cnt
Clk library
On – Typically associated with gate-level components,
(Cnt_Eq_0)'Controller
muxes, registers, etc.
• Results in more accurate simulation
• Note: Synthesis tools ignore delays
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Frank Vahid and Roman Lysecky Frank Vahid and Roman Lysecky

Simulation with Timing Delays Added Algorithmic-Level Behavior

• Waveforms show key internal signals: B
Cnt, Cnt_Eq_0, and State • Higher than HLSM?
X
• Description with comparator delay shifts – HLSM high-level, but even higher
the Cnt_Eq_0 signal to right by 7 ns Clk sometimes better
Rst A SAD
Without comparator delay • Algorithmic-level
Cnt 256-byte array
Cnt_Eq_0
– Behavior described as sequence of 32-bits
steps B Sad_Out
State
– Similar to sequential program 256-byte array
B
• SAD example Go
X
Clk
– Compute sum of absolute
differences of corresponding pairs in
Rst
With comparator delay (note shift) two arrays
Cnt
• Common task in video compression
Cnt_Eq_0 to determine difference between two
State successive video frames

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Frank Vahid and Roman Lysecky Frank Vahid and Roman Lysecky

Algorithmic-Level
`timescale 1 ns/1 ns

module SAD(Go, SAD_Out);

Algorithmic-Level Behavior for SAD Behavior for SAD input Go;

output reg [31:0] SAD_Out;

A SAD reg [7:0] A [0:255];

• Description uses several reg [7:0] B [0:255];
256-byte array language features to be described integer Sum;
• Most easily described as an algorithm on next several slides integer I;
32-bits
– Input is two arrays A and B B SAD_Out • User-defined function function integer ABS;
– Wait until Go is '1' – Returns a value to be used in an input integer IntVal;
256-byte array begin
– Use for loop to step through each array Go
expression ABS = (IntVal>=0)?IntVal:-IntVal;
item – This function named "ABS" end
• Adds absolute difference to running • Will compute absolute value endfunction
sum • Returns integer value // Initialize Arrays
– Update output after loop completes • One input argument, integer initial $readmemh("MemA.txt", A);
Wait until Go equals 1
• Contents assign return value to initial $readmemh("MemB.txt", B);
• Note: No intention of providing this Sum = 0
for I in 0 to 255 loop be positive version of input
always begin
description to synthesis tool Sum = Sum + |A(I) - B(I)| argument
if (!(Go==1)) begin
end loop • This function contains only one
– Merely used for early system SAD_Out = Sum statement, but may contain any
@(Go==1);
end
simulation number Sum = 0;
Note: Above algorithm written in pseudo- – ABS can then be called by later for (I=0; I<=255; I=I+1) begin
code, not in a particular language parts of the description Sum = Sum + ABS(A[I] - B[I]);
end
#50;
SAD_Out <= Sum;
Verilog for Digital Design Verilog for Digital Design end vldd_ch5_SADAlg.v
Copyright © 2007 23 Copyright © 2007 endmodule 24
Frank Vahid and Roman Lysecky Frank Vahid and Roman Lysecky

4
 Algorithmic-Level
`timescale 1 ns/1 ns

module SAD(Go, SAD_Out);

Behavior for SAD input Go; Event Control with an Expression

output reg [31:0] SAD_Out;

reg [7:0] A [0:255]; • Uses @(Go==1) – Event control with an expression

• Description declares A and B as 256- reg [7:0] B [0:255];
element arrays of bytes integer Sum; – If Go not 1, wait until Go becomes 1
integer I;
• Initializes those arrays using built-in system – Previous event control expressions were either one event, such as @(X) or
task $readmemh function integer ABS; @(posedge Clk), or a list of events such as @(X,Y)
– Reads file of hex numbers (first argument) input integer IntVal;
– Each number placed into subsequent begin – But expression can be a longer expression too, like @(Go==1)
ABS = (IntVal>=0)?IntVal:-IntVal;
element of array (second argument) end • Waits not just for change on Go, but for a change on Go such that Go equals 1
• Number of numbers in file should match endfunction
number of elements ...
• No length or base format for numbers // Initialize Arrays always begin
• Separated by white space initial $readmemh("MemA.txt", A); if (!(Go==1)) begin
• e.g., 00 FF A1 04 ... initial $readmemh("MemB.txt", B); @(Go==1);
end
– $readmemb: Reads file of binary numbers always begin Sum = 0;
• Note: Called as only statement of "initial" if (!(Go==1)) begin for (I=0; I<=255; I=I+1) begin
procedure @(Go==1); Sum = Sum + ABS(A[I] - B[I]);
end end
– Could have used begin-end block: Sum = 0; #50;
initial begin for (I=0; I<=255; I=I+1) begin SAD_Out <= Sum;
$readmemh("MemA.txt", A); Sum = Sum + ABS(A[I] - B[I]); end
end end ...
#50;
SAD_Out <= Sum; Delay of 50 ns added just so that result doesn't appear instantaneously
Verilog for Digital Design end vldd_ch5_SADAlg.v Verilog for Digital Design
Copyright © 2007 endmodule 25 Copyright © 2007 vldd_ch5_SADAlg.v 26
Frank Vahid and Roman Lysecky Frank Vahid and Roman Lysecky

Algorithmic-Level Behavior Convert Algorithm to HLSM

`timescale 1 ns/1 ns
• Testbench
– Setup similar to previous testbenches module Testbench();
– Activate SAD with Go_s <= 1
reg Go_s; Local registers: Sum, SAD_Reg (32 bits); I (integer)
• Simulation generates SAD_out wire [31:0] SAD_Out_s;
– SAD_out is uninitialized at first, resulting
in unknown value SAD CompToTest(Go_s, SAD_Out_s);
– 50 ns later, result is 4 S0 !Go
// Vector Procedure
• Which is correct for the value with which initial begin Go
we initialized the memories A and B
Go_s <= 0; Sum = 0
• More thorough algorithmic-level #10 Go_s <= 1; S1
I=0
description would be good #10 Go_s <= 0;
#60 if (SAD_Out_s != 4) begin
– Perhaps try different sets of values (I<256)’
$display("SAD failed -- should equal 4");
end S2
end
endmodule I<256
vldd_ch5_SADAlgTB.v Sum=Sum+ABS(A[I]-B[I])
S3
I=I+1
Go
SAD_Out xxxxxx
S4 SAD_Reg = Sum

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Frank Vahid and Roman Lysecky Frank Vahid and Roman Lysecky

// High-level state machine

always @(posedge Clk) begin
Describe HLSM in Verilog if (Rst==1) begin `timescale 1 ns/1 ns

Describe HLSM in Verilog

State <= S0;
Sum <= 0; module Testbench();
`timescale 1 ns/1 ns SAD_Reg <= 0;
I <= 0; reg Go_s;
module SAD(Go, SAD_Out, Clk, Rst); end
• Use similar testbench as for algorithmic- reg Clk_s, Rst_s;
else begin wire [31:0] SAD_Out_s;
input Go; case (State) level description
output [31:0] SAD_Out; Clk and Rst inputs and S0: begin
input Clk, Rst; – Clk, Rst introduced SAD CompToTest(Go_s, SAD_Out_s, Clk_s, Rst_s);
functionality introduced if (Go==1)
State <= S1; – Minor change – wait for (256*2+3) * (20
// Clock Procedure
parameter S0 = 0, S1 = 1, else ns) for SAD result to appear always begin
S2 = 2, S3 = 3, State <= S0; • HLSM involves better clock cycle accuracy Clk_s <= 0;
S4 = 4; end than algorithmic model #10;
S1: begin Clk_s <= 1;
reg [7:0] A [0:255]; Sum <= 0; • Implementation – Proceed to convert
#10;
reg [7:0] B [0:255]; I <= 0; HLSM to controller/datapath, as before end // Note: Procedure repeats
reg [2:0] State; State <= S2;
integer Sum, SAD_Reg; end // Vector Procedure
integer I; S2: begin initial begin
if (!(I==255)) Rst_s <= 1;
function integer ABS; State <= S3; Go Go_s <= 0;
input integer IntVal; else @(posedge Clk_s);
begin State <= S4; SAD_Out Rst_s <= 0;
ABS = (IntVal>=0)?IntVal:-IntVal; end
end Clk Go_s <= 1;
S3: begin @(posedge Clk_s);
endfunction Sum <= Sum + ABS(A[I]-B[I]); Rst Go_s <= 0;
I <= I + 1; #((256*2+3)*20) if (SAD_Out_s != 4) begin
// Initialize Arrays State <= S2; $display("SAD failed -- should equal 4");
initial $readmemh("MemA.txt", A); end time=10,290 ns end
initial $readmemh("MemB.txt", B); S4: begin end
SAD_Reg <= Sum; endmodule
Verilog for Digital Design State <= S0; Verilog for Digital Design
Copyright © 2007 end 29 Copyright © 2007 30
vldd_ch5_SADHLSM.v
Frank Vahid and Roman Lysecky endcase Frank Vahid and Roman Lysecky vldd_ch5_SADHLSMTB.v
end

5
 Automated Synthesis from the Algorithmic Level Simulation Speed
• Behavioral synthesis (or high-level synthesis) tools • Higher-level descriptions yield faster simulations
– Introduced in the 1990s and 2000s – Due to fewer procedures, fewer variables, fewer events, ...
– Automatically synthesize algorithmic-code to RTL code or directly to circuits – 10x difference means difference between tens of minutes versus hours; 100x
– Not yet adopted as widely as RTL synthesis tools could mean days
– Each tool imposes strong requirements and restrictions on the algorithmic- – High-level descriptions (e.g., algorithmic) preferred early in design, and for
level code integrated systems with many (hundreds) of sub-systems
– The quality of RTL code or circuits created from such tools also varies • One-procedure clocked procedure state machine is also faster than
tremendously procedure approach where one procedure is combinational
– Interesting direction and may prove increasingly useful in coming years – Again, fewer procedures, fewer variables, fewer events, ...
• Differences become significant for very large systems, or for very lengthy
testbenches

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Copyright © 2007 31 Copyright © 2007 32
Frank Vahid and Roman Lysecky Frank Vahid and Roman Lysecky

Accessing Memory Simple Memory Entity

module SAD(Go, SAD_Out);
• Memory may be initially
input Go;
accessed as array for output reg [31:0] SAD_Out;
• Simple read-only memory
`timescale 1 ns/1 ns
simplicity reg [7:0] A [0:255];
– Addr and data ports only
module SADMem(Addr, Data);
– SAD example reg [7:0] B [0:255]; – Declares array named Memory for
• Declared two 256-item arrays storage input [7:0] Addr;
output [7:0] Data;
• Eventually, may want to – Procedure uses continuous
assignment statement to always reg [7:0] Memory [0:255];
describe memory as external
output Memory data element assign Data = Memory[Addr];
component endmodule
corresponding to current address
– Closer to real implementation input value

SAD A SAD

A 256-byte memory

SAD_Out B SAD_Out
B 256-byte memory
Go Go

Verilog for Digital Design Verilog for Digital Design vldd_ch5_SADMem.v

Copyright © 2007 33 Copyright © 2007 34
Frank Vahid and Roman Lysecky Frank Vahid and Roman Lysecky

always @(posedge Clk) begin S3a: begin

if (Rst==1) begin A_Addr <= I;
`timescale 1 ns/1 ns
Accessing Memory A_Addr <= 0; B_Addr <= I;
B_Addr <= 0; State <= S3;
module SAD(Go, A_Addr, A_Data, end
B_Addr, B_Data, State <= S0;
Sum <= 0; S3: begin
SAD_Out, Clk, Rst); Sum <= Sum +
• Modify SAD's HLSM Local registers: Sum, SAD_Reg (32 bits); I (integer)
SAD_Reg <= 0;
I <= 0; ABSDiff(A_Data, B_Data);
with extra state (S3a) input Go;
input [7:0] A_Data, B_Data; end I <= I + 1;
State <= S2;
for reading the output reg [7:0] A_Addr, B_Addr; else begin
case (State) end
memories S0 !Go output [31:0] SAD_Out; S4: begin
input Clk, Rst; S0: begin
SAD_Reg <= Sum;
– Extra state necessary Go if (Go==1)
State <= S0;
State <= S1;
due to use of fully- Sum = 0 parameter S0 = 0, S1 = 1,
else end
S1 S2 = 2, S3 = 3, S3a = 4,
synchronous HLSM I=0 S4 = 5; State <= S0; endcase
end end
(modeled as one S1: begin end
(I<256)’ reg [2:0] State;
procedure sensitive S2 reg [31:0] Sum, SAD_Reg; Sum <= 0;
assign SAD_Out = SAD_Reg;
only to clock) integer I; I <= 0;
I<256 State <= S2;
– A_addr & B_addr are A_Addr = I function [7:0] ABSDiff; end endmodule
output ports S3a B_Addr = I input [7:0] A; S2: begin
if (!(I==255))
connected to memory input [7:0] B;
State <= S3a;
Sum=Sum+ABS(A_Data - B_Data) begin
address inputs S3 if (A>B) ABSDiff = A - B; else
I=I+1 State <= S4; vldd_ch5_SADHLSM_Mem.v
– A_data and B_data else ABSDiff = B - A;
end
end
are input ports endfunction
connected to memory S4 SAD_Reg = Sum Created AbsDiff function for improved readability
data outputs Note: Violated our own guideline of using begin-end block with if-else
Verilog for Digital Design Verilog for Digital Design statements, to save space in this figure
Copyright © 2007 35 Copyright © 2007 36
Frank Vahid and Roman Lysecky Frank Vahid and Roman Lysecky

6
 module Testbench();
reg Go_s;

Testbench wire [7:0] A_Addr_s, B_Addr_s;

wire [7:0] A_Data_s, B_Data_s;
reg Clk_s, Rst_s; Waveforms
wire [31:0] SAD_Out_s;
• Instantiate and connect modules parameter ClkPeriod = 20; • Waveforms now include address and data lines with memories
for SAD, SADMemA, and
– We also added some internal signals, State, I, Sum, and SAD_Reg
SADMemB SAD CompToTest(Go_s, A_Addr_s, A_Data_s,
B_Addr_s, B_Data_s,
– Note two instances of same SAD_Out_s, Clk_s, Rst_s);
• SAD_Out result appears later than previously, due to extra state
memory SADMem SADMemA(A_Addr_s, A_Data_s);
SADMem SADMemB(B_Addr_s, B_Data_s);
• Initialize memories Clk
– Note how we can access // Clock Procedure
Rst
SADMemA.Memory (and B) always begin
Clk_s <= 0; #(ClkPeriod/2); Go
from testbench Clk_s <= 1; #(ClkPeriod/2);
A_Addr
• Vector procedure adjusted from end
A_Data
earlier to account for extra state // Initialize Arrays B_Addr
– ((256*2+3)*20) changed to initial $readmemh("MemA.txt", SADMemA.Memory);
initial $readmemh("MemB.txt", SADMemB.Memory); B_Data
((256*3+3)*ClkPeriod)
– Also note use of parameter State
// Vector Procedure
ClkPeriod – allows us to change initial begin I
period in one place ... // Reset behavior not shown Sum
Go_s <= 1;
@(posedge Clk_s); SAD_Reg
Go_s <= 0; SAD_Out
#((256*3+3)*ClkPeriod) if (SAD_Out_s != 4) begin
vldd_ch5_SADHLSM_MemTB.v $display("SAD failed -- should equal 4");
Verilog for Digital Design end Verilog for Digital Design 15390 ns
Copyright © 2007 end 37 Copyright © 2007 38
Frank Vahid and Roman Lysecky endmodule Frank Vahid and Roman Lysecky