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Computer Organization MCQ

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Computer Organization MCQ

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bbsmdr
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© © All Rights Reserved
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Computer Organization MCQ

https://www.sanfoundry.com/computer-organization-mcqs

1.The method which offers higher speeds of I/O transfers is ___________


a) Interrupts
b) Memory mapping
c) Program-controlled I/O
d) DMA

2. The method of accessing the I/O devices by repeatedly checking the status flags is
___________
a) Program-controlled I/O
b) Memory-mapped I/O
c) I/O mapped
d) None of the mentioned

3. To overcome the lag in the operating speeds of the I/O device and the processor
we use ___________
a) BUffer spaces
b) Status flags
c) Interrupt signals
d) Exceptions

4. In order to read multiple bytes of a row at the same time, we make use of ______
a) Memory extension
b) Cache
c) Shift register
d) Latch

5. In the case of, Zero-address instruction method the operands are stored in _____
a) Registers
b) Accumulators
c) Push down stack
d) Cache

6. The instruction, Add #45,R1 does _______


a) Adds the value of 45 to the address of R1 and stores 45 in that address
b) Adds 45 to the value of R1 and stores it in R1
c) Finds the memory location 45 and adds that content to that of R1
d) None of the mentioned
7. The addressing mode which makes use of in-direction pointers is ______
a) Indirect addressing mode
b) Index addressing mode
c) Relative addressing mode
d) Offset addressing mode

8. The addressing mode, where you directly specify the operand value is _______
a) Immediate
b) Direct
c) Definite
d) Relative

9. Which method/s of representation of numbers occupies a large amount of


memory than others?
a) Sign-magnitude
b) 1’s complement
c) 2’s complement
d) 1’s & 2’s compliment

10. Which representation is most efficient to perform arithmetic operations on the


numbers?
a) Sign-magnitude
b) 1’s complement
c) 2’S complement
d) None of the mentioned

11. The interrupt-request line is a part of the ___________


a) Data line
b) Control line
c) Address line
d) None of the mentioned

12. The signal sent to the device from the processor to the device after receiving an
interrupt is ___________
a) Interrupt-acknowledge
b) Return signal
c) Service signal
d) Permission signal

13. The DMA transfers are performed by a control circuit called as __________
a) Device interface
b) DMA controller
c) Data controller
d) Overlooker
14. he DMA transfer is initiated by _____
a) Processor
b) The process being executed
c) I/O devices
d) OS

15. ________ are the different type/s of generating control signals.


a) Micro-programmed
b) Hardwired
c) Micro-instruction
d) Both Micro-programmed and Hardwired

16. What does the hardwired control generator consist of?


a) Decoder/encoder
b) Condition codes
c) Control step counter
d) All of the mentioned

17. The disadvantage/s of the hardwired approach is ________


a) It is less flexible
b) It cannot be used for complex instructions
c) It is costly
d) less flexible & cannot be used for complex instructions

18. The CISC stands for ___________


a) Computer Instruction Set Compliment
b) Complete Instruction Set Compliment
c) Computer Indexed Set Components
d) Complex Instruction set computer
19. The RISC stands for ___________
a) Random Instruction Set Compliment
b) Rural Instruction Set Compliment
c) Random Indexed Set Components
d) Reduced Instruction set computer

20. The computer architecture aimed at reducing the time of execution of


instructions is ________
a) CISC
b) RISC
c) ISA
d) ANNA

21. The Sun micro systems processors usually follow _____ architecture.
a) CISC
b) ISA
c) ULTRA SPARC
d) RISC

22.) instruction format consists of


a) Data, bit , operands
b) Data , operand, operator
C) Opcode, operand
d) Mode, opcode, operand
23. pc holds

a) Operand
b) Operator
c) Opcode
d) Next address

24. Pipe-lining is a unique feature of _______


a) RISC
b) CISC
c) ISA
d) IANA

25. In CISC architecture most of the complex instructions are stored in _____
a) Register
b) Diodes
c) CMOS
d) Transistors
26. Which of the architecture is power efficient?
a) CISC
b) RISC
c) ISA
d) IANA
27. CPU, ALU, I/O devices are connected through
a) Single bus
b) Multiple bus
c) System bus
d) None of the above

28. Each stage in pipelining should be completed within ___________ cycle.


a) 1
b) 2
c) 3
d) 4
29. The number successful accesses to memory stated as a fraction is called as _____
a) Hit rate
b) Miss rate
c) Success rate
d) Access rate
30. The number failed attempts to access memory, stated in the form of a fraction is
called as _________
a) Hit rate
b) Miss rate
c) Failure rate
d) Delay rate
31. The memory blocks are mapped on to the cache with the help of ______
a) Hash functions
b) Vectors
c) Mapping functions
d) None of the mentioned
32. The method of mapping the consecutive memory blocks to consecutive cache
blocks is called ______
a) Set associative
b) Associative
c) Direct
d) Indirect
33. The fastest data access is provided using _______
a) Caches
b) DRAM’s
c) SRAM’s
d) Registers
34. The memory which is used to store the copy of data or instructions stored in
larger memories, inside the CPU is called _______
a) Level 1 cache
b) Level 2 cache
c) Registers
d) TLB
35. The larger memory placed between the primary cache and the memory is called ______
a) Level 1 cache
b) Level 2 cache
c) EEPROM
d) TLB
36. In micro-programmed approach, the signals are generated by ______
a) Machine instructions
b) System programs
c) Utility tools
d) None of the mentioned
37. The techniques which move the program blocks to or from the physical memory
is called as ______
a) Paging
b) Virtual memory organisation
c) Overlays
d) Framing
38. __________ is used to implement virtual memory organisation.
a) Page table
b) Frame table
c) MMU
d) None of the mentioned
39. ______ translates the logical address into a physical address.
a) MMU
b) Translator
c) Compiler
d) Linker
40. The main aim of virtual memory organisation is ________
a) To provide effective memory access
b) To provide better memory transfer
c) To improve the execution of the program
d) All of the mentioned
41. The ___________ subsystem of a computer provides communication between
central system and outside environment.
A. input/output.
B. input.
C. output.
D. exit.
42. Which functional component of the computer system is
responsible for the computing?
a) RAM
b) CPU
c) Input
d) Both a and b
43. When an instruction is read from the memory, it is called
a. Memory Read cycle
b. Fetch cycle
c. Instruction cycle
d. Memory write cycle
44. What does a computer bus line consists of?
Set of parallel lines
Accumulators
Registers
None of the above
45. In which of the following term the performance of cache memory is measured?
Chat ratio
Hit ratio
Copy ratio
Data ratio
46. A CPU register that keeps the track of execution of the program and contains the
instructions currently being executed is called
a) Index register
b) Memory address register
c) Instruction register
d) Stack pointer
47. A special register that holds the address of location to or from which data are to be
transferred is known as
a) Memory data register
b) Memory address register
c) Index register
d) Program counter
48. A unit that decodes, interprets each instruction and generates the required enable
signal for ALU and other units is called
a) arithmetic unit
b) CPU
c) logical unit
d) control unit
49. An instruction cycle consists of
a) fetching, and decoding
b) decoding, and executing
c) fetching, decoding, executing, and storing
d) fetching, executing, and storing
50. The central processing unit and memory are located on the
a) expansion board
b) motherboard
c) storage device
d) None of these
51. Motherboard is also known as
a) electronic board
b) Printed circuit board (PCB)
c) Combined device board
d) CPU board

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