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Vedic-Based Squaring Circuit Using Parallel Prefix Adders

Conference Paper · February 2020

DOI: 10.1109/SPIN48934.2020.9070866

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 2020 7th International Conference on Signal Processing and Integrated Networks (SPIN)

Vedic-Based Squaring Circuit Using Parallel Prefix

Adders
Avinash Jain Somya Bansal Shamim Akhter
Department of Electronics and Commu- Department of Electronics and Commu- Department of Electronics and Commu-
nication Engineering nication Engineering nication Engineering
Jaypee Institute of Information Technol- Jaypee Institute of Information Technol- Jaypee Institute of Information Technol-
ogy ogy ogy
Noida, India Noida, India Noida, India
[email protected] [email protected] [email protected]

Shaheen Khan
Department of Electronics and Commu-
nication Engineering
Mewat Engineering College
Haryana, India
[email protected]

Abstract- This paper proposes a novel method using Vedic results and performance comparison for the squaring circuits
mathematics for calculating the square of binary numbers. An designed using Verilog HDL are presented in Section VII.
improved Vedic multiplier architecture is used in the binary This section also discusses the circuit synthesis results and
squaring circuit. The circuit is further improved by using performance comparison for different families of FPGA.
parallel prefix adder. Parallel prefix adder provides the best
delay performance at the expense of area overhead. In this
The circuit synthesis is performed using Xilinx ISE 14.7.
work, the parallel prefix adders like Kogge-Stone adder, Finally, the conclusion is drawn in Section VIII.
Brent-Kung adder, Sklansky adder, Ladner-Fischer adder and
Han-Carlson adder are used. The circuit is designed in Verilog II. 2-BIT MULTIPLIER
HDL. The circuit synthesis has been performed in Xilinx ISE
14.7. Simulation has been performed for 4-bit and 8-bit de- Figure 1 shows the block diagram for a 2-bit binary multi-
signs. Performance comparison has been performed taking plier [1]. It uses 2 half-adder blocks. 2 bit inputs for the
into consideration several parameters measured on different multiplier are X = X1X0 and Y = Y1Y0, and 4 bit output is
FPGA families. An improved speed performance is observed in M.
this paper when compared with the previously reported cir-
cuits.
Keywords- Vedic multiplier, Vedic squarer, Parallel prefix
adder, Verilog

I. INTRODUCTION

Vedic mathematic technique is widely known and used to

improve the overall computational speed of various arithme-
tic operations. Several Vedic based multipliers and squaring
circuits [1]-[10] have been designed and published in litera- Figure 1: Block diagram for 2-bit binary multiplier
ture. This paper proposes a novel method for calculating the
square of binary numbers using an improved Vedic multi- III. 2-BIT SQUARER
plier circuit. The circuit is further improved by using paral-
lel prefix adder. Parallel prefix adder provides the best delay A 2 bit squarer can be designed using the multiplier in Sec-
performance at the expense of area overhead. In this work, tion I by providing the same number at both inputs, i.e. X =
the parallel prefix adders like Kogge-Stone adder, Brent- Y. The output of this 2-bit squarer is:
Kung adder, Sklansky adder, Ladner-Fischer adder and M[0] = X0.X0 = X0
Han-Carlson adder are used. The paper consists of the fol- M[1] (Output sum from half adder 1) = X1.X0 XOR X0.X1 =
lowing sections: Section II shows the 2-bit binary multiplier 0
circuit. 2-bit binary squaring circuit has been presented in The output carry of first half adder is forwarded as input to
Section III along with the modified design for 2-bit binary the next half adder.
squaring circuit. In Section IV, the 4 bit Vedic based multi- M[2] (Output sum from half adder 2) = X1.X1 XOR output
plier is presented [9]. Section V summarizes the various carry of half adder 1 = X1 XOR X1.X0
parallel prefix adders. Section VI presents the proposed 4- M[3] (Output carry from half adder 2) = X1.X1 AND output
bit Vedic squarer implemented using various adders for carry of half adder 1 = X1 AND X1.X0
performance comparison. The simulation results, synthesis The squarer is shown in Figure 2.

978-1-7281-5475-6/20/$31.00 ©2020 IEEE 970

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 2020 7th International Conference on Signal Processing and Integrated Networks (SPIN)

V. PARALLEL PREFIX ADDER

Parallel prefix adders [14-17] are a variant adder schemes

which provide the best delay performance at the expense of
large circuit implementation. This is achieved by processing
the sum and carry separately. In parallel prefix addition,
three stages are used to compute the output namely pre-
processing stage, carry generation stage and post processing
stage.
Figure 2: Block Diagram for 2-bit binary squarer • Stage 1: Pre Processing
o This stage provides group generate and group prop-
The above 2-bit squarer circuit can be further improved. agate signal for each input bits.
This can be achieved by reducing the design. Half adder in P = Ai XOR Bi
Figure 2 takes X1 and X1.X0 as inputs and generates the G = Ai AND Bi
following output: • Stage 2: Carry Generation
Sum (i.e. S[2]) = X1 XOR (X1.X0) = X1.(NOT X0) o This stage generates the carry using group generate
Carry (i.e. S[3]) = X1.X0 and group propagate signal obtained in Stage 1.
From these reduced expressions, we conclude that the half o Pi+1 = Pi AND Pi prev
adder can be reduced. The modified 2-bit binary squarer is o Gi+1 = (Pi AND Giprev) OR Gi
shown in Figure 3 below. o Ci+1 = Gi+1
• Stage 3: Post Processing
o This stage generates sum using carry generated in
stage 2 and the propagate signals.
o Si = Pi XOR Ci-1

Various parallel prefix adders can be designed by varying

the number of logic levels, logic gates, fan-out and the num-
ber of wiring between the levels.

Figure 3: Block Diagram for 2-bit modified binary squarer Figure 1 shows the black cell, gray cell and buffer involved
at different stages of prefix adder.
The modified 2 bit squarer has been used to design 4-bit and
8-bit squarer. The proposed topology can be used for de-
signing squarer with large number of bits.

IV. VEDIC-BASED 4-BIT MULTIPLICATION

The proposed Vedic based multiplier [9] has been used to

design the squarer proposed in this paper.
Figure 4 shows the block diagram of the Vedic based multi- Figure 5: Different modules in parallel prefix adders
plier [9-10]. The Vedic based multiplier takes two 4-bit
inputs A and B and provides an 8 bit output M. various Several parallel prefix adder schemes are available in open
adder circuits can be analyzed as discussed in [11-13]. literature. They are discussed in brief below.

(A) Brent Kung Adder: The Brent Kung adder scheme

uses 2-bit groups to compute the prefixes. They are further
used to compute 4-bit group prefixes, which are in turn then
used for the computation of 8-bit group prefixes. The pro-
cess is similarly carried on to further find the higher bit
prefixes. The output carry of a particular bit stage is ob-
tained using these prefixes.

To obtain the Sum bit of a particular stage, the output carry

is used along with the next stage Group Propagate signal.
Figure 2 below shows the structure of the Brent Kung PPA.

Figure 4: Block diagram for 4-bit Vedic multiplier

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 2020 7th International Conference on Signal Processing and Integrated Networks (SPIN)

Figure 6: Structure of Brent Kung Adder

Figure 9: Structure of Han Carlson Adder
(B) Sklansky Adder: The Sklansky adder reduces the delay
to log2N. Due to this, it is also called the divide-and- (E) Ladner Fischer Adder: Ladner Fischer adder uses the
conquer tree adder scheme. It computes the intermediate and best of Sklansky and Brent Kung adders. The scheme is
the large group prefixes simultaneously. Fanout is doubled similar to Sklansky but the prefixes are computed for the
at every stage. For wide adders, higher fan-outs mean poor odd bits. The scheme adds one more stage for the even bits.
performance. To improve the performance, we can limit the Figure.6 below shows the structure of the Ladner Fisher
fan-out and/or use buffer for the critical signals before using adder.
for the intermediate prefixes.

Figure 3 below shows the structure of the Sklansky PPA.

Figure 10: Structure of Ladner-Fisher Adder

VI. PROPOSED 4-BIT VEDIC SQUARER

Figure 7: Structure of the Sklansky Adder

(C) Kogge-Stone Adder: Koggestone adder is able to Building on the above techniques, an improved circuit for 4
achieve a fan-out of 2 at each stage as well as log2N stages. bit squarer based on Vedic mathematics has been proposed.
But, this also involves a cost. The scheme consists of several The steps involved in the calculation of the square are given
long wires between stages and also an increased number of below. A 4 bit number A is the input to the squarer.
PG cells. Although these do not affect the layout area, but
the number of gates increases. This results into a major
increase in power consumption. Despite the increased power
consumption, Kogge Stone scheme is widely used for de-
signing 32-bit and 64-bit high performance adders. Figure 4
below shows the structure of the Kogge Stone PPA.

The modified 2-bit squarer (discussed in Section III) is used

for computing (A3A2) x (A3A2) and (A1A0) x (A1A0). The 2-
bit multiplier (discussed in Section III) is used for compu-
ting (A3A2) x (A1A0). The outputs are as given below:
(A1A0) x (A1A0): I0
(A3A2) x (A1A0): I1
(A3A2) x (A3A2): I2

It can be observed that I1 is added twice. Therefore, the

input to the adder can be represented by shifting I1 left 1 bit.
Figure 8: Structure of Kogge Stone Adder Due to reduction of one operand, we can replace the CSA
with a normal 4-bit full adder in the middle stage. The in-
(D) Han-Carlson Adder: Han Carlson adder uses the best puts for the OR gate are I1[3] and Cout of the adder. The
of Kogge-Stone adder and Brent-Kung adder. The scheme output of OR gate acts as the control signal for the 2-bit IBO
applies Kogge-Stone tree method for the odd numbered bits. module. Figure 11 shows the schematic diagram of the pro-
One more atage is added for the even positions. Figure.5 posed 4-bit Vedic based squarer.
shows the structure of the Han Carlson PPA.

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 2020 7th International Conference on Signal Processing and Integrated Networks (SPIN)

Figure 14 shows the simulation waveforms for the proposed

8-bit Vedic based squarer. Signal p is the 16 bit output.
For 8-bit input m1 = 01100110, the output
p = 0010100010100100
For 8-bit input m1 = 11111111, the output
p = 1111111000000001

(a)

(b)
Figure 14: Simulation waveforms for the 8-bit squaring circuit using (a)
Ripple Carry Adder (RCA) and (b) Parallel Prefix Adder (PPA)

Figure 11: Block diagram for proposed 4-bit Vedic based squarer Synthesis has been performed on different Xilinx FPGA
families. Table 1 shows the performance parameters of the
The proposed scheme can be further used to design 8-bit proposed Vedic based squarer and the previously published
Vedic based squarer following the topology of 8 bit Vedic designs.
Multiplier. Figure 12 shows the schematic diagram of the
proposed 8-bit Vedic based squarer. TABLE 1. Performance comparison of proposed Vedic based squarer
Virtex-4: XC4VSX35
4 Bit 8 Bit
Scheme
Delay (ns) LUT Delay (ns) LUT
Ripple Carry Adder 4.993 6 10.701 61
Kogge Stone 4.993 6 11.129 74
Brent Kung 4.993 6 10.396 65
PPA Ladner Fischer 4.993 6 10.438 63
Han Carlson 4.993 6 10.436 62
Sklansky 4.993 6 10.434 64

Spartan-3: XC3S50
4 Bit 8 Bit
Scheme
Delay (ns) LUT Delay (ns) LUT
Ripple Carry Adder 7.931 6 20.239 61
Kogge Stone 7.862 6 20.810 75
Brent Kung 7.862 6 19.759 64
PPA Ladner Fischer 7.862 6 19.748 63
Figure 12: Block diagram for proposed 8-bit Vedic based squarer Han Carlson 7.862 6 19.676 62
Sklansky 7.862 6 19.701 64
VI. RESULTS AND DISCUSSION [4] 9.070 NR
[5] 17.30 23 NR
[6] NR 19.800 32
The synthesis and simulation results of the proposed 4-bit
and 8-bit Vedic based squarer using ModelSim, Xilinx ISE
and Synopsys Design Vision tool are presented in this sec- Spartan-6: XC6SLX150T
tion. 4 Bit 8 Bit
Scheme
Delay (ns) LUT Delay (ns) LUT
Figure 13 shows the simulation waveforms for the proposed Ripple Carry Adder 5.567 6 14.500 43
4-bit Vedic based squarer. Signal p is the 8 bit output. Kogge Stone 5.537 6 13.843 44
Brent Kung 5.537 6 14.393 40
For 4-bit input m1 = 0110, the output p = 00100100 PPA Ladner Fischer 5.537 6 13.795 38
For 4-bit input m1 = 1111, the output p = 11100001 Han Carlson 5.537 6 13.744 44
Sklansky 5.537 6 13.710 41

Virtex-4: XC4VLX15
(a) 4 Bit 8 Bit
Scheme
Delay (ns) LUT Delay (ns) LUT
Ripple Carry Adder 4.993 6 10.701 61
Kogge Stone 4.993 6 11.129 74
Brent Kung 4.993 6 10.396 65
(b) PPA Ladner Fischer 4.993 6 10.438 63
Figure 13: Simulation waveforms for the 4-bit squaring circuit using (a) Han Carlson 4.993 6 10.436 62
Ripple Carry Adder (RCA) and (b) Parallel Prefix Adder (PPA) Sklansky 4.993 6 10.434 64
[8] 4.990 6 14.260 35
NR: Not reported in corresponding reference

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 2020 7th International Conference on Signal Processing and Integrated Networks (SPIN)

TABLE 2. Area and owner consumption of proposed Vedic based squarer Applied Engineering Research, vol. 13, no. 6, pp. 4471-4474,
Area (nm2) Power (μW) 2018.
Scheme
4 Bit 8 Bit 4 Bit 8 Bit [6] P. Vidyashankari and B. Lokesha, “Design and
Ripple Carry 4.7057 28.5555 0.5741 4.6756 implementation of square and cube architectures using Vedic
Kogge Stone 4.6863 33.0265 0.5553 5.7989
sutras on FPGA,” International Journal of Emerging
Brent Kung 4.6863 21.7995 0.5553 2.8134
Technology in Computer Science & Electronics, vol. 14, no.
Ladner Fischer 4.6863 29.6378 0.5553 5.0101
Han Carlson 4.6863 30.1467 0.5553 5.1763 2, pp. 377-381, Apr. 2015.
Sklansky 4.6863 28.5555 0.5553 5.2018 [7] R. K. Barik, M. Pradhan, and R. Panda, “Time efficient
NR: Not reported in corresponding reference signed Vedic multiplier using redundant binary
representation,” The Journal of Engineering, vol. 2017, no. 3,
From Table 1, using Spartan-3 XC3S50, it is observed that pp. 60-68, 2017.
the proposed 4-bit Vedic based squarer exhibits reduced [8] P. S. Kasliwal, B. P. Patil, and D. K. Gautam, “Performance
delay by 13.32% and 54.55% as compared to the squarer in evaluation of squaring operation by Vedic mathematics,”
[4] and [5], respectively. LUT usage is also reduced by IETE Journal of Research, vol. 57, no. 1, pp. 39-41, Jan.-Feb.
2011.
73.91% compared to the squarer presented in [6].
[9] S. Akhter and S. Chaturvedi, “Modified binary multiplier
circuit based on Vedic mathematics,” in Proc. IEEE 2019
Using Virtex-4 XC4VLX15, it is observed that the proposed International Conference on Signal Processing and
8-bit Vedic based squarer exhibits reduced delay by 27.09% Integrated Networks, 2019, pp. 234-237.
as compared to the squarer in [8]. [10] S. Akhter and S. Chaturvedi, “HDL based implementation of
N×N bit-serial multiplier,” in Proc. IEEE 2014 International
From Table 1, Table 2 and the above performance compari- Conference on Signal Processing and Integrated Networks,
son, it can be concluded that Vedic based squarer proposed 2014, pp. 470-474.
in this paper is more efficient. Designs incorporating the [11] S. Akhter, V.K.Saini, J.Saini, "Analysis of Vedic Multiplier
parallel prefix adder provide further reduction in delay. But using Various Adder Topologies", in Proc. 4th International
this is at the cost of increased area and power as shown in Conference on Signal Processing and Integrated Networks
Table 3. Thus it can be used in computational applications SPIN , pp-173-176 March 2017.
requiring high-performance. [12] V. K. Saini, S.Akhter, and T.Chauhan, "Implementation, Test
Pattern Generation, and Comparative Analysis of Different
Adder Circuits," VLSI Design, vol. 2016, Article ID 1260879,
VII. CONCLUSION 2016.
[13] S.Akhter, S. Chaturvedi, and K.Pardhasardi, “CMOS
This paper proposes a novel method for calculating the Implementation of Efficient 16-Bit Square Root Carry-Select
square of binary numbers using an improved Vedic multi- Adder, “ in Proc. 2nd International Conference on Signal
plier circuit. The circuit is further improved by using paral- Processing and Integrated Networks (SPIN), pp. 891 – 896,
lel prefix adder. The various performance parameters ob- Feb 2015.
tained from synthesis indicate that the design proposed in [14] S. Daphni, K. S. Vijula Grace, “A review analysis of parallel
this paper is more efficient in terms of delay. Although prefix adders for better performance in VLSI applications,”
using parallel prefix adder increases area and power, but it IEEE International Conference on Circuits and Systems
(ICCS), pp. 103-106, 2017.
further reduces the delay. Hence, the final choice of design
[15] Aradhana Raju, Richi Patnaik, Ritto Kurian Babu, Purabi,
shall be on the basis of the applications requirements. The
“Parallel prefix adders - A comparative study for fastest
scheme can be easily extended and applied to larger input response,” International Conference on Communication and
data size and various applications where adder or multiplier Electronics Systems (ICCES), Coimbatore, 2016.
is an integral part [18]. [16] Gayathri. G, Raju S.S, Suresh. S, “Parallel Prefix Speculative
Han Carlson Adder,” IOSR Journal of Electronics and
REFERENCES Communication Engineering (IOSRJECE), ISSN 2278-8735,
vol. 11, issue 3, pp. 38 -43, May 2016.
[1] B. D. Kumar and M. Bharathi, “A high speed and efficient [17] S. Baba Fariddin, E. Vargil Vijay, “Design of Efficient 16-Bit
design for binary number squaring using Dwandwa yoga,” Parallel Prefix Ladner-Fischer Adder”, International Journal
International Journal of Advanced Research in Computer of Computer Applications, vol. 79, issue 16, pp. 11-14,
Engineering & Technology, vol. 1, no. 4, pp. 476-479, Jun. October 2013.
2012. [18] A. Jain, S. Bansal, S. Khan, S. Akhter and S. Chaturvedi,
[2] S. Akhter, “VHDL implementation of fast N×N multiplier “Implementation of an efficient N×N multiplier based on
based on Vedic mathematics,” in Proc. 18th European Vedic mathematics and Booth-Wallace tree multiplier,” in
Conference on Circuit Theory and Design, 2007, pp. 472-475. Proc. International Conference on Power Electronics,
[3] H. Goyal and S. Akhter, “VHDL implementation of fast Control and Automation (ICPECA), 2019, pp. 1-5.
multiplier based on Vedic mathematic using modified square
root carry select adder,” International Journal of Computer
Applications, vol. 127, no. 2, pp. 24-27, Oct. 2015.
[4] R. Jaikumar, M. Karpagam, and L. Raju, “A novel approach
to implement high speed squaring circuit using ancient Vedic
mathematics techniques,” International Journal of Applied
Engineering Research, vol. 10, no. 67, pp. 1-6, 2015.
[5] A. Deepa and C. N. Marimuthu, “High speed VLSI
architecture for squaring binary numbers using Yavadunam
sutra and bit reduction technique,” International Journal of

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