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Cache Memory Organization

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KARTHIKA THEVAR
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69 views4 pages

Cache Memory Organization

Uploaded by

KARTHIKA THEVAR
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Cache memory Organization

21 March 2024 09:49

PENTIUM – CACHE MEMORY ORGANISATION


 Features of Pentium Cache
 The Pentium processor has a separate code and data cache each of 8k bytes.
 The cache line size is 32-bytes.
 Since the Pentium processor has data bus of 8 bytes (64-bits), it requires a burst of four consecutive
transfers to fill the cache line of 32 bytes.
 Each cache is organized as two-way set-associative.
 The data cache can be configured as a write-through or a write-back cache on a line-byline basis and it
follows the MESI protocol.
 The code cache does not require a write policy, as it is a read-only cache.
 Each cache has a dedicated translation look aside buffer (TLB) to translate linear addresses to physical
addresses.
 The data cache tags are triple ported to support two data transfers and a snoop cycle in the same clock.
 The code cache tags are triple ported to support snooping and split line access simultaneously.
 Individual pages in the main memory can be configured as cacheable or non-cacheable by software or
hardware.
 The cache can be enabled or disabled by software or hardware.

 Code Cache
 The code cache is 8 KB read only cache and is organized as a 2-way set associative cache. The two
ways are called way zero and way one. Each cache line is 32 bytes.
 Total size of cache = 8 KB.
 Size of each way = 4 KB.
 Cache line size = 32 bytes.
 Total number of lines in one way = 128
 There is a separate 128 entry directory associated with each cache way. The 4Gb memory space of the
processor is mapped into the 4KB cache way, i.e. the 4 GB memory space is assumed to be divided into
pages each of size 4 KB.
 Hence total number of pages = 1 M or 220
 Thus, each cache directory entry stores this 20 bit tag (page no) address A [31-12].
 The entry also consists of one state bit (to indicate S/I) and a parity bit P.
 The parity bit is used to detect errors when reading each entry.
 The cache directories are triple ported to allow three simultaneous directory accesses.
 Two of the ports support the split line access capability, while the third port is used for snooping.
 Each cache line holds four quad words and a parity bit for each quad word.
 When the prefetcher issues an instruction request, the code cache is checked to see if a copy is
available.
 Assuming a cache miss, a cache line-fill request is made to the bus unit, i.e. a cache line is brought in
from L2 cache/ memory.
 Main Memory Address (32-bits) Interpretation

Page Number (Tag) Line Number (Index) Location within the line (byte)
20 bits 7 bits 5 bits
 Code Cache Directory Entry

Parity Tag (page Number – Address[31-12]) S/I

 Code Cache line (32-bytes)

P3 QW3 P2 QW2 P1 QW1 P0 QW0

 Split-Line Access(Optional)
 In a CISC Processor like Pentium , instructions are of variable length
 In the Pentium Processor the smallest instruction is one byte while the maximum length is 15 bytes
 A code cache always results in a 32 byte cache line fill, if it’s a cacheable address
 Multi byte instructions may span two sequential lines stored in the code cache
 When the prefetcher determines that the instruction is straddled across two lines, it would have to
perform two sequential cache accesses, which would hamper performance
 For this reason the Pentium processor incorporate a split line access which allows the upper half of
one line and lower half of next line to be accessed in one cycle

When a split line access is made the byte must be rotated so that they are in proper order for the split
access to work efficiently , instruction boundaries within the cache line need to be defined.
When an instruction is decoded for the first time the length of instruction is fed back to the cache.
Each code cache entry marks instruction boundries within the line , so that if necessary split line
accesses can be performed.

 The Data Cache


The data cache is 8KB and is organized as a 2-way set associative cache. The two ways are
called way 0 and way 1. Each cache line is 32 bytes.
Total size of cache = 8 KB
Size of each way = 4 KB
Cache line size = 32 bytes.
Number of lines = 128.
1. Each 4 KB cache way is divided into 128 lines. There are thus correspondingly 128 entries in each tag
directory.
2. Each directory stores a 20-bit tag (page) address A [31-12]. The entry also consists of two state bits (to
indicate one of four states M-E-S or I) and a parity bit P.
3. Parity is generated for each byte within a data cache line.
4. When a byte of information is read from the data cache, the parity is checked. On detecting a parity
error, an internal parity error is signaled to external logic through the IERR# (Internal Error) output.
5. One processor also generates a special shutdown bus cycle and stops execution.
6. The data cache itself is single ported, but the cache directories are triple ported to allow access form
both pipelines (U and V) and allow an external snoop simultaneously.
 Main Memory Address (32-bits) Interpretatione

Page Number (Tag) Line Number (Index) Bank Select XX (Don't care)
20 bits 7 bits 3 bits 2 bits

 Data Cache Directory Entry

Parity Tag (page Number – Address[31-12]) MESI


2 bits
00-Invalid
01-Exclusive
10-Modified
11-Shared

 DATA Cache line (32-Bytes)

P31 Byte31 … … P1 Byte 1 P0 Byte 0

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