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Round Robin Arbiter

The ultimate goat

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19 views

Round Robin Arbiter

The ultimate goat

Uploaded by

vermamaggi
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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Birla Institute of

Technology & Science,


Pilani, Hyderabad Campus

Question-2: Any one Arbitration Algorithm – Round


Robin Arbitration

ID No. Name
2023H1400128H V. Sahat Monal
Verilog Design Code for Round Robin Arbiter
module arbiter#(parameter N = 4) (clk,rst,req,gnt3);
// PORT DECLARATION
input clk; //CLOCK
input rst; //RESET
input [N-1:0] req; //REQUEST SIGNALS
output [N-1:0] gnt3; //GRANT SIGNALS

//INTERNAL REGISTERS
wire [$clog2(N)-1:0] gnt;
wire comreq;
wire beg; // BEGIN SIGNAL
wire [$clog2(N)-1:0] llgnt; // LATCHED ENCODED GRANT
wire lcomreq ; // BUS STATUS
reg [N-1:0] lgnt; // LATCHED GRANTS
reg mask_enable ;
reg lmask0;
reg lmask1 ;
reg ledge ;

//--//

always @ (posedge clk)

if (rst) //if reset is true


begin
lgnt[N-1:0] <= 0;
end

else
begin
lgnt[0] <=(~lcomreq & ~lmask1 & ~lmask0 & ~req[3] & ~req[2] & ~req[1] &
req[0])
| (~lcomreq & ~lmask1 & lmask0 & ~req[3] & ~req[2] & req[0])
| (~lcomreq & lmask1 & ~lmask0 & ~req[3] & req[0])
| (~lcomreq & lmask1 & lmask0 & req[0] )
| ( lcomreq & lgnt[0]);

lgnt[1] <=(~lcomreq & ~lmask1 & ~lmask0 & req[1])


| (~lcomreq & ~lmask1 & lmask0 & ~req[3] & ~req[2] & req[1] & ~req[0])
| (~lcomreq & lmask1 & ~lmask0 & ~req[3] & req[1] & ~req[0])
| (~lcomreq & lmask1 & lmask0 & req[1] & ~req[0])
| ( lcomreq & lgnt[1]);

lgnt[2] <=(~lcomreq & ~lmask1 & ~lmask0 & req[2] & ~req[1])
| (~lcomreq & ~lmask1 & lmask0 & req[2])
| (~lcomreq & lmask1 & ~lmask0 & ~req[3] & req[2] & ~req[1] &
~req[0])
| (~lcomreq & lmask1 & lmask0 & req[2] & ~req[1] & ~req[0])
| ( lcomreq & lgnt[2]);

lgnt[3] <=(~lcomreq & ~lmask1 & ~lmask0 & req[3] & ~req[2] & ~req[1])
| (~lcomreq & ~lmask1 & lmask0 & req[3] & ~req[2])
| (~lcomreq & lmask1 & ~lmask0 & req[3])
| (~lcomreq & lmask1 & lmask0 & req[3] & ~req[2] & ~req[1] & ~req[0])
| ( lcomreq & lgnt[3]);
end

//BEGIN SIGNAL

assign beg = (req[3] | req[2] | req[1] | req[0]) & ~lcomreq;

// comreq logic (BUS STATUS)

assign lcomreq = ( req[3] & lgnt[3] )


| ( req[2] & lgnt[2] )
| ( req[1] & lgnt[1] )
| ( req[0] & lgnt[0] );

// Encoder logic

assign llgnt = {(lgnt[3] | lgnt[2]),(lgnt[3] | lgnt[1])};

// lmask register.

always @ (posedge clk )


if( rst )
begin
lmask1 <= 0;
lmask0 <= 0;
end
else if(mask_enable)
begin
lmask1 <= llgnt[1];
lmask0 <= llgnt[0];
end
else
begin
lmask1 <= lmask1;
lmask0 <= lmask0;
end
assign comreq = lcomreq;
assign gnt = llgnt;

// Drive the outputs

assign gnt3 = lgnt;

endmodule

Verilog Test Bench for Round Robin Arbiter


module top#(parameter N = 4) ();
reg clk;
reg rst;
reg [N-1 : 0] req;
wire [N-1 : 0] gnt3;
// Clock generator
always #1 clk = ~clk;

initial begin
$dumpfile ("arbiter.vcd");
$dumpvars();
clk = 0;
rst = 1;
req = 4'b0;
#10 rst = 0;
repeat (1) @ (posedge clk);
req[0] <= 1;
repeat (1) @ (posedge clk);
req[0] <= 0;
repeat (1) @ (posedge clk);
req[0] <= 1;
req[1] <= 1;
repeat (1) @ (posedge clk);
req[2] <= 1;
req[1] <= 0;
repeat (1) @ (posedge clk);
req[3] <= 1;
req[2] <= 0;
repeat (1) @ (posedge clk);
req[3] <= 0;
repeat (1) @ (posedge clk);
req[0] <= 0;
repeat (1) @ (posedge clk)
#10 $finish;
end
// Connect the DUT
arbiter U (
clk,
rst,
req,
gnt3
);

endmodule

Verilog Test Bench Output for Round Robin Arbiter


in Vivado

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