Reconfigurable Computing

CS G553

Dr. A. Amalin Prince

BITS - Pilani K K Birla Goa Campus
Department of Electrical and Electronics Engineering

‹#›
Lecture – 13,14
Reconfigurable Computing Device: Circuit Design of FPGA
fabrics, Architecture of FPGA Fabrics

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Circuit Design of FPGAs

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Topics

 Circuit design for FPGAs:

o Logic elements.
o Interconnect.

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LEs vs. Logic Gates

 LE is more complex than standard CMOS gate

o CMOS – one function
o LE – number of functions
 Antifuse-based FPGA’s program their logic elements by
connecting various signals, either constants or variables to
the input of the logic elements

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Multiplexers as Logic Elements

Q
1

CLR
A

01

CLR
0
D (AB)’
latch
A^B
D
A
CLR

01
0B
CLK
0

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Using Antifuses

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Static CMOS Gate vs. LUT

 Number of transistors:
o NAND/NOR gate has 2n transistors.
o 4-input LUT has 128 transistors in SRAM, 96 in multiplexer.
 Delay:
o 4-input NAND gate has 9t delay.
o SRAM decoding has 21t delay.
 Power:
o Static gate’s power depends on activity.
o SRAM always burns power.

Because the logic element is so complex, its design requires

careful attention to circuit characteristics

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Lookup Table Circuitry

 Demultiplexer or multiplexer?
adrs
adrs

LUT LUT

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Traditional RAM/ROM

 Cell drives long bit line:

Bit line
adrs

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Lookup Memory

 Multiplexer presents smaller load to memory cells.

o Allows smaller memory cells.

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Multiplexer Styles

Should that multiplexer be made of static gates or pass transistor ?

static gates
pass transistors
This choice depends on the size of the lookup table
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Multiplexer Design

 Pass transistor multiplexer uses fewer transistors than fully

complementary gates.
 Static gates based implementation gives better noise
immunity

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Static Gate Four-Input Mux

 Delay through n-input

NAND is (n+2)/3.
 lg b + 1 inputs at first level,
so delay is (lg b + 3)/3.
 Delay at second level is
(b+2)/3.
 Delay grows as b lg b.

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Tree-based four-input mux

 Delay proportional to
square of path length.
 Delay grows as lg b2.

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Delay Through an RC Transmission Line

 An RC Transmission line models a wire as infinitesimal RC

sections
o Each representing a differential resistance and capacitance.

o The transmission line’s voltage response is modeled by

1 d 2V dV
= c
r dx 2 dt

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Delay Through an RC Transmission Line

 Elmore Delay
o Elmore defined the delay through a linear network as the first
moment of the impulse response of the network


 E =  tVout (t )dt
0

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Delay Through an RC Transmission Line

 Elmore Delay
o Elmore delay can be computed by taking the sum of RC products,
where each resistance is multiplied by the sum of all the
downstream capacitors

n
1
 E =  r (n − i )c = rc  n(n − 1)
i =1 2

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Pass-Transistor-Based Four-Input Mux

 Must include decode logic

in total delay.

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Transmission Gates based MUX

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LE Output Drivers

 Must drive load:

o Wire
o Destination LE
 Different types of wiring present different loads.

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Avoiding Programming Hazards

 Want to disable connections to routing channel

before programming.

From LE

config
progb
Routing channel

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Interconnect circuits

 Why so many types of

interconnect?
o Provide a choice of delay
alternatives.
o FPGA has
• Short wires
• General-purpose wires
• Global interconnects
• Specialized clock distribution
network Short wire has almost equal delay of a Gate
 Sources of delay: LE slower than Gates, interconnect gives some
compensation
o Wires.
o Programming points.

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Styles of Programmable Interconnection
Point
Researchers concluded that most of the area in an SRAM-based FPGA is consumed
by the routing switches, so we must carefully design the programmable interconnect
to make best use of the available area

pass transistor Three-state

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Pass Transistor Programmable Interconnect
Point
 Small area.
 Resistive switch.
 Delay grows as the square
of the number of switches.

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Three-state Programmable Interconnection
Point
 Larger area.
 Regenerative driver.

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Switch Area * Wire Delay vs. Pass Transistor
Width (Betz & Rose)

© 1999 IEEE

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Switch Area * Wire Delay vs. Buffer Size
(Betz & Rose)

© 1999 IEEE

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Wire Delay vs. Switch Sizes (Chandra and
Schmit)

 Delay vs. switch

size for various
driver sizes.
 U-shaped curve:
o Resistance initially
decreases.
o Increased
capacitance
eventually
dominates.

© 2002 IEEE
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Clock Drivers

Clock driver tree:

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Clock Nets

 Must drive all LEs.

 Design parameters:
o number of fanouts
o load per fanout
o wiring tree capacitance
 Determine optimal buffer sizes.

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H tree

 Regular layout
structure.
o Recursive.

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Architecture of FPGA Fabrics

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Topics

 Architecture of FPGA
o Logic elements
o Interconnect
o Pins

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Architectural Issues
 How many logic elements in the FPGA?
 LE structure:
o What functions?
o How many inputs?
o Dedicated logic?
 What types of interconnect?
o How much of each type?
 How long should interconnect segments be?
 How should we vary interconnect?
o Uniform or non-uniform over chip?

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FPGA Architecture Evaluation Methodology

FPGA Logic
fabric benchmarks
architecture

Place +
route

Area and
performance
evaluation

metrics
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Evaluation Metrics

 Structural
o Size of the logic element
o Size of interconnect
 Mapping-related
o Logic utilization
o Interconnect utilization
o Delay

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Logic Element Parameters

 How many inputs?

o Too few inputs---more overhead per LE
o Too many inputs---wasted capacity when mapping logic to LEs
 Depends on circuit design of LE and characteristics of logic.
 Typical choice: 4-inputs.

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Styles of FPGA Interconnect

 Local
 Intermediate
 Global
o clock
o signal

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Interconnect Paths

channel
LE

SW channel

LE channel

channel SW

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Pinout

 How many pins?

o Limited by technology.
o Too much logic, not enough
pins means we can’t get
signals off-chip.
o Too many pins means
logic/pins won’t be efficiently
utilized.

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Rent’s Rule

 Developed by E. F. Rent (IBM) in 1960.

o Experimentally derived from sample designs.
 Number of pins vs. number of components is a line on a
log-log plot:
o Rent’s Rule N p = K p N gb

 Parameters may vary based on technology:

o Rent measured b = 0.6, Kp = 2.5.
o Modern microprocessor has b = 0.455, Kp = 0.82.

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FPGAs and Pins

 Chip capacity is growing somewhat faster than package

pinout.
 Harder to use logic in a multi-FPGA design.
o Must try to fit a large function with a small interface into the FPGA.

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The End

 Questions ?

 Thank you for your attention

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