2011 International Coriference on Electronics and Optoelectronics (ICEOE 2011)

Asynchronous FIFO Implementation Using FPGA

Yanjun Zhang!,2,Chunli Yi! and Jinqi Wang! Jinye Zhang

1 Key Laboratory of Instrumentation Science & Dynamic Jin xi industrial group technology center
Measurement(North University of China) Taiyuan, Shanxi Province, China
2 Ministry of Education and Science Technology on [email protected]
Electronic Test & Measurement Laboratory
North University of China
Taiyuan, Shanxi Province, China
[email protected], yichunli [email protected]
wangjinqi�[email protected]

Abstract-We introduce a design of asynchronous FIFO on and read address generator, Gray code counter and flag
FPGA for the purpose of high-speed, steady data transmission generation unit.
between asynchronous clock domains. In the design , the Write Wr_dat Full
memory address was organized into one ring list , using gray •

code as its address code, making uses of double jump

technology to finish two asynchronous clock regions between
address signals transmission, avoiding the meta-stability well.
Write clock
Keywords-FPGA; asynchronous FIFO; grey code; double region
Double jump to
jump technology synchronize

1. INTRODUCTION

With the development of integrated circuit technology,

the scale of circuit design is increasing rapidly and the
system clock is also used more and more often. Including the
handling of many asynchronous clocks, they will cause
conflict quasi-steady signals, which may lead to the design
function of the system failure. Therefore, treatment of
asynchronous clock has been difficulties in circuit ,
Rd
design[1l.There are many solutions to this problem, such as
Empty _ dal Read
Figure 1. Simplified asynchronous FIFO
the phase control method, double jump technology. However,
these methods are low efficiency, the best approach is to use A. Dualyort RAM
asynchronous clock asynchronous FIFO, which passes
Xilinx's Virtex and SpartanII series FPGA chip are
signals between the clock regions is more flexible and
integrated with "Select + Block RAM (block RAM), it can
commonly used in the standard bus interface to transfer data
be configured into a real dual-port RAM. Therefore, select
between the memory read and write burst. In this paper, we
the block RAMB S4 S4 as the storage body, the dual-port
introduce a high-speed asynchronous FIFO method within
RAM's two ports A:- B completely independent read and
the FPGA, according to the excellent control logic of FPGA,
write clock frequency up to IOOMHz, is not only fast and
and low power consumption, high reliability,
simple design. in the design, configure a port A write port,
reconfigurability, short development cycle and lower
another port B configured as a read port, and then block the
development costs and so on[2l. The method is suitable for
RAMB S8 S8 connecting pin can be configured as a storage
high frequency data acquisition system, such as video image
capacitY of512-byte in the FIFO, the FPGA to control the
acquisition pretreatment systems.
read and write its address and clock signals.

II. THE DESIGN OF ASYNCHRONOUS FIFO

We construct the FIFO in the FPGA using dual-port

RAM. In the design, the difficult is to generate the empty
and full flag, because the flag of input control is due to
output, similarly the flag of output control is usually
generated by input. Therefore, both the write address and
read address must be re-synchronized when transfer to
another area. Below is a simplified diagram of asynchronous
FIFO. Including the following modules: dual-port ram, write

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 2011 International Coriference on Electronics and Optoelectronics (ICEOE 2011)

read, write operation, read, write, will jump to address 0, this

work ways are used to describe the structure of the unsigned
critical state is very suitable.
C. Gray Counter
FPGA chip is the input and output modules (Input /
Output Block, lOB), can be configured module
(Configurable Logic Block, CLB) and programmable
connection resources (Programmable Interconnect Array,
PIA) 3 modules to form. PIA is located between the chip's
logic blocks, underwent programmed into a network
connection, internal logic for the connection between the
chip and transfer information between them. As input to the
logical block address the alignment may be different, so each
bit of the address change counter can not be completely
synchronized, the address data may be in a period of
instability. If the asynchronous clock is just the address in
the address instability in the comparison when sampling,
Figure 2. The structure of FIFO
then it may output the wrong result. Therefore, the design
B. State Logic Module refers to Gray code, Gray code is only one among the
adjacent count encoding changes, the address counter with a
State logic module task is to provide FIFO empty and full
Gray code can be done to eliminate fuzziness in the circuit,
flag signal, this signal tells the external circuit FIFO has
so as to solve the above problems, and its implementation
reached a critical condition: if there is full signal, then the
block diagram is shown below.
FIFO write operation for the critical state, that there is no
Empty flag
space to store more data; if there is an empty signal, the
FIFO read operation for the critical state that no more data
FIFO can be read. So empty, FIFO full signal is a very Gray

important role to play, read and write it in order to achieve

counter

their own independent operation and management of

obstructive data storage. We can list the memory organized
into a ring, shown in Figure 3, for the empty or full of signs
can be read, write, to get the relative position of the address. Gray
- -
counter

Write addres s"'-----!'--_ Full flag

Read addres'g- ----t'----

-- i-__-=+_----l Figure 4. Conversion fIgure

I\ Gray code can be achieved with a binary counter, which

\
counts the clock the clock with the same binary, Gray code
Ring read address counter with a read clock CLK�Rd, write the
Form Downto address of the Gray code used to write the clock CLK�Wr;
address data input binary data of two adjacent Duanyou bit different
or produce: Dgi Db (i) XOR Db (i + I). Here "Dg" said
=

Gray code, "Db" said binary code, i on behalf of the counter

I02� digits. Read, write address generator and the Gray code
transformation, shift, respectively, by empty and full flag
control. When generating an empty flag to prohibit the read
address generator and Gray code conversion, the shift
operation; Similarly, when the full flag is generated to
prohibit write address generator and Gray code conversion,
Figure 3. Ring address the shift operation.
System reset, read, write addresses are 0, which is FIFO D. Synchronization Designs
empty status, not allowed to read. To the F IFO reading and In Figure 1, the use of write address and read address
writing data in the process, read, write, change of address generating empty and full flag, the address must be passed to
was increasing, if the write address and read address another clock in the region, but also to ensure that the
difference is greater than I or more to be read until FIFO address of the synchronization. During a number of
empty so far; the same token, if you write address and read addresses in the re-synchronization problems may occur,
address difference is greater than 1 or more to write, until the some other bits may be delayed a bit clock cycle, depending
FIFO is full. Because memory is organized into a ring form, on the propagation characteristics of each respective lead. In
so when writing the address or read address 1023, the next other words, due to the asynchronous nature of the two clock

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 2011 International Coriference on Electronics and Optoelectronics (ICEOE 2011)

regions are likely to sample some of the first rising edge of Practice has proved that with this design of asynchronous F
the clock is captured, the other may be the next rising clock IFO high speed, small size, empty full status flags and
is captured, depending on whether the data to the first reliability.
flip-flop before the arrival of the clock edge, After sufficient
setup time and hold time. We use technology to complete the ACKNOWLEDGMENT
double jump between the regions address the two The research was supported by the National Basic
asynchronous clock signal transmission, and its schematic Research Program of China (973 Program) under the grant
diagram is shown below. of N0.2010CB334703, Additionally, the research was also
Output address after supported by National Natural Science Foundation of China
SET SET
Input address synchronization under grant of NO.51075375.
D Q D Q

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