1. An OR gate has 4 inputs. One input is high and the other three are low.

The output

A. is low
B. is high
C. is alternately high and low
D. may be high or low depending on relative magnitude of inputs

2. Both OR and AND gates can have only two inputs.

A. True

B. False

2. A device which converts BCD to seven segment is called

A. encoder
B. decoder
C. multiplexer
D. none of these

4. A decade counter skips

A. binary states 1000 to 1111

B. binary states 0000 to 0011

C. binary states 1010 to 1111

D. binary states 1111 to higher

5. A ring counter with 5 flip flops will have

A. 5 states

B. 10 states

C. 32 states

D. infinite states

6. For the gate in the given figure the output will be

 A. 0

B. 1

C. A

D. A’

7. The basic storage element in a digital system is

A. flip flop

B. counter

C. multiplexer

D. encoder

8. A full adder can be made out of

A. two half adders

B. two half adders and a OR gate

C. two half adders and a NOT gate

D. three half adders

9. Which device has one input and many outputs?

A. Multiplexer

B. Demultiplexer

C. Decoder

D. Encoder

10. A carry look ahead adder is frequently used for addition because
 A. it costs less

B. it is faster

C. it is more accurate

D. is uses fewer gates

11. 7BF16 = __________ 2

A. 0111 1011 1110

B. 0111 1011 1111

C. 0111 1011 0111

D. 0111 1011 0011

12. A three state switch has three outputs. These are

A. low, low and high

B. low, high, high

C. low. floating, low

D. low, high, floating

13. Any number with an exponent of zero is equal to:

A. zero

B. one

C. that number

D. ten

14. What is the meaning of RAM, and what is its primary role?

A. Readily Available Memory; it is the first level of memory used by the computer in all of its
operations.

B. Random Access Memory; it is memory that can be reached by any sub- system within a
computer, and at any time.

C. Random Access Memory; it is the memory used for short-term temporary data storage within
the computer.
 D. Resettable Automatic Memory; it is memory that can be used and then automatically reset,
or cleared, after being read from or written to.

15. The condition occurring when two or more devices try to write data to a bus simultaneously is
called ________.

A. address decoding

B. bus contention

C. bus collisions

D. address multiplexing

16. How is a J-K flip-flop made to toggle?

A. J = 0, K = 0

B. J = 1, K = 0

C. J = 0, K = 1

D. J = 1, K = 1

17. How many flip-flops are required to produce a divide-by-128 device?

A. 1

B. 4

C. 6

D. 7

18. A 64-bit word consists of ________.

A. 4 bytes

B. 8 bytes

C. 10 bytes

D. 12 bytes

19. One hex digit is sometimes referred to as :

A. byte

B. nibble
 C. grouping

D. instruction

20. Which of the following is the most widely used alphanumeric code for computer input and
output?

A. Gray

B. ASCII

C. Parity

D. EBCDIC

21. How many flip-flops are required to make a MOD-32 binary counter?

A. 3

B. 4

C. 5

D. 6

22. How many data select lines are required for selecting eight inputs?

A. 1

B. 2

C. 3

D. 4

23. The devices that provide the means for a computer to communicate with the user or other
computers are referred to as:

A. CPU

B. ALU

C. I/O

D. none of the above

24. The software used to drive microprocessor-based systems is called:

A. assembly language
 B. firmware

C. machine language code

D. BASIC interpreter instructions

25. Single-bit indicators that may be set or cleared to show the results of logical or arithmetic
operations are the:

A. flags

B. registers

C. monitors

D. decisions

26. The technique of assigning a memory address to each I/O device in the computer system is called:

A. memory-mapped I/O

B. ported I/O

C. dedicated I/O

D. wired I/O

27. The register in the 8085A that is used to keep track of the memory address of the next op-code to
be run in the program is the:

A. stack pointer

B. program counter

C. instruction pointer

D. accumulator

28. Which of the following oscillators is suitable for frequencies in the range of mega hertz?

A. RC phase shift

B. Wien bridge

C. Hartley

D. Both (a) and (c)

29. In figure v1 = 8 V and v2 = 4 V. Which diode will conduct?

 A. D2 only

B. D1 only

C. Both D1 and D2

D. Neither D1 nor D2

30. An RC coupled amplifier has an open loop gain of 200 and a lower cutoff frequency of 50 Hz. If
negative feedback with β = 0.1 is used, the lower cut off frequency will be

A. about 50 Hz

B. about 5 Hz

C. about 2.38 Hz

D. about 70.5 Hz

31. In a BJT circuit a pnp transistor is replaced by npn transistor. To analyse the new circuit

A. all calculations done earlier have to be repeated

B. replace all calculated voltages by reverse values

C. replace all calculated currents by reverse values

D. replace all calculated voltages and currents by reverse values

32. The input impedance of op-amp circuit of figure is

 A. 120 k ohm

B. 110 k ohm

C. Infinity

D. 10 k ohm

33. Bootstrap principle is concerned with

A. darling connection

B. multistage amplifier

C. current controlled current source

D. none of the above ]

34. A source follower using FET usually has a voltage gain which is

A. greater than +100

B. slightly less than unity but positive

C. exactly unit but negative

D. about -10

35. To obtain very high input and output impedances in a feedback amplifier ,the topology mostly
used in

A. voltage-series

B. current-series
 C. voltage-shunt

D. current-shunt

36. In differential amplifier ,CMRR can be improved by using an increased

A. collector resistance

B. emitter resistance

C. power supply voltage

D. source resistance

37. In a CE amplifier the input impedance is equal to the ratio of

A. ac base voltage to ac base current

B. ac base voltage to ac emitter current

C. ac emitter voltage to ac collector current

D. ac collector voltage to ac collector current

38. For a system to work, as oscillator the total phase shift of the loop gain must be equal to

A. 90°

B. 45°

C. 270°

D. 360°

39. An amplifier has a large ac input signal. The clipping occurs on both the peaks. The output voltage
will be nearly a

A. sine wave

B. square wave

C. triangular wave

D. (a) or (c)

40. Negative feedback reduces noise originating at the amplifier input.

A. True

B. False
41. Assertion (A): CE amplifier is the most widely used BJT amplifier

Reason (R): CE amplifier has zero phase difference between input and output

A. Both A and R are correct and R is correct explanation for A

B. Both A and R are correct but R is not correct explanation for A

C. A is correct R is wrong

D. A is wrong R is correct

42. The self bias provides

A. stable Q point

B. large voltage gain

C. high input impedance

D. high base current

43. Consider the following statements : A clamper circuit

1. adds or subtracts a dc voltage to a waveform

2. does not change the waveform

3.amplifiers the waveform

Which are correct?

A. 1, 2

B. 1, 3

C. 1, 2, 3

D. 2, 3

44. A forward voltage of 9 V is applied to a diode in series with a 1 kΩ load resistor. The voltage across
load resistor is zero. It indicates that

A. diode is short circuited

B. diode is open circuited

C. resistor is open circuited

D. diode is either short circuited or open circuited

45. Which power amplifier can deliver maximum load power?

A. Class A

B. Class AB

C. Class B

D. Class C

46. In class C operation of an amplifier circuit, the collector current exists for

A. 360° of input wave

B. 180° of input wave

C. more than 180° of input wave

D. less than 180° of input wave

47. The quiescent collector current IC, and collector to emitter voltage VCE in a CE connection are the
values when

A. ac signal is zero

B. ac signal is low

C. ac signal is negative

D. either (a) or (b)

48. In the op-amp circuit of figure, V0 =

A. Vi

B. 3 Vi
 C. 5 Vi

D. 0.5 Vi

49. A full adder can be implemented with half-adders and OR gates. A 4-bit parallel full adder
without any initial carry requries

A. 8 half-adders, 4-OR gates

B. 8 half-adders, 3-OR gates

C. 7 half-adders, 4-OR gates

D. 7 half-adders, 3-OR gates

50. Meta stability in D-Flip Flop occurs when

A. Set up time of input data is not met

B. Clock period is too large

C. Set and reset are active simultaneously

D. D and Q pins are shorted