H

High Speed CMOS

Optocouplers
Technical Data
HCPL-7100
HCPL-7101

Features Description compatible and is controlled by

• 1 µm CMOS IC Technology The HCPL-7100/7101 optocoup- the output enable pin, VOE.
• Compatibility with All +5 V ler combines the latest CMOS IC
The HCPL-7100/7101 consumes
CMOS and TTL Logic technology, a new high-speed
very little power, due to the
Families high-efficiency AlGaAs LED, and
CMOS IC technology and the light
• No External Components an optimized light coupling system
coupling system. The entire
Required for Logic Interface to achieve outstanding perfor- optocoupler typically uses only 10
• High Speed: 15 MBd mance with very low power mA of supply current, including
(HCPL-7100) and 50 MBd consumption. It requires only two the LED current.
(HCPL-7101) Guaranteed bypass capacitors for complete
• Low Power Consumption CMOS/TTL compatibility. World-wide safety approval and
• Safety Approvals 3750 Vac/1 minute dielectric with-
Basic building blocks of the stand is achieved with our
UL 1577 (3750 Vac/1 Min)
HCPL-7100/7101 are a CMOS patented “light-pipe” optocoupler
VDE 0884 (VIORM = 848
LED driver IC, an AlGaAs LED, packaging technology.
V peak)
CSA and a CMOS detector IC. A CMOS
or TTL logic input signal controls The HCPL-7100/7101 provides he
• 3-State Output user with an easy-to-use CMOS or
the LED driver IC which supplies
• 3750 Vac/1 Minute Dielectric current to the LED. The detector TTL compatible optocoupler
Withstand ideally suited for a variety of
IC incorporates an integrated
• High Common Mode photodiode, a high-speed trans- applications where high speed
Transient Immunity impedance amplifier and a voltage and low power consumption are
comparator with hysteresis. The desired.
Applications 3-state output is CMOS and TTL
• Multiplexed Data
Transmission
Schematic
• Computer-Peripheral
Interface
• Microprocessor System TRUTH TABLE
Interface (POSITIVE LOGIC)
INPUT ENABLE OUTPUT
• Digital Isolation for A/D, H H Z
L H Z
D/A Conversion H L H
L L L
• Instrument Input/Output
Isolation
• Motor Control
• Power Inverter

CAUTION: It is advised that normal static precautions be taken in handling and assembly of this component to
prevent damage and/or degradation which may be induced by ESD.

1-402 5965-3578E
 OPTOCOUPLERS
Ordering Information
HCPL-710x
0 = 15 MBd Minimum Data Rate
1 = 50 MBd Minimum Data Rate

Option yyy
300 = Gull Wing Surface Mount Lead Option
500 = Tape/Reel Package Option (1 k min.)

Option data sheets available. Contact your Hewlett-Packard sales representative or authorized distributor for
information.

Package Outline Drawings

Standard DIP Package
9.40 (0.370)
9.90 (0.390)

8 7 6 5
TYPE NUMBER 0.20 (0.008)
DATE CODE 6.10 (0.240) 0.33 (0.013)
HP XXXX
6.60 (0.260)
YYWW RU 7.36 (0.290)
7.88 (0.310) 5° TYP.
UL
PIN ONE 1 2 3 4 RECOGNITION

1.78 (0.070) MAX.

1.19 (0.047) MAX.

4.70 (0.185) MAX. 1 VDD1 VDD2 8

2 VI VOE 7
0.51 (0.020) MIN.
3 * VO 6
2.92 (0.115) MIN.
4 GND1 GND2 5
0.76 (0.030) 0.65 (0.025) MAX.
1.40 (0.055)
2.28 (0.090) * PIN 3 IS THE ANODE
2.80 (0.110) * PIN 3 IS THE ANODE OFOF THE
THE INTERNAL
INTERNAL LED
LED AND
AND
MUSTBE
MUST BELEFT
LEFTUNCONNECTED
UNCONNECTEDFORFORGUARANTEED
GUARANTEED
DATA SHEET PERFORMANCE.
DATA SHEET PERFORMANCE.
DIMENSIONS IN MILLIMETERS AND (INCHES).
DIMENSIONS IN MILLIMETERS AND (INCHES).

1-403
Gull Wing Surface Mount Option 300*
PIN LOCATION (FOR REFERENCE ONLY)
9.65 ± 0.25 1.02 (0.040)
(0.380 ± 0.010) 1.19 (0.047)

8 7 6 5
TYPE NUMBER 4.83 TYP.
DATE CODE (0.190)
HP XXXX 6.350 ± 0.25
YYWW RU (0.250 ± 0.010) 9.65 ± 0.25
(0.380 ± 0.010)

1 2 3 4
MOLDED

UL 0.380 (0.015)
RECOGNITION 1.19 (0.047) 0.635 (0.025)
1.78 (0.070)

1.780 9.65 ± 0.25

(0.070) (0.380 ± 0.010)
1.19 MAX.
(0.047) 7.62 ± 0.25
MAX. (0.300 ± 0.010)
0.20 (0.008)
4.19 MAX. 0.33 (0.013)
(0.165)

1.080 ± 0.320 0.635 ± 0.25

(0.043 ± 0.013) (0.025 ± 0.010)
0.51 ± 0.130
2.540 (0.020 ± 0.005) 12° NOM.
(0.100)
BSC

DIMENSIONS IN MILLIMETERS (INCHES).

TOLERANCES (UNLESS OTHERWISE SPECIFIED): xx.xx = 0.01 LEAD COPLANARITY
xx.xxx = 0.005 MAXIMUM: 0.102 (0.004)

*Refer to Option 300 data sheet for more information.

Maximum Solder Reflow Thermal Profile

260
240
∆T = 145°C, 1°C/SEC
220
∆T = 115°C, 0.3°C/SEC
200
TEMPERATURE – °C

180
160
140
120
100
80
∆T = 100°C, 1.5°C/SEC
60
40
20
0
0 1 2 3 4 5 6 7 8 9 10 11 12
TIME – MINUTES

(NOTE: USE OF NON-CHLORINE ACTIVATED FLUXES IS RECOMMENDED.)

1-404
Regulatory Information CSA VDE

OPTOCOUPLERS
The HCPL-7100/1 has been Approved under CSA Component Approved according to VDE
approved by the following Acceptance Notice #5, File CA 0884/06.92
organizations: 88324.
UL
Recognized under UL 1577,
Component Recognition Program,
File E55361.

Insulation and Safety Related Specifications

Parameter Symbol Value Units Conditions
Min. External Air Gap L(IO1) 7.4 mm Measured from input terminals to output terminals,
(External Clearance) shortest distance through air
Min. External Tracking L(IO2) 8.0 mm Measured from input terminals to output terminals,
Path (External Creepage) shortest distance path along body
Min. Internal Plastic 0.5 mm Through insulation distance, conductor to conductor,
Gap (Internal Clearance) usually the direct distance between the photoemitter
and photodetector inside the optocoupler cavity
Tracking Resistance CTI 175 V DIN IEC 112/VDE 0303 PART 1
(Comparative
Tracking Index)
Isolation Group IIIa Material Group (DIN VDE 0110, 1/89, Table 1)
Option 300 – surface mount classification is Class A in accordance with CECC 00802.

VDE 0884 (06.92) Insulation Characteristics

Description Symbol Characteristic Unit
Installation classification per DIN VDE 0110, Table 1
for rated mains voltage ≤ 300 V rms I-IV
for rated mains voltage ≤ 600 V rms I-III
Climatic Classification 40/85/21
Pollution Degree (DIN VDE 0110, Table 1)* 2
Maximum Working Insulation Voltage VIORM 848 V peak
Input to Output Test Voltage, Method b**
VPR = 1.875 x VIORM, Production test with tp = 1 sec, VPR 1591 V peak
Partial discharge < 5 pC
Input to Output Test Voltage, Method a**
VPR = 1.5 x VIORM, Type and sample test, tp = 60 sec, VPR 1273 V peak
Partial discharge < 5 pC
Highest Allowable Overvoltage** VTR 6000 V peak
(Transient Overvoltage, tTR = 10 sec)
Safety-limiting values (Maximum values allowed in the event
of a failure, also see Figure 15)
Case Temperature TS 175 °C
Input Power PS,INPUT 80 mW
Output Power PS,OUTPUT 250 mW
Insulation Resistance at TS, VIO = 500 V RS ≥ 1 x 1012 Ω
*This part may also be used in Pollution Degree 3 environments where the rated mains voltage is ≤ 300 V rms (per DIN VDE 0110).
**Refer to the front of the optocoupler section in the current catalog for a more detailed description of VDE 0884 and other product
safety requirements.

Note: Optocouplers providing safe electrical separation per VDE 0884 do so only within the safety-limiting values to which they are
qualified. Protective cut-out switches must be used to ensure that the safety limits are not exceeded.

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Absolute Maximum Ratings
Parameter Symbol Min. Max. Unit
Storage Temperature TS -55 125 °C
Ambient Operating Temperature TA -40 85 °C
Supply Voltages VDD1,2 0.0 5.5 V
Input Voltage VI -0.5 VDD1 + 0.5 V
Output Voltage VO -0.5 VDD2 + 0.5 V
Output Enable Voltage VOE -0.5 VDD2 + 0.5 V
Average Output Current IO 25 mA
Package Power Dissipation PPD 220 mW
Lead Solder Temperature TLS 260 °C
(1.6 mm Below Seating Plane, 10 sec.)
Reflow Temperature Profile See Package Outline Drawings Section

Recommended Operating Conditions

Parameter Symbol Min. Max. Unit Test Conditions
Operating Temperature TA -40 85 °C
Supply Voltages VDD1,2 4.5 5.5 V
Logic High Input Voltage VIH 2.0 VDD1 V
Logic Low Input Voltage VIL 0.0 0.8 V
Logic High Output VOEH 2.0 VDD2 V Output in high impedance
Enable Voltage state
Logic Low Output VOEL 0.0 0.8 V Output enabled
Enable Voltage
Input Signal Rise and tr, tf 1 ms
Fall Times
TTL Fanout N 6 Standard Loads

1-406
 OPTOCOUPLERS
Electrical Specifications
Guaranteed across recommended operating conditions. Test conditions represent worst case values for the
parameter under test. Test conditions that are not specified can be anywhere within their operating range.
All typicals are at 25°C and 5 V supplies unless otherwise noted.
Parameter Symbol Min. Typ. Max. Unit Test Conditions Fig. Note
Logic Low Input Supply IDD1L 5.2 10.0 mA VDD1 = 5.5 V 1
Current VI = VIL
Logic High Input Supply IDD1H 0.3 0.6 mA VI = 4.5 V VDD1 = 5.5 V 1
Current 0.9 1.6 VI = 2.0 V
Logic Low Output IDD2L 5.0 9.0 mA VDD2 = 5.5 V
Supply Current VOE = VOEL
VI = VIL
Logic High Output IDD2H 5.2 9.0 mA VDD2 = 5.5 V
Supply Current VOE = VOEL
IO = 0 mA
VI = VIH
Tri-State Output Supply IDD2Z 5.1 9.0 mA VOE = 4.5 V VDD2 = 5.5 V
Current 5.6 10.0 VOE = 2.0 V
Input Current II -1 1 µA VI = VDD1 or GND
VDD1 = 5.5 V
Output Enable Current IOE -1 1 µA VOE = VDD2 or GND
VDD2 = 5.5 V
Logic High Output VOH 4.4 5.0 IO = -20 µA VDD2 = 4.5 V 6
Voltage 4.0 4.8 V IO = -4.0 mA VI = VIH
VOE = VOEL
3.7 4.7 IO = -6.0 mA
Logic High Output IOH -7.5 -25 mA VDD2 = 4.5 V 6
Current VO = 3.6 V
VI = VIH
VOE = VOEL
Logic Low Output VOL 0.0 0.1 IO = 20 µA VDD2 = 4.5 V 5
Voltage 0.1 0.3 V IO = 4.0 mA VI = VIL
VOE = VOEL
0.15 0.4 IO = 6.0 mA

Logic Low Output IOL 10.5 23 mA VDD2 = 4.5 V 5

Current VO = 0.6 V
VI = VIL
VOE = VOEL
High Impedance IOZ -5 5 µA VDD2 = 5.5 V
State Output VOE = VOEH
Current VO = VDD2 or GND
Input Capacitance CI 4.3 pF f = 1 MHz 4
Input-Output RI-O 1012 1013 Ω TA = 25°C VI-O = 500 Vdc 2
1011 TA = 100°C
Input-Output CI-O 0.7 pF f = 1 MHz 2
Capacitance
Resistance
*The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output
continuous voltage rating. For the continuous voltage rating refer to the VDE 0884 Insulation Characteristics Table (if applicable),
your equipment level safety specification, or HP Application Note 1074, “Optocoupler Input-Output Endurance Voltage.”

1-407
Switching Specifications
Guaranteed across recommended operating conditions. Test conditions represent worst case values for the
parameter under test. Test conditions that are not specified can be anywhere within their operating range. All
typicals are at 25°C and 5 V supplies unless otherwise noted.

Parameter Symbol Device Min. Typ. Max. Unit Test Conditions Fig. Note

Propagation tPHL HCPL-7100 70 ns CL = 50 pF 7, 8 5, 6

Delay Time CMOS Signal Levels
to Logic HCPL-7101 28 40
Low Output
HCPL-7100 70 ns CL = 15 pF
TTL Signal Levels
HCPL-7101 40

Propagation tPLH HCPL-7100 70 ns CL = 50 pF 7, 8 5, 6

Delay Time CMOS Signal Levels
to Logic HCPL-7101 27 40
High Output
HCPL-7100 70 ns CL = 15 pF
TTL Signal Levels
HCPL-7101 40

Pulse Width PWD HCPL-7100 20 ns CL = 50 pF 7, 9 6, 7

Distortion CMOS Signal Levels
|tPHL- tPLH| HCPL-7101 2 6

HCPL-7100 20 ns CL = 15 pF
TTL Signal Levels
HCPL-7101 6

Data Rate HCPL-7100 15 MBd % PWD < 30% 8

HCPL-7101 50 65

Propagation tPSK HCPL-7101 10 ns 10 9

Delay Skew

Output Rise tR HCPL-7100 12 ns CL = 50 pF 7

Time CMOS Signal Levels
(10-90%) HCPL-7101 10

Output Fall tF HCPL-7100 8 ns CL = 50 pF 7

Time CMOS Signal Levels
(90-10%) HCPL-7101 7

Random Jitter RJ HCPL-7101 50 ps rms V1 = 0-5 V square wave,

f = 25 MHz, input rise/
fall time = 5 ns.
RL = 10 kΩ,
CL = 5 pF.
TTL Threshold Levels.

Propagation tPZH 13 ns CL = 50 pF 12 6
Delay Time From CMOS Signal Levels
Output Enabled
to Logic High 12 ns CL = 15 pF
Output TTL Signal Levels

Propagation tPZL 11 ns CL = 50 pF 12 6
Delay Time From CMOS Signal Levels
Output Enabled
to Logic Low 10 ns CL = 15 pF
Output TTL Signal Levels

1-408
 OPTOCOUPLERS
Switching Specifications (cont.)
Guaranteed across recommended operating conditions. Test conditions represent worst case values for the
parameter under test. Test conditions that are not specified can be anywhere within their operating range. All
typicals are at 25°C and 5 V supplies unless otherwise noted.

Parameter Symbol Device Min. Typ. Max. Unit Test Conditions Fig. Note

Propagation tPHZ 12 ns CL = 50 pF 12 6
Delay Time from CMOS Signal Levels
Logic High to
Output Disabled 12 ns CL = 15 pF
TTL Signal Levels

Propagation tPLZ 9 ns CL = 50 pF 12 6
Delay Time from CMOS Signal Levels
Logic Low to
Output Disabled 11 ns CL = 15 pF
TTL Signal Levels
Common Mode |CMH| HCPL-7100 1000 V/µs VCM = 50 V VI = VIH 13, 10
Transient VD > 3.2 V 14
Immunity at HCPL-7101 2000 VCM = 200 V
Logic High
Output

Common Mode |CML| HCPL-7100 1000 V/µs VCM = 50 V VI = VIL 13, 10

Transient VD < 0.8 V 14
Immunity at HCPL-7101 2000 VCM = 200 V
Logic Low
Output

Input Dynamic CPD1 68 pF 11

Power Dissipation
Capacitance

Output Dynamic CPD2 10 pF 11

Power Dissipation
Capacitance

Package Characteristics
Guaranteed across recommended operating conditions. Test conditions represent worst case value for the
parameter under test. Test conditions that are not specified can be anywhere within their operating range.
All typicals are at TA = 25°C and 5 V supplies unless otherwise noted.
Parameter Sym. Min. Typ. Max. Units Test Conditions Fig. Note
Input-Output VISO 3750 V rms t = 1 min., RH < 50%, 2, 3
Momentary TA = 25°C
Withstand Voltage*
Input-Output RI-O 1012 1013 Ω TA = 25°C VI-O = 500 Vdc 2
Resistance 1011 TA =100°C
Input-Output CI-O 0.7 pF f = 1 MHz 2
Capacitance

*The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output
continuous voltage rating. For the continuous voltage rating refer to the VDE 0884 Insulation Characteristics Table (if applicable),
your equipment level safety specification or HP Application Note 1074 entitled “Optocoupler Input-Output Endurance Voltage.”

1-409
Notes:
1. The LED is OFF when the VI is high and ON when VI is low.
2. Device considered a two terminal device; pins 1-4 shorted together and pins 5-8 shorted together.
3. In accordance with UL 1577, for devices with minimum VISO specified at 3750 V rms, each optocoupler is proof-tested by applying an
insulation test voltage greater than 4500 V rms for one second (leakage current detection limit II-O < 5 µA). This test is performed
before the method b, 100% production test for partial discharge shown in the VDE 0884 Insulation Characteristics Table.
4. CI is the capacitance measured at pin 2 (VI).
5. tPHL propagation delay is measured from the 50% level on the falling edge of the VI signal to the logic switching level of the VO signal.
tPLH propagation delay is measured from the 50% level on the rising edge of the VI signal to the logic switching level of the VO signal.
6. The logic switching levels are 1.5 V for TTL signals (0-3 V) and 2.5 V for CMOS signals (0-5 V).
7. PWD is defined as |tPHL - tPLH|. %PWD (percent pulse width distortion) is equal to PWD in ns divided by symbol duration (bit length)
in ns.
8. Minimum data rate is calculated as follows: %PWD/PWD where %PWD is typically chosen by the design engineer (30% is common).
9. tPSK is equal to the worst case difference in tPHL and/or tPLH that will be seen between units at the same temperature, supply voltage,
and output load within the recommended operating condition range.
10. CMH is the maximum common mode voltage slew rate that can be sustained while maintaining VO > 3.2 V. CML is the maximum
common mode voltage slew rate that can be sustained while maintaining VO < 0.8 V. The common mode voltage slew rates apply to
both rising and falling common mode voltage edges.
11. Unloaded dynamic power dissipation is calculated as follows: CPD • VDD2 • f + IDD • VDD where f is switching frequency in MHz.

Figure 1. Recommended Application Circuit.

Figure 2. Recommended Printed Circuit Board Layout.

1-410
 OPTOCOUPLERS
5.50
5.00
VDD1 = 5.0 V
4.50
85 °C
4.00
-40 °C
3.50
25 °C
3.00
VO (V)

2.50
2.00
1.50
1.00
0.50
0
0 1.00 2.00 3.00 4.00 5.00

VI (V)

Figure 3. Typical Output Voltage vs. Input Voltage. Figure 4. Typical Input Voltage Switching Threshold vs.
Input Supply Voltage.

VDD2 = 5.0 V

VDD2 = 5.0 V

Figure 5. Typical Logic Low Output Voltage vs. Logic Low Figure 6. Typical Logic High Output Voltage vs. Logic High
Output Current. Output Current.

1-411
Figure 7. Test Circuit for Propagation Delay, Rise Time and Fall Time.

VDD1 = 5.0 V VDD1 = 5.0 V

VDD2 = 5.0 V VDD2 = 5.0 V

Figure 8. HCPL-7101 Typical Propagation Delay vs. Figure 9. HCPL-7101 Typical Pulse Width Distortion vs.
Temperature. Temperature.

1-412
 OPTOCOUPLERS
Figure 10. Propagation Delay Skew Waveform. Figure 11. Parallel Data Transmission Example.

Figure 12. Test Circuit for 3-State Output Enable and Disable Propagation Delays.

1-413
 VDD1 = 5.0 V
VDD2 = 5.0 V
TA = 25 °C

Figure 14. Typical Common Mode

Transient Immunity vs. Common Mode
Transient Voltage.

OUTPUT, VO

VOL

Figure 13. Test Circuit for Common Mode Transient

Immunity and Typical Waveforms.

400
OUTPUT POWER, PS
INPUT POWER, PS
300
PS – POWER – mW

200

100

0
0 20 40 60 80 100 120 140 160 180
175
TA – TEMPERATURE – °C

Figure 15. Dependence of Safety-Limiting Data on

Ambient Temperature.

1-414
 OPTOCOUPLERS
HCPL-7100/7101 value. PWD is defined as the As mentioned earlier, tPSK can
Application Information difference between tPLH and tPHL determine the maximum parallel
The HCPL-7100/7101 is and often determines the maxi- data transmission rate. Figure 11
extremely easy to use. Because mum data rate capability of a is the timing diagram of a typical
the optocoupler uses high-speed transmission system. PWD can be parallel data application with both
CMOS IC technology, the inputs expressed in percent by dividing the clock and the data lines being
and output are fully compatible the PWD (in ns) by the minimum sent through optocouplers. The
with all +5 V TTL and CMOS pulse width (in ns) being figure shows data and clock
logic. TTL or CMOS logic can be transmitted. Typically, PWD on signals at the inputs and outputs
connected directly to the inputs the order of 20-30% of the of the optocouplers. To obtain the
and output; no external interface minimum pulse width is tolerable; maximum data transmission rate,
circuitry is required. the exact figure depends on the both edges of the clock signal are
particular application (RS232, being used to clock the data; if
As shown in Figure 1, the only RS422, T-1, etc.). only one edge were used, the
external components required for clock signal would need to be
proper operation are two ceramic Propagation delay skew, tPSK, is twice as fast.
bypass capacitors. Capacitor an important parameter to con-
values should be between 0.01 µF sider in parallel data applications Propagation delay skew repre-
and 0.1 µF. For each capacitor, where synchronization of signals sents the uncertainty of where an
the total lead length between both on parallel data lines is a concern. edge might be after being sent
ends of the capacitor and the If the parallel data is being sent through an optocoupler. Figure
power-supply pins should not through a group of optocouplers, 11 shows that there will be
exceed 20 mm. Figure 2 differences in propagation delays uncertainty in both the data and
illustrates the recommended will cause the data to arrive at the the clock lines. It is important
printed circuit board layout for outputs of the optocouplers at that these two areas of uncertainty
the HCPL-7100/7101. different times. If this difference not overlap, otherwise the clock
in propagation delays is large signal might arrive before all of
Propagation Delay, Pulse- enough, it will determine the the data outputs have settled, or
Width Distortion, and maximum rate at which parallel some of the data outputs may
Propagation Delay Skew data can be sent through the start to change before the clock
Propagation delay is a figure of optocouplers. signal has arrived. From these
merit which describes how considerations, the absolute
quickly a logic signal propagates Propagation delay skew is defined minimum pulse width that can be
through a system. The propaga- as the difference between the sent through optocouplers in a
tion delay from low to high (tPLH) minimum and maximum propaga- parallel application is twice tPSK. A
is the amount of time required for tion delays, either tPLH or tPHL, for cautious design should use a
an input signal to propagate to any given group of optocouplers slightly longer pulse width to
the output, causing the output to which are operating under the ensure that any additional
change from low to high. same conditions (i.e., the same uncertainty in the rest of the
Similarly, the propagation delay supply voltage, output load, and circuit does not cause a problem.
from high to low (tPHL) is the operating temperature). As illus-
amount of time required for the trated in Figure 10, if the inputs The HCPL-7101 optocoupler offers
input signal to propagate to the of a group of optocouplers are the advantages of guaranteed
output, causing the output to switched either ON or OFF at the specifications for propagation
change from high to low (see same time, tPSK is the difference delays, pulse-width distortion and
Figure 7). between the shortest propagation propagation delay skew over the
delay, either tPLH or tPHL, and the recommended temperature, and
Pulse-width distortion (PWD) longest propagation delay, either power supply ranges.
results when tPLH and tPHL differ in tPLH or tPHL.

1-415