Proceedings of the International Conference on Sustainable Computing and Data Communication Systems (ICSCDS-2023)

IEEE Xplore Part Number: CFP23AZ5-ART; ISBN: 978-1-6654-9199-0

High Security and Low Power AES Crypto

Processor Security Algorithm for Image Encryption
2023 International Conference on Sustainable Computing and Data Communication Systems (ICSCDS) | 978-1-6654-9199-0/23/$31.00 ©2023 IEEE | DOI: 10.1109/ICSCDS56580.2023.10105112

Dr.N.SENTHILKUMAR A SATHISH
Assistant Professor Department of Electronics and Communication
Department of Electronics and Communication Engineering
Engineering M.Kumarasamy College of Engineering
M.Kumarasamy College of Engineering
Karur-639113, India
Karur-639113, India
[email protected]
[email protected]

S SATHEESH
S SASIKUMAR Department of Electronics and Communication
Department of Electronics and Communication Engineering
Engineering M.Kumarasamy College of Engineering
M.Kumarasamy College of Engineering Karur-639113, India
Karur-639113, India [email protected]
[email protected]

P SRIDHAR
Department of Electronics and Communication
Engineering
M.Kumarasamy College of Engineering
Karur-639113, India
[email protected]

Abstract—Data encryption specifications include the recipient(s) from accessing or using the encrypted data.
Advanced Encryption Standard (AES) algorithm. This A crypto system can be utilized to encrypt a message [1].
AES algorithm has been incorporated into both hardware Only when the proper algorithm and keys are used to
and software, making it one of the most used forms of decode the communication can the recipient see its
encryption technologies. A symmetric cryptography encrypted contents. The primary use of cryptography is
method with adequate security uses Field Programmable the transmission of private data via computer networks.
Gate Arrays (FPGA). The proposed design includes 8bit (1- When a document is encrypted, a key and a
byte) data route and 5 main blocks. The Key Register and mathematical method are applied to turn it from clear
State Register are the register banks to store text files,
text into crypto-text [2]. Crypto-text cannot be read if the
credential keys, and intermediate data. Shift Rows are
reader does not possess the decryption key. It was
added to the State Register to reduce an area. The Mix
Column will be changed to an 8bit data route. has four commonly accepted that DES was no longer reliable due
internal registers, each of which can send and receive 8 to advances in computer processing power. The main
bits, an 8-bit or 1- byte block that is designed for Mix objective NIST's to provide an alternative to DES that
Columns. Additionally, the key expansion and encryption US government agencies could use for non-military
phases employ shared optimized Sub-Bytes. To make information security applications [3]. The fact that
different Sub-Bytes more efficient, we combine and NIST's work would benefit businesses and other non-
streamline them. To cut down on power usage, the design government users and that it would be broadly embraced
makes use of the clock gating technique. AES architecture as a commercial standard was obviously understood. The
for a 128- bit image-based image encryption system is (NIST) invited professionals having knowledge of data
presented in this work. Verilog HDL, Model sim 6.4.c was security and cryptography from throughout participating
used to implement this design in an FPGA XC3S 200 TQ- in the selection process from across the globe and
144. To synthesize Xilinx to tool is being used. discussion. Five encryption methods were selected for
study. The AES algorithm still frequently used today
Keywords—Power Analysis Attack (PAA), Advanced onwards. NIST formally approved the AES algorithm for
Encryption Standard (AES), Field Programmable Gate encryption in the year 2000, and FIPS-197 was then
Array (FPGA), MATLAB. published as a government standard. On the NIST
website, you may view the whole FIPS-197 standard. As
I. INTRODUCTION was to be predicted, a large number of manufacturers of
The encryption is used to a crypto system or cypher encryption- related hardware and software now provide
to prevent anybody other than preventing the intended AES encryption. The block cypher AES and encryption

978-1-6654-9199-0/23/$31.00 ©2023 IEEE 1251

d licensed use limited to: Vignan's Foundation for Science Technology & Research (Deemed to be University). Downloaded on September 20,2023 at 10:07:59 UTC from IEEE Xplore. Restrictio
 Proceedings of the International Conference on Sustainable Computing and Data Communication Systems (ICSCDS-2023)
IEEE Xplore Part Number: CFP23AZ5-ART; ISBN: 978-1-6654-9199-0

algorithm using a cipher key and done some several outcome, Add Round Key receives the results
rounds of encryption. A block cypher, a type of byte by byte [10]. The data path for the Key-
encryption technology, only one set of information is Register does not need to be 32 bits longer than
encrypted at a time. The block size for our basic AES the data path for 32bit mixing columns, nor is it
encryption is 128 bits, or 16 bytes [4]. The word required to store the outcomes in the registers.
"rounds" is denoting ten to fourteen times that the data is
encrypted and decrypted throughout the encryption  The clock gating approach is used in various
process, according to the size of the key. portions of the plan to lower the amount of
energy used, which results in a lower power
consumption [11].
II. EXISTING SYSTEM In regard to factors of the design, we employ to
minimize dynamic power usage by using the clock gating
It makes use of the SDRR (Secure Double Rate
approach. Individual clock gating is performed for the
Registers) in a well-known AES-128 architecture to
State Register and internal registers of the Mix Columns.
increase the cryptographic hardware's resilience to
For example, State Register and Mix Columns clock is
current PAAs [5]. Combinational and sequential logics
turned off Since these two blocks aren't used during the
are both kept secure by the interleaved processing of real
essential stage of growth, energy must be conserved.
and random data in the AES-128 employing SDRR,
which is when the most power is saved [12]. Fig 2 shows
which uses a combinational approach to analyze random
the proposed system's block diagram.
data constantly throughout the clock cycle [6]. Fig 1
shown the block diagram of existing model.

0 1
Input Plain Text Sub Bytes State Register Mix Columns Output
Add Round 1 0
Key
Mix
Sub bytes Shift Rows
SDRR SDRR
Column
SDRR SDRR
OUT 2
RNG

Cipher Text
RNG

Input Key RCON

CK

0
SEL

RNG
SEL

SEL
CK

CK

Plain Text Round sell

Round_sel2 Key Register
1 OUT 1 CNTL
Real data
Random data
RNG SDRR
Round Key
Control
CK
Unit

SEL

Fig 2: Block Diagram of Proposed System

Fig 1: Shown the Block diagram of Existing Model
A. Algorithm

III. PROPOSED SYSTEM

The masked clock gating and the AES core are PLAIN TEXT PLAIN TEXT
applied in the AES implementation to create the
encryption masks. 128bit encryption is performed using Add Round Key
Add Round key
Round 10

the masked AES core. Relative to a fully folded in half Sub Bytes Sub Bytes
implementation, in order to conserve space, the
Round 1

Shift Rows Shift Rows

procedure is carried out in 10 cycles, computing 1 round Mix Columns
ENCRYPTION

DECRYPTION

every cycle. The figure below shows the suggested Add Round key
Add Round key
Round 9

masked AES. Masking the real data with a random Inv Mix Columns
mask first (plaintext). The "Nano AES core" is then fed Inv Sub Bytes
Sub Bytes
the mask and the masked plaintext, encrypting the Inv Shift Rows
Round 9

masked data using the secret key. The cipher-text is Shift Rows
delivered to the module [7]. It is meant to be generated Mix Columns
Add Round key
alongside the findings that were masked.
Round 1

Add Round key Inv Mix Columns

0
 In an effort to minimize the amount of logic Sub Bytes Inv Sub Bytes
Round 10

required, State Register holds information on the Shift Rows Inv Shift Rows
Shift Rows [8]. Add Round key Add Round Key

 After optimizing it, we distribute the Block of CIPHER TEXT

sub bytes to the phases of key expansion and
encryption [9]. Fig 3: Algorithm of Proposed system

 Considering the topology, a stream of 8bit data, A block cypher with symmetric iteration is the
we construct an 8-bit block that is ideal for Add- Pipelined algorithm. The lengths of the block and key
Round-Key with 8 bit input and output. As an can be 128, 192, or 256 bits. The AES was required to

978-1-6654-9199-0/23/$31.00 ©2023 IEEE 1252

d licensed use limited to: Vignan's Foundation for Science Technology & Research (Deemed to be University). Downloaded on September 20,2023 at 10:07:59 UTC from IEEE Xplore. Restrictio
 Proceedings of the International Conference on Sustainable Computing and Data Communication Systems (ICSCDS-2023)
IEEE Xplore Part Number: CFP23AZ5-ART; ISBN: 978-1-6654-9199-0

create a symmetric block cypher with a block size of 128

bits by the NIST. Variations of Pipelined that can
function on greater block sizes will not be included in
the actual standard as a result of this requirement.
Additionally, Pipelined provides a customizable number
of rounds or iterations: 10, 12, and 14 for keys with
lengths of 128, 192, and 256, respectively. The data
block is viewed by the transformations in Pipelined as a
rectangular array with four columns and four-byte
vectors. A rectangular array of 4-byte vectors is also
thought of as the key; the number of columns depends on
the key length.
B. Software Requirements
This work provides a 128-bit AES architecture for
image cryptography. Verilog HDL is used to implement
this design in the FPGA XC3S 200 TQ-144. Modelsim
6.4.c is used to simulate it [13], and the Xilinx tool is
used to reprocess it. In Synthesis Process will generate
RTL Viewer and Technology Viewer. X power Tool
performs power calculations. MATLAB Tool is used
for image processing [14].
Fig 5: encryption and decryption
C. Application Block Diagram
Fig 6: Plaintext and Ciphertext
As shown Fig 3 Using the proposed scheme as a
base, A decryption technique will be created. The basis B. Xilinx device utilization summary of encryption
for encryption and decryption will be images [15]. For module
this process, MATLAB and VLSI will be combined (Fig
4). This is devise utilization summary for the proposed
encryption algorithm, here we show number of registers
used, number of LUT occupied [18-19], Slices and all
AES Decryption
AES Encryption (Fig 7).

Plain Text Cipher Text Plain Text

Encryption Decryption

Fig 4: Application Block Diagram

IV. RESULTS
A. Simulation result of Encryption & Decryption
This is Encryption & Decryption Simulation Result. Fig 7: Devise utilization Summary for the Proposed Encryption
Plaintext is Primary Input Data and Key is Key for
Encryption Process. Ciphertext is Encrypted Output. C. RTL VIEW OF AES MAIN MODULE
Key1 to Key 10 are the Generated key for Each Round
by Key Generation Unit [16]. This waveform Simulated This is RTL View of Proposed Design. RTL Means
by Modelsim Tool and we can give the Input based on Register transfer Level. Here the Verilog HDL Code is
Binary Number and we Showed op as Hexa Decimal converted as Schematic View [20]. It shows Each and
format [17] in the Fig 5 and Fig 6 shows our Encrypted Every individual Module as internal module. Various
plaintext and Ciphertext. design blocks. It caused the area of the Spartan 3 xc3s
200 tq144 board to be reduced by 30% (Fig 8).

978-1-6654-9199-0/23/$31.00 ©2023 IEEE 1253

d licensed use limited to: Vignan's Foundation for Science Technology & Research (Deemed to be University). Downloaded on September 20,2023 at 10:07:59 UTC from IEEE Xplore. Restrictio
 Proceedings of the International Conference on Sustainable Computing and Data Communication Systems (ICSCDS-2023)
IEEE Xplore Part Number: CFP23AZ5-ART; ISBN: 978-1-6654-9199-0

V. CONCLUSION
The Nano AES symmetric cryptography technique is
used in many applications and networks with a high
quality of security. As a result, AES is a practical
algorithm for little IoT devices. For IoT devices with
constrained resources, this study has developed a
compact AES architecture in this study. The architecture
included two specified register banks with an 8bit data
path in order to save simple text, interim results, and
keys. Shift-Rows were executed within the State-
Register to lessen the amount of logic needed.
Additionally, the design shared improved Sub-Bytes
with the encryption and key expansion phases. In
addition, this study has created Mix-Columns, a suitable
Fig 8: RTL View of proposed system
block for low- area design, using an output and input of
D. COMPARISION TABLE 8 bits. To decrease the amount of space and energy used,
this study has employed the clock gating method in
As shown in Fig 9, area has been reduced by using various design blocks. It caused the area of the Spartan 3
the proposed clock gating technique. xc3s 200 tq144 board to be reduced by 30% is set up
to issue an alert in the event of emergency.
REFERENCES
700 [1] Tanya Bindu, R. and Kavitha, T., 2023. A Survey on Various
Crypto-steganography Techniques for Real-Time Images.
In Intelligent Cyber Physical Systems and Internet of Things:
600 ICoICI 2022 (pp. 365-373). Cham: Springer International
Publishing.
500 Existing AES [2] Patil, Lakhichand Khushal, and Kalpesh A. Popat. "Comparative
Analysis of Several Approaches of Encoding Audio Files."
400 without Clock In Advancements in Smart Computing and Information Security:
Gating First International Conference, ASCIS 2022, Rajkot, India,
November 24–26, 2022, Revised Selected Papers, Part II, pp.
300 Proposed Nano 128-143. Cham: Springer Nature Switzerland, 2023.
AES with clock [3] Bhat, M. Iqbal, and Kaiser J. Giri. "Impact of computational
200 power on cryptography." Multimedia Security: Algorithm
Gating Development, Analysis and Applications (2021): 45-88.
100
[4] Yazdeen, Abdulmajeed Adil, Subhi RM Zeebaree, Mohammed
Mohammed Sadeeq, Shakir Fattah Kak, Omar M. Ahmed, and
0 Rizgar R. Zebari. "FPGA implementations for data encryption
LUT Slices Gates and decryption via concurrent and parallel computation: A
review." Qubahan Academic Journal 1, no. 2 (2021): 8-16.
[5] Harshitha, P. D., Darshan, R. V., Firdous, S., & Nayana, K.
(2021, May). High Performance Advanced Encryption Standard
Fig 9: it shows area of proposed and existing system system using Secure Double Rate Registers. In 2021 2nd
International Conference for Emerging Technology (INCET) (pp.
1-5). IEEE.
E. High Security Achieved [6] Rahman, M. T., Tajik, S., Rahman, M. S., Tehranipoor, M., &
The AES data encryption method's main benefit is Asadizanjani, N. (2020, December). The key is left under the
mat: On the security assumption of logic locking schemes.
the availability of various key lengths, despite the fact In 2020 IEEE International Symposium on Hardware Oriented
that it is potentially more complex and appealing. The Security and Trust (HOST) (pp. 262-272). IEEE.
AES algorithm is a symmetric block cypher that can [7] Shahbazi, K., & Ko, S. B. (2020). Area-efficient nano-AES
both encrypt (encipher) and decrypt (decipher) data. implementation for Internet-of-Things devices. IEEE
Encryption converts data into cypher text, an unreadable Transactions on Very Large Scale Integration (VLSI)
Systems, 29(1), 136-148.
form, and decryption converts the cypher text back into [8] de Fine Licht, J., Besta, M., Meierhans, S., & Hoefler, T. (2020).
plaintext. mostly because of one important factor: key Transformations of high-level synthesis codes for high-
size. AES uses longer keys because they are safer. performance computing. IEEE Transactions on Parallel and
Finding patterns is a common tactic for breaking a Distributed Systems, 32(5), 1014-1029.
cypher. AES is used to encrypt private data in hardware [9] Singhvi, Ankur. "Optimization and implementation of AES-128
algorithm on FPGA board." In Advances in Electrical and
and software all over the world. Computer Technologies: Select Proceedings of ICAECT 2019,
pp. 713-722. Springer Singapore, 2020
[10] [Liu, Leibo, Shaojun Wei, Jianfeng Zhu, and Chenchen Deng.
"Current Application Fields." In Software Defined Chips:
Volume II, pp. 167-277. Singapore: Springer Nature Singapore,
2022.
[11] Caforio, A., Balli, F. and Banik, S., 2020. Energy analysis of
lightweight AEAD circuits. In Cryptology and Network Security:
19th International Conference, CANS 2020, Vienna, Austria,

978-1-6654-9199-0/23/$31.00 ©2023 IEEE 1254

d licensed use limited to: Vignan's Foundation for Science Technology & Research (Deemed to be University). Downloaded on September 20,2023 at 10:07:59 UTC from IEEE Xplore. Restrictio
 Proceedings of the International Conference on Sustainable Computing and Data Communication Systems (ICSCDS-2023)
IEEE Xplore Part Number: CFP23AZ5-ART; ISBN: 978-1-6654-9199-0

December 14–16, 2020, Proceedings 19 (pp. 23-42). Springer

International Publishing.
[12] Schellenberg, F., Gnad, D.R., Moradi, A. and Tahoori, M.B.,
2021. An inside job: Remote power analysis attacks on
FPGAs. IEEE Design & Test, 38(3), pp.58-66.
[13] Sowmya, K.B. and Chandran, R., 2019, November. A 6tap Fir
Filter Implementation Using Modified Bachet Architecture For
Reduced Mapped Resources. In 2019 International Conference on
Smart Systems and Inventive Technology (ICSSIT) (pp. 1237-
1240). IEEE.
[14] Hameed, M., Hameed, A.L. and Jasm, K.N., 2022, March.
Dynamic Power Reduction in Huffman Design using 130 nm
Technology Library. In 2022 International Conference on
Computer Science and Software Engineering (CSASE) (pp. 19-
23). IEEE.
[15] Ganorkar, S., Sharma, S. and Jain, A., 2022, April.
Implementation of FIR Adaptive Filter with FPGA. In 2022 IEEE
11th International Conference on Communication Systems and
Network Technologies (CSNT) (pp. 146-149). IEEE.
[16] Reyad, O., Mansour, H.M., Heshmat, M. and Zanaty, E.A., 2021,
March. Key-based enhancement of data encryption standard for
text security. In 2021 National Computing Colleges Conference
(NCCC) (pp. 1-6). IEEE.
[17] Khan, M., Baig, D., Khan, U.S. and Karim, A., 2020, October.
Malware classification framework using convolutional neural
network. In 2020 International Conference on Cyber Warfare and
Security (ICCWS) (pp. 1-7). IEEE.
[18] Wegener, F., De Meyer, L. and Moradi, A., 2020. Spin me right
round rotational symmetry for FPGA-specific AES: Extended
version. Journal of Cryptology, 33, pp.1114-1155.
[19] Li, Y., Zhu, Q., Lyu, Z., Huang, Z. and Sun, J., 2021, April.
Dycuckoo: dynamic hash tables on gpus. In 2021 IEEE 37th
International Conference on Data Engineering (ICDE) (pp. 744-
755). IEEE.[20]
[20] Singh, D. and Chandel, R., 2020. Register-Transfer-Level
Design for Application-Specific Integrated Circuits. Nanoscale
VLSI: Devices, Circuits and Applications, pp.295-319.
[21] Chidananda Datta, P., Vinay Kumar, C., Singh, R. and
Mummaneni, K., 2022. Optimized RTL Design of a Vending
Machine Through FSM Using Verilog HDL. In Micro and
Nanoelectronics Devices, Circuits and Systems: Select
Proceedings of MNDCS 2022 (pp. 305-316). Singapore: Springer
Nature Singapore.

978-1-6654-9199-0/23/$31.00 ©2023 IEEE 1255

d licensed use limited to: Vignan's Foundation for Science Technology & Research (Deemed to be University). Downloaded on September 20,2023 at 10:07:59 UTC from IEEE Xplore. Restrictio