25AA080A/B, 25LC080A/B

8K SPI Bus Serial EEPROM

Device Selection Table

Part Number VCC Range Page Size Temp. Ranges Packages

25LC080A 2.5-5.5V 16 Byte I, E P, SN, ST, MS
25AA080A 1.8-5.5V 16 Byte I P, SN, ST, MS
25LC080B 2.5-5.5V 32 Byte I, E P, SN, ST, MS
25AA080B 1.8-5.5V 32 Byte I P, SN, ST, MS

Features Description
• Max. clock 10 MHz The Microchip Technology Inc. 25AA080A/B,
• Low-power CMOS technology 25LC080A/B (25XX080A/B*) are 8 Kbit Serial
• 1024 x 8-bit organization Electrically Erasable PROMs. The memory is accessed
via a simple Serial Peripheral Interface (SPI)
• 16 byte page (‘A’ version devices)
compatible serial bus. The bus signals required are a
• 32 byte page (‘B’ version devices) clock input (SCK) plus separate data in (SI) and data
• Write cycle time: 5 ms max. out (SO) lines. Access to the device is controlled
• Self-timed ERASE and WRITE cycles through a Chip Select (CS) input.
• Block write protection Communication to the device can be paused via the
- Protect none, 1/4, 1/2 or all of array hold pin (HOLD). While the device is paused, transi-
• Built-in write protection tions on its inputs will be ignored, with the exception of
chip select, allowing the host to service higher priority
- Power-on/off data protection circuitry
interrupts.
- Write enable latch
The 25XX080A/B is available in standard packages
- Write-protect pin
including 8-lead PDIP and SOIC, and advanced
• Sequential read packaging including 8-lead MSOP, and 8-lead TSSOP.
• High reliability All packages are Pb-free and RoHS compliant.
- Endurance: 1,000,000 erase/write cycles
- Data retention: > 200 years Package Types (not to scale)
- ESD protection: > 4000V
• Pb-free and RoHS compliant TSSOP/MSOP PDIP/SOIC
(ST, MS) (P, SN)
• Temperature ranges supported;
CS 1 8 VCC
- Industrial (I): -40°C to +85°C 2 7
CS 1 8 VCC
SO HOLD
- Automotive (E): -40°C to +125°C WP 3 6 SCK SO 2 7 HOLD
VSS 4 5 SI 3 6
WP SCK
Pin Function Table VSS 4 5 SI

Name Function
CS Chip Select Input
SO Serial Data Output
WP Write-Protect
VSS Ground
SI Serial Data Input
SCK Serial Clock Input
HOLD Hold Input
*25XX080A/B is used in this document as a generic part
VCC Supply Voltage number for the 25AA080A/B, 25LC080A/B.

© 2007 Microchip Technology Inc. DS21808D-page 1

25XX080A/B
1.0 ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings (†)
VCC .............................................................................................................................................................................7.0V
All inputs and outputs w.r.t. VSS ......................................................................................................... -0.6V to VCC +1.0V
Storage temperature .................................................................................................................................-65°C to 150°C
Ambient temperature under bias ...............................................................................................................-65°C to 125°C
ESD protection on all pins ..........................................................................................................................................4 kV

† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for an
extended period of time may affect device reliability.

TABLE 1-1: DC CHARACTERISTICS

Industrial (I): TAMB = -40°C to +85°C VCC = 1.8V to 5.5V
DC CHARACTERISTICS
Automotive (E): TAMB = -40°C to +125°C VCC = 2.5V to 5.5V
Param.
Sym. Characteristic Min. Max. Units Test Conditions
No.
D001 VIH1 High-level input 2.0 VCC +1 V VCC ≥ 2.7V (Note)
D002 VIH2 voltage 0.7 VCC VCC +1 V VCC< 2.7V (Note)
D003 VIL1 Low-level input -0.3 0.8 V VCC ≥ 2.7V (Note)
D004 VIL2 voltage -0.3 0.2 VCC V VCC < 2.7V (Note)
D005 VOL Low-level output — 0.4 V IOL = 2.1 mA
D006 VOL voltage — 0.2 V IOL = 1.0 mA, VCC < 2.5V
D007 VOH High-level output VCC -0.5 — V IOH = -400 μA
voltage
D008 ILI Input leakage current ±1 μA CS = VCC, VIN = VSS TO VCC
D009 ILO Output leakage ±1 μA CS = VCC, VOUT = VSS TO VCC
current
D010 CINT Internal Capacitance — 7 pF TAMB = 25°C, CLK = 1.0 MHz,
(all inputs and VCC = 5.0V (Note)
outputs)
D011 ICC Read — 6 mA VCC = 5.5V; FCLK = 10.0 MHz;
— SO = Open
Operating Current 2.5 mA VCC = 2.5V; FCLK = 5.0 MHz;
SO = Open
D012 ICC Write — 3 mA VCC = 5.5V
—
D013 Iccs — 5 μA CS = VCC = 5.5V, Inputs tied to VCC or
Standby Current — VSS, TAMB = -40°C TO +125°C
1 μA CS = VCC = 2.5V, Inputs tied to VCC or
VSS, TAMB = -40°C TO +85°C
Note: This parameter is periodically sampled and not 100% tested.

DS21808D-page 2 © 2007 Microchip Technology Inc.

 25XX080A/B

TABLE 1-2: AC CHARACTERISTICS

Industrial (I): TAMB = -40°C to +85°C VCC = 1.8V to 5.5V

AC CHARACTERISTICS
Automotive (E): TAMB = -40°C to +125°C VCC = 2.5V to 5.5V

Param.
Sym. Characteristic Min. Max. Units Test Conditions
No.

1 FCLK Clock Frequency — 10 MHz 4.5V ≤ VCC ≤ 5.5V

— 5 MHz 2.5V ≤ VCC < 4.5V
— 3 MHz 1.8V ≤ VCC < 2.5V
2 TCSS CS Setup Time 50 — ns 4.5V ≤ VCC ≤ 5.5V
100 — ns 2.5V ≤ VCC < 4.5V
150 — ns 1.8V ≤ VCC < 2.5V
3 TCSH CS Hold Time 100 — ns 4.5V ≤ VCC ≤ 5.5V
200 — ns 2.5V ≤ VCC < 4.5V
250 — ns 1.8V ≤ VCC < 2.5V
4 TCSD CS Disable Time 50 — ns —
5 Tsu Data Setup Time 10 — ns 4.5V ≤ VCC ≤ 5.5V
20 — ns 2.5V ≤ VCC < 4.5V
30 — ns 1.8V ≤ VCC < 2.5V
6 THD Data Hold Time 20 — ns 4.5V ≤ VCC ≤ 5.5V
40 — ns 2.5V ≤ VCC < 4.5V
50 — ns 1.8V ≤ VCC < 2.5V
7 TR CLK Rise Time — 500 ns (Note 1)
8 TF CLK Fall Time — 500 ns (Note 1)
9 THI Clock High Time 50 — ns 4.5V ≤ VCC ≤ 5.5V
100 — ns 2.5V ≤ VCC < 4.5V
150 — ns 1.8V ≤ VCC < 2.5V
10 TLO Clock Low Time 50 — ns 4.5V ≤ VCC ≤ 5.5V
100 — ns 2.5V ≤ VCC < 4.5V
150 — ns 1.8V ≤ VCC < 2.5V
11 TCLD Clock Delay Time 50 — ns —
12 TCLE Clock Enable Time 50 — ns —
13 TV Output Valid from Clock — 50 ns 4.5V ≤ VCC ≤ 5.5V
Low — 100 ns 2.5V ≤ VCC < 4.5V
— 160 ns 1.8V ≤ VCC < 2.5V
14 THO Output Hold Time 0 — ns (Note 1)
15 TDIS Output Disable Time — 40 ns 4.5V ≤ VCC ≤ 5.5V (Note 1)
— 80 ns 2.5V ≤ VCC < 4.5V (Note 1)
— 160 ns 1.8V ≤ VCC < 2.5V (Note 1)
16 THS HOLD Setup Time 20 — ns 4.5V ≤ VCC ≤ 5.5V
40 — ns 2.5V ≤ VCC < 4.5V
80 — ns 1.8V ≤ VCC < 2.5V
Note 1: This parameter is periodically sampled and not 100% tested.
2: This parameter is not tested but ensured by characterization. For endurance estimates in a specific
application, please consult the Total Endurance™ Model which can be obtained from our web site:
www.microchip.com.
3: TWC begins on the rising edge of CS after a valid write sequence and ends when the internal write cycle
is complete.

© 2007 Microchip Technology Inc. DS21808D-page 3

25XX080A/B
TABLE 1-2: AC CHARACTERISTICS (CONTINUED)

Industrial (I): TAMB = -40°C to +85°C VCC = 1.8V to 5.5V

AC CHARACTERISTICS
Automotive (E): TAMB = -40°C to +125°C VCC = 2.5V to 5.5V

Param.
Sym. Characteristic Min. Max. Units Test Conditions
No.
17 THH HOLD Hold Time 20 — ns 4.5V ≤ VCC ≤ 5.5V
40 — ns 2.5V ≤ VCC < 4.5V
80 — ns 1.8V ≤ VCC < 2.5V
18 THZ HOLD Low to Output 30 — ns 4.5V ≤ VCC ≤ 5.5V (Note 1)
High-Z 60 — ns 2.5V ≤ VCC < 4.5V (Note 1)
160 — ns 1.8V ≤ VCC < 2.5V (Note 1)
19 THV HOLD High to Output 30 — ns 4.5V ≤ VCC ≤ 5.5V
Valid 60 — ns 2.5V ≤ VCC < 4.5V
160 — ns 1.8V ≤ VCC < 2.5V
20 TWC Internal Write Cycle Time — 5 ms (Note 3)
21 — Endurance 1,000,000 — E/W (Note 2)
Cycles
Note 1: This parameter is periodically sampled and not 100% tested.
2: This parameter is not tested but ensured by characterization. For endurance estimates in a specific
application, please consult the Total Endurance™ Model which can be obtained from our web site:
www.microchip.com.
3: TWC begins on the rising edge of CS after a valid write sequence and ends when the internal write cycle
is complete.

TABLE 1-3: AC TEST CONDITIONS

AC Waveform:
VLO = 0.2V —
VHI = VCC - 0.2V (Note 1)
VHI = 4.0V (Note 2)
Timing Measurement Reference Level
Input 0.5 VCC
Output 0.5 VCC
Note 1: For VCC ≤ 4.0V
2: For VCC > 4.0V

DS21808D-page 4 © 2007 Microchip Technology Inc.

 25XX080A/B
FIGURE 1-1: HOLD TIMING

CS
17 17
16 16

SCK
18 19
high-impedance
SO n+2 n+1 n n n-1

don’t care 5
SI n+2 n+1 n n n-1

HOLD

FIGURE 1-2: SERIAL INPUT TIMING

CS 12
2 11
7
Mode 1,1 8 3

SCK Mode 0,0

5 6

SI MSB in LSB in

high-impedance
SO

FIGURE 1-3: SERIAL OUTPUT TIMING

CS

9 10 3
Mode 1,1
SCK Mode 0,0
13
14 15

SO MSB out ISB out

don’t care
SI

© 2007 Microchip Technology Inc. DS21808D-page 5

25XX080A/B
2.0 FUNCTIONAL DESCRIPTION 2.3 Write Sequence
Prior to any attempt to write data to the 25XX080A/B,
2.1 Principles of Operation the write enable latch must be set by issuing the WREN
The 25XX080A/B are 1024 byte Serial EEPROMs instruction (Figure 2-4). This is done by setting CS low
designed to interface directly with the Serial and then clocking out the proper instruction into the
Peripheral Interface (SPI) Port of many of today’s 25XX080A/B. After all eight bits of the instruction are
popular microcontroller families, including transmitted, the CS must be brought high to set the
Microchip’s PIC® microcontrollers. It may also inter- write enable latch. If the write operation is initiated
face with microcontrollers that do not have a built-in immediately after the WREN instruction without CS
Synchronous Serial Port by using discrete being brought high, the data will not be written to the
I/O lines programmed properly with the software. array because the write enable latch will not have been
properly set.
The 25XX080A/B contains an 8-bit instruction register.
The device is accessed via the SI pin, with data being Once the write enable latch is set, the user may
clocked in on the rising edge of SCK. The CS pin must proceed by setting the CS low, issuing a WRITE
be low and the HOLD pin must be high for the entire instruction, followed by the 16-bit address, with the six
operation. MSBs of the address being don’t care bits, and then the
data to be written. Up to 16 bytes (25XX080A) or 32
Table 2-1 contains a list of the possible instruction bytes (25XX080B) of data can be sent to the device
bytes and format for device operation. All instructions, before a write cycle is necessary. The only restriction is
addresses, and data are transferred MSB first, LSB that all of the bytes must reside in the same page.
last.
Note: Page write operations are limited to writing
Data (SI) is sampled on the first rising edge of SCK
bytes within a single physical page,
after CS goes low. If the clock line is shared with other
regardless of the number of bytes
peripheral devices on the SPI bus, the user can assert
actually being written. Physical page
the HOLD input and place the 25XX080A/B in ‘HOLD’
boundaries start at addresses that are
mode. After releasing the HOLD pin, operation will
integer multiples of the page buffer size (or
resume from the point when the HOLD was asserted.
‘page size’) and, end at addresses that are
integer multiples of page size - 1. If a Page
2.2 Read Sequence Write command attempts to write across a
The device is selected by pulling CS low. The 8-bit read physical page boundary, the result is that
instruction is transmitted to the 25XX080A/B followed the data wraps around to the beginning of
by the 16-bit address, with the six MSBs of the address the current page (overwriting data
being don’t care bits. After the correct read instruction previously stored there), instead of being
and address are sent, the data stored in the memory at written to the next page as might be
the selected address is shifted out on the SO pin. The expected. It is therefore necessary for the
data stored in the memory at the next address can be application software to prevent page write
read sequentially by continuing to provide clock pulses. operations that would attempt to cross a
The internal address pointer is automatically page boundary.
incremented to the next higher address after each byte For the data to be actually written to the array, the CS
of data is shifted out. When the highest address is must be brought high after the Least Significant bit (D0)
reached (03FFh), the address counter rolls over to of the nth data byte has been clocked in. If CS is
address 0000h allowing the read cycle to be continued brought high at any other time, the write operation will
indefinitely. The read operation is terminated by raising not be completed. Refer to Figure 2-2 and Figure 2-3
the CS pin (Figure 2-1). for more detailed illustrations on the byte write
sequence and the page write sequence respectively.
While the write is in progress, the Status Register may
be read to check the status of the WPEN, WIP, WEL,
BP1 and BP0 bits (Figure 2-6). A read attempt of a
memory array location will not be possible during a
write cycle. When the write cycle is completed, the
write enable latch is reset.

DS21808D-page 6 © 2007 Microchip Technology Inc.

 25XX080A/B
Block Diagram
Status
HV Generator
Register

Memory EEPROM
I/O Control X
Control Array
Logic
Logic Dec

Page Latches

SI
SO Y Decoder
CS
SCK
HOLD Sense Amp.
R/W Control
WP
VCC
VSS

TABLE 2-1: INSTRUCTION SET

Instruction Name Instruction Format Description
READ 0000 0011 Read data from memory array beginning at selected address
WRITE 0000 0010 Write data to memory array beginning at selected address
WRDI 0000 0100 Reset the write enable latch (disable write operations)
WREN 0000 0110 Set the write enable latch (enable write operations)
RDSR 0000 0101 Read Status Register
WRSR 0000 0001 Write Status Register

FIGURE 2-1: READ SEQUENCE

CS

0 1 2 3 4 5 6 7 8 9 10 11 21 22 23 24 25 26 27 28 29 30 31
SCK

instruction 16-bit address

SI 0 0 0 0 0 0 1 1 15 14 13 12 2 1 0

data out
high-impedance
SO 7 6 5 4 3 2 1 0

© 2007 Microchip Technology Inc. DS21808D-page 7

25XX080A/B
FIGURE 2-2: BYTE WRITE SEQUENCE

CS
Twc
0 1 2 3 4 5 6 7 8 9 10 11 21 22 23 24 25 26 27 28 29 30 31
SCK
instruction 16-bit address data byte
SI 0 0 0 0 0 0 1 0 15 14 13 12 2 1 0 7 6 5 4 3 2 1 0

high-impedance
SO

FIGURE 2-3: PAGE WRITE SEQUENCE

CS

0 1 2 3 4 5 6 7 8 9 10 11 21 22 23 24 25 26 27 28 29 30 31
SCK
instruction 16-bit address data byte 1
SI 0 0 0 0 0 0 1 0 15 14 13 12 2 1 0 7 6 5 4 3 2 1 0

CS

32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SCK
data byte 2 data byte 3 data byte n (16/32 max)
SI 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0

DS21808D-page 8 © 2007 Microchip Technology Inc.

 25XX080A/B
2.4 Write Enable (WREN) and Write The following is a list of conditions under which the
Disable (WRDI) write enable latch will be reset:
• Power-up
The 25XX080A/B contains a write enable latch. See
Table 2-4 for the Write-Protect Functionality Matrix. • WRDI instruction successfully executed
This latch must be set before any write operation will be • WRSR instruction successfully executed
completed internally. The WREN instruction will set the • WRITE instruction successfully executed
latch, and the WRDI will reset the latch.

FIGURE 2-4: WRITE ENABLE SEQUENCE (WREN)

CS

0 1 2 3 4 5 6 7
SCK

SI 0 0 0 0 0 1 1 0

high-impedance
SO

FIGURE 2-5: WRITE DISABLE SEQUENCE (WRDI)

CS

0 1 2 3 4 5 6 7
SCK

SI 0 0 0 0 0 1 10 0

high-impedance
SO

© 2007 Microchip Technology Inc. DS21808D-page 9

25XX080A/B
2.5 Read Status Register Instruction The Write Enable Latch (WEL) bit indicates the status
(RDSR) of the write enable latch and is read only. When set to
a ‘1’, the latch allows writes to the array or the Status
The Read Status Register instruction (RDSR) provides Register, when set to a ‘0’, the latch prohibits writes to
access to the Status Register. The Status Register may the array or the Status Register. The state of this bit can
be read at any time, even during a write cycle. The always be updated via the WREN or WRDI commands
Status Register is formatted as follows: regardless of the state of write protection on the Status
Register. These commands are shown in Figure 2-4
TABLE 2-2: STATUS REGISTER and Figure 2-5.
7 6 5 4 3 2 1 0 The Block Protection (BP0 and BP1) bits indicate
which blocks are currently write-protected. These bits
W/R – – – W/R W/R R R
are set by the user issuing the WRSR instruction, which
WPEN X X X BP1 BP0 WEL WIP is in Figure 2-7. These bits are nonvolatile and are
W/R = writable/readable. R = read-only. shown in Table 2-3.
The Write-In-Process (WIP) bit indicates whether the See Figure 2-6 for the RDSR timing sequence.
25XX080A/B is busy with a write operation. When set
to a ‘1’, a write is in progress, when set to a ‘0’, no write
is in progress. This bit is read-only.

FIGURE 2-6: READ STATUS REGISTER TIMING SEQUENCE (RDSR)

CS

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

SCK

instruction

SI 0 0 0 0 0 1 0 1

data from Status Register

high-impedance
SO 7 6 5 4 3 2 1 0

DS21808D-page 10 © 2007 Microchip Technology Inc.

 25XX080A/B
2.6 Write Status Register Instruction See Figure 2-7 for the WRSR timing sequence.
(WRSR)
TABLE 2-3: ARRAY PROTECTION
The Write Status Register instruction (WRSR) allows the
user to write to the nonvolatile bits in the Status Array Addresses
Register as shown in Table 2-2. The user is able to BP1 BP0
Write-Protected
select one of four levels of protection for the array by
writing to the appropriate bits in the Status Register. 0 0 none
The array is divided up into four segments. The user 0 1 upper 1/4
has the ability to write-protect none, one, two or all four (0300h - 03FFh)
of the segments of the array. The partitioning is 1 0 upper 1/2
controlled as shown in Table 2-3. (0200h - 03FFh)
The Write-Protect Enable (WPEN) bit is also a 1 1 all
nonvolatile bit that is available as an enable bit for the WP (0000h - 03FFh)
pin. The Write-Protect (WP) pin and the Write-Protect
Enable (WPEN) bit in the Status Register control the
programmable hardware write-protect feature. Hardware
write protection is enabled when WP pin is low and the
WPEN bit is high. Hardware write protection is disabled
when either the WP pin is high or the WPEN bit is low.
When the chip is hardware write-protected, only writes to
nonvolatile bits in the Status Register are disabled. See
Table 2-4 for a matrix of functionality on the WPEN bit.

FIGURE 2-7: WRITE STATUS REGISTER TIMING SEQUENCE (WRSR)

CS

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

SCK

instruction data to Status Register

SI 0 0 0 0 0 0 0 1 7 6 5 4 3 2 1 0

high-impedance
SO

© 2007 Microchip Technology Inc. DS21808D-page 11

25XX080A/B
2.7 Data Protection 2.8 Power-On State
The following protection has been implemented to The 25XX080A/B powers on in the following state:
prevent inadvertent writes to the array: • The device is in low-power Standby mode
• The write enable latch is reset on power-up (CS = 1)
• A write enable instruction must be issued to set • The write enable latch is reset
the write enable latch • SO is in high-impedance state
• After a byte write, page write or Status Register • A high-to-low-level transition on CS is required to
write, the write enable latch is reset enter active state
• CS must be set high after the proper number of
clock cycles to start an internal write cycle
• Access to the array during an internal write cycle
is ignored and programming is continued

TABLE 2-4: WRITE-PROTECT FUNCTIONALITY MATRIX

WEL WPEN WP
Protected Blocks Unprotected Blocks Status Register
(SR bit 1) (SR bit 7) (pin 3)
0 x x Protected Protected Protected
1 0 x Protected Writable Writable
1 1 0 (low) Protected Writable Protected
1 1 1 (high) Protected Writable Writable
x = don’t care

DS21808D-page 12 © 2007 Microchip Technology Inc.

 25XX080A/B
3.0 PIN DESCRIPTIONS 3.4 Serial Input (SI)
The descriptions of the pins are listed in Table 3-1. The SI pin is used to transfer data into the device. It
receives instructions, addresses and data. Data is
TABLE 3-1: PIN FUNCTION TABLE latched on the rising edge of the serial clock.

Name Pin Number Function 3.5 Serial Clock (SCK)

CS 1 Chip Select Input The SCK is used to synchronize the communication
between a master and the 25XX080A/B. Instructions,
SO 2 Serial Data Output
addresses or data present on the SI pin are latched on
WP 3 Write-Protect Pin the rising edge of the clock input, while data on the SO
VSS 4 Ground pin is updated after the falling edge of the clock input.
SI 5 Serial Data Input
SCK 6 Serial Clock Input 3.6 Hold (HOLD)
HOLD 7 Hold Input The HOLD pin is used to suspend transmission to the
VCC 8 Supply Voltage 25XX080A/B while in the middle of a serial sequence
without having to retransmit the entire sequence again.
It must be held high any time this function is not being
3.1 Chip Select (CS) used. Once the device is selected and a serial
A low level on this pin selects the device. A high level sequence is underway, the HOLD pin may be pulled
deselects the device and forces it into Standby mode. low to pause further serial communication without
However, a programming cycle which is already resetting the serial sequence. The HOLD pin must be
initiated or in progress will be completed, regardless of brought low while SCK is low, otherwise the HOLD
the CS input signal. If CS is brought high during a function will not be invoked until the next SCK high-to-
program cycle, the device will go into Standby mode as low transition. The 25XX080A/B must remain selected
soon as the programming cycle is complete. When the during this sequence. The SI, SCK and SO pins are in
device is deselected, SO goes to the high-impedance a high impedance state during the time the device is
state, allowing multiple parts to share the same SPI paused and transitions on these pins will be ignored. To
bus. A low-to-high transition on CS after a valid write resume serial communication, HOLD must be brought
sequence initiates an internal write cycle. After power- high while the SCK pin is low, otherwise serial
up, a low level on CS is required prior to any sequence communication will not resume. Lowering the HOLD
being initiated. line at any time will tri-state the SO line.

3.2 Serial Output (SO)

The SO pin is used to transfer data out of the
25XX080A/B. During a read cycle, data is shifted out
on this pin after the falling edge of the serial clock.

3.3 Write-Protect (WP)

This pin is used in conjunction with the WPEN bit in the
Status Register to prohibit writes to the nonvolatile bits
in the Status Register. When WP is low and WPEN is
high, writing to the nonvolatile bits in the Status Regis-
ter is disabled. All other operations function normally.
When WP is high, all functions, including writes to the
nonvolatile bits in the Status Register operate normally.
If the WPEN bit is set, WP low during a Status Register
write sequence will disable writing to the Status
Register. If an internal write cycle has already begun,
WP going low will have no effect on the write.
The WP pin function is blocked when the WPEN bit in
the Status Register is low. This allows the user to install
the 25XX080A/B in a system with WP pin grounded
and still be able to write to the Status Register. The WP
pin functions will be enabled when the WPEN bit is set
high.

© 2007 Microchip Technology Inc. DS21808D-page 13

25XX080A/B
4.0 PACKAGING INFORMATION
4.1 Package Marking Information

8-Lead MSOP (150 mil) Example:

MSOP 1st Line Marking Codes

XXXXXXT 5L8AI
YWWNNN 6281L7 Device Code
25AA080A 5A8A
25AA080B 5A8B
25LC080A 5L8A
25LC080B 5L8B
8-Lead PDIP Example:

XXXXXXXX 25LC080A
T/XXXNNN I/P e3 1L7
YYWW 0628

8-Lead SOIC Example:

XXXXXXXT 25L080AI
XXXXYYWW SN e3 0628
NNN 1L7

8-Lead TSSOP Example:

TSSOP 1st Line Marking Codes
XXXX 5L8A
TYWW I628 Device Code
NNN 1L7
25AA080A 5A8A
25AA080B 5A8B
25LC080A 5L8A
25LC080B 5L8B

Legend: XX...X Customer-specific information

Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
e3 Pb-free JEDEC designator for Matte Tin (Sn)
* This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.

Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.

DS21808D-page 14 © 2007 Microchip Technology Inc.

 25XX080A/B

8-Lead Plastic Micro Small Outline Package (MS or UA) [MSOP]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

D
N

E
E1

NOTE 1

1 2
e

c φ
A A2

A1 L1 L

Units MILLIMETERS
Dimension Limits MIN NOM MAX
Number of Pins N 8
Pitch e 0.65 BSC
Overall Height A – – 1.10
Molded Package Thickness A2 0.75 0.85 0.95
Standoff A1 0.00 – 0.15
Overall Width E 4.90 BSC
Molded Package Width E1 3.00 BSC
Overall Length D 3.00 BSC
Foot Length L 0.40 0.60 0.80
Footprint L1 0.95 REF
Foot Angle φ 0° – 8°
Lead Thickness c 0.08 – 0.23
Lead Width b 0.22 – 0.40
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side.
3. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-111B

© 2007 Microchip Technology Inc. DS21808D-page 15

25XX080A/B

8-Lead Plastic Dual In-Line (P or PA) – 300 mil Body [PDIP]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

NOTE 1
E1

1 2 3

D
E

A A2

A1 L
c

e
b1 eB
b

Units INCHES
Dimension Limits MIN NOM MAX
Number of Pins N 8
Pitch e .100 BSC
Top to Seating Plane A – – .210
Molded Package Thickness A2 .115 .130 .195
Base to Seating Plane A1 .015 – –
Shoulder to Shoulder Width E .290 .310 .325
Molded Package Width E1 .240 .250 .280
Overall Length D .348 .365 .400
Tip to Seating Plane L .115 .130 .150
Lead Thickness c .008 .010 .015
Upper Lead Width b1 .040 .060 .070
Lower Lead Width b .014 .018 .022
Overall Row Spacing § eB – – .430
Notes:
1. Pin 1 visual index feature may vary, but must be located with the hatched area.
2. § Significant Characteristic.
3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" per side.
4. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.

Microchip Technology Drawing C04-018B

DS21808D-page 16 © 2007 Microchip Technology Inc.

 25XX080A/B

8-Lead Plastic Small Outline (SN or OA) – Narrow, 3.90 mm Body [SOIC]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

e
N

E1

NOTE 1

1 2 3
h α
b
h

c
A A2 φ

A1 L

L1 β

Units MILLIMETERS
Dimension Limits MIN NOM MAX
Number of Pins N 8
Pitch e 1.27 BSC
Overall Height A – – 1.75
Molded Package Thickness A2 1.25 – –
Standoff § A1 0.10 – 0.25
Overall Width E 6.00 BSC
Molded Package Width E1 3.90 BSC
Overall Length D 4.90 BSC
Chamfer (optional) h 0.25 – 0.50
Foot Length L 0.40 – 1.27
Footprint L1 1.04 REF
Foot Angle φ 0° – 8°
Lead Thickness c 0.17 – 0.25
Lead Width b 0.31 – 0.51
Mold Draft Angle Top α 5° – 15°
Mold Draft Angle Bottom β 5° – 15°
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. § Significant Characteristic.
3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side.
4. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-057B

© 2007 Microchip Technology Inc. DS21808D-page 17

25XX080A/B

8-Lead Plastic Thin Shrink Small Outline (ST) – 4.4 mm Body [TSSOP]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

E1

NOTE 1

1 2
b
e

c
A A2 φ

A1 L1 L

Units MILLIMETERS
Dimension Limits MIN NOM MAX
Number of Pins N 8
Pitch e 0.65 BSC
Overall Height A – – 1.20
Molded Package Thickness A2 0.80 1.00 1.05
Standoff A1 0.05 – 0.15
Overall Width E 6.40 BSC
Molded Package Width E1 4.30 4.40 4.50
Molded Package Length D 2.90 3.00 3.10
Foot Length L 0.45 0.60 0.75
Footprint L1 1.00 REF
Foot Angle φ 0° – 8°
Lead Thickness c 0.09 – 0.20
Lead Width b 0.19 – 0.30
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side.
3. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.

Microchip Technology Drawing C04-086B

DS21808D-page 18 © 2007 Microchip Technology Inc.

 25XX080A/B
APPENDIX A: REVISION HISTORY

Revision C (10/2006)
Updated Package Drawings and Product ID System.

Revision D (2/2007)
Replace Package Drawings; Revise Product ID
System (SOIC-SN package).

© 2007 Microchip Technology Inc. DS21808D-page 19

25XX080A/B
NOTES:

DS21808D-page 20 © 2007 Microchip Technology Inc.

 25XX080A/B
THE MICROCHIP WEB SITE CUSTOMER SUPPORT
Microchip provides online support via our WWW site at Users of Microchip products can receive assistance
www.microchip.com. This web site is used as a means through several channels:
to make files and information easily available to • Distributor or Representative
customers. Accessible by using your favorite Internet
• Local Sales Office
browser, the web site contains the following
information: • Field Application Engineer (FAE)
• Technical Support
• Product Support – Data sheets and errata,
application notes and sample programs, design • Development Systems Information Line
resources, user’s guides and hardware support Customers should contact their distributor,
documents, latest software releases and archived representative or field application engineer (FAE) for
software support. Local sales offices are also available to help
• General Technical Support – Frequently Asked customers. A listing of sales offices and locations is
Questions (FAQ), technical support requests, included in the back of this document.
online discussion groups, Microchip consultant Technical support is available through the web site
program member listing at: http://support.microchip.com
• Business of Microchip – Product selector and
ordering guides, latest Microchip press releases,
listing of seminars and events, listings of
Microchip sales offices, distributors and factory
representatives

CUSTOMER CHANGE NOTIFICATION

SERVICE
Microchip’s customer notification service helps keep
customers current on Microchip products. Subscribers
will receive e-mail notification whenever there are
changes, updates, revisions or errata related to a
specified product family or development tool of interest.
To register, access the Microchip web site at
www.microchip.com, click on Customer Change
Notification and follow the registration instructions.

© 2007 Microchip Technology Inc. DS21808D-page 21

25XX080A/B
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip prod-
uct. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation
can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150.
Please list the following information, and use this outline to provide us with your comments about this document.

To: Technical Publications Manager Total Pages Sent ________

RE: Reader Response

From: Name
Company
Address
City / State / ZIP / Country
Telephone: (_______) _________ - _________ FAX: (______) _________ - _________
Application (optional):
Would you like a reply? Y N

Device: 25XX080A/B Literature Number: DS21808D

Questions:

1. What are the best features of this document?

2. How does this document meet your hardware and software development needs?

3. Do you find the organization of this document easy to follow? If not, why?

4. What additions to the document do you think would enhance the structure and subject?

5. What deletions from the document could be made without affecting the overall usefulness?

6. Is there any incorrect or misleading information (what and where)?

7. How would you improve this document?

DS21808D-page 22 © 2007 Microchip Technology Inc.

 25XX080A/B
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO. X – X /XX
Examples:
Device Tape & Reel Temp Range Package a) 25AA080A-I/MS = 8 Kbit, 16-byte page, 1.8V
Serial EEPROM, Industrial temp., MSOP
package
b) 25AA080AT-I/SN = 8 Kbit, 16-byte page, 1.8V
Serial EEPROM, Industrial temp., Tape & Reel,
Device: 25AA080A 8 Kbit, 1.8V, 16 Byte Page SPI Serial EEPROM SOIC package
25AA080B 8 Kbit, 1.8V, 32 Byte Page SPI Serial EEPROM c) 25LC080BT-I/SN = 8 Kbit, 32-byte page, 2.5V
25LC080A 8 Kbit, 2.5V, 16 Byte Page SPI Serial EEPROM Serial EEPROM, Industrial temp., Tape & Reel,
25LC080B 8 Kbit, 2.5V, 32 Byte Page SPI Serial EEPROM SOIC package
d) 25LC080BT-I/ST = 8 Kbit, 32-byte page, 2.5V
Tape & Reel: Blank = Standard packaging Serial EEPROM, Industrial temp., Tape & Reel,
T = Tape and Reel TSSOP package
Temperature I = -40°C to+85°C
Range: E = -40°C to+125°C

Package: MS = Plastic MSOP (Micro Small Outline), 8-lead

P = Plastic DIP (300 mil body), 8-lead
SN = Plastic SOIC (3.90 mm body), 8-lead
ST = TSSOP, 8-lead

© 2007 Microchip Technology Inc. DS21808D-page 23

25XX080A/B
NOTES:

DS21808D-page 24 © 2007 Microchip Technology Inc.

Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device Trademarks

applications and the like is provided only for your convenience
The Microchip name and logo, the Microchip logo, Accuron,
and may be superseded by updates. It is your responsibility to
dsPIC, KEELOQ, KEELOQ logo, microID, MPLAB, PIC,
ensure that your application meets with your specifications.
PICmicro, PICSTART, PRO MATE, PowerSmart, rfPIC, and
MICROCHIP MAKES NO REPRESENTATIONS OR
SmartShunt are registered trademarks of Microchip
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
Technology Incorporated in the U.S.A. and other countries.
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION, AmpLab, FilterLab, Linear Active Thermistor, Migratable
INCLUDING BUT NOT LIMITED TO ITS CONDITION, Memory, MXDEV, MXLAB, PS logo, SEEVAL, SmartSensor
QUALITY, PERFORMANCE, MERCHANTABILITY OR and The Embedded Control Solutions Company are
FITNESS FOR PURPOSE. Microchip disclaims all liability registered trademarks of Microchip Technology Incorporated
arising from this information and its use. Use of Microchip in the U.S.A.
devices in life support and/or safety applications is entirely at Analog-for-the-Digital Age, Application Maestro, CodeGuard,
the buyer’s risk, and the buyer agrees to defend, indemnify and dsPICDEM, dsPICDEM.net, dsPICworks, ECAN,
hold harmless Microchip from any and all damages, claims, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB,
suits, or expenses resulting from such use. No licenses are In-Circuit Serial Programming, ICSP, ICEPIC, Mindi, MiWi,
conveyed, implicitly or otherwise, under any Microchip MPASM, MPLAB Certified logo, MPLIB, MPLINK, PICkit,
intellectual property rights. PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal,
PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB,
rfPICDEM, Select Mode, Smart Serial, SmartTel, Total
Endurance, UNI/O, WiperLock and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2007, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.

Microchip received ISO/TS-16949:2002 certification for its worldwide

headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona, Gresham, Oregon and Mountain View, California. The
Company’s quality system processes and procedures are for its PIC®
MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial
EEPROMs, microperipherals, nonvolatile memory and analog
products. In addition, Microchip’s quality system for the design and
manufacture of development systems is ISO 9001:2000 certified.

© 2007 Microchip Technology Inc. DS21808D-page 25

 WORLDWIDE SALES AND SERVICE
AMERICAS ASIA/PACIFIC ASIA/PACIFIC EUROPE
Corporate Office Asia Pacific Office India - Bangalore Austria - Wels
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Tel: 86-29-8833-7250
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Fax: 86-29-8833-7256
Tel: 905-673-0699
Fax: 905-673-6509

12/08/06

DS21808D-page 26 © 2007 Microchip Technology Inc.