Low Noise, High Speed Amplifier

for 16-Bit Systems

AD8021
FEATURES CONNECTION DIAGRAM
Low noise AD8021
LOGIC
2.1 nV/√Hz input voltage noise 1 8 DISABLE
REFERENCE
2.1 pA/√Hz input current noise –IN 2 7 +VS

Custom compensation +IN 3 6 VOUT

Constant bandwidth from G = −1 to G = −10

01888-001
–VS 4 5 CCOMP
High speed
200 MHz (G = −1) Figure 1. SOIC-8 (R-8) and MSOP-8 (RM-8)
190 MHz (G = −10)
Low power
34 mW or 6.7 mA typical for 5 V supply The AD8021 allows the user to choose the gain bandwidth
Output disable feature, 1.3 mA product that best suits the application. With a single capacitor,
Low distortion the user can compensate the AD8021 for the desired gain with
−93 dBc second harmonic, fC = 1 MHz little trade-off in bandwidth. The AD8021 is a well-behaved
−108 dBc third harmonic, fC = 1 MHz amplifier that settles to 0.01% in 23 ns for a 1 V step. It has a fast
DC precision overload recovery of 50 ns.
1 mV maximum input offset voltage
0.5 μV/°C input offset voltage drift The AD8021 is stable over temperature with low input offset
Wide supply range, 5 V to 24 V voltage drift and input bias current drift, 0.5 μV/°C and 10 nA/°C,
Low price respectively. The AD8021 is also capable of driving a 75 Ω line
Small packaging with ±3 V video signals.
Available in SOIC-8 and MSOP-8
The AD8021 is both technically superior and priced considerably
less than comparable amps drawing much higher quiescent
APPLICATIONS current. The AD8021 is a high speed, general-purpose amplifier,
ADC preamps and drivers ideal for a wide variety of gain configurations and can be used
Instrumentation preamps throughout a signal processing chain and in control loops. The
Active filters AD8021 is available in both standard 8-lead SOIC and MSOP
Portable instrumentation packages in the industrial temperature range of −40°C to +85°C.
Line receivers
Precision instruments
Ultrasound signal processing 24
VOUT = 50mV p-p
High gain circuits 21
G = –10, RF = 1kΩ, RG = 100Ω,
18
RIN = 100Ω, CC = 0pF
GENERAL DESCRIPTION
CLOSED-LOOP GAIN (dB)

15
The AD8021 is an exceptionally high performance, high speed G = –5, RF = 1kΩ, RG = 200Ω,
12
RIN = 66.5Ω, CC = 1.5pF
voltage feedback amplifier that can be used in 16-bit resolution
9
systems. It is designed to have both low voltage and low current
6
noise (2.1 nV/√Hz typical and 2.1 pA/√Hz typical) while operating G = –2, RF = 499Ω, RG = 249Ω,
at the lowest quiescent supply current (7 mA @ ±5 V) among 3 RIN = 63.4Ω, CC = 4pF

today’s high speed, low noise op amps. The AD8021 operates 0

G = –1, RF = 499Ω, RG = 499Ω,
over a wide range of supply voltages from ±2.25 V to ±12 V, as
01888-002

–3 RIN = 56.2Ω, CC = 7pF

well as from single 5 V supplies, making it ideal for high speed, –6
low power instruments. An output disable pin allows further 0.1M 1M 10M 100M 1G
FREQUENCY (Hz)
reduction of the quiescent supply current to 1.3 mA.
Figure 2. Small Signal Frequency Response

Rev. F
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 www.analog.com
Trademarks and registered trademarks are the property of their respective owners. Fax: 781.461.3113 ©2006 Analog Devices, Inc. All rights reserved.
AD8021

TABLE OF CONTENTS
Features .............................................................................................. 1 Applications..................................................................................... 19

Applications....................................................................................... 1 Using the Disable Feature.......................................................... 20

General Description ......................................................................... 1 Theory of Operation ...................................................................... 21

Connection Diagram ....................................................................... 1 PCB Layout Considerations...................................................... 21

Revision History ............................................................................... 2 Driving 16-Bit ADCs ................................................................. 22

Specifications..................................................................................... 3 Differential Driver...................................................................... 22

Absolute Maximum Ratings............................................................ 7 Using the AD8021 in Active Filters ......................................... 23

Maximum Power Dissipation ..................................................... 7 Driving Capacitive Loads.......................................................... 23

ESD Caution.................................................................................. 7 Outline Dimensions ....................................................................... 25

Pin Configuration and Function Descriptions............................. 8 Ordering Guide .......................................................................... 25

Typical Performance Characteristics ............................................. 9

Test Circuits................................................................................. 17

REVISION HISTORY
5/06—Rev. E to Rev. F 7/03—Rev. B to Rev. C
Updated Format..................................................................Universal Deleted All References to Evaluation Board...................Universal
Changes to General Description .................................................... 1 Replaced Figure 2 ..............................................................................5
Changes to Figure 3.......................................................................... 7 Updated Outline Dimensions....................................................... 20
Changes to Figure 60...................................................................... 19
Changes to Table 9.......................................................................... 23 2/03—Rev. A to Rev. B
Edits to Evaluation Board Applications....................................... 20
3/05—Rev. D to Rev. E Edits to Figure 17 ........................................................................... 20
Updated Format..................................................................Universal
Change to Figure 19 ....................................................................... 11 6/02—Rev. 0 to Rev. A
Change to Figure 25 ....................................................................... 12 Edits to Specifications .......................................................................2
Change to Table 7 and Table 8 ...................................................... 22
Change to Driving 16-Bit ADCs Section .................................... 22

10/03—Rev. C to Rev. D
Updated Format..................................................................Universal

Rev. F | Page 2 of 28
 AD8021

SPECIFICATIONS
VS = ±5 V, @ TA = 25°C, RL = 1 kΩ, gain = +2, unless otherwise noted.
Table 1.
AD8021AR/AD8021ARM
Parameter Conditions Min Typ Max Unit
DYNAMIC PERFORMANCE
−3 dB Small Signal Bandwidth G = +1, CC = 10 pF, VO = 0.05 V p-p 355 490 MHz
G = +2, CC = 7 pF, VO = 0.05 V p-p 160 205 MHz
G = +5, CC = 2 pF, VO = 0.05 V p-p 150 185 MHz
G = +10, CC = 0 pF, VO = 0.05 V p-p 110 150 MHz
Slew Rate, 1 V Step G = +1, CC = 10 pF 95 120 V/μs
G = +2, CC = 7 pF 120 150 V/μs
G = +5, CC = 2 pF 250 300 V/μs
G = +10, CC = 0 pF 380 420 V/μs
Settling Time to 0.01% VO = 1 V step, RL = 500 Ω 23 ns
Overload Recovery (50%) ±2.5 V input step, G = +2 50 ns
DISTORTION/NOISE PERFORMANCE
f = 1 MHz
HD2 VO = 2 V p-p −93 dBc
HD3 VO = 2 V p-p −108 dBc
f = 5 MHz
HD2 VO = 2 V p-p −70 dBc
HD3 VO = 2 V p-p −80 dBc
Input Voltage Noise f = 50 kHz 2.1 2.6 nV/√Hz
Input Current Noise f = 50 kHz 2.1 pA/√Hz
Differential Gain Error NTSC, RL = 150 Ω 0.03 %
Differential Phase Error NTSC, RL = 150 Ω 0.04 Degrees
DC PERFORMANCE
Input Offset Voltage 0.4 1.0 mV
Input Offset Voltage Drift TMIN to TMAX 0.5 μV/°C
Input Bias Current +Input or −input 7.5 10.5 μA
Input Bias Current Drift 10 nA/°C
Input Offset Current 0.1 0.5 ±μA
Open-Loop Gain 82 86 dB
INPUT CHARACTERISTICS
Input Resistance 10 MΩ
Common-Mode Input Capacitance 1 pF
Input Common-Mode Voltage Range −4.1 to +4.6 V
Common-Mode Rejection Ratio VCM = ±4 V −86 −98 dB
OUTPUT CHARACTERISTICS
Output Voltage Swing −3.5 to +3.2 −3.8 to +3.4 V
Linear Output Current 60 mA
Short-Circuit Current 75 mA
Capacitive Load Drive for 30% Overshoot VO = 50 mV p-p/1 V p-p 15/120 pF
DISABLE CHARACTERISTICS
Off Isolation f = 10 MHz −40 dB
Turn-On Time VO = 0 V to 2 V, 50% logic to 50% output 45 ns
Turn-Off Time VO = 0 V to 2 V, 50% logic to 50% output 50 ns
DISABLE Voltage—Off/On VDISABLE − VLOGIC REFERENCE 1.75/1.90 V
Enabled Leakage Current LOGIC REFERENCE = 0.4 V 70 μA
DISABLE = 4.0 V 2 μA

Rev. F | Page 3 of 28
AD8021
AD8021AR/AD8021ARM
Parameter Conditions Min Typ Max Unit
Disabled Leakage Current LOGIC REFERENCE = 0.4 V 30 μA
DISABLE = 0.4 V 33 μA
POWER SUPPLY
Operating Range ±2.25 ±5 ±12.0 V
Quiescent Current Output enabled 7.0 7.7 mA
Output disabled 1.3 1.6 mA
+Power Supply Rejection Ratio VCC = 4 V to 6 V, VEE = −5 V −86 −95 dB
−Power Supply Rejection Ratio VCC = 5 V, VEE = −6 V to −4 V −86 −95 dB

VS = ±12 V, @ TA = 25°C, RL = 1 kΩ, gain = +2, unless otherwise noted.

Table 2.
AD8021AR/AD8021ARM
Parameter Conditions Min Typ Max Unit
DYNAMIC PERFORMANCE
−3 dB Small Signal Bandwidth G = +1, CC = 10 pF, VO = 0.05 V p-p 520 560 MHz
G = +2, CC = 7 pF, VO = 0.05 V p-p 175 220 MHz
G = +5, CC = 2 pF, VO = 0.05 V p-p 170 200 MHz
G = +10, CC = 0 pF, VO = 0.05 V p-p 125 165 MHz
Slew Rate, 1 V Step G = +1, CC = 10 pF 105 130 V/μs
G = +2, CC = 7 pF 140 170 V/μs
G = +5, CC = 2 pF 265 340 V/μs
G = +10, CC = 0 pF 400 460 V/μs
Settling Time to 0.01% VO = 1 V step, RL = 500 Ω 21 ns
Overload Recovery (50%) ±6 V input step, G = +2 90 ns
DISTORTION/NOISE PERFORMANCE
f = 1 MHz
HD2 VO = 2 V p-p −95 dBc
HD3 VO = 2 V p-p −116 dBc
f = 5 MHz
HD2 VO = 2 V p-p −71 dBc
HD3 VO = 2 V p-p −83 dBc
Input Voltage Noise f = 50 kHz 2.1 2.6 nV/√Hz
Input Current Noise f = 50 kHz 2.1 pA/√Hz
Differential Gain Error NTSC, RL = 150 Ω 0.03 %
Differential Phase Error NTSC, RL = 150 Ω 0.04 Degrees
DC PERFORMANCE
Input Offset Voltage 0.4 1.0 mV
Input Offset Voltage Drift TMIN to TMAX 0.2 μV/°C
Input Bias Current +Input or −input 8 11.3 μA
Input Bias Current Drift 10 nA/°C
Input Offset Current 0.1 0.5 ±μA
Open-Loop Gain 84 88 dB
INPUT CHARACTERISTICS
Input Resistance 10 MΩ
Common-Mode Input Capacitance 1 pF
Input Common-Mode Voltage Range −11.1 to +11.6 V
Common-Mode Rejection Ratio VCM = ±10 V −86 −96 dB

Rev. F | Page 4 of 28
 AD8021
AD8021AR/AD8021ARM
Parameter Conditions Min Typ Max Unit
OUTPUT CHARACTERISTICS
Output Voltage Swing −10.2 to +9.8 −10.6 to +10.2 V
Linear Output Current 70 mA
Short-Circuit Current 115 mA
Capacitive Load Drive for 30% Overshoot VO = 50 mV p-p/1 V p-p 15/120 pF
DISABLE CHARACTERISTICS
Off Isolation f = 10 MHz −40 dB
Turn-On Time VO = 0 V to 2 V, 50% logic to 50% output 45 ns
Turn-Off Time VO = 0 V to 2 V, 50% logic to 50% output 50 ns
DISABLE Voltage—Off/On VDISABLE − VLOGIC REFERENCE 1.80/1.95 V
Enabled Leakage Current LOGIC REFERENCE = 0.4 V 70 μA
DISABLE = 4.0 V 2 μA
Disabled Leakage Current LOGIC REFERENCE = 0.4 V 30 μA
DISABLE = 0.4 V 33 μA
POWER SUPPLY
Operating Range ±2.25 ±5 ±12.0 V
Quiescent Current Output enabled 7.8 8.6 mA
Output disabled 1.7 2.0 mA
+Power Supply Rejection Ratio VCC = 11 V to 13 V, VEE = −12 V −86 −96 dB
−Power Supply Rejection Ratio VCC = 12 V, VEE = −13 V to −11 V −86 −100 dB

VS = 5 V, @ TA = 25°C, RL = 1 kΩ, gain = +2, unless otherwise noted.

Table 3.
AD8021AR/AD8021ARM
Parameter Conditions Min Typ Max Unit
DYNAMIC PERFORMANCE
−3 dB Small Signal Bandwidth G = +1, CC = 10 pF, VO = 0.05 V p-p 270 305 MHz
G = +2, CC = 7 pF, VO = 0.05 V p-p 155 190 MHz
G = +5, CC = 2 pF, VO = 0.05 V p-p 135 165 MHz
G = +10, CC = 0 pF, VO = 0.05 V p-p 95 130 MHz
Slew Rate, 1 V Step G = +1, CC = 10 pF 80 110 V/μs
G = +2, CC = 7 pF 110 140 V/μs
G = +5, CC = 2 pF 210 280 V/μs
G = +10, CC = 0 pF 290 390 V/μs
Settling Time to 0.01% VO = 1 V step, RL = 500 Ω 28 ns
Overload Recovery (50%) 0 V to 2.5 V input step, G = +2 40 ns
DISTORTION/NOISE PERFORMANCE
f = 1 MHz
HD2 VO = 2 V p-p −84 dBc
HD3 VO = 2 V p-p −91 dBc
f = 5 MHz
HD2 VO = 2 V p-p −68 dBc
HD3 VO = 2 V p-p −81 dBc
Input Voltage Noise f = 50 kHz 2.1 2.6 nV/√Hz
Input Current Noise f = 50 kHz 2.1 pA/√Hz

Rev. F | Page 5 of 28
AD8021
AD8021AR/AD8021ARM
Parameter Conditions Min Typ Max Unit
DC PERFORMANCE
Input Offset Voltage 0.4 1.0 mV
Input Offset Voltage Drift TMIN to TMAX 0.8 μV/°C
Input Bias Current +Input or −input 7.5 10.3 μA
Input Bias Current Drift 10 nA/°C
Input Offset Current 0.1 0.5 ±μA
Open-Loop Gain 72 76 dB
INPUT CHARACTERISTICS
Input Resistance 10 MΩ
Common-Mode Input Capacitance 1 pF
Input Common-Mode Voltage Range 0.9 to 4.6 V
Common-Mode Rejection Ratio 1.5 V to 3.5 V −84 −98 dB
OUTPUT CHARACTERISTICS
Output Voltage Swing 1.25 to 3.38 1.10 to 3.60 V
Linear Output Current 30 mA
Short-Circuit Current 50 mA
Capacitive Load Drive for 30% Overshoot VO = 50 mV p-p/1 V p-p 10/120 pF
DISABLE CHARACTERISTICS
Off Isolation f = 10 MHz −40 dB
Turn-On Time VO = 0 V to 1 V, 50% logic to 50% output 45 ns
Turn-Off Time VO = 0 V to 1 V, 50% logic to 50% output 50 ns
DISABLE Voltage—Off/On VDISABLE − VLOGIC REFERENCE 1.55/1.70 V
Enabled Leakage Current LOGIC REFERENCE = 0.4 V 70 μA
DISABLE = 4.0 V 2 μA
Disabled Leakage Current LOGIC REFERENCE = 0.4 V 30 μA
DISABLE = 0.4 V 33 μA
POWER SUPPLY
Operating Range ±2.25 ±5 ±12.0 V
Quiescent Current Output enabled 6.7 7.5 mA
Output disabled 1.2 1.5 mA
+Power Supply Rejection Ratio VCC = 4.5 V to 5.5 V, VEE = 0 V −74 −82 dB
−Power Supply Rejection Ratio VCC = 5 V, VEE = −0.5 V to +0.5 V −76 −84 dB

Rev. F | Page 6 of 28
 AD8021

ABSOLUTE MAXIMUM RATINGS

Table 4. MAXIMUM POWER DISSIPATION
Parameter Rating
The maximum power that can be safely dissipated by the
Supply Voltage 26.4 V
AD8021 is limited by the associated rise in junction tempera-
Power Dissipation Observed power
derating curves ture. The maximum safe junction temperature for plastic
Input Voltage (Common Mode) ±VS ± 1 V encapsulated devices is determined by the glass transition
Differential Input Voltage1 ±0.8 V temperature of the plastic, approximately 150°C. Temporarily
Differential Input Current ±10 mA exceeding this limit can cause a shift in parametric performance
Output Short-Circuit Duration Observed power due to a change in the stresses exerted on the die by the package.
derating curves Exceeding a junction temperature of 175°C for an extended
Storage Temperature Range −65°C to +125°C period can result in device failure.
Operating Temperature Range −40°C to +85°C
While the AD8021 is internally short-circuit protected, this can
Lead Temperature (Soldering, 10 sec) 300°C
not be sufficient to guarantee that the maximum junction tem-
1
perature (150°C) is not exceeded under all conditions. To ensure
The AD8021 inputs are protected by diodes. Current-limiting resistors are
not used to preserve the low noise. If a differential input exceeds ±0.8 V, the proper operation, it is necessary to observe the maximum
input current should be limited to ±10 mA. power derating curves.
Stresses above those listed under Absolute Maximum Ratings 2.0

may cause permanent damage to the device. This is a stress

MAXIMUM POWER DISSIPATION (W)

rating only; functional operation of the device at these or any
other conditions above those indicated in the operational 1.5
8-LEAD SOIC
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability. 1.0

8-LEAD MSOP

0.5

01888-004
0.01
–55 –45 –35 –25 –15 –5 5 15 25 35 45 55 65 75 85
AMBIENT TEMPERATURE (°C)

Figure 3. Maximum Power Dissipation vs. Temperature 1

1
Specification is for device in free air: 8-lead SOIC: θJA = 125°C/W; 8-lead
MSOP: θJA = 145°C/W.

ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

Rev. F | Page 7 of 28
AD8021

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

LOGIC AD8021
1 8 DISABLE
REFERENCE
–IN 2 7 +VS

+IN 3 6 VOUT

01888-003
–VS 4 5 CCOMP

Figure 4. Pin Configuration

Table 5. Pin Function Descriptions

Pin No. Mnemonic Description
1 LOGIC REFERENCE Reference for Pin 8 1 Voltage Level. Connect to logic low supply.
2 −IN Inverting Input.
3 +IN Noninverting Input.
4 −VS Negative Supply Voltage.
5 CCOMP Compensation Capacitor. Tie to −VS. (See the Applications section for value.)
6 VOUT Output.
7 +VS Positive Supply Voltage.
8 DISABLE Disable, Active Low.
1
When Pin 8 (DISABLE) is higher than Pin 1 (LOGIC REFERENCE) by approximately 2 V or more, the part is enabled. When Pin 8 is brought down to within about 1.5 V of
Pin 1, the part is disabled. (See the Specifications tables for exact disable and enable voltage levels.) If the disable feature is not going to be used, Pin 8 can be tied to
+VS or a logic high source, and Pin 1 can be tied to ground or logic low. Alternatively, if Pin 1 and Pin 8 are not connected, the part is in an enabled state.

Rev. F | Page 8 of 28
 AD8021

TYPICAL PERFORMANCE CHARACTERISTICS

TA = 25°C, VS = ±5 V, RL = 1 kΩ, G = +2, RF = RG = 499 Ω, RS = 49.9 Ω, RO = 976 Ω, RD = 53.6 Ω, CC = 7 pF, CL = 0, CF = 0, VOUT = 2 V p-p,
frequency = 1 MHz, unless otherwise noted.
24 9
G = +2
G = +10, RF = 1kΩ, RG = 110Ω, CC = 0pF VS = ±2.5V
21 8
VS = ±5V
18 7
CLOSED-LOOP GAIN (dB)

15 G = +5, RF = 1kΩ, RG = 249Ω, CC = 2pF 6

12 5

GAIN (dB)
9 4
G = +2, RF = RG = 499Ω, CC = 7pF
6 3 VS = ±12V

3 2
G = +1, RF = 75Ω, CC = 10pF
0 1 VS = ±2.5V

01888-008
01888-005
–3 0

–6 –1
0.1M 1M 10M 100M 1G 1M 10M 100M 1G
FREQUENCY (Hz) FREQUENCY (Hz)

Figure 5. Small Signal Frequency Response vs. Frequency and Gain, Figure 8. Small Signal Frequency Response vs. Frequency and Supply,
VOUT = 50 mV p-p, Noninverting (See Figure 48) VOUT = 50 mV p-p, Noninverting (See Figure 48)

24 3
G = –1
21 2 VS = ±2.5V
VS = ±5V
G = –10, RF = 1kΩ, RG = 100Ω, 1
18
RIN = 100Ω, CC = 0pF
15 0
G = –5, RF = 1kΩ, RG = 200Ω, –1
12 VS = ±12V
GAIN (dB)
GAIN (dB)

RIN = 66.5Ω, CC = 1.5pF

9 –2

6 –3
G = –2, RF = 499Ω, RG = 249Ω,
3 RIN = 63.4Ω, CC = 4pF –4

0 –5
G = –1, RF = 499Ω, RG = 499Ω,
VS = ±2.5V

01888-009
01888-006

–3 RIN = 56.2Ω, CC = 7pF –6

–6 –7
0.1M 1M 10M 100M 1G 1M 10M 100M 1G
FREQUENCY (Hz) FREQUENCY (Hz)

Figure 6. Small Signal Frequency Response vs. Frequency and Figure 9. Small Signal Frequency Response vs. Frequency and Supply,
Gain, VOUT = 50 mV p-p Inverting (See Figure 48) VOUT = 50 mV p-p, Inverting (See Figure 50)

9 9
G = +2 CC = 5pF G = +2
8 8

7 7 VOUT = 0.1V AND 50mV p-p

CC = 7pF
6 6
GAIN (dB)

5 5
GAIN (dB)

CC = 9pF
4 4
VOUT = 4V p-p
3 3

2 2
VOUT = 1V p-p
1 CC = 7pF 1
01888-010
01888-007

0 CC = 9pF 0

–1 –1
0.1M 1M 10M 100M 1G 1M 10M 100M 1G
FREQUENCY (Hz) FREQUENCY (Hz)

Figure 7. Small Signal Frequency Response vs. Frequency and Figure 10. Frequency Response vs. Frequency and VOUT, Noninverting
Compensation Capacitor, VOUT = 50 mV p-p (See Figure 48) (See Figure 48)

Rev. F | Page 9 of 28
AD8021
10 10
G = +2 G = +2 RF = 1kΩ
9 9 RF = RG
RF = 499Ω
8 8

7 7
RF = 250Ω

GAIN (dB)
6 6
GAIN (dB)

RF = 150Ω
5 5

4 4
RL = 1kΩ
3 3
RL = 100Ω
2 2 RF = 75Ω

01888-014
01888-011
1 1
RF = 1kΩ AND CF = 2.2pF
0 0
0.1M 1M 10M 100M 1G 0.1M 1M 10M 100M 1G
FREQUENCY (Hz) FREQUENCY (Hz)

Figure 11. Large Signal Frequency Response vs. Frequency and Figure 14. Small Signal Frequency Response vs. Frequency and RF,
Load, Noninverting (See Figure 49) Noninverting, VOUT = 50 mV p-p (See Figure 48)

9 15
G = +2 +85°C G = +2
8 12
+25°C
7 9

6 6

5 –40°C VOUT = 3
GAIN (dB)

GAIN (dB)
50mV p-p RS = 49.9Ω
4 +85°C 0

3 VOUT = –3
2V p-p
2 –6 RS = 100Ω

1 +25°C –9
RS = 249Ω
01888-012

01888-015
–40°C –12

–1 –15
1M 10M 100M 1G 0.1M 1M 10M 100M 1G
FREQUENCY (Hz) FREQUENCY (Hz)

Figure 12. Frequency Response vs. Frequency, Temperature, and Figure 15. Small Signal Frequency Response vs. Frequency and RS,
VOUT, Noninverting (See Figure 48) Noninverting, VOUT = 50 mV p-p (See Figure 48)

18 100
G = +2 50pF
15 30pF 90

12 80
20pF
9
OPEN-LOOP GAIN (dB)

70 180
10pF

PHASE (Degrees)
6 60 135
GAIN (dB)

3 50 90
0pF
0 40 45

–3 30 0

–6 20 –45
01888-013

–9
01888-016

10 –90

–12 0 –135
1M 10M 100M 1G
10k 100k 1M 10M 100M 1G
FREQUENCY (Hz)
FREQUENCY (Hz)

Figure 13. Small Signal Frequency Response vs. Figure 16. Open-Loop Gain and Phase vs. Frequency, RG = 100 Ω,
Frequency and Capacitive Load, Noninverting, VOUT = 50 mV p-p RF = 1 kΩ, RO = 976 Ω, RD = 53.6 Ω, CC = 0 pF (See Figure 50)
(See Figure 49 and Figure 71)

Rev. F | Page 10 of 28
 AD8021
6.4 –20
G = +2
–30
VS = ±2.5V
6.2 –40
f1 f2
–50
Δf = 0.2MHz POUT
6.0 –60

POUT (dBm)
GAIN (dB)

976Ω
–70
VS = ±5V 53.6Ω 50Ω
5.8 VS = ±12V
–80

–90

5.6 –100

01888-017

01888-020
–110

5.4 –120
1M 10M 100M 9.5 9.7 10.0 10.3 10.5
FREQUENCY (Hz) FREQUENCY (MHz)

Figure 17. 0.1 dB Flatness vs. Frequency and Supply, VOUT = 1 V p-p, Figure 20. Intermodulation Distortion vs. Frequency
RL = 150 Ω, Noninverting (See Figure 49)

–20 50

–30

–40 45

THIRD-ORDER INTERCEPT (dBm)

–50 SECOND
40
DISTORTION (dBc)

–60
VS = ±5V
–70
RL = 100Ω 35
–80
RL = 1kΩ VS = ±2.5V
–90
30
–100

–110 25
01888-018

01888-021
–120 THIRD
–130 20
0.1M 1M 10M 20M 0 5 10 15 20
FREQUENCY (Hz) FREQUENCY (MHz)

Figure 18. Second and Third Harmonic Distortion vs. Frequency and RL Figure 21. Third-Order Intercept vs. Frequency and Supply Voltage

–30 –50

–40
–60
–50

–60 –70
SECOND
DISTORTION (dBc)
DISTORTION (dBc)

–70 THIRD
SECOND –80 RL = 100Ω
VS = ±2.5V
–80
THIRD
–90
–90 SECOND
SECOND
–100 –100
VS = ±5V RL = 1kΩ
–110
VS = ±12V –110
01888-019

–120 SECOND
01888-022

THIRD
THIRD
–130 –120
100k 1M 10M 20M 1 2 3 4 5 6
FREQUENCY (Hz) VOUT (V p-p)

Figure 19. Second and Third Harmonic Distortion vs. Frequency and VS Figure 22. Second and Third Harmonic Distortion vs. VOUT and RL

Rev. F | Page 11 of 28
AD8021
–50 3.5 –3.1

–60 3.4 –3.2

NEGATIVE OUTPUT VOLTAGE (V)

POSITIVE OUTPUT VOLTAGE (V)
SECOND POSITIVE OUTPUT
–70 3.3 –3.3
DISTORTION (dBc)

fC = 5MHz
–80 3.2 –3.4
THIRD
–90 SECOND 3.1 –3.5

–100 fC = 1MHz 3.0 –3.6

–110 2.9 –3.7

01888-023
NEGATIVE OUTPUT

01888-026
THIRD

–120 2.8 –3.8

1 2 3 4 5 6 0 400 800 1200 1600 2000
VOUT (V p-p) LOAD (Ω)

Figure 23. Second and Third Harmonic Distortion vs. VOUT and Figure 26. DC Output Voltages vs. Load (See Figure 48)
Fundamental Frequency (fC), G = +2

–40 120

–50
fC = 5MHz 100 VS = ±12V

SHORT-CIRCUIT CURRENT (mA)

–60 SECOND
DISTORTION (dBc)

80 VS = ±5.0V
–70
THIRD 60
–80 VS = ±2.5V
SECOND
40
–90 fC = 1MHz

THIRD 20
–100
01888-024

01888-027
–110 0
1 2 3 4 5 6 –50 –30 –10 10 30 50 70 90 110
VOUT (V p-p)
TEMPERATURE (°C)

Figure 24. Second and Third Harmonic Distortion vs. VOUT and Figure 27. Short-Circuit Current to Ground vs. Temperature
Fundamental Frequency (fC), G = +10

–70 50
fC = 1MHz G=2
RL = 1kΩ 40
RF = RG RL = 1kΩ, 150Ω
–80 30
G = +2
20
DISTORTION (dBc)

–90 10
VOUT (mV)

SECOND

–100 –10

–20
THIRD
–110 –30
01888-025

01888-028

–40

–120 –50
0 200 400 600 800 1000 0 40 80 120 160 200
FEEDBACK RESISTANCE (Ω) TIME (ns)

Figure 25. Second and Third Harmonic Distortion vs. Feedback Resistor (RF) Figure 28. Small Signal Transient Response vs.
RL, VO = 50 mV p-p, Noninverting (See Figure 49)

Rev. F | Page 12 of 28
 AD8021
VO = 4V p-p VO = 2V p-p
2.0 G=2 2.0 G=2

RL = 1kΩ
1.0 1.0
VOUT (V)

VOUT (V)
RL = 150Ω VS = ±2.5V

–1.0 –1.0
VS = ±5V

01888-029

01888-032
–2.0 –2.0

0 40 80 120 160 200 0 40 80 120 160 200

TIME (ns) TIME (ns)

Figure 29. Large Signal Transient Response vs. RL, Noninverting Figure 32. Large Signal Transient Response vs. VS (See Figure 48)
(See Figure 49)

5 VIN = ±3V
VO = 4V p-p
G = +2
4 G = –1
VIN = 1V/DIV VOUT, RL = 1kΩ
VOUT = 2V/DIV
3
VIN
2

1 RL = 150Ω
VOLTS

–1
VOUT
–2

–3

01888-033
01888-030

–4
VIN
–5 0 100 200 300 400 500
0 50 100 150 200 250
TIME (ns)
TIME (ns)

Figure 30. Large Signal Transient Response, Inverting (See Figure 50) Figure 33. Overdrive Recovery vs. RL (See Figure 49)

CL = 50pF VO = 4V p-p G=2

2.0 G=2

CL = 10pF, 0pF
1.0
OUTPUT SETTLING

+0.01%
VOUT (V)

–0.01%
25ns
–1.0
01888-034
01888-031

–2.0
VERT = 0.2mV/DIV HOR = 5ns/DIV

0 40 80 120 160 200

TIME (ns)

Figure 31. Large Signal Transient Response vs. CL (See Figure 48) Figure 34. 0.01% Settling Time, 2 V Step

Rev. F | Page 13 of 28
AD8021
100 100

80

INPUT CURRENT NOISE (pA/√Hz)

60

40
PULSE WIDTH = 120ns
SETTLING (µV)

20

0 10

–20
PULSE WIDTH = 300µs
–40

–60 5V

0V

01888-035
–80

01888-038
t1
–100 1
0 4 8 12 16 20 24 28 32 10 100 1k 10k 100k 1M 10M
TIME (µs) FREQUENCY (Hz)

Figure 35. Long-Term Settling, 0 V to 5 V, VS = ±12 V, G = +13 Figure 38. Input Current Noise vs. Frequency

50 0.48
G = +1
40
0.44
30

VOLTAGE OFFSET (mV)

20
0.40
10
VOUT (mV)

0.36

–10
0.32
–20

–30
0.28

01888-039
01888-036

–40

–50 0.24
0 40 80 120 160 200 –50 –25 0 25 50 75 100
TIME (ns) TEMPERATURE (°C)

Figure 36. Small Signal Transient Response, VO = 50 mV p-p, G = +1 Figure 39. VOS vs. Temperature
(See Figure 48)

100 8.4

8.0
VOLTAGE NOISE (nV/ √ Hz)

INPUT BIAS CURRENT (μA)

7.6

10 7.2

6.8

2.1nV/ √Hz
6.4
01888-037

01888-040

1 6.0
10 100 1k 10k 100k 1M 10M –50 –25 0 25 50 75 100
FREQUENCY (Hz)
TEMPERATURE (°C)

Figure 37. Input Voltage Noise vs. Frequency Figure 40. Input Bias Current vs. Temperature

Rev. F | Page 14 of 28
 AD8021
–20 0

–30 –10

–40 –20

DISABLED ISOLATION (dB)

–50 –30

–60 –40
CMRR (dB)

–70 –50

–80 –60

–90 –70

–100 –80

01888-044
01888-041
–110 –90

–120 –100
10k 100k 1M 10M 100M 0.1M 1M 10M 100M 1G
FREQUENCY (Hz) FREQUENCY (Hz)

Figure 41. CMRR vs. Frequency (See Figure 51) Figure 44. Input-to-Output Isolation, Chip Disabled (See Figure 54)

300 300k

100 100k

30 30k
OUTPUT IMPEDANCE (Ω)

OUTPUT IMPEDANCE (Ω)

10 10k

3 3k

1 1k

0.3 300

0.1 100

0.03 30
01888-042

01888-045
0.01 10

0.003 3
10k 100k 1M 10M 100M 1G 10k 100k 1M 10M 100M 1G
FREQUENCY (Hz) FREQUENCY (Hz)

Figure 42. Output Impedance vs. Frequency, Chip Enabled Figure 45. Output Impedance vs. Frequency, Chip Disabled
(See Figure 52) (See Figure 55)

0
DISABLE
4V –10
2V –20 –PSRR

–30

–40
PSRR (dB)

VOUTPUT
VS = ±2.5V +PSRR
2V –50

–60 VS = ±12V
tEN = 45ns
1V –70
tDIS = 50ns
VS = ±5V
–80
01888-043

–90
01888-046

–100
0 100 200 300 400 500 10k 100k 1M 10M 100M 500M
TIME (ns) FREQUENCY (Hz)

Figure 43. Enable (tEN)/Disable (tDIS) Time vs. VOUT (See Figure 53) Figure 46. PSRR vs. Frequency and Supply Voltage
(See Figure 56 and Figure 57)

Rev. F | Page 15 of 28
AD8021
8.5

8.0
SUPPLY CURRENT (mA)

7.5

7.0

6.5

6.0

01888-047
5.5
–50 –25 0 25 50 75 100
TEMPERATURE (°C)

Figure 47. Quiescent Supply Current vs. Temperature

Rev. F | Page 16 of 28
 AD8021

TEST CIRCUITS
+VS AD8021
50Ω CABLE RS HP8753D
50Ω CABLE +VS
RO NETWORK
50Ω
ANALYZER
5
RIN CC 100Ω
RD 5 50Ω
49.9Ω CC
–VS

RG RF 7pF
–VS

01888-048
CF RG RF

01888-052
499Ω 499Ω

Figure 48. Noninverting Gain Figure 52. Output Impedance, Chip Enabled

FET AD8021
PROBE
+VS +VS
50Ω CABLE RS 49.9Ω

50Ω 1
5 1.0V 49.9Ω 976Ω
LOGIC REF
CL
RIN
RL 8 DISABLE 5 53.6Ω
49.9Ω
CC CC
–VS 4V 49.9Ω

RF –VS 7pF
RG
01888-049

499Ω 499Ω

01888-053
CF

Figure 49. Noninverting Gain and FET Probe Figure 53. Enable/Disable

+VS
HP8753D
RO 50Ω CABLE NETWORK
49.9Ω ANALYZER
5

RD
50Ω 50Ω
50Ω CABLE –VS CC
50Ω CABLE
+VS
50Ω RIN RG RF
49.9Ω
01888-050

49.9Ω AD8021 FET

1 PROBE
49.9Ω
LOGIC REF
Figure 50. Inverting Gain 8 DISABLE
5 1kΩ

CC
HP8753D –VS 7pF

01888-054
NETWORK
499Ω 499Ω
ANALYZER

50Ω 50Ω
Figure 54. Input-to-Output Isolation, Chip Disabled

AD8021
49.9Ω
+VS AD8021 HP8753D
499Ω
1 +VS
8 NETWORK
499Ω 5 ANALYZER
CC 100Ω
5 50Ω
7pF
–VS
CC
01888-055

499Ω 499Ω 7pF

01888-051

55.6Ω –VS

Figure 55. Output Impedance, Chip Disabled

Figure 51. CMRR

Rev. F | Page 17 of 28
AD8021
BIAS BIAS HP8753D
BNC HP8753D BNC
NETWORK
NETWORK
ANALYZER
ANALYZER 50Ω
50Ω

50Ω
+VS 50Ω –VS

50Ω CABLE
50Ω CABLE
+VS
49.9Ω, 5W
976Ω
+VS 249Ω
5
976Ω 53.6Ω
249Ω
5 53.6Ω CC
–VS
7pF
CC 49.9Ω
–VS 7pF 5W

499Ω 499Ω
01888-056 499Ω

01888-057
499Ω

Figure 56. Positive PSRR Figure 57. Negative PSRR

Rev. F | Page 18 of 28
 AD8021

APPLICATIONS
The typical voltage feedback op amp is frequency stabilized degraded to about 20 MHz and the phase margin increases to
with a fixed internal capacitor, CINTERNAL, using dominant pole 90° (Arrow B). However, by reducing CC to 0 pF, the bandwidth
compensation. To a first-order approximation, voltage feedback and phase margin return to about 200 MHz and 60° (Arrow C),
op amps have a fixed gain bandwidth product. For example, if respectively. In addition, the slew rate is dramatically increased,
its −3 dB bandwidth is 200 MHz for a gain of G = +1; at a gain as it roughly varies with the inverse of CC.
of G = +10, its bandwidth is only about 20 MHz. The AD8021 is 10

a voltage feedback op amp with a minimal CINTERNAL of about 9

COMPENSATION CAPACITANCE (pF)

1.5 pF. By adding an external compensation capacitor, CC, the
8
user can circumvent the fixed gain bandwidth limitation of
7
other voltage feedback op amps.
6
Unlike the typical op amp with fixed compensation, the 5
AD8021 allows the user to:
4

• Maximize the amplifier bandwidth for closed-loop gains 3

between 1 and 10, avoiding the usual loss of bandwidth 2

and slew rate.

01888-059
1

• Optimize the trade-off between bandwidth and phase 0

1 2 3 4 5 6 7 8 9 10 11
margin for a particular application. NOISE GAIN (V/V)

Figure 59. Suggested Compensation Capacitance vs. Gain for

• Match bandwidth in gain blocks with different noise gains, Maintaining 1 dB Peaking
such as when designing differential amplifiers (as shown in
Table 6 and Figure 59 provide recommended values of com-
Figure 65).
pensation capacitance at various gains and the corresponding
110 180 slew rate, bandwidth, and noise. Note that the value of the
100 135 compensation capacitor depends on the circuit noise gain, not
90 90 the voltage gain. As shown in Figure 60, the noise gain, GN, of
86
80 (B) (A) 45
CC = 0pF an op amp gain block is equal to its noninverting voltage gain,
OPEN-LOOP GAIN (dB)

(C)
70 CC = 10pF 0 regardless of whether it is actually used for inverting or nonin-
PHASE (Degrees)

60
verting gain. Thus,
50
40
Noninverting GN = RF/RG + 1
(C) Inverting GN = RF/RG + 1
30
20
RG RF
10 RS 249Ω 1kΩ
(B) 3
1 +
01888-058

0
(A) 2
6 –
–10 AD8021
1k 10k 100k 1M 10M 100M 1G 10G
6
FREQUENCY (Hz) 2 5 AD8021
–
Figure 58. Simplified Diagram of Open-Loop Gain and Phase Response –VS RF 5
3
1kΩ + G = –4
–VS GN = +5
CCOMP
Figure 58 is the AD8021 gain and phase plot that has been
G = GN = +5 RG CCOMP
simplified for instructional purposes. Arrow A in Figure 58
01888-060

249Ω
shows a bandwidth of about 200 MHz and a phase margin at NONINVERTING INVERTING
about 60° when the desired closed-loop gain is G = +1 and Figure 60. The Noise Gain of Both is 5
the value chosen for the external compensation capacitor is
CC = 10 pF. If the gain is changed to G = +10 and CC is fixed at
10 pF, then (as expected for a typical op amp) the bandwidth is

Rev. F | Page 19 of 28
AD8021
CF = CL = 0, RL = 1 kΩ, RIN = 49.9 Ω (see Figure 49).
Table 6. Recommended Component Values
Noise Gain −3 dB Output Noise Output Noise
(Noninverting SS BW (AD8021 Only) (AD8021 with Resistors)
Gain) RS (Ω) RF (Ω) RG (Ω) CCOMP (pF) Slew Rate (V/μs) (MHz) (nV/√Hz) (nV/√Hz)
1 75 75 NA 10 120 490 2.1 2.8
2 49.9 499 499 7 150 205 4.3 8.2
5 49.9 1k 249 2 300 185 10.7 15.5
10 49.9 1k 110 0 420 150 21.2 27.9
20 49.9 1k 52.3 0 200 42 42.2 52.7
100 49.9 1k 10 0 34 6 211.1 264.1

With the AD8021, a variety of trade-offs can be made to fine- Additionally, any resistance in series with the source creates a
tune its dynamic performance. Sometimes more bandwidth pole with the input capacitance (as well as dampen high
or slew rate is needed at a particular gain. Reducing the frequency resonance due to package and board inductance
compensation capacitance, as illustrated in Figure 7, increases and capacitance), the effect of which is shown in Figure 15.
the bandwidth and peaking due to a decrease in phase margin.
On the other hand, if more stability is needed, increasing the It must also be noted that increasing resistor values increases
compensation capacitor decreases the bandwidth while the overall noise of the amplifier and that reducing the feedback
increasing the phase margin. resistor value increases the load on the output stage, thus
increasing distortion (see Figure 22).
As with all high speed amplifiers, parasitic capacitance and
inductance around the amplifier can affect its dynamic USING THE DISABLE FEATURE
response. Often, the input capacitance (due to the op amp itself, When Pin 8 (DISABLE) is higher than Pin 1 (LOGIC
as well as the PC board) has a significant effect. The feedback REFERENCE) by approximately 2 V or more, the part is
resistance, together with the input capacitance, can contribute enabled. When Pin 8 is brought down to within about 1.5 V
to a loss of phase margin, thereby affecting the high frequency of Pin 1, the part is disabled. See Table 1 for exact disable and
response, as shown in Figure 14. A capacitor (CF) in parallel enable voltage levels. If the disable feature is not used, Pin 8 can
with the feedback resistor can compensate for this phase loss. be tied to VS or a logic high source, and Pin 1 can be tied to
ground or logic low. Alternatively, if Pin 1 and Pin 8 are not
connected, the part is in an enabled state.

Rev. F | Page 20 of 28
 AD8021

THEORY OF OPERATION
The AD8021 is fabricated on the second generation of Analog PCB LAYOUT CONSIDERATIONS
Devices proprietary High Voltage eXtra-Fast Complementary As with all high speed op amps, achieving optimum performance
Bipolar (XFCB) process, which enables the construction of PNP from the AD8021 requires careful attention to PC board layout.
and NPN transistors with similar fTs in the 3 GHz region. The Particular care must be exercised to minimize lead lengths
transistors are dielectrically isolated from the substrate (and between the ground leads of the bypass capacitors and between
each other), eliminating the parasitic and latch-up problems the compensation capacitor and the negative supply. Otherwise,
caused by junction isolation. It also reduces nonlinear capaci- lead inductance can influence the frequency response and even
tance (a source of distortion) and allows a higher transistor, fT, cause high frequency oscillations. Use of a multilayer printed
for a given quiescent current. The supply current is trimmed, circuit board, with an internal ground plane, reduces ground
which results in less part-to-part variation of bandwidth, slew noise and enables a compact component arrangement.
rate, distortion, and settling time.
Due to the relatively high impedance of Pin 5 and low values of
As shown in Figure 61, the AD8021 input stage consists of an the compensation capacitor, a guard ring is recommended. The
NPN differential pair in which each transistor operates at a guard ring is simply a PC trace that encircles Pin 5 and is
0.8 mA collector current. This allows the input devices a high connected to the output, Pin 6, which is at the same potential as
transconductance; thus, the AD8021 has a low input noise of Pin 5. This serves two functions. It shields Pin 5 from any local
2.1 nV/√Hz @ 50 kHz. The input stage drives a folded cascode circuit noise generated by surrounding circuitry. It also
that consists of a pair of PNP transistors. The folded cascode minimizes stray capacitance, which would tend to otherwise
and current mirror provide a differential-to-single-ended reduce the bandwidth. An example of a guard ring layout is
conversion of signal current. This current then drives the high shown in Figure 62.
impedance node (Pin 5), where the CC external capacitor is
connected. The output stage preserves this high impedance with Also shown in Figure 62, the compensation capacitor is located
a current gain of 5000, so that the AD8021 can maintain a high immediately adjacent to the edge of the AD8021 package, spanning
open-loop gain even when driving heavy loads. Pin 4 and Pin 5. This capacitor must be a high quality surface-
mount COG or NPO ceramic. The use of leaded capacitors is
Two internal diode clamps across the inputs (Pin 2 and Pin 3) not recommended. The high frequency bypass capacitor(s)
protect the input transistors from large voltages that could should be located immediately adjacent to the supplies,
otherwise cause emitter-base breakdown, which would result in Pin 4 and Pin 7.
degradation of offset voltage and input bias current.
To achieve the shortest possible lead length at the inverting
+VS
input, the feedback resistor RF is located beneath the board and
spans the distance from the output, Pin 6, to inverting input
Pin 2. The return node of Resistor RG should be situated as close
as possible to the return node of the negative supply bypass
OUTPUT capacitor connected to Pin 4.
+IN
(TOP VIEW)
BYPASS
LOGIC REFERENCE 1 8 DISABLE CAPACITOR
CINTERNAL
1.5pF
–IN 2 +VS 7
–IN

–VS VOUT
+IN 3 6
GROUND
PLANE
01888-061

CCOMP CC
–VS 4 5 CCOMP

Figure 61. Simplified Schematic METAL

BYPASS
CAPACITOR
COMPENSATION
CAPACITOR
01888-062

GROUND
PLANE

Figure 62. Recommended Location of

Critical Components and Guard Ring

Rev. F | Page 21 of 28
AD8021
DRIVING 16-BIT ADCs Table 8. Summary of ADC Driver Performance
Low noise and adjustable compensation make the AD8021 (fC = 100 kHz, VOUT = 20 V p-p)
especially suitable as a buffer/driver for high resolution ADCs. Parameter Measurement Unit
Second Harmonic Distortion −92.6 dBc
As seen in Figure 19, the harmonic distortion is better than 90 dBc Third Harmonic Distortion −86.4 dBc
at frequencies between 100 kHz and 1 MHz. This is an THD −84.4 dBc
advantage for complex waveforms that contain high frequency SFDR +5.4 dBc
information, because the phase and gain integrity of the sampled
waveform can be preserved throughout the conversion process. DIFFERENTIAL DRIVER
The increase in loop gain results in improved output regulation
The AD8021 is uniquely suited as a low noise differential driver
and lower noise when the converter input changes state during
for many ADCs, balanced lines, and other applications requiring
a sample. This advantage is particularly apparent when using
differential drive. If pairs of internally compensated op amps are
16-bit high resolution ADCs with high sampling rates.
configured as inverter and follower, the noise gain of the inverter
Figure 63 shows a typical ADC driver configuration. The is higher than that of the follower section, resulting in an
AD8021 is in an inverting gain of −7.5, fC is 65 kHz, and its imbalance in the frequency response (see Figure 66).
output voltage is 10 V p-p. The results are listed in Table 7.
A better solution takes advantage of the external compensation
+12V feature of the AD8021. By reducing the CCOMP value of the
+5V
3
+
inverter, its bandwidth can be increased to match that of the
590Ω AD8021
6 IN follower, avoiding compromises in gain bandwidth and phase
2 5 HI
– delay. The inverting and noninverting bandwidths can be
CC
10pF closely matched using the compensation feature, thus
AD7665
16 BITS

570kSPS minimizing distortion.

RG RF
200Ω –12V 1.5kΩ
Figure 65 illustrates an inverter-follower driver circuit operating
50Ω
IN
at a gain of 2, using individually compensated AD8021s. The
56pF
01888-063

HI values of feedback and load resistors were selected to provide a

total load of less than 1 kΩ, and the equivalent resistances seen
Figure 63. Inverting ADC Driver, Gain = −7.5, fC = 65 kHz
at each op amp’s inputs were matched to minimize offset voltage
Table 7. Summary of ADC Driver Performance (fC = 65 kHz, and drift. Figure 67 is a plot of the resulting ac responses of
VOUT = 10 V p-p) driver halves.
Parameter Measurement Unit 249Ω 3 + G = +2
VIN
Second Harmonic Distortion −101.3 dBc
6
Third Harmonic Distortion −109.5 dBc 49.9Ω
AD8021
2 5
THD −100.0 dBc –

SFDR +100.3 dBc –VS 7pF

499Ω 499Ω
VOUT1
Figure 64 shows another ADC driver connection. The circuit 1kΩ
was tested with a noninverting gain of 10.1 and an output 232Ω 3 + G = –2

voltage of approximately 20 V p-p for optimum resolution and AD8021

6
VOUT2
noise performance. No filtering was used. An FFT was 2 5
1kΩ
–
performed using Analog Devices evaluation software for the –VS 5pF
AD7665 16-bit converter. The results are listed in Table 8.
01888-065

332Ω 664Ω
+12V
50Ω 3
+5V Figure 65. Differential Amplifier
+
50Ω 6 IN
50Ω AD8021
5 HI
2
– CC
16 BITS

RF AD7665
–12V 570kSPS
750Ω

RG ADC
82.5Ω
OPTIONAL CF
IN
01888-064

LO

Figure 64. Noninverting ADC Driver, Gain = 10, fC = 100 kHz

Rev. F | Page 22 of 28
 AD8021
12 C1

9 +VS
R1 R2
AD8021
VIN 3
6 6
VOUT
2 5
3 C2

0 G = –2 CC
GAIN (dB)

G = +2 –VS
–3
RF

01888-068
–6 RG

–9 Figure 68. Schematic of a Second-Order, Low-Pass Active Filter

–12
Table 9. Typical Component Values for Second-Order, Low-

01888-066
–15 Pass Active Filter of Figure 68
–18 Gain R1 R2 RF RG C1 C2 CC
100k 1M 10M 100M 1G
FREQUENCY (Hz)
(Ω) (Ω) (Ω) (Ω) (nF) (nF) (pF)
Figure 66. AC Response of Two Identically Compensated High Speed Op 2 71.5 215 499 499 10 10 7
Amps Configured for a Gain of +2 and a Gain of −2 5 44.2 365 365 90.9 10 10 2
12
50
9
40
6
30
3 G = ±2 20 G=5
0
10
GAIN (dB)

–3 GAIN (dB)
0
–6 G=2
–10
–9
–20
–12
–30
01888-067

–15

01888-069
–40
–18
100k 1M 10M 100M 1G –50
1k 10k 100k 1M 10M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 67. AC Response of Two Dissimilarly Compensated AD8021 Op Amps
Figure 69. Frequency Response of the Filter Circuit of Figure 68
(Figure 66) Configured for a Gain of +2 and a Gain of −2,
for Two Different Gains
(Note the Close Gain Match)

USING THE AD8021 IN ACTIVE FILTERS DRIVING CAPACITIVE LOADS

The low noise and high gain bandwidth of the AD8021 make it When the AD8021 drives a capacitive load, the high frequency
an excellent choice in active filter circuits. Most active filter response can show excessive peaking before it rolls off. Two
literature provides resistor and capacitor values for various techniques can be used to improve stability at high frequency
filters but neglects the effect of the op amp’s finite bandwidth on and reduce peaking. The first technique is to increase the
filter performance; ideal filter response with infinite loop gain is compensation capacitor, CC, which reduces the peaking while
implied. Unfortunately, real filters do not behave in this manner. maintaining gain flatness at low frequencies. The second
Instead, they exhibit finite limits of attenuation, depending on technique is to add a resistor, RSNUB, in series between the output
B

the gain bandwidth of the active device. Good low-pass filter pin of the AD8021 and the capacitive load, CL. Figure 70 shows
performance requires an op amp with high gain bandwidth for the response of the AD8021 when both CC and RSNUB are used to B

attenuation at high frequencies, and low noise and high dc gain reduce peaking. For a given CL, Figure 71 can be used to
for low frequency, pass-band performance. determine the value of RSNUB that maintains 2 dB of peaking in
B

the frequency response. Note, however, that using RSNUB attenuates

Figure 68 shows the schematic of a 2-pole, low-pass active filter the low frequency output by a factor of RLOAD/(RSNUB + RLOAD). B

and lists typical component values for filters having a Bessel-

type response with a gain of 2 and a gain of 5. Figure 69 is a
network analyzer plot of this filter’s performance.

Rev. F | Page 23 of 28
AD8021
18 20
+VS FET
PROBE
16 CC = 7pF; 18
5 RSNUB RSNUB = 0Ω
49.9Ω
14 16
49.9Ω 6 RL
33pF CC = 8pF;
12 1kΩ 14
–VS RSNUB = 0Ω
CC
10 12

R SNUB (Ω)
GAIN (dB)

499Ω
499Ω
8 10

6 8

4 6

2 4
CC = 8pF;

01888-070

01888-071
0 RSNUB = 17.4Ω 2

0
0.1 1.0 10 100 1000 0 5 10 15 20 25 30 35 40 45 50
FREQUENCY (MHz) CAPACITIVE LOAD (pF)

Figure 70. Peaking vs. RSNUB and CC for CL = 33 pF Figure 71. Relationship of RSNUB vs. CL for 2 dB Peaking at a Gain of +2
B

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 AD8021

OUTLINE DIMENSIONS
5.00 (0.1968)
4.80 (0.1890)

8 5
4.00 (0.1574) 6.20 (0.2440)
3.80 (0.1497) 1 4 5.80 (0.2284)

1.27 (0.0500) 0.50 (0.0196)

BSC 1.75 (0.0688) × 45°
0.25 (0.0099)
0.25 (0.0098) 1.35 (0.0532)
0.10 (0.0040)
0.51 (0.0201) 8°
COPLANARITY 0.25 (0.0098) 0° 1.27 (0.0500)
0.10 SEATING 0.31 (0.0122) 0.40 (0.0157)
PLANE 0.17 (0.0067)

COMPLIANT TO JEDEC STANDARDS MS-012-AA

CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.

Figure 72. 8-Lead Standard Small Outline Package [SOIC]

Narrow Body (R-8)
Dimensions shown in millimeters and (inches)

3.20
3.00
2.80

8 5 5.15
3.20
4.90
3.00
4.65
2.80 1
4

PIN 1
0.65 BSC
0.95
0.85 1.10 MAX
0.75
0.80
0.15 0.38 8° 0.60
0.23
0.00 0.22 0° 0.40
0.08
COPLANARITY SEATING
0.10 PLANE

COMPLIANT TO JEDEC STANDARDS MO-187-AA

Figure 73. 8-Lead Mini Small Outline Package [MSOP]

(RM-8)
Dimensions shown in millimeters

ORDERING GUIDE
Model Temperature Range Package Description Package Option Branding
AD8021AR −40°C to +85°C 8-Lead SOIC R-8
AD8021AR-REEL −40°C to +85°C 8-Lead SOIC R-8
AD8021AR-REEL7 −40°C to +85°C 8-Lead SOIC R-8
AD8021ARZ 1 −40°C to +85°C 8-Lead SOIC R-8
AD8021ARZ-REEL1 −40°C to +85°C 8-Lead SOIC R-8
AD8021ARZ-REEL71 −40°C to +85°C 8-Lead SOIC R-8
AD8021ARM −40°C to +85°C 8-Lead MSOP RM-8 HNA
AD8021ARM-REEL −40°C to +85°C 8-Lead MSOP RM-8 HNA
AD8021ARM-REEL7 −40°C to +85°C 8-Lead MSOP RM-8 HNA
AD8021ARMZ1 −40°C to +85°C 8-Lead MSOP RM-8 HNA#
AD8021ARMZ-REEL1 −40°C to +85°C 8-Lead MSOP RM-8 HNA#
AD8021ARMZ-REEL71 −40°C to +85°C 8-Lead MSOP RM-8 HNA#
1
Z = Pb-free part, # denotes lead-free product may be top or bottom marked.

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AD8021

NOTES

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 AD8021

NOTES

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AD8021

NOTES

©2006 Analog Devices, Inc. All rights reserved. Trademarks and

registered trademarks are the property of their respective owners.
C01888-0-5/06(F)

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