TRANSISTOR

EXPERIMENT 1
CHARACTERISTICS OF NMOS
NAME : Shivam Varshney
22BLC1365
OBJECTIVE:

To analyze the characteristics of NMOS transistor by visualizing ID v/s VDS graphs and draw
comparisons between the ideal and observed result.

TOOLS:

Linux operated computing system, application cadence Virtuoso -64

PROCEDURE:

● DC Analysis-

o In the black screen with dots, where you draw the schematic, draw the required circuits
for the given objectives using components from create → instance → browse.
o Save project. Check for error or warnings.
o To analyze the circuit, choose launch→ ADEL
o In analysis, choose DC analysis → save DC operating point→ check component
parameter.
o After checking component parameter, select component name.
o In analysis window, in sweep range, give start=0, stop = 1.8V. In sweep type, choose
linear→ step size = 0.2→OK.
o In virtuoso analog design environment window , select outputs → to be plotted → drain
of NMOS.
o Click on run button.
o Output graph is observed.

● Parametric analysis
o Same steps are repeated as done in DC analysis, only incorporating the following
changes.
o In the schematic, give the bias voltage supply as X volts.
o In the analysis window, select the component as the voltage supply VDC=1.8V
o Repeat the same steps, henceforth.
 o In virtuoso analog design environment window , select outputs → to be plotted → drain
of NMOS.
o Again in virtuoso analog design environment window, click variable
→ copy from cell view.
o Give name: X, Value : 1.8V → apply → OK
o Go to tools → parametric analysis.
o Add variable: X, Range (From/To): 0-1.8V
o Click on run button.
o Output graph is observed.

OBSERVATIONS:

Fig. 1: Circuit diagram for DC analysis

 Fig.2: Graph of ID v/s VDS

Fig. 3: Circuit diagram for Parametric analysis

 Fig. 4: Graph of ID v/s VDS(Parametric)

INFERENCE:

Characteristics of NMOS transistor were analysed by visualizing the output graphs of ID v/s VGS
and ID v/s VDS.

As we can see from the observed graphs,

o In the cut off region,

Vgs > Vtn and ID=0, we can approximate the value of Vtn=0.4V
o In the saturation
mode, Vgs < Vtn
VDS <= Vgs – Vtn,
ID= ½*(µ*Cox*W/L ( Vgs – Vtn)^2
Approximating from ID v/s Vds graph, saturation starts roughly when Vds=0.6V.
o In the triode mode,
Vgs < Vtn, Vds > Vgs- Vtn,
ID = (µ*Cox*W/L) [Vgs-Vtn-Vds/2]Vds
 EXPERIMENT 1)b CHARACTERISTICS
OF PMOS TRANSISTOR

NAME : Shivam varshney

-22BLC1365
OBJECTIVE:

To analyze the characteristics of PMOS transistor by visualizing ID v/s VDS graphs and draw
comparisons between the ideal and observed result.

TOOLS:

Linux operated computing system, application cadence Virtuoso -64

PROCEDURE:

● DC Analysis-

o In the black screen with dots, where you draw the schematic, draw the required circuits
for the given objectives using components from create → instance → browse.
o Save project. Check for error or warnings.
o To analyze the circuit, choose launch→ ADEL
o In analysis, choose DC analysis → save DC operating point→ check component
parameter.
o After checking component parameter, select component name.
o In analysis window, in sweep range, give start=-1.8V, stop = 0V. In sweep type, choose
linear→ step size = 0.2→OK.
o In virtuoso analog design environment window , select outputs → to be plotted → drain
of NMOS.
o Click on run button.
o Output graph is observed.

● Parametric analysis
o Same steps are repeated as done in DC analysis, only incorporating the following
changes.
o In the schematic, give the bias voltage supply as X volts.
o In the analysis window, select the component as the voltage supply VDC=1.8V
o Repeat the same steps, henceforth.
 o In virtuoso analog design environment window , select outputs → to be plotted → drain
of NMOS.
o Again in virtuoso analog design environment window, click variable
→ copy from cell view.
o Give name: X, Value : -1.8V → apply → OK
o Go to tools → parametric analysis.
o Add variable: X, Range (From/To): -1.8V – 0V
o Click on run button.
o Output graph is observed.

OBSERVATIONS:

Fig. 1: Circuit diagram for DC analysis

 Fig. 2: Graph of ID v/s VDS

Fig. 3: Graph of ID v/s VDS(parametric)

 Fig 4:Graph for Id v/s Vds with axes reversed
INFERENCE:

Characteristics of NMOS transistor were analysed by visualizing the output graphs of ID v/s VGS
and ID v/s VDS.

As we can see from the observed graphs,

o In the cut off region,

Vgs > Vtn and ID=0, we can approximate the value of Vtp=0.5V
o In the saturation
mode, Vgs < Vtn
VDS <= Vgs – Vtp,
ID= ½*(µ*Cox*W/L ( Vgs – Vtn)^2
Approximating from ID v/s Vds graph, saturation starts roughly when Vds= -0.75V.
o In the triode mode,
Vgs < Vtp, Vds > Vgs- Vtp,
ID = (µ *Cox*W/L) [Vgs-Vtn-Vds/2]Vds

CONCLUSION:
Therefore the characteristics of NMOS and PMOS are successfully plotted using Virtuoso and
Cadence tools
 DC TRANSFER
CHARACTERISTICS OF CMOS
CHARACTERISTICS

EXPERIMENT-2
Name: Shivam varshney 22BLC1365
OBJECTIVE:

To analyze the transfer characteristics of CMOS transistor by visualizing Vout v/s Vin graphs and
plot parametric analysis for different values of transistor width.

TOOLS:

Linux operated computing system, application cadence Virtuoso -64

PROCEDURE:

● DC Analysis-

o In the black screen with dots, where you draw the schematic, draw the CMOS inverter
circuit for the given objectives using components from create → instance(Q) → browse.
o Save project. Check for error or warnings.
o To analyze the circuit, choose launch→ ADE L
o In analysis, choose DC analysis → save DC operating point→ check component
parameter.
o Give 1.8V as Vdd and 1V as Vi.
o Create an o/p pin Vout
o After checking component parameter, select component name.
o In analysis window, in sweep range, give start=0, stop = 1.8V. In sweep type, choose
linear→ step size = 0.2→OK.
o In virtuoso analog design environment window, select outputs → to be plotted → Vout
and Vin.
o Click on run button.
o Output graph is observed and analysed.

● Parametric analysis
o Same steps are repeated as done in DC analysis, only incorporating the following
changes.
o In the schematic drawn, give the width of the PMOS as X nm.
o In the analysis window, select the component as the voltage supply VDC=1.8V
o Repeat the same steps, henceforth.
 o In virtuoso analog design environment window, select outputs → to be plotted →Vout.
o Again in virtuoso analog design environment window, click variable
→ copy from cell view.
o Give name: X, Value : 1.8nm → apply → OK
o Go to tools → parametric analysis.
o Add variable: X, Range (From/To): 0-1.8
o Click on run button.
o Output graph is observed.

● Calculations
o Choose the o/p graph on the output plane
o Apply deriv function to get the derivative
o Select the derivative function and apply the cross function to calculate points
where the function crosses 1.
o First choose falling,then evaluate one point then choose rising then evaluate the
next point

OBSERVATIONS:

Fig. 1: Transfer characteristics for DC analysis

 Fig. 2: Transfer characteristics for Parametric
analysis

Fig 3:Circuit diagram CMOS inverter

Fig 4:Calculation of noise margin

INFERENCE:

Characteristics of NMOS transistor were analysed by visualizing the output graphs of ID v/s VGS
and ID v/s VDS.

As we can see from the observed graphs,

● We know that β=µn*CoxW/L

● As the value of transistor width increases the value of beta for the PMOS increases which
means that the transistor stays in the pmos region for greater and greater periods of time

● Vm also increases as Kp increases

● The noise margin is the region between the 2 points where slope is -1

CONCLUSION

Hence the CMOS characteristics are successfully plotted and noise margin is calculated.
VLSI
Thank
you
 EXPERIMENT-3
TRANSFER CHARACTERISTICS OF CMOS INVERTER

Date: 09-02-24
Name: Shivam Varshney
RegNo: 22BLC1365

OBJECTIVE:
To analyze the transient analysis of CMOS inverter using pulse voltage

TOOLS:
Linux operated computing system, application cadence Virtuoso -64
PROCEDURE:

• DC Analysis- o In the black screen with dots, where you draw the schematic,
draw the CMOS inverter circuit forthe given objectives using components from
create → instance → browse.
o Save project. Check for error or warnings.
o To analyze the circuit, choose launch→ ADEL
o In analysis, choose DC analysis → save DC operating point→ check
componentparameter.
o Give 1.8V as Vdd and 1V as Vi. o Create an output pin Vout o Create an input
pin Vin at the input
• Symbol
o Go to create->from cellview->create symbol o Give Vin as input and Vout
as output o Now we get a rectangle like shape which behaves as exactly as an
inverter. This is useful when there are a lot of inverters in the circuit, we can
simply substitute them with a symbol
• Voltage pulse o Now go to vpulse which creates a pulse voltage and give the
following values in the properties V1=0,V2=1.8V and tr = 5ns (voltage switches
from input to output between these values since it’s a pulse voltage)
o Now go to ADEL window and select outputs to be plotted as the input wire,
the output pin

o For the inputs, go to transient analysis->choose moderate->stop time as

 200ns o
Now run it
• Calculations o Choose the o/p graph on the output plane o Apply delay function
and set the threshold value to 0.9 o First choose falling, then evaluate one point
then choose rising then evaluate the next point by switching falling and rising

OBSERVATIONS:

Fig. 1: Transfer characteristics for transient analysis

 Fig 2: Circuit diagram MOS inverter

Fig-3: Circuit diagram of inverter symbol

 Fig 4: Calculation of delay value
INFERENCE:
Characteristics of CMOS inverter were analyzed by visualizing the transfer
characteristics of the pulse
As we can see from the observed graphs,

• The midpoint is the region between the 2 points where the input voltage is
crossing the output or Vin=Vout
• In this since Vin=1.8V,threshold value is 0.9V
CONCLUSION:
Hence the cmos transient characteristics are successfully plotted and points at which
threshold voltage value is obtained is calculated successfully.
22BLC1365
Shivam Varshney
EXPERIMENT 5
NAND Gate - Prelayout
Contamination & Propagation Delay
AIM: To stimulate NAND gate on Virtuoso Cadence and find its output and propagation delay
APPARATUS USED: Virtuoso Cadence

METHODOLOGY:

1. Launch Cadence Virtuoso: Open the Cadence Virtuoso IC design tool on your computer.
2. Create a New Schematic: Start by creating a new schematic where you will design your NAND
gate. This is where you'll draw the circuit diagram.
3. Design the NAND Gate: Using the schematic editor, draw the NAND gate circuit using
transistors. For a basic CMOS NAND gate, you'll need to connect 2 NMOS in series and 2 PMOS
in parallel configuration.
4. Add Power Supplies: Make sure to add power supply connections (VDD=1.8V and GND) to your
circuit to power the transistors.
5. Verify the Schematic: Before proceeding, verify that your schematic is correct by checking for
any errors or connectivity issues.
6. Set Up the Simulation Configuration: In ADE L, set up the simulation configuration. Define the
simulation type (transient analysis), simulation parameters (simulation time=40ns), and specify
the input signals for your NAND gate.
7. Add Probes: Add probes to the input and output nodes of your NAND gate circuit. These probes
will allow you to monitor the signal waveforms during simulation.
8. Run the Simulation: Once everything is set up, simulate ADE L. This will simulate the behavior
of your NAND gate circuit based on the input signals provided.
9. View Simulation Results: After the simulation is over, you can view the results within ADE L.
You should be able to see the input and output waveforms plotted on the waveform viewer.
10. Identify the Rising and Falling Edges: Determine which edges of the input signals you want to
measure the propagation delay for. For example, you might be interested in the propagation delay
from the rising edge of the input to the falling edge of the output.
11. Open Calculator Tool: In Cadence Virtuoso, navigate to the calculator tool. This tool allows you
to perform various mathematical operations on simulation data.
12. Select Waveforms: Load the input and output waveforms of your NAND gate simulation into the
calculator tool.
13. Identify Reference Points: Identify the reference points on the input and output waveforms
corresponding to the edges you want to measure the propagation delay between.
 14. Measure Time Difference: Use the calculator tool to find the delay between the input and output
signals. This will give you the propagation delay.
15. Repeat if Necessary: If you want to measure the propagation delay for multiple edges or under
different conditions, repeat the process for each case.

OUTPUT:
RESULT: The stimulation of NAND Gate was successful with no errors in the output graph. The delay
in the output was found to be: for falling edge: 58.88E-12 and for rising edge: 29.35E-12.
NAME:SHIVAM VARSHNEY

REG.NO:22BLC1365

EXP-6 NAND GATE POST LAYOUT SIMULATION

NAND SCHEMATIC

NAND SYMBOL SCHEMATIC

NAND SYMBOL

NAND POST SIMULATION LAYOUT