Digital Electronics Unit 11

Unit 11 Counters

Structure:
11.1 Introduction
Objectives
11.2 Introduction to Counters
11.3 Types of Counters
Asynchronous counters
Synchronous counters
11.4 Up/Down Synchronous Counters
11.5 Counter Decoding
11.6 State Table and Excitation Table Concepts
11.7 Design of Counters
Design of asynchronous counters
Design of synchronous counters
11.8 Summary
11.9 Terminal Questions
11.10 Answers

11.1 Introduction
In the previous unit we have studied shift registers and their types. We have
also studied some ICs in relation to shift registers. In electronics, a counter
is a logic device which is capable of counting the number of times an event
has occurred. It can also display the count. The counter for its operation
needs a trigger which conveys that an event has occurred. This trigger is
usually supplied to a counter in the form of a signal called ‘clock’.
Depending on whether the count value increases/decreases, counters can
be up counters or down counters. Counters are generally implemented
using basic storage elements such as flip-flops. There are many types of
counters with different designs.
Objectives:
After studying this unit, you should be able to:
 define counters
 classify the counters and explain them
 discuss the operation of Up/Down synchronous counters
 explain the requirement of counter decoding
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 define a state table, and excitation table

 design counters for the desired modulus

11.2 Introduction to Counters

A counter is a digital sequential circuit that counts the number of input
pulses applied. A Counter is constructed using a group of flip flops
connected in cascade.
Modulus of a Counter
Modulus (or mod) of a counter is the number of different states that a
counter can go through before it comes back to initial state to repeat the
count sequence. An n-bit counter that counts through all its natural states
and does not skip any of the states has a modulus of 2n. For example, 3
stage counter consists of cascade of 3 flip flops and can count maximum of
23=8 counts. Hence the Modulus of this counter is 8.
Natural Count
If a counter counts all the maximum possible counts, it is called natural
count and in this case the modulus of a counter is equal to the natural
count. Note that a counter with three flip-flops (i.e. 3 bit counter) can count a
maximum of 8 counts from 0 through 7. So in this case the natural count =
modulus = 8. Suppose this same counter is designed to count from
0 through 5, instead of 0 to 7 then modulus of the counter is 6. So it is called
Modulo-6 counter. In this case the modulus of a counter is not equal to the
natural count.
Some of the important applications of counters are:
1. Digital clock
2. Automobile parking
Self-Assessment Questions
1. The ____________ is a digital sequential circuit that counts the
number of input pulses applied.
2. ________________ of a counter is the number of different states that a
counter can go through before it comes back to initial state to repeat
the count sequence.
3. For the counter with three flip-flops, the natural count is equal to
________________.

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11.3 Types of Counters

Binary counters count in terms of binary numbers. They can even count
BCD (Binary Coded Decimal) numbers. There are different types of
counters which can count binary numbers. And these are classified based
on how the clock is applied, and the number of flip-flops or states used.
Based on how the flip-flops are clocked, counters are classified as:
 Asynchronous (ripple) counters
 Synchronous counters

Asynchronous or ripple counters are those counters in which all the flip-flops
are not clocked by the same clock and all flip-flops do not change their state
in exact synchronism with the applied clock pulses. Usually the clock pulse
is applied to the first flip-flop and the output of the first flip flop is connected
as a clock for the next flip-flop. Asynchronous counters are also called ripple
counters because the flip-flops change their state in a ripple fashion i.e. the
clock pulse fed into first flip-flop ripples through the other counters after
propagation delay, like a ripple on water, and hence, the name Ripple
Counter.
Synchronous counters are those in which all the flip-flops are clocked by the
same clock and all flip-flops change their state in exact synchronism with
the applied clock pulses. A common clock is connected to clock inputs of all
the flip flops. The delay involved is equal to the propagation delay of one
flip-flop only, irrespective of the number of flip-flops used to construct the
counter.
A counter may count up or count down or count up and down depending on
the input control. The count sequence usually repeats itself. So based on
whether the count value increases or decreases, counters are classified as:
 Up counters
 Down counters
 Up/Down counters

Up counters count in upward direction or in an ascending order. For

example, for a 4-bit counter when counting up, the count sequence goes
from 0000, 0001, 0010, ... 1110, 1111 in increasing order (or ascending
order). When the counter reaches 1111, once again it starts counting from

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0000 and the counting sequence continues as long as the clock pulses are
applied.
Down counters count in a downward direction or in a descending order. For
example, in case of a 4-bit counter, the count sequence goes in the
opposite manner to that of the up counter: 1111, 1110, ... 0010, 0001, 0000
in decreasing order (or descending order). Once the counter reaches 0000,
the counter starts counting again from 1111 and the counting sequence
continues as long as the clock pulses are applied.
Counters which count in both up and down directions are called UP/DOWN
counters.
11.3.1 Asynchronous Counters
As we mentioned already, asynchronous or ripple counters do not change
their state in exact synchronism with the applied clock pulses. So all the flip-
flops used to construct the counters are not clocked by the same clock.
Normally the clock input of the first flip flop (FF0) will be clocked by the clock
signal and remaining flip-flops receive their clock signal from the output of
previous flip flop.
Now let us study some of the asynchronous counters.
3- Bit Asynchronous Up Counter:
A 3 bit asynchronous up counter counts from 0 to 7 in upward direction
(i.e. the count increases in an ascending order). The figure 11.1(a) shows a
3 bit asynchronous up counter constructed using T flip-flops and figure
11.1(b) shows the timing diagram. You can also use JK flip flop in place of
T flip flop to get toggling condition but the condition required is J and K
inputs should be equal to 1 i.e. when J=K=1, the JK flip flop toggles.

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Figure 11.1: 3–Bit Asynchronous Up Counter

The table 11.1 shows the truth table of 3-Bit asynchronous Up counters
Table 11.1: Truth table of 3-Bit Asynchronous Up Counter

When the T input of each flip-flop = 1(High), the state of each flip-flop will be
toggled (i.e. changed to the opposite state) at each positive edge of its

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clock. The clock input of the first flip-flop (FF0) is connected to the Clock
line, so FF0 toggles whenever the clock signal changes from 0 to 1 i.e.
during positive edge of every clock signal. The other flip-flops receive their
clock inputs driven by the output ( Q ) of the preceding flip-flop. Therefore,
the flip-flop FF1 toggles whenever the output of preceding flip-flop FF0
changes its state from 1 to 0 (i.e., when Q0 changes from 1 to 0). Similarly
FF2 toggle their state whenever the preceding flip-flop FF1 changes its state
from 1 to 0 (i.e., when Q1 changes from 1 to 0.) We can also put the
toggling operation of FF1 and FF2 in terms of complemented output Q .
i.e. the FF1 toggles whenever Q 0 changes from 0 to 1, and the flip flop FF2
toggles whenever Q 1 changes from 0 to 1. Note that Q 0 acts as a clock
signal for FF1 and Q 1 acts as a clock signal for FF2.

Figure 11.1(b) shows a timing diagram for the counter. The value of Q0
toggles once after each positive edge of the Clock signal. The second flip-
flop is clocked by Q 0. So the output state Q1 changes after the negative
edge of the Q0 signal (or positive edge of Q 0.). Similarly, Q2 changes its
state after the negative edge of the Q1 signal.
Further if we look at the values Q2Q1Q0 in truth table, counting is in
ascending order in the sequence 0, 1, 2, 3, 4, 5, 6, 7, 0, 1, and so on. This is
a modulo-8 counter as it counts from 0 to 7.
3 Bit (mod 8) Ripple Counter using JK Flip flop:
The figure 11.2 shows the logic diagram of a 3 bit (mod 8) ripple up counter
using JK flip-flops. The counting sequence is the same as that of the table
11.1.

(a) Logic circuit

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(b) Timing diagram (or wave form)

Figure 11.2: 3 bit (mod 8) ripple up counter using JK flip-flops

Note that in the above figure 11.2, the J and K data inputs of the flip-flops
are tied to logical 1. This means that each flip-flop is in its toggle mode, and
acts as T flip flop. Each clock pulse will then cause the flip-flop to toggle to
its opposite state when they are clocked by negative edge of the clock
signal. i.e., the flips flops are negative edge triggered. This means the flip
flops change their state on receiving negative or falling edge on the clock
signal. The clock (CLK) of FF0 is directly connected to clock input. So the
FF0 changes state whenever there is transition of the clock signal from
1 to 0 (i.e., negative or falling edge of the clock signal). However the flip-
flop1 (FF1) changes its state when Q0 changes from 1 to 0 since it is acting
as clock input for FF1. Similarly the flip-flop2 (FF2) changes state when Q1
changes from 1 to 0 since Q1 acts as clock signal for FF2.
3-Bit asynchronous Down Counter
A 3 bit asynchronous down counter counts in a descending or a decreasing
order from 111 to 000 and repeats the sequence.
The figure 11.3 shows a 3-bit asynchronous down counter along with timing
diagram and truth table. The difference between figure 11.1(a) and figure
11.3(a) is that only the clock inputs of the second and the third flip-flops are
driven by the Q outputs of the preceding flip-flops, instead of the Q outputs.
The timing diagram shown in 11.3(b) indicates how the counter counts
during clock pulse. From the truth table shown in table 11.2, it is clear that
the counter counts in downward direction and the sequence is 7, 6, 5, 4, 3,
2, 1, 0, 7, and so on (i.e. from 111 to 000 and the sequence repeats). Since
the counter counts in the downward direction, it is called down-counter.

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Figure 11.3: 3 –Bit asynchronous Up Counter

(a) Circuit diagram (b) Timing diagram
Table 11.2: Truth Table of a 3-bit Asynchronous Down Counter

11.3.2 Synchronous Counters:

The asynchronous counters are simple but not very fast. If a counter with a
larger number of bits is constructed in this manner, then the delays caused
by the cascaded clocking scheme may become too long to meet the desired
performance requirements. Also note that the time required to settle in a
state or output called settling time in case of asynchronous counter is
approximately the product of the delay time of a single flip-flop and the total
number of flip-flops. So the delay is more in case of asynchronous counters.
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This problem is overcome if all the flip flops are clocked simultaneously.
Then the resulting circuit is called synchronous counter. In other words, we
can build a faster counter by clocking all flip-flops at the same time.
Synchronous counters change their state in exact synchronism with the
applied clock pulses. So all the flip-flops used to construct the counters are
clocked by the same clock.
Now let us study some of the synchronous counters.
3-Bit Synchronous Up-Counter (or Mod 8 Synchronous Up-Counter )
The figure 11.4(a) shows a 3-bit synchronous up-counter and its timing
diagram is shown in figure 11.4(b).

(a)

(b)
Figure 11.4: 3 –Bit Synchronous Up Counter
(a) Logic circuit diagram (b) Timing diagram

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The table 11.3 shows the truth table of a 3-Bit Synchronous binary counter.
Table: 11.3: Truth table of a 3-Bit Synchronous Binary Counter

Note that all the flip flops are clocked by the same clock signal. So they
change their states in exact synchronism or in parallel with the clock signal
applied.
Only the J0 and K0 inputs of the first flip-flop (FF0) is connected permanently
to logic 1 (i.e., HIGH), while J and K inputs of the other flip-flops are driven
by some combination of flip-flop outputs. The J1 and K1 input of flip-flop FF2
is connected to the output Q0 of flip-flop FF0; the J2 and K2 inputs of flip-flop
FF2 is connected with the AND operated output of Q0 and Q1.
From the circuit, we can see that flip-flop FF0 changes its state with the
positive edge transition of each clock pulse. Flip-flop FF1 changes its state
only when the value of Q0 is 1 and a positive edge transition of the clock
pulse takes place. Similarly, flip-flop FF2 changes its state only when both
Q0 and Q1 are 1 and a positive edge transition of the clock pulse takes
place.
Note from the truth table, the counter counts from 000 to 111 and then
repeats the sequence. So the total counts (i.e. different states) are only 8
from 000 to 111 (i.e. 0 to 7 in decimal). Hence this synchronous counter is
called mod-8 counter or mod-8 up synchronous counter.

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4-bit Synchronous Up-Counter

A 4-bit synchronous up-counter using T flip-flop is shown in figure 11.5. This
counter counts from 0000 to 1111 (i.e. from 0 to 15 in decimal). Hence it is
called Mod-16 synchronous up-counter.

Figure 11.5: 4-bit synchronous up-counter

The table 11.4 shows the contents of such a 4-bit up-counter for sixteen
consecutive clock cycles, assuming that the counter is initially 0.
Table 11.4: Contents of a 4−bit up−counter for 16 consecutive clock cycles

Observing the pattern of bits in each row of the table, it is apparent that bit
Q0 changes on each clock cycle. Bit Q1 changes only when Q0 = 1. Bit Q2
changes only when both Q1 and Q0 are equal to 1. Bit Q3 changes only
when Q2 = Q1 = Q0 = 1. Then the T inputs should be defined as

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T0 = 1
T1 = Q0
T2 = Q0Q1
T3 = Q0Q1Q2
Figure 11.6 shows timing diagram for the 4-bit synchronous up-counter.

Figure 11.6: Timing diagram for a 4−bit synchronous up−counter

Activity 1:
Draw the logic diagram of Mod16 down counter and write the truth table.

11.4 Up/Down Synchronous Counters

In certain applications it is required have a counter that must be able to
count both up and down. This can be done by using a control input called
“count up/down” and depending on the status of this signal. The up/down
counter counts both in up and down directions. We can use even separate
control lines for Up and Down count. The figure 11.7 shows the circuit for a
3-bit up–down synchronous counter.

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Figure 11.7: A 3-bit synchronous Up-down-counter.

Here the control input (countup/down) used allows the counter either to
count up or to count down. When the count-up/down=1, then the upper AND
gates 1 and 2 will be active and the lower AND gates 3 and 4 will be
disabled and hence the normal output of each flip-flop is carried forward to
the following flip-flop and the counter works as up counter and will count
from 000 to 111. When the control line =0, then the upper AND gates 1 and
2 remain disabled (inactive) and the lower AND gates 3 and 4 will become
active. So the inverted output comes into operation and the counter works
as down counter and will counts from 111 to 000.
Self-Assessment Questions
4. In _____________ counters all the flip-flops are not clocked by the
same clock and all flip-flops do not change their state in exact
synchronism with the applied clock pulses.
5. In _____________ counters a common clock is connected to clock
inputs of all the flip flops.
6. A 3 bit asynchronous up counter counts from _________ in upward
direction.
7. We can build a faster counter by clocking all flip-flops. (True or False?)
8. When the control input count-up/down=0 in UP/Down counter, then the
counter works as up counter. (State true or false)

11.5 Counter Decoding

The output state of a counter at any time instant, when it is clocked is in the
form of a sequence of binary digits. In many applications, it is important to
decode different states of the counter whose number equals the modulus of

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the counter. The decoding circuit takes its inputs from the outputs of the
different flip-flops constituting the counter and then makes use of those data
to generate outputs equal to the modulus (or Mod) of the counter. This
decoded output can be active HIGH or active LOW.
We can explain the concept of decoding, by considering the MOD-4 ripple
counter shown in figure 11.8(a.) This counter has four states, 00, 01, 10
and 11, and these counts need to be decoded. Let us now consider the
arrangement of four two-input AND gates as shown in 11.8(b). Note that the
number of AND gates used in the decoder circuit equals the number of logic
states to be decoded. Also note that, the number of inputs to each AND
gate equals the number of flip-flops used in the counter.

(a) Circuit

(c) Decoder logic

Figure 11.8: MOD-4 ripple counter with decoding logic

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From the waveforms of figure 11.8(b),we observe that, when the counter is
in the 00 state, the AND gate designated ‘0’ is in the logic HIGH state and
the outputs of the other gates designated ‘1’, ‘2’ and ‘3’ are in the logic LOW
state. Similarly, for 01, 10 and 11 states of the counter, the outputs of gates
1, 2 and 3 are in the logic HIGH state respectively. This is active HIGH
decoding. If we replace AND gates with NAND gates with the inputs to the
gates remaining the same, then we get an active LOW decoder. For a
counter that uses n flip-flops and has a modulus of ‘M’, the decoder will
have ‘M’ number of n-input AND or NAND gates, depending upon whether
we want an active HIGH or active LOW decoder.

11.6 State Table and Excitation Table Concepts

In the general model for sequential circuits, the effect of all previous inputs
on the outputs is represented by a state of the circuit. Thus, the output of
the circuit at any time depends upon its current state and the input. These
also determine the next state of the circuit. The relationship that exists
among the inputs, outputs, present states and next states can be specified
by either the state table or the state diagram.
State Table
The state table representation of a sequential circuit consists of three
sections labelled present state, next state and output. The present state
represents the state of flip-flops before the occurrence of a clock pulse. The
next state shows the states of flip-flops after the clock pulse, and the output
lists the value of the output variables during the present state. Again, both
the output and the next state have two columns, one for x = 0 and the other
for x = 1. Consider the logic diagram shown in figure 11.9. Its state table is
shown in the table in table 11.5.

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Figure 11.9: Clocked sequential circuit.

Table 11.5: State table for the figure 11.9.

We can start analysing the circuit from any arbitrary state. Let us start the
analysis from the initial state 00 or when the present state is 00 (,i.e. A = 0
and B = 0). From the logic diagram shown in figure 11.9 with input x = 0, we
find both AND gates 1 and 2 produce logic 0 signal and hence the next state
remains unchanged. Also, for FFB, both AND gates 3 and 4 produce logic 0
signal and hence the next state of B also remains unchanged. Hence, with
the clock pulse, flip-flop A and B are both in the memory state. So the next
state is 00. Similarly, with A = 0 and B = 0, with input x = 1, we find that gate
1 produces logic 0, whereas gate 2 produces logic 1. Again, with the same
condition, gate 3 produces logic 1 whereas gate 4 produces logic 0. Hence,
with the clock pulse, flip-flop A is cleared and B is set, making the next state
01. This information is listed in the first row of the state table.

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In a similar manner, we can derive the other conditions of the state table
also. When the present state is 01 (i.e. A = 0 and B = 1). When x = 0, gate 1
produces 1 and gate 2 produces 0. For B flip-flop both gates 3 and 4
produce logic 0 and hence the next state of B remains unchanged. Hence,
with the clock pulse, flip-flop A is set and B remains in the memory state,
this makes the next state 11. Similarly, with A = 0 and B = 1, with x = 1, both
gates 1 and 2 produce logic 0. Again, with the same condition, both gates 3
and 4 produce logic 0. Hence, with the clock pulse, both flip-flops A and B
remain in the memory state, making the next state 01. This is listed in the
second row of the state table.
When the present state is 10 (i.e. A = 1 and B = 0). From the logic When,
with x = 0, both gates 1 and 2 produce logic 0. For B flip-flop gate 3
produces logic 0 but gate 4 produces logic 1. Hence, with the clock pulse,
flip-flop A remains in the memory state and B is reset, making the next state
10. Similarly, with A = 1 and B = 0, with x =1, we find that gate 1 produces
0, and gate 2 produces 1. Again, with the same condition, both gates 3 and
4 produce logic 0. Hence, with the clock pulse, A is reset and B remains in
the memory state, making the next state 00. This is listed in the third row of
the state table.
When the present state is 11 (i.e A = 1 and B = 1), with x = 0, gate
1 produces logic 1 and gate 2 produces logic 0. For B flip-flop gate
3 produces 0 but gate 4 produces logic 1. Hence, with the clock pulse, flip-
flop A remains in the memory state and B is reset, making the next state 10.
Similarly, with A = 1 and B = 1, with x = 1, both gates 1 and 2 produce 0.
Again, with the same condition, both gates 3 and 4 produce 0. Hence, with
the clock pulse, both A and B remain in the memory state, making the next
state 11. This is listed in the last row of the state table.
The entries in the output are easier to derive. The output y is equal to 1 only
when x = 1, A = 1, and B = 0. Hence the output columns are marked with 0s
except when the present state is 10 and input x = 1, for which y is marked
as 1.
The external output of a sequential circuit may come from memory elements
or logic gates. The output is only included in the state table if there are
outputs from logic gates.

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State Diagram
A sequential circuit can also be represented by a state diagram (also known
as a state transition graph).
The state diagram or state transition diagram is a graphical representation
of different states of a given sequential circuit and the sequence in which
these states occur in response to a clock input. Different states are
represented by circles, and the arrows joining them indicate the sequence in
which different states occur. Note that state transition from one state to
another takes place only when a clock transition takes place. As an
example, figure 11.10 shows the state transition diagram of a Mod-5 binary
counter. It is assumed that the initial state is 000 (i.e. 0 in decimal).

Figure 11.10: State diagram

Now consider the state diagram shown in figure 11.11.

Figure 11.11: State Diagram

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The two digit binary number inside each circle represents the state. The
directed lines are labelled with two binary numbers separated by a slash (/).
Here the input value that causes the state transition is labelled first, and the
number after the slash symbol / gives the value of the output. For example,
the directed line from state 00 to 01 is labelled 1/0, meaning that, if the
sequential circuit is in a present state and the input is 1, then the next state
is 01 and the output is 0. If it is in a present state 00 and the input is 0, it will
remain in that state. A directed line connecting a circle with itself indicates
that no change of state occurs. The state diagram provides exactly the
same information as the state table and is obtained directly from the state
table.
Excitation table:
The excitation table lists the present state, the next state and the flip-flop
inputs (for example, J, K) required to achieve that. Table 11.6 shows the
excitation table for a J-K flip-flop.
Table 11.6: Excitation table of JK flip flop

Referring to table 11.6, if the output is in ‘0’ state and if we want the next
state to be ‘1’ state on occurrence of the clock pulse, then J input must be in
the ‘1’ state and the K input can be either in the logic ‘0’ or logic ‘1’ state
indicated by X. This is true as for a ‘0’ to ‘1’ transition is concerned. There
are two possible input conditions that can achieve this. These are when J =
1, K = 0 and J = K = 1 (toggle mode), which further leads to J = 1, K = X
(either 0 or 1). We can explain the other entries of the excitation table on
similar lines.
Self-Assessment Questions
9. In many applications, it is important to decode different states of the
counter whose number equals the modulus of the counter. (True or
False?)
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10. The ______________ representation of a sequential circuit consists of

three sections labelled present state, next state and output.
11. The ______________ is a graphical representation of different states
of a given sequential circuit.
12. The _____________ table lists the present state, the next state and the
flip-flop inputs required to achieve that.

11.7 Design of Counters

In a counter, the sequence of states may follow a binary count or any other
sequence of states. A counter that follows the binary sequence is called a
binary counter. A single flip-flop used gives two states output and is referred
to as mod-2 counter. With two flip-flops four output states can be counted in
ascending or in descending order and is referred to as mod-4 counter. With
‘n’ flip-flops a mod-2n counting is possible either of ascending or of
descending type. So, an n-bit binary counter consists of n flip-flops and can
count in binary from 0 to 2n - 1.
11.7.1 Design of asynchronous counters
To design an asynchronous counter to count till mod-M where M is a
modulus of a counter and is not a power of 2, the following procedure is
used.
 Find the number of flip-flops required using the equation n = log2 M. If
the calculated value is not an integer then select n by rounding to the
next integer value.
 First write the sequence of counting till M either in ascending or in
descending order.
 Tabulate the value to reset the flip-flops in a mod-M count.
 Find the flip-flop outputs which are to reset from the tabulated value.
 Tap the output from these flip-flops and feed it to a suitable gate whose
output is connected to the clear pin.
Let's illustrate design of asynchronous counter with the example 1.
Example1: Design a Mod-6 counter using JK flip flop
Solution: The mod-6 counter counts from 0 through 5 (i.e. 000 to 101 in
binary). After this this counter is reset to initial count 000, it starts counting
again. Since 23 = 8, only three flip flops are required, and the number 8 is

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greater than mod-6. Now we draw the table 11.7 to represent the desired
output of the combinational circuit to reset FFs as.
Table 11.7: The truth table for Mod 6-counter.

From the truth table 11.7, it can be observed that we want the counter to
count only from 000 to 101 and the count 110 is not required to be counted.
So the counter should reset to 000 immediately after the count 101.
Observe that count 110 corresponds to Q2=1, Q1=1 and Q0=0. So we give
the Q2 and Q1 as inputs to two input NAND gate so that whenever the
value Q2=1 , Q1=1 appears the NAND gate outputs zero(o) and this output
in turn activates the asynchronous inputs Clear (i.e. CLR) so that the
counter resets back to 000 and starts counting again. This mod-6 counter is
shown in the figure 11.12 Note that J=K=1 so that each flip-flop acts as a
Toggle flip-flop (i.e. T-flip flop).

Figure 11.12: Mod-6 counter

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2nd method:
Initially we draw the state diagram as shown in the figure 11.13. Assume
that the initial count is 0 (i.e. 000 in binary).

Figure 11.13: State diagram for Mod-6 counter

We draw the truth table to represent the desired output of the combinational
circuit to reset FFs as shown in the table 11.8.

Table 11.8: The truth table for Mod 6-counter ( for 2nd method).

Note that the output is 1 for required count (or combinations) and is 0 for the
count 110 onwards.

Now we use k-map to get the simplified circuit as shown in the figure 11.14

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Figure 11.14: K-map for mod-6 design using 2nd method

And the equation we get is output = Q1 + Q 2 .

= Q1Q 2
So, output= NAND (Q1 and Q2)
And the circuit is shown in figure 11.12.

11.7.2 Design of Synchronous Counters

To design synchronous counter, the following procedure can be used.
 Develop a state diagram for a given sequence.
 Develop a next-state table for a specific counter sequence.
 Create a FF transition table. (You can use JK Flip Flops)
 Use K-map to derive the logic equations. (Optional: Use Truth Table)
 Convert the logic equations to Boolean Algebra
 Implement a counter to produce a specified sequence of states.
Let's illustrate the design of synchronous counter using the example 2 and
example 3.
Example 2: Design a Mod-5 synchronous counter
Solution: To design a mod-5 counter, the number of flip-flops required are
found by the equation 2n ≥ M ≥ 2n-1 where n is the number of flip-flops
required and M is the number of states present in the counter. Now M=5,
then n=3. So three flip flops are required to design a Mod-5 counter.
The state diagram for mod-5 counter is shown in figure 11.15. It is assumed
that the initial count is 000 (i.e. 0 in decimal).

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Figure 11.15: State diagram for Mod-5 counter.

The state table for the counter is given in the table 11.9 and table 11.10
gives its excitation table. Note that the outputs are represented by A2A1A0
instead of Q2Q1Q0.
Table 11.9: State table for the counter

Table 11.10: Excitation table for Mod-5 counter

Now transfer the JK states of the flip-flop inputs from the excitation table to
Karnaugh maps to derive a simplified Boolean expression for each flip-flop
input.

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The figure 11.16 shows the Karnaugh Map for Mod-5 Counter.

Figure 11.16: Karnaugh Map for Mod-5 counter

The figure 11.17 shows the logic circuit diagram for Mod-5 counter.

Figure 11.17: Logic diagram of a Mod-5 counter

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Example 3: Design a counter for the sequence of states shown in figure

11.18.

Figure 11.18: State diagram of a 3-bit binary counter.

Solution: The circuit has no inputs other than the clock pulse and no
outputs other than its internal state (outputs are taken off each flip-flop in the
counter). The next state of the counter depends entirely on its present state,
and the state transition occurs every time the clock pulse occurs.
Once the sequential circuit is defined by the state diagram, the next step is
to obtain the next-state table, as shown in table 11.11 which is derived from
the state diagram shown in figure 11.18.
Table 11.11: State table of figure 11.18

Since there are eight states, the number of flip-flops required would be three.
Now we want to implement the counter design using JK flip-flops.

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Next step is to develop an excitation table from the state table, which is
shown in table 11.12.
Table 11.12: Excitation table

Now transfer the JK states of the flip-flop inputs from the excitation table to
Karnaugh maps to derive a simplified Boolean expression for each flip-flop
input. This is shown in figure 11.19.

Figure 11.19: Karnaugh maps

From the K-map, we get the following expressions for the J and K inputs of
each flip-flop:
J0 = K0 = 1
J1 = K1 = Q0
J2 = K2 = Q0 Q1

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From the equations, the counter is realized as shown in figure 11.20.

Figure 11.20: Logic of a 3-bit binary counter

Activity 2:
Design a MOD10 asynchronous counter. Also draw the timing diagram.

Self-Assessment Questions
13. An n-bit binary counter consists of n flip-flops and can count in binary
from _____________.
14. How many flip-flops are required to design a Mod-6 counter?

11.8 Summary
Let us recapitulate the important concepts discussed in this unit:
 The counter is a digital sequential circuit that counts the number of input
pulses applied.
 Modulus of a counter is the number of different states that a counter can
go through before it comes back to initial state to repeat the count
sequence.
 Based on how the flip-flops are clocked, counters are classified as:
Asynchronous (ripple) counters and Synchronous counters.
 Counters are also classified as: Up counters, and Down counters.
 Asynchronous or ripple counters are those counters in which all the flip-
flops are not clocked by the same clock.
 Synchronous counters are those in which all the flip-flops are clocked by
the same clock pulse.

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 Counters which count in both up and down directions are called

UP/DOWN counters.
 The state diagram or state transition diagram is a graphical
representation of different states of a given sequential circuit.
 The excitation table lists the present state, the next state and the flip-flop
inputs required to achieve that.

Glossary:
Counter: A digital sequential circuit that counts the number of input pulses
applied.
Modulus of a counter: The number of different states that a counter can go
through before it comes back to initial state to repeat the count sequence.
Asynchronous: Counters in which all the flip-flops are not clocked by the
same clock pulse.
Synchronous counters: Counters in which all the flip-flops are clocked by
the same clock pulse.
UP/DOWN Counters: Counters which count in both up and down directions.

11.9 Terminal Questions

1. What is a counter? Explain modulus of a counter.
2. Give the classification of counters and explain their function.
3. Explain the operation of 3 bit asynchronous Up counter.
4. Draw the diagram of 4-bit synchronous up-counter and explain its
working.
5. Describe the working of up/down synchronous counter.
6. Explain why counter decoding is required.
7. Discuss the design of a Mod-6 asynchronous counter using JK flip flop.

11.10 Answers
Self-Assessment Questions
1. Counter
2. Modulus
3. 8
4. Asynchronous
5. Synchronous

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6. 0 to 7
7. True
8. False
9. True
10. State table
11. State diagram
12. Excitation
13. 0 to 2n – 1
14. Three(3)

Terminal Questions
1. The counter is a digital sequential circuit that counts the number of
input pulses applied. Refer to section 11.2.
2. Based on how the flip-flops are clocked, counters are classified as:
Asynchronous (ripple) counters and Synchronous counters. Refer to
section 11.3.
3. A 3 bit asynchronous down counter counts in descending or decreasing
order from 111 to 000 and repeats the sequence. Refer to sub-section
11.3.1.
4. A 4-bit synchronous up-counter counts from 0000 to 1111. Refer to
sub-section 11.3.2.
5. Up/Down counter counts in both up and down directions. Refer to
section 11.4.
6. In many applications, it is important to decode different states of the
counter. Refer to section 11.5.
7. The mod-6 counter counts from 0 through 5 (i.e. 000 to 101 in binary).
Refer to sub-section 11.7.1.

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