EC200A Series

Hardware Design

LTE Standard Module Series

Version: 1.0

Date: 2022-01-11

Status: Released
 LTE Standard Module Series

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 LTE Standard Module Series

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b) We shall bear no liability resulting from any inaccuracies or omissions, or from the use of the
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c) While we have made every effort to ensure that the functions and features under development are
free from errors, it is possible that they could contain errors, inaccuracies, and omissions. Unless
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and exclude all liability for any loss or damage suffered in connection with the use of features and
functions under development, to the maximum extent permitted by law, regardless of whether such
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Copyright © Quectel Wireless Solutions Co., Ltd. 2022. All rights reserved.

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 LTE Standard Module Series

Safety Information
The following safety precautions must be observed during all phases of operation, such as usage, service
or repair of any cellular terminal or mobile incorporating the module. Manufacturers of the cellular terminal
should notify users and operating personnel of the following safety information by incorporating these
guidelines into all manuals of the product. Otherwise, Quectel assumes no liability for customers’ failure to
comply with these precautions.

Full attention must be paid to driving at all times in order to reduce the risk of an
accident. Using a mobile while driving (even with a handsfree kit) causes
distraction and can lead to an accident. Please comply with laws and regulations
restricting the use of wireless devices while driving.

Switch off the cellular terminal or mobile before boarding an aircraft. The operation
of wireless appliances in an aircraft is forbidden to prevent interference with
communication systems. If there is an Airplane Mode, it should be enabled prior to
boarding an aircraft. Please consult the airline staff for more restrictions on the use
of wireless devices on an aircraft.

Wireless devices may cause interference on sensitive medical equipment, so

please be aware of the restrictions on the use of wireless devices when in
hospitals, clinics or other healthcare facilities.

Cellular terminals or mobiles operating over radio signal and cellular network
cannot be guaranteed to connect in certain conditions, such as when the mobile bill
is unpaid or the (U)SIM card is invalid. When emergent help is needed in such
conditions, use emergency call if the device supports it. In order to make or receive
a call, the cellular terminal or mobile must be switched on in a service area with
adequate cellular signal strength. In an emergency, the device with emergency call
function cannot be used as the only contact method considering network
connection cannot be guaranteed under all circumstances.

The cellular terminal or mobile contains a transceiver. When it is ON, it receives

and transmits radio frequency signals. RF interference can occur if it is used close
to TV sets, radios, computers or other electric equipment.

In locations with explosive or potentially explosive atmospheres, obey all posted

signs and turn off wireless devices such as mobile phone or other cellular
terminals. Areas with explosive or potentially explosive atmospheres include
fueling areas, below decks on boats, fuel or chemical transfer or storage facilities,
and areas where the air contains chemicals or particles such as grain, dust or
metal powders.

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 LTE Standard Module Series

About the Document

Revision History

Version Date Author Description

Anthony LIU/
- 2022-01-05 Creation of the document
Kexiang ZHANG
Anthony LIU/
1.0 2022-01-11 First official release
Kexiang ZHANG

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 LTE Standard Module Series

Contents

Safety Information ....................................................................................................................................... 3

About the Document ................................................................................................................................... 4
Contents ....................................................................................................................................................... 5
Table Index ................................................................................................................................................... 7
Figure Index ................................................................................................................................................. 9

1 Introduction ........................................................................................................................................ 11
1.1. Special Marks .......................................................................................................................... 11

2 Product Overview .............................................................................................................................. 12

2.1. Frequency Bands and Functions ............................................................................................ 12
2.2. Key Features ........................................................................................................................... 13
2.3. Functional Diagram ................................................................................................................. 16
2.4. Pin Assignment........................................................................................................................ 17
2.5. Pin Description ........................................................................................................................ 18
2.6. EVB ......................................................................................................................................... 25

3 Operating Characteristics ................................................................................................................. 26

3.1. Operating Modes ..................................................................................................................... 26
3.2. Sleep Mode ............................................................................................................................. 27
3.2.1. UART Application ........................................................................................................... 27
3.2.2. USB Application with USB Remote Wakeup Function .................................................. 27
3.2.2.1. USB Application with USB Suspend/Resume and RI Function ..................... 28
3.2.2.2. USB Application without USB Suspend Function .......................................... 29
3.3. Airplane Mode ......................................................................................................................... 30
3.4. Power Supply .......................................................................................................................... 30
3.4.1. Power Supply Pins ......................................................................................................... 30
3.4.2. Reference Design for Power Supply .............................................................................. 31
3.4.3. Requirements for Voltage Stability ................................................................................. 32
3.5. Turn On ................................................................................................................................... 33
3.5.1. Turn on the Module with PWRKEY ................................................................................ 33
3.6. Turn Off.................................................................................................................................... 35
3.6.1. Turn off the Module with PWRKEY ................................................................................ 35
3.6.2. Turn off the Module with AT Command .......................................................................... 35
3.7. Reset ....................................................................................................................................... 36

4 Application Interfaces ....................................................................................................................... 38

4.1. USB Interface .......................................................................................................................... 38
4.2. USB_BOOT Interface .............................................................................................................. 40
4.3. (U)SIM Interface ...................................................................................................................... 41
4.4. PCM and I2C Interfaces .......................................................................................................... 43
4.5. SPI Interface............................................................................................................................ 46
4.6. Analog Audio Interfaces .......................................................................................................... 46
4.6.1. Notes on Audio Interface Design ................................................................................... 47

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4.6.2. Microphone Interface Circuit .......................................................................................... 47

4.6.3. Handset Interface Circuit ............................................................................................... 48
4.7. UART Interface ........................................................................................................................ 48
4.8. SD card Interface .................................................................................................................... 50
4.9. ADC Interface .......................................................................................................................... 52
4.10. RGMII/RMII Interface .............................................................................................................. 53
4.11. Indication Signal ...................................................................................................................... 56
4.11.1. Network Status Indication .............................................................................................. 56
4.11.2. STATUS .......................................................................................................................... 57
4.12. Behaviors of the MAIN_RI....................................................................................................... 58

5 RF Specifications ............................................................................................................................... 59
5.1. Cellular Network ...................................................................................................................... 59
5.1.1. Antenna Interface & Frequency Bands .......................................................................... 59
5.1.2. Tx Power ........................................................................................................................ 62
5.1.3. Rx Sensitivity .................................................................................................................. 63
5.1.4. Reference Design .......................................................................................................... 65
5.2. Reference Design of RF Routing ............................................................................................ 66
5.3. Requirements for Antenna Design .......................................................................................... 68
5.4. RF Connector Recommendation ............................................................................................ 69

6 Electrical Characteristics & Reliability ............................................................................................ 71

6.1. Absolute Maximum Ratings .................................................................................................... 71
6.2. Power Supply Ratings ............................................................................................................. 72
6.3. Power Consumption ................................................................................................................ 72
6.4. Digital I/O Characteristic ......................................................................................................... 82
6.5. ESD ......................................................................................................................................... 83
6.6. Operating and Storage Temperatures..................................................................................... 84

7 Mechanical Information ..................................................................................................................... 85

7.1. Mechanical Dimensions .......................................................................................................... 85
7.2. Recommended Footprint......................................................................................................... 87
7.3. Top and Bottom Views............................................................................................................. 88

8 Storage, Manufacturing & Packaging .............................................................................................. 89

8.1. Storage Conditions .................................................................................................................. 89
8.2. Manufacturing and Soldering .................................................................................................. 90
8.3. Packaging Specifications ........................................................................................................ 91
8.3.1. Carrier Tape.................................................................................................................... 92
8.3.2. Plastic Reel .................................................................................................................... 92
8.3.3. Packaging Process ........................................................................................................ 93

9 Appendix References ........................................................................................................................ 94

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Table Index

Table 1: Special Marks ................................................................................................................................11

Table 2: Brief Introduction of the Module ................................................................................................... 12
Table 3: Wireless Network Type ................................................................................................................. 12
Table 4: Key Features ................................................................................................................................ 13
Table 5: I/O Parameters Definition ............................................................................................................. 18
Table 6: Pin Description ............................................................................................................................. 18
Table 7: Overview of Operating Modes ...................................................................................................... 26
Table 8: Pin Definition of Power Supply ..................................................................................................... 31
Table 9: Pin Definition of PWRKEY ............................................................................................................ 33
Table 10: Pin Definition of RESET ............................................................................................................. 36
Table 11: Functions of the USB Interface................................................................................................... 38
Table 12: Pin Definition of USB Interface ................................................................................................... 38
Table 13: Pin Definition of USB_BOOT Interface ...................................................................................... 40
Table 14: Pin Definition of (U)SIM Interface............................................................................................... 41
Table 15: Pin Definition of PCM Interface .................................................................................................. 44
Table 16: Pin Definition of I2C Interface..................................................................................................... 45
Table 17: Pin Definition of SPI Interface .................................................................................................... 46
Table 18: Pin Definition of Analog Audio Interfaces ................................................................................... 46
Table 19: Pin Definition of Main UART Interface ....................................................................................... 49
Table 20: Pin Definition of Debug UART Interface..................................................................................... 49
Table 21: Pin Definition of SD Card Interface ............................................................................................ 50
Table 22: Pin Definition of ADC Interface ................................................................................................... 52
Table 23: Characteristics of ADC Interface ................................................................................................ 52
Table 24: Pin Definition of RGMII/RMII Interface ....................................................................................... 53
Table 25: Pin Definition of Indication Signal ............................................................................................... 56
Table 26: Working State of the Network Connection Status/Activity Indication ......................................... 56
Table 27: Behaviors of the MAIN_RI .......................................................................................................... 58
Table 28: Pin Definition of Cellular Network Interface ............................................................................... 59
Table 29: Operating Frequency of EC200A-CN......................................................................................... 59
Table 30: Operating Frequency of EC200A-AU ......................................................................................... 60
Table 31: Operating Frequency of EC200A-EU ......................................................................................... 61
Table 32: Tx Power..................................................................................................................................... 62
Table 33: Conducted RF Receiving Sensitivity of EC200A-CN ................................................................. 63
Table 34: Conducted RF Receiving Sensitivity of EC200A-AU ................................................................. 63
Table 35: Conducted RF Receiving Sensitivity of EC200A-EU ................................................................. 64
Table 36: Requirements for Antenna Design ............................................................................................. 68
Table 37: Absolute Maximum Ratings ........................................................................................................ 71
Table 38: The Module’s Power Supply Ratings ......................................................................................... 72
Table 39: EC200A-CN Current Consumption ............................................................................................ 72
Table 40: EC200A-AU Current Consumption ............................................................................................ 75
Table 41: EC200A-EU Current Consumption ............................................................................................ 79

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Table 42: 1.8 V I/O Requirements .............................................................................................................. 82

Table 43: (U)SIM 1.8 V I/O Requirements ................................................................................................. 83
Table 44: (U)SIM 3.0 V I/O Requirements ................................................................................................. 83
Table 45: Electrostatics Discharge Characteristics (25 °C, 45 % Relative Humidity) ............................... 84
Table 46: Operating and Storage Temperatures ........................................................................................ 84
Table 47: Recommended Thermal Profile Parameters .............................................................................. 91
Table 48: Carrier Tape Dimension Table (Unit: mm) .................................................................................. 92
Table 49: Plastic Reel Dimension Table (Unit: mm) ................................................................................... 93
Table 50: Related Documents .................................................................................................................... 94
Table 51: Terms and Abbreviations ............................................................................................................ 94

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Figure Index

Figure 1: Functional Diagram ..................................................................................................................... 16

Figure 2: Pin Assignment (Top View) ......................................................................................................... 17
Figure 3: Sleep Mode Application via UART .............................................................................................. 27
Figure 4: Sleep Mode Application with USB Remote Wakeup .................................................................. 28
Figure 5: Sleep Mode Application with MAIN_RI ....................................................................................... 29
Figure 6: Sleep Mode Application without Suspend Function ................................................................... 29
Figure 7: Reference Design of Power Supply ............................................................................................ 31
Figure 8: Power Supply Limits during Burst Transmission ........................................................................ 32
Figure 9: Star Structure of the Power Supply ............................................................................................ 32
Figure 10: Reference Circuit of Turning on the Module Using Driving Circuit ........................................... 33
Figure 11: Reference Circuit of Turning on the Module with Button .......................................................... 33
Figure 12: Power-up Timing ....................................................................................................................... 34
Figure 13: Timing of Turning off Module .................................................................................................... 35
Figure 14: Reference Circuit of RESET_N with Driving Circuit ................................................................. 36
Figure 15: Reference Circuit of RESET_N with Button ............................................................................. 36
Figure 16: Timing of Resetting Module ...................................................................................................... 37
Figure 17: Reference Circuit of USB Interface .......................................................................................... 39
Figure 18: Reference Circuit of USB_BOOT Interface .............................................................................. 40
Figure 19: Timing Sequence for Entering Emergency Download Mode.................................................... 41
Figure 20: Reference Circuit of (U)SIM Interface with an 8-pin (U)SIM Card Connector ......................... 42
Figure 21: Reference Circuit of (U)SIM Interface with a 6-pin (U)SIM Card Connector ........................... 43
Figure 22：Timing Sequence for Short Frame Mode ................................................................................ 44
Figure 23: PCM and I2C Interface Circuit Reference Design .................................................................... 45
Figure 24: Microphone Interface Reference Circuit ................................................................................... 47
Figure 25: Handset Interface Reference Circuit ........................................................................................ 48
Figure 26: Reference Circuit with Translator Chip ..................................................................................... 49
Figure 27: Reference Circuit with Transistor Circuit .................................................................................. 50
Figure 28: Reference Circuit of SD Card Interface .................................................................................... 51
Figure 29: Reference Circuit of RMII to PHY Interface .............................................................................. 54
Figure 30: Reference Circuit of RGMII to PHY Interface ........................................................................... 55
Figure 31: Reference Circuit of the Network Status Indication .................................................................. 57
Figure 32: Reference Circuits of STATUS ................................................................................................. 57
Figure 33: Reference Circuit for RF Antenna Interfaces............................................................................ 65
Figure 34: Microstrip Design on a 2-layer PCB ......................................................................................... 66
Figure 35: Coplanar Waveguide Design on a 2-layer PCB ....................................................................... 66
Figure 36: Coplanar Waveguide Design on a 4-layer PCB (Layer 3 as Reference Ground) .................... 67
Figure 37: Coplanar Waveguide Design on a 4-layer PCB (Layer 4 as Reference Ground) .................... 67
Figure 38: Dimensions of U.FL-R-SMT Connector (Unit: mm) .................................................................. 69
Figure 39: Mechanicals of U.FL-LP Connectors ........................................................................................ 69
Figure 40: Space Factor of Mated Connector (Unit: mm).......................................................................... 70
Figure 41: Module Top and Side Dimensions (Unit: mm) .......................................................................... 85

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Figure 42: Module Bottom Dimensions View (Unit: mm) ........................................................................... 86

Figure 43: Recommended Footprint (Perspective View) ........................................................................... 87
Figure 44: Top and Bottom Views of the Module ....................................................................................... 88
Figure 45: Recommended Reflow Soldering Thermal Profile ................................................................... 90
Figure 46: Carrier Tape Dimension Drawing .............................................................................................. 92
Figure 47: Plastic Reel Dimension Drawing .............................................................................................. 92
Figure 48: Packaging Process ................................................................................................................... 93

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 LTE Standard Module Series

1 Introduction
This document defines the EC200A series module and describes its air interfaces and hardware
interfaces which are connected with customers’ applications.

It can help customers quickly understand interface specifications, electrical and mechanical details, as
well as other related information of the module. Associated with application notes and user guides,
customers can use this module to design and to set up mobile applications easily.

1.1. Special Marks

Table 1: Special Marks

Mark Definition

Unless otherwise specified, when an asterisk (*) is used after a function, feature, interface,
pin name, AT command, or argument, it indicates that the function, feature, interface, pin,
*
AT command, or argument is under development and currently not supported; and the
asterisk (*) after a model indicates that the sample of such model is currently unavailable.
Brackets ([…]) used after a pin enclosing a range of numbers indicate all pins of the same
[…] type. For example, SD_SDIO_DATA[0:3] refers to all four SD_SDIO_DATA pins,
SD_SDIO_DATA0, SD_SDIO_DATA1, SD_SDIO_DATA2, and SD_SDIO_DATA3.

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2 Product Overview
EC200A is a series of LTE-FDD/LTE-TDD/WCDMA/GSM wireless communication module with receive
diversity, which provides data connectivity on LTE-FDD, LTE-TDD, HSDPA, HSUPA, HSPA+, WCDMA,
EDGE and GPRS network data connection. It also provides voice functionality for your specific
applications. EC200A series contains 3 variants: EC200A-CN, EC200A-AU, and EC200A-EU. You can
choose a dedicated type based on the region or operator. The following table shows the frequency bands
of EC200A series module.

Table 2: Brief Introduction of the Module

Categories

Packaging and pins number LCC 80-pin; LGA 64-pin

Dimensions (29.0 ±0.15) mm × (32.0 ±0.15) mm × (2.4 ±0.2) mm

Weight 4.4 g

Wireless network functions LTE/WCDMA/GSM

Variants EC200A-CN, EC200A-AU, EC200A-EU

2.1. Frequency Bands and Functions

Table 3: Wireless Network Type

Wireless Network
EC200A-CN EC200A-AU EC200A-EU
Type
B1/B2/B3/B4/B5/B7/B8/
LTE-FDD B1/B3/B5/B8 B1/B3/B5/B7/B8/B20/B28
B28/B66
LTE-TDD B34/B38/B39/B40/B41 B40 B38/B40/B41

WCDMA B1/B5/B8 B1/B2/B4/B5/B8 B1/B5/B8

GSM 900/1800 MHz 850/900/1800/1900 MHz 900/1800 MHz

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2.2. Key Features

Table 4: Key Features

Features Details

⚫ Supply voltage: 3.4~4.5 V

Power Supply
⚫ Typical supply voltage: 3.8 V
⚫ Text and PDU mode
⚫ Point-to-point MO and MT
SMS
⚫ SMS cell broadcast
⚫ SMS storage: ME by default
(U)SIM Interface ⚫ Supports (U)SIM card: 1.8/3.0 V

⚫ Supports one digital audio interface: PCM Interface

⚫ Supports one analog audio interface: MIC/SPK Interface
⚫ GSM: HR/FR/EFR/AMR/AMR-WB
Audio Features
⚫ WCDMA: AMR/AMR-WB
⚫ LTE: AMR/AMR-WB
⚫ Supports echo cancellation and noise suppression.
⚫ Used for audio function with external codec
⚫ Supports 16 format
PCM Interface
⚫ Supports short frame
⚫ Supports master and slave modes*
⚫ Supports one analog audio input and one analog audio output
Analog audio Interface
channel
⚫ Supports one SPI interface
SPI Interface ⚫ Maximum clock frequency 52 MHz
⚫ Supports master
⚫ Supports one I2C interface
⚫ Complies with I2C bus protocol specifications
I2C Interface
(100/400 kHz)
⚫ The multi-host mode is not supported
⚫ Compliant with USB 2.0 specification (slave only); the data
transfer rate can reach up to 480 Mbps
⚫ Used for AT command communication, data transmission,
USB Interface
software debugging and firmware upgrade
⚫ Supports USB serial driver for Windows 7/8/8.1/10, Linux
2.6~5.12 and Android 4.x–11.x systems
SD Interface ⚫ Supports SD 3.0 protocol.
⚫ Supports RMII: 1.8/3.3 V; default: 3.3 V
RMII/RGMII Interface
⚫ Supports RGMII: 1.8 V

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Main UART:
⚫ Used for AT command communication and data transmission
⚫ Baud rate: 115200 bps by default, Max 921600 bps
UART Interfaces ⚫ Supports RTS and CTS hardware flow control
Debug UART:
⚫ Used for the output of partial logs
⚫ Baud rate: 115200 bps.
⚫ Supports two ADC interfaces
ADC Interfaces
⚫ Voltage range: 0 V~VBAT_BB
⚫ NET_MODE and NET_STATUS to indicate network connectivity
Network Indication
status
⚫ Compliant with 3GPP TS 27.007, 3GPP TS 27.005 and Quectel
AT Commands
enhanced AT commands
Rx-diversity ⚫ Supports LTE Rx-diversity
⚫ Main antenna interface (ANT_MAIN) and Rx-diversity antenna
Antenna Interface interface (ANT_DRX)
⚫ 50 Ω impedance
⚫ GSM850: Class 4 (33 dBm ±2 dB)
⚫ EGSM900: Class 4 (33 dBm ±2 dB)
⚫ DCS1800: Class 1 (30 dBm ±2 dB)
⚫ PCS1900: Class 1 (30 dBm ±2 dB)
⚫ GSM850 8-PSK: Class E2 (27 dBm ±3 dB)
Transmitting Power ⚫ EGSM900 8-PSK: Class E2 (27 dBm ±3 dB)
⚫ DCS1800 8-PSK: Class E2 (26 dBm ±3 dB)
⚫ PCS1900 8-PSK: Class E2 (26 dBm ±3 dB)
⚫ WCDMA: Class 3 (24 dBm +1/-3 dB)
⚫ LTE-FDD: Class 3 (23 dBm ±2 dB)
⚫ LTE-TDD: Class 3 (23 dBm ±2 dB)
⚫ Supports 3GPP R9 non-CA Cat 4 FDD and TDD
⚫ Supports 1.4/3/5/10/15 to 20 MHz RF bandwidth
⚫ Supports MIMO in DL direction
LTE Features ⚫ Supports uplink QPSK, 16-QAM modulation
⚫ Supports downlink QPSK, 16-QAM and 64-QAM modulation
⚫ FDD: Max. 150 Mbps (DL)/ 50 Mbps (UL)
⚫ TDD: Max. 130 Mbps (DL)/ 30 Mbps (UL)
⚫ Supports 3GPP R7 HSPA+/HSDPA/HSUPA and WCDMA
⚫ Supports QPSK, 16QAM, 64QAM modulation
UMTS Features ⚫ HSPA+: Max. 21 Mbps (DL)
⚫ HSUPA: Max. 5.76 Mbps (UL)
⚫ WCDMA: Max. 384 kbps (DL)/384 kbps (UL)
GPRS:
GSM Features ⚫ Supports GPRS multi-slot class 12
⚫ Coding scheme: CS 1-4

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⚫ Max. 85.6 kbps (DL)/85.6 kbps (UL)

EDGE:
⚫ Supports EDGE multi-slot class 12
⚫ Supports GMSK and 8-PSK for different MCS (Modulation
and Coding Scheme)
⚫ Downlink coding schemes: MCS 1-9
⚫ Uplink coding schemes: MCS 1-9
⚫ Max. 236.8 kbps (DL)/236.8 kbps (UL)
⚫ Supports TCP/UDP/PPP/NTP/NITZ/FTP/HTTP/PING/CMUX/
Internet Protocol Features HTTPS/FTPS/SSL/FILE/MQTT/MMS/SMTP/SMTPS protocols
⚫ Supports PAP and CHAP for PPP connections
⚫ Operating temperature range 1: -35 to +75 °C
Temperature Range ⚫ Extended temperature range 2: -40 to +85 °C
⚫ Storage temperature range: -40 to +90 °C

Firmware Upgrade Use USB interface or DFOTA to upgrade.

RoHS All hardware components are fully compliant with EU RoHS directive.

1 Within the operating temperature range, the module meets 3GPP specifications.
2 Within the extended temperature range, the module remains the ability to establish and maintain functions such as voice,
SMS, data transmission, etc., without any unrecoverable malfunction. Radio spectrum and radio network are not influenced,
while one or more specifications, such as Pout, may exceed the specified tolerances of 3GPP. When the temperature
returns to the operating temperature range, the module meets 3GPP specifications again.

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2.3. Functional Diagram

The following figure shows a block diagram of the module and illustrates the major functional parts.

⚫ Power management
⚫ Baseband
⚫ DDR + NAND flash
⚫ Radio frequency
⚫ Peripheral interface

ANT_MAIN ANT_DRX

PAM Switch

SAW
Duplex
SAW
VBAT_RF
PA
PRx DRx

Tx

26M
FLASH
DCXO

VBAT_BB
PMIC Control
PWRKEY Transceiver RAM
Baseband
ADCs

VDD_EXT MIC/SPK PCM RESET_N USB (U)SIM I2C SPI UARTs STATUS SD RGMII/RMII

Figure 1: Functional Diagram

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2.4. Pin Assignment

The following figure illustrates the pin assignment of the module.

RESERVED
RESERVED

RESERVED
MAIN_DTR
MAIN_RXD

MAIN_CTS
MAIN_RTS

MAIN_DCD

VBAT_RF
MAIN_TXD
USB_VBUS

VBAT_RF
VBAT_BB
VBAT_BB
MAIN_RI
USB_DM

STATUS
USB_DP
114
113

55
62

58
57
67

65
64

61
60
59

56
71

63
70
69
68

66
72

GND
GND
1 54
WAKEUP_IN GND

2 53
AP_READY GND
129 117
3
RESERVED
RESERVED RESERVED 52
GND
108 103 99 95 90 85
4
W_DISABLE#
130 118 GND GND GND GND GND GND
51
GND
RESERVED RESERVED

5 50
NET_MODE
131 119 GND

6
NET_STATUS
RESERVED
R GM I I/R MI I
_R ST_N 49
A NT _ M A IN

7 132 120
R GM I I/R MI I
109 104 100 96 91 86 48
VDD_EXT GND
RESERVED _I NT
GND GND GND GND
GND GND

141
RESERVED 133 121 144
RESERVED
R GM I I/R MI I
RESERVED
142
RESERVED
_M D_I O
82
R GM I I_ R
79
R GM I I_ R
76
R GM I I/R M
73
R GM I I/R M
143
RESERVED
134 122 X_3 X_2 I I_ R X_0 I I_R X_1

47
8 R GM I I/R MI I

83 80 77 74
GND RESERVED _M D_C LK
110 105 R GM I I_ C R GM I I_ T R GM I I/ R MI R GM I I/R MI I_ 92 87 RESERVED

9
GND 135 123 GND GND
K_TX X_2 I_TX _0 C TL_R X

GND GND 46
GND
RESERVED SPK_N 84 81 78 75
10
USIM _GND
R GM I I_T
X_3
R GM I I/R MI I_
C TL_TX
R GM I I/R MI
I_TX _1
R GM I I/R
M I _C LK 45
ADC0
136 124
11
DBG_RXD
RESERVED SPK_P 44
ADC1

12
DBG_TXD
137 125 111 106 101 97 93 88 43
RESERVED
RESERVED MIC_P

13 GND GND GND GND GND GND

42
USIM _DET
138 126 I2C_SDA

14
USIM _VDD
RESERVED MIC_N 41
I2C_SCL

15 139 127 40
USIM _DATA RESERVED RESERVED SPI_CLK
112 107 102 98 94 89
16 39
USIM _CLK 140 128 GND GND GND GND GND GND SPI_DIN

MICBIAS RESERVED
17
USIM _RST
38
SPI_DOUT
SD_SDIO _DATA3

SD_SDIO _DATA2

SD_SDIO _DATA1

SD_SDIO _DATA0

SD_SDIO _VDD
SD_SDIO _CMD

18 37
SD_SDIO _CLK
RESERVED

PCM_DOUT

PCM_SYNC

ANT_DRX
PCM_DIN
RESET_N

PWRKEY

PCM_CLK
U SB _ B OO T

SD_DET
116
115

36
23
24

27
28

32
33
21

25
26

29
30
31

34
35
20

22

GND
19

SPI_CS
GND

GND

RESERVED

Power Pins Debug PCM Pi ns ANT RESERVED

Si gnal Pi ns Main I2C ADC MIC/SPK
(U)SI M SD USB SPI GND RMI I/RGMII

Figure 2: Pin Assignment (Top View)

NOTE

1. USB_BOOT cannot be pulled up before startup.

2. Other unused and RESERVED pins are kept open, and all GND pins are connected to the ground
network.

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 LTE Standard Module Series

2.5. Pin Description

The following table shows the DC characteristics and pin descriptions.

Table 5: I/O Parameters Definition

Type Description

AI Analog Input

AO Analog Output

AIO Analog Input/Output

DI Digital Input

DO Digital Output

DIO Digital Input/Output

OD Open Drain

PI Power Input

PO Power Output

Table 6: Pin Description

Power Supply

DC
Pin Name Pin No. I/O Description Comment
Characteristics
It must be
Vmax = 4.5 V
Power supply for the provided with
VBAT_BB 59, 60 PI Vmin = 3.4 V
module’s baseband part sufficient current
Vnom = 3.8 V
up to 0.8 A.
It must be
Vmax = 4.5 V
Power supply for the provided with
VBAT_RF 57, 58 PI Vmin = 3.4 V
module’s RF part sufficient current
Vnom = 3.8 V
up to 1.8 A.
It can provide a
pull-up power to
Provide 1.8 V for Vnom = 1.8 V
VDD_EXT 7 PO the external
external circuit IOmax = 50 mA
GPIO.
If unused, keep

EC200A_Series_Hardware_Design 18 / 97
 LTE Standard Module Series

it open.

GND 8, 9, 10,19, 22, 36, 46, 48, 50~54, 56, 72, 85~112

Turn On/Off

DC
Pin Name Pin No. I/O Description Comment
Characteristics
VBAT power
PWRKEY 21 DI Turn on/off the module domain.
Active low.
VILmax = 0.5 V 1.8 V power
domain.
RESET_N 20 DI Reset the module
Active low after
turn-on.

Indication Interface

DC
Pin Name Pin No. I/O Description Comment
Characteristics
External pull to
Indicate the module's
STATUS 61 OD 1.8 V. If unused,
operation status
keep it open.
1.8 V power
Indicate the module's VOHmin = 1.35 V domain. If
NET_STATUS 6 DO
network activity status VOLmax = 0.45 V unused, keep it
open.
1.8 V power
Indicate the module’s
VOHmin = 1.35 V domain. If
NET_MODE 5 DO network registration
VOLmax = 0.45 V unused, keep it
mode
open.

USB Interface

DC
Pin Name Pin No. I/O Description Comment
Characteristics
Vmax = 5.25 V Typ. 5.0 V.
USB_VBUS 71 AI USB connection detect Vmin = 3.0 V If unused, keep
Vnom = 5.0 V it open.

USB_DP 69 AIO USB differential data (+) 90 Ω differential

impedance.
USB 2.0
USB_DM 70 AIO USB differential data (-) compliant.
If unused, keep
it open.

(U)SIM Interface

EC200A_Series_Hardware_Design 19 / 97
 LTE Standard Module Series

DC
Pin Name Pin No. I/O Description Comment
Characteristics
1.8 V (U)SIM： Either 1.8 V or
Vmax = 1.9 V 3.0 V (U)SIM
Vmin = 1.7 V card is
(U)SIM card power
USIM_VDD 14 PO supported and
supply
3.0 V (U)SIM： can be identified
Vmax = 3.05 V automatically by
Vmin = 2.7 V the module.
1.8 V (U)SIM：
VILmax = 0.6 V
VIHmin = 1.2 V
VOLmax = 0.45 V
VOHmin = 1.35 V
USIM_DATA 15 DIO (U)SIM card data
3.0 V (U)SIM：
VILmax = 1.0 V
VIHmin = 1.95 V
VOLmax = 0.45 V
VOHmin = 2.55 V
1.8 V (U)SIM：
USIM_CLK 16 DO (U)SIM card clock
VOLmax = 0.45 V
VOHmin = 1.35 V

USIM_RST 17 DO (U)SIM card reset 3.0 V (U)SIM：

VOLmax = 0.45 V
VOHmin = 2.55 V
VILmin = -0.3 V 1.8 V power
(U)SIM card hot-plug VILmax = 0.6 V domain.
USIM_DET 13 DI
detect VIHmin = 1.2 V If unused, keep
VIHmax = 2.0 V it open.

SD Interface

DC
Pin Name Pin No. I/O Description Comment
Characteristics

SD_SDIO_CLK 32 DO SD card SDIO clock

SD_SDIO_CMD 33 DIO SD card SDIO command 1.8/2.8 V power

domain.
SD_SDIO_DATA0 31 DIO SD card SDIO bit 0
If unused, keep
SD_SDIO_DATA1 30 DIO SD card SDIO bit 1 it open.

SD_SDIO_DATA2 29 DIO SD card SDIO bit 2

EC200A_Series_Hardware_Design 20 / 97
 LTE Standard Module Series

SD_SDIO_DATA3 28 DIO SD card SDIO bit 3

SD card SDIO power

SD_SDIO_VDD 34 PO
supply
1.8 V power
domain. If
SD_DET* 23 DI SD card hot-plug detect
unused, keep it
open.

Main UART Interface

DC
Pin Name Pin No. I/O Description Comment
Characteristics
Main UART ring VOLmax = 0.45 V
MAIN_RI 62 DO
indication VOHmin = 1.35 V
Main UART data carrier VOLmax = 0.45 V
MAIN_DCD 63 DO
detect VOHmin = 1.35 V
DTE clear to send signal
VOLmax = 0.45 V
MAIN_CTS 64 DO from DCE (Connect to
VOHmin = 1.35 V
DTE’s CTS) 1.8 V power
DTE request to send domain.
MAIN_RTS 65 DI signal to DCE (Connect If unused, keep
VILmin = -0.3 V
to DTE’s RTS) it open.
VILmax = 0.6 V
Main UART data terminal VIHmin = 1.2 V
MAIN_DTR 66 DI
ready VIHmax = 2.0 V
MAIN_RXD 68 DI Main UART receive

VOLmax = 0.45 V
MAIN_TXD 67 DO Main UART transmit
VOHmin = 1.35 V

Debug UART Interface

DC
Pin Name Pin No. I/O Description Comment
Characteristics
VILmin = -0.3 V
VILmax = 0.6 V 1.8 V power
DBG_RXD 11 DI Debug UART receive
VIHmin = 1.2 V domain.
VIHmax = 2.0 V If unused, keep
VOLmax = 0.45 V it open.
DBG_TXD 12 DO Debug UART transmit
VOHmin = 1.35 V

SPI Interface

DC
Pin Name Pin No. I/O Description Comment
Characteristics
VOLmax = 0.45 V 1.8 V power
SPI_CS 37 DO SPI chip select
VOHmin = 1.35 V domain.

EC200A_Series_Hardware_Design 21 / 97
 LTE Standard Module Series

VOLmax = 0.45 V If unused, keep

SPI_DOUT 38 DO SPI data output
VOHmin = 1.35 V it open.
VILmin = -0.3 V
VILmax = 0.6 V
SPI_DIN 39 DI SPI data input
VIHmin = 1.2 V
VIHmax = 2.0 V
VOLmax = 0.45 V
SPI_CLK 40 DO SPI clock
VOHmin = 1.35 V

I2C Interface

DC
Pin Name Pin No. I/O Description Comment
Characteristics

I2C_SCL 41 OD I2C serial clock Used for

external codec.
An external 1.8
I2C_SDA 42 OD I2C serial data V pull-up
resistor is
needed.

PCM Interface

DC
Pin Name Pin No. I/O Description Comment
Characteristics

PCM_SYNC 26 DIO PCM data frame sync 1.8 V power

domain.
VILmin = -0.3 V In master mode,
VILmax = 0.6 V it serves as an
VIHmin = 1.2 V output signal.
PCM_CLK 27 DIO PCM clock VIHmax = 2.0 V In slave mode, it
VOLmax = 0.45 V is used as an
VOHmin = 1.35 V input signal.
If unused, keep
it open.
VILmin = -0.3 V
VILmax = 0.6 V 1.8 V power
PCM_DIN 24 DI PCM data input
VIHmin = 1.2 V domain.
VIHmax = 2.0 V If unused, keep
VOLmax = 0.45 V it open.
PCM_DOUT 25 DO PCM data output
VOHmin = 1.35 V

RF Antenna Interface

DC
Pin Name Pin No. I/O Description Comment
Characteristics
Diversity antenna 50 Ω
ANT_DRX 35 AI
interface impedance.

EC200A_Series_Hardware_Design 22 / 97
 LTE Standard Module Series

ANT_MAIN 49 AIO Main antenna interface

ADC Interface

DC
Pin Name Pin No. I/O Description Comment
Characteristics

ADC0 45 AI General-purpose ADC Voltage Range: If unused, keep

ADC1 44 AI interface 0 V–VBAT_BB it open.

RMII/RGMII Interface

DC
Pin Name Pin No. I/O Description Comment
Characteristics
RGMII/RMII_RX_ RGMII/RMII receive data
73 DI
1 bit 1
RGMII/RMII_CTL RGMII/RMII receive
74 DI
_RX control

RGMII/RMII_CLK 75 DI RGMII/RMII clock

RGMII/RMII_RX_ RGMII/RMII receive data

76 DI
0 bit 0
RGMII/RMII transmit
RGMII/RMII_TX_0 77 DO
data bit 0
RGMII/RMII transmit 1.8 V power
RGMII/RMII_TX_1 78 DO
data bit 1 domain for
RGMII_RX_2 79 DI RGMII receive data bit 2 RGMII.
1.8/3.3 V
RGMII_TX_2 80 DO RGMII transmit data bit 2 (default 3.3 V)
RGMII/RMII_CTL RGMII/RMII transmit power domain
81 DO
_TX control for RMII.
If unused, keep
RGMII_RX_3 82 DI RGMII receive data bit 3
it open.
RGMII_CK_TX 83 DO RGMII transmit clock

RGMII_TX_3 84 DO RGMII transmit data bit 3

RGMII/RMII interrupt
RGMII/RMII_INT 120 DI
input
RGMII/RMII
RGMII/RMII_MD_
121 IO management data
IO
input/output
RGMII/RMII_MD_ RGMII/RMII
122 DO
CLK management data clock
RGMII/RMII_RST 1.8 V power
119 DIO RGMII/RMII reset
_N domain.

EC200A_Series_Hardware_Design 23 / 97
 LTE Standard Module Series

Low level by
default.
Cannot be
pulled high
before module’s
successful
power-on.

Analog Audio Interface

DC
Pin Name Pin No. I/O Description Comment
Characteristics
Analog audio differential
SPK_N 123 AO
output channel (-)
Analog audio differential
SPK_P 124 AO
output channel (+)
Microphone input
MIC_P 125 AI
channel (+)
Microphone input
MIC_N 126 AI
channel (-)

MICBIAS 140 PO Microphone bias voltage

Other Interface

DC
Pin Name Pin No. I/O Description Comment
Characteristics
1.8 V power
domain.
VILmin = -0.3 V
Active High.
Forces the module to VILmax = 0.6 V
USB_BOOT 115 DI It is
enter download mode VIHmin = 1.2 V
recommended
VIHmax = 2.0 V
to reserve test
points.
1.8 V power
domain.
WAKEUP_IN* 1 DI Wake up the module
If unused, keep
it open.
VILmin = -0.3 V 1.8 V power
Application processor VILmax = 0.6 V domain.
AP_READY 2 DI
ready VIHmin = 1.2 V If unused, keep
VIHmax = 2.0 V it open.
1.8 V power
domain.
W_DISABLE# 4 DI Airplane mode control
Pull-up by
default.

EC200A_Series_Hardware_Design 24 / 97
 LTE Standard Module Series

In low voltage
level, module
can enter into
airplane mode.
If unused, keep
it open.

RESERVED Pins

Pin Name Pin No. Comment

Keep these pins

RESERVED 3, 18, 43, 47, 55, 113, 114, 116~119, 127~139, 141~144
unconnected.

2.6. EVB

In order to help customers to develop applications with the module conveniently, Quectel supplies an
evaluation board (EVB), USB data cable, earphone, antenna, and other peripherals to control or to test
the module. For more details, please refer to document [1].

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 LTE Standard Module Series

3 Operating Characteristics

3.1. Operating Modes

The table below outlines operating modes of the module.

Table 7: Overview of Operating Modes

Mode Details
Software is active. The module is registered on the network
Idle
and ready to send and receive data.
Normal Operation Network connection is ongoing. In this mode, the power
Talk/Data consumption is decided by network setting and data transfer
rate.
Minimum AT+CFUN=0 command can set the module to a minimum functionality mode. In
Functionality Mode this case, both RF function and (U)SIM card will be invalid.
AT+CFUN=4 command or W_DISABLE# pin can set the module to airplane
Airplane Mode
mode. In this case, RF function will be invalid.
In this mode, current consumption of the module will be reduced to the minimal
Sleep Mode level. In this mode, the module can still receive paging, SMS, voice call and
TCP/UDP data from network.
In this mode, the VBAT power supply is constantly turned on and the software
Power Down Mode
stops working.

NOTE

For more details about the AT command, see document [2].

EC200A_Series_Hardware_Design 26 / 97
 LTE Standard Module Series

3.2. Sleep Mode

In sleep mode, the module can reduce power consumption to a very low level, the following section
describes power saving procedures of EC200A series module.

3.2.1. UART Application

If the host communicates with module via UART interface, the following preconditions should be met to
enable the module enter sleep mode.

⚫ Execute AT+QSCLK=1 to enable sleep mode.

⚫ Drive MAIN_DTR to high level.

The following figure shows the connection between the module and the host.

Module Host
MAIN_RXD TXD

MAIN_TXD RXD

MAIN_RI EINT

MAIN_DTR GPIO

AP_READY GPIO

GND GND

Figure 3: Sleep Mode Application via UART

⚫ Driving MAIN_DTR to low level by host will wake up the module.

⚫ When the module has a URC to report, the URC will trigger the behavior of MAIN_RI pin. Please
refer to Chapter 4.12 for details about MAIN_RI behavior.

3.2.2. USB Application with USB Remote Wakeup Function

If the host supports USB Suspend/Resume and remote wakeup functions, the following three
preconditions must be met to let the module enter sleep mode.

⚫ Execute AT+QSCLK=1 command to enable the sleep mode.

⚫ Ensure the MAIN_DTR is kept at high level or kept open.
⚫ The host’s USB bus, which is connected with the module’s USB interface, enters Suspend state.

The following figure shows the connection between the module and the host.

EC200A_Series_Hardware_Design 27 / 97
 LTE Standard Module Series

Module Host
USB_VBUS VDD

USB_DP USB_DP

USB_DM USB_DM

AP_READY GPIO
GND GND

Figure 4: Sleep Mode Application with USB Remote Wakeup

⚫ Sending data to the module through USB will wake up the module.
⚫ When the module has a URC to report, the module will send remote wakeup signals via USB bus to
wake up the host.

NOTE

The AP_READY is active low and the default state is high.

3.2.2.1. USB Application with USB Suspend/Resume and RI Function

If the host supports USB Suspend/Resume, but does not support remote wakeup function, the MAIN_RI
signal is needed to wake up the host.

There are three preconditions to let the module enter sleep mode.

⚫ Execute AT+QSCLK=1 to enable the sleep mode.

⚫ Ensure the MAIN_DTR is held at high level or keep it open.
⚫ The host’s USB bus, which is connected with the module’s USB interface, enters Suspend state.

The following figure shows the connection between the module and the host.

EC200A_Series_Hardware_Design 28 / 97
 LTE Standard Module Series

Module Host
USB_VBUS VDD

USB_DP USB_DP

USB_DM USB_DM

AP_READY GPIO
MAIN_RI EINT
GND GND

Figure 5: Sleep Mode Application with MAIN_RI

⚫ Sending data to EC200A series through USB will wake up the module.
⚫ When EC200A series has a URC to report, the URC will trigger the behavior of MAIN_RI pin. Please
refer to Chapter 4.12 for details about MAIN_RI behavior.

3.2.2.2. USB Application without USB Suspend Function

If the host does not support USB Suspend function, please disconnect USB_VBUS with additional control
circuit to let the module enter into sleep mode.

⚫ Execute AT+QSCLK=1 command to enable the sleep mode.

⚫ Ensure the MAIN_DTR is held at high level or keep it open.
⚫ Disconnect USB_VBUS.

The following figure shows the connection between the module and the host.

Module Host
GPIO

Power
USB_VBUS Switch VDD

USB_DP USB_DP

USB_DM USB_DM

MAIN_RI EINT

AP_READY GPIO

GND GND

Figure 6: Sleep Mode Application without Suspend Function

Turn on the power switch and supply power to USB_VBUS will wake up the module.

EC200A_Series_Hardware_Design 29 / 97
 LTE Standard Module Series

NOTE

Please pay attention to the level match shown in dotted line between the module and the host.

3.3. Airplane Mode

When the module enters into airplane mode, the RF function will be disabled, and all AT commands
related to it will be inaccessible. This mode can be set via the following ways.

Hardware:

The W_DISABLE# pin is pulled up by default. Its control function for airplane mode is disabled by default,
and AT+QCFG=“airplanecontrol”,1 can be used to enable the function. Driving the pin to low level can
make the module enter airplane mode.

Software:

AT+CFUN=<fun> command provides choices of the functionality level through setting <fun> into 0, 1
or 4.

⚫ AT+CFUN=0: Minimum functionality mode (Both (U)SIM and RF functions are disabled.).
⚫ AT+CFUN=1: Full functionality mode (by default).
⚫ AT+CFUN=4: Airplane mode (RF function is disabled.).

⚫ NOTE

For more details about AT command, see document [2].

3.4. Power Supply

3.4.1. Power Supply Pins

The module provides four VBAT pins dedicated to the connection with the external power supply. There
are two separate voltage domains for VBAT.

⚫ Two VBAT_RF pins for module’s RF part

⚫ Two VBAT_BB pins for module’s baseband part

The following table shows the details of power supply and GND pins.

EC200A_Series_Hardware_Design 30 / 97
 LTE Standard Module Series

Table 8: Pin Definition of Power Supply

Pin Name Pin No. I/O Description Comment

It must be provided with
Power supply for the
VBAT_BB 59、60 PI sufficient current up to
module’s baseband part
0.8 A.
It must be provided with
Power supply for the
VBAT_RF 57、58 PI sufficient current up to
module’s RF part
1.8 A.
It can provide a pull-up
Provide 1.8V for external power to the external
VDD_EXT 7 PO
circuit GPIO.
If unused, keep it open.

3.4.2. Reference Design for Power Supply

The performance of the module largely depends on the power source. The power supply of the module
should be able to provide sufficient current of 3 A at least. If the voltage drops between input and output
is not too high, it is suggested that an LDO should be used to supply power to the module. If there is a
big voltage difference between input and the desired output VBAT, a buck converter is preferred as the
power supply.

The following figure shows a reference design for +5 V input power source. The design uses the LDO
MIC29302WU from Micrel company. The typical output of the power supply is about 3.8 V and the
maximum load current is 3.0 A.

MIC29302WU

DC_IN VBAT
2 4
IN OUT
GND

ADJ
EN

100K
1%
1

51K

4.7K 330R
470 µF 100 nF 470 µF 100 nF
47K
VBAT_EN 47K 1%

Figure 7: Reference Design of Power Supply

⚫
NOTE

It is recommended to design switch control for power supply.

EC200A_Series_Hardware_Design 31 / 97
 LTE Standard Module Series

3.4.3. Requirements for Voltage Stability

The power supply range of the module is from 3.4 V to 4.5 V. Please make sure the input voltage will
never drop below 3.4 V.

Burst Burst
Transmission Transmission

VBAT Ripple
Drop

Figure 8: Power Supply Limits during Burst Transmission

To decrease voltage drop, a bypass capacitor of about 100 µF with low ESR (ESR = 0.7 Ω) should be
used, and a multi-layer ceramic chip (MLCC) capacitor array should also be reserved due to its ultra-low
ESR. It is recommended to use three ceramic capacitors (100 nF, 33 pF, 10 pF) for composing the MLCC
array, and place these capacitors close to the VBAT_BB and VBAT_RF pins. The main power supply from
an external application has to be a single voltage source and can be expanded to two sub paths with star
structure. The width of VBAT_BB trace should be no less than 1 mm; and the width of VBAT_RF trace
should be no less than 2 mm. In principle, the longer the VBAT trace is, the wider it will be.

In addition, in order to ensure the stability of power source, it is suggested that a TVS diode of which
reverse stand-off voltage is 4.7 V and peak pulse power is up to 2550 W should be used. The following
figure shows the star structure of the power supply.

VBAT

VBAT_RF

VBAT_BB
+ +
D1 C1 C2 C3 C4 C5 C6 C7 C8

WS4.5D3HV 100 µF 100 nF 33 pF 10 pF 100 µF 100 nF 33 pF 10 pF

Module

Figure 9: Star Structure of the Power Supply

EC200A_Series_Hardware_Design 32 / 97
 LTE Standard Module Series

3.5. Turn On

3.5.1. Turn on the Module with PWRKEY

Table 9: Pin Definition of PWRKEY

Pin Name Pin No. I/O Description Comment

VBAT power domain.

PWRKEY 21 DI Turn on/off the module
Active low.

When the module is in power down mode, it can be turned on to normal mode by driving the PWRKEY pin
to a low level for at least 500 ms. It is recommended to use an open drain/collector driver to control the
PWRKEY. A simple reference circuit is illustrated in the following figure.

PWRKEY

≥ 500 ms
4.7K
10 nF
Turn-on pulse

47K

Figure 10: Reference Circuit of Turning on the Module Using Driving Circuit

The other way to control the PWRKEY is using a button directly. When pressing the button, electrostatic
strike may generate from finger. Therefore, a TVS component is indispensable to be placed nearby the
button for ESD protection. A reference circuit is shown in the following figure.

S1

PWRKEY

TVS
Turn-on pulse

Close to S1 Module

Figure 11: Reference Circuit of Turning on the Module with Button

EC200A_Series_Hardware_Design 33 / 97
 LTE Standard Module Series

The power-up scenario is illustrated in the following figure.

NOTE 1

VBAT ≥ 500 ms

PWRKEY VIL ≤ 0.5 V

About 5 ms
VDD_EXT

≥ 100 ms. After this time, the pin can be set

high level by an external circuit.
USB_BOOT
About 22 ms
RESET_N
≥ 10 s

STATUS
(OD)

≥ 10 s

UART I nactive Active

≥ 10 s

USB Inactive Active

Figure 12: Power-up Timing

. NOTE

1. Make sure that VBAT is stable before pulling down PWRKEY pin. It is recommended that the time
difference between powering up VBAT and pulling down PWRKEY pin is no less than 30 ms.
2. PWRKEY can be pulled down directly to GND with a recommended 4.7 kΩ resistor if module needs
to be powered on automatically and shutdown is not needed.

EC200A_Series_Hardware_Design 34 / 97
 LTE Standard Module Series

3.6. Turn Off

The following procedures can be used to turn off the module:

3.6.1. Turn off the Module with PWRKEY

Driving the PWRKEY to a low-level voltage for at least 650 ms, then the module will execute power-down
procedure after the PWRKEY is released. The timing of turning off the module is illustrated in the following
figure.

VBAT

≥ 650 ms ≥ 2s

PWRKEY

STATUS
(OD)

Module Running Power-down procedure OFF

Status

Figure 13: Timing of Turning off Module

3.6.2. Turn off the Module with AT Command

It is safe to use AT+QPOWD command to turn off the module, which is equal to turn off the module via
PWRKEY Pin.

Please refer to document [2] for details about AT+QPOWD command.

. NOTE

1. To avoid damaging internal flash, do not switch off the power supply when the module works
normally. Only after shutting down the module with PWRKEY or AT command can you cut off the
power supply.
2. When turning off module with the AT command, please keep PWRKEY at high level after the
execution of the command. Otherwise, the module will be turned on again after successfully
turn-off.

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3.7. Reset

The module can be reset by driving the RESET_N low for at least 300 ms and then releasing it. The
RESET_N signal is sensitive to interference, so it is recommended to route the trace as short as possible
and surround it with ground.

Table 10: Pin Definition of RESET

Pin Name Pin No. I/O Description Comment

1.8 V power domain.

RESET_N 20 DI Reset the module
Active low after turn-on.

The recommended circuit is equal to the PWRKEY control circuit. An open drain/collector driver or button
can be used to control the RESET_N.

RESET_N

≥ 300 ms
4.7K

Reset pulse

47K

Figure 14: Reference Circuit of RESET_N with Driving Circuit

S2
RESET_N

TVS

Close to S2

Figure 15: Reference Circuit of RESET_N with Button

EC200A_Series_Hardware_Design 36 / 97
 LTE Standard Module Series

The timing of resetting module is illustrated in the following figure.

VBAT

≥ 300 ms

RESET_N
VIL ≤ 0.5 V

Module Running Baseband resetting Baseband restart

Status

Figure 16: Timing of Resetting Module

⚫
NOTE

1. Please ensure that there is no large capacitance with the max value exceeding 10 nF on PWRKEY
and RESET_N pins.
2. RESET_N only resets the internal baseband chip of the module and does not reset the power
management chip.

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4 Application Interfaces

4.1. USB Interface

EC200A series provides one integrated Universal Serial Bus (USB) interface which complies with the
USB 2.0 specification and supports full-speed (12 Mbps) and high-speed (480 Mbps) modes. The USB
interface can only serve as a slave device and is used for AT command communication, data transmission,
software debugging and firmware upgrade. The following table shows the pin definition of USB interface.

Table 11: Functions of the USB Interface

Functions

AT command communication YES

Data transmission YES

Software debugging YES

Firmware upgrade YES

Pin definition of the USB interface is here as follows:

Table 12: Pin Definition of USB Interface

Pin Name Pin No. I/O Description Comment

Typ. 5.0 V.
USB_VBUS 71 AI USB connection detect
If unused, keep it open.
USB_DP 69 AIO USB differential data (+) 90 Ω differential
impedance. USB 2.0
USB_DM 70 AIO USB differential data (-) compliant.
If unused, keep it open.

For more details about the USB 2.0 specifications, please visit http://www.usb.org/home.

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 LTE Standard Module Series

It is recommended to reserve test points for debugging and firmware upgrade in your designs. The
following figure shows a reference circuit of USB interface.

Test Points
Minimize these stubs

Module MCU
R1 NM_0 R
VDD R2 NM_0 R

USB_VBUS ESD Array

L1 USB_DM
USB_DM
USB_DP USB_DP

Close to Module GND

GND

Figure 17: Reference Circuit of USB Interface

A common mode choke L1 is recommended to be added in series between the module and your MCU in
order to suppress EMI spurious transmission. Meanwhile, the 0 Ω resistors (R1 and R2) should be added
in series between the module and the test points so as to facilitate debugging, and the resistors are not
mounted by default. In order to ensure the integrity of USB data line signal, L1, R1 and R2 components
must be placed close to the module, and also resistors R1 and R2 should be placed close to each other.
The extra stubs of trace must be as short as possible.

The following principles should be complied with when designing the USB interface, to meet USB
specifications.

⚫ It is important to route the USB signal traces as differential pairs with ground surrounded. The
impedance of USB differential trace is 90 Ω.
⚫ Do not route signal traces under crystals, oscillators, magnetic devices, PCIe and RF signal traces.
It is important to route the USB differential traces in inner-layer of the PCB, and surround the traces
with ground on that layer and ground planes above and below.
⚫ Junction capacitance of the ESD protection device might cause influences on USB data lines, so
please pay attention to the selection of the device. Typically, the stray capacitance should be less
than 2 pF for USB.
⚫ If possible, reserve a 0 Ω resistor on USB_DP and USB_DM lines respectively.

For more details about the USB specifications, please visit http://www.usb.org/home.

EC200A_Series_Hardware_Design 39 / 97
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4.2. USB_BOOT Interface

The module provides a USB_BOOT pin. You can pull up USB_BOOT to VDD_EXT before powering on
the module, thus the module will enter emergency download mode when powered on. In this mode, the
module supports firmware upgrade over USB interface.

Table 13: Pin Definition of USB_BOOT Interface

Pin Name Pin No. I/O Description Comment

1.8 V power domain.

Forces the module to enter Active High.
USB_BOOT 115 DI
download mode It is recommended to
reserve test points.

The following figure shows a reference circuit of USB_BOOT interface.

Module

VDD_EXT

Test point
4.7K
USB_BOOT
Close to test point

TVS

Figure 18: Reference Circuit of USB_BOOT Interface

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 LTE Standard Module Series

NOTE 1

VBAT 500 ms

PWRKEY VIL 0.5V

About 5 ms
VDD_EXT USB_BOOT can be pulled up to 1.8 V before
VDD_EXT is powered up, and the module will enter
emergency download mode when it is powered on.

USB_BOOT
About 22 ms

RESET_N

Figure 19: Timing Sequence for Entering Emergency Download Mode

. NOTE

1. Please make sure that VBAT is stable before pulling down PWRKEY pin. It is recommended that the
time between powering up VBAT and pulling down PWRKEY pin is no less than 30 ms.
2. When using MCU to control module to enter the emergency download mode, please follow the
above timing sequence. It is not recommended to pull up FORCE_USB_BOOT to 1.8 V before
powering up VBAT. Directly connect the test points as shown in Figure 18 can manually force the
module into download mode.
3. USB_BOOT cannot be pulled up before startup.

4.3. (U)SIM Interface

The (U)SIM interface circuitry meets ETSI and IMT-2000 requirements. Both 1.8 V and 3.0 V (U)SIM
cards are supported.

Table 14: Pin Definition of (U)SIM Interface

Pin Name Pin No. I/O Description Comment

USIM_VDD 14 PO (U)SIM card power supply Either 1.8 V or 3.0 V

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 LTE Standard Module Series

USIM_DATA 15 DIO (U)SIM card data (U)SIM card is

supported and can be
USIM_CLK 16 DO (U)SIM card clock identified automatically
by the module.
USIM_RST 17 DO (U)SIM card reset
1.8 V power domain.
USIM_DET 13 DI (U)SIM card hot-plug detect
If unused, keep it open.

The module supports (U)SIM card hot-plug via the USIM_DET pin, The function supports low level and
high level detections. By default, It is disabled, and can be configured via AT+QSIMDET command.
Please refer to document [2] for details about the command.

The reference circuit of the 8-pin (U)SIM interface is as follows.

VDD_EXT USIM_VDD

51K 15K
USIM_GND 100 nF (U)SIM Card Connector
USIM_VDD
VCC GND
USIM_RST 0R
RST VPP
Module USIM_CLK
CLK IO
USIM_DET 0R
USIM_DATA 0R

GND
33 pF 33 pF 33 pF

GND GND

Figure 20: Reference Circuit of (U)SIM Interface with an 8-pin (U)SIM Card Connector

If (U)SIM card detection function is not needed, please keep USIM_DET unconnected. A reference circuit
for (U)SIM interface with a 6-pin (U)SIM card connector is illustrated in the following figure.

EC200A_Series_Hardware_Design 42 / 97
 LTE Standard Module Series

USIM_VDD

15K
USIM_GND 100 nF
(U)SIM Card Connector
USIM_VDD
VCC GND
USIM_RST 0R
RST VPP
Module USIM_CLK
CLK IO
0R
USIM_DATA 0R

33 pF 33 pF 33 pF

GND GND

Figure 21: Reference Circuit of (U)SIM Interface with a 6-pin (U)SIM Card Connector

In order to enhance the reliability and availability of the (U)SIM card in applications, please follow the
criteria below in (U)SIM circuit design.

⚫ Keep (U)SIM card connector as close as possible to the module. Keep the trace length as less than
200 mm as possible.
⚫ Keep (U)SIM card signal traces away from RF and VCC traces.
⚫ USIM_VDD maximum bypass capacitor does not exceed 1uF.
⚫ Ensure the ground between the module and the (U)SIM card connector short and wide. Keep the
trace width of ground and USIM_VDD no less than 0.5 mm to maintain the same electric potential.
⚫ To avoid cross-talk between USIM_DATA and USIM_CLK, keep them away from each other and
shield them with ground surrounded.
⚫ In order to offer good ESD protection, it is recommended to add a TVS diode array whose parasitic
capacitance should not be more than 15 pF. The 0 Ω resistors should be added in series between the
module and the (U)SIM card to facilitate debugging. The 33 pF capacitors on the USIM_DATA,
USIM_CLK and USIM_RST trances are used for filtering interference. Please note that the (U)SIM
peripheral circuit should be close to the (U)SIM card connector.
⚫ The pull-up resistor on USIM_DATA can improve anti-jamming capability of the (U)SIM card. If the
(U)SIM card traces are too long, or the interference source is relatively close, it is recommended to
add a pull-up resistor near the (U)SIM card connector.

4.4. PCM and I2C Interfaces

The module provides one Pulse Code Modulation (PCM) digital interface for audio design, which supports
the primary mode (short frame synchronization) and the module works as both master and slave.

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The module can only be used as primary devices in applications related to I2C interfaces and does not
support multi-host mode. It conforms to the I2C bus protocol specification (100/400 kHz).

In short frame mode, the data is sampled on the falling edge of the PCM_CLK and transmitted on the
rising edge. The PCM_SYNC falling edge represents the MSB. In this mode, the PCM interface supports
256 kHz, 512 kHz, 1024, 2048 kHz PCM_CLK at 8 kHz PCM_SYNC, and also supports 4069 kHz
PCM_CLK at 16 kHz PCM_SYNC.

The module supports a 16-bit linear encoding format. The following figure shows the sequence diagram of
short frame mode. (PCM_SYNC = 8 kHz, PCM_CLK = 2048 kHz).

125 µs

PCM_CLK 1 2 255 256

PCM_SYNC

MSB LSB MSB

PCM_DOUT

MSB LSB MSB

PCM_DIN

Figure 22：Timing Sequence for Short Frame Mode

Table 15: Pin Definition of PCM Interface

Pin Name Pin No. I/O Description Comment

PCM_SYNC 26 DIO PCM data frame sync 1.8 V power domain.

In master mode, it serves
as an output signal.
PCM_CLK 27 DIO PCM clock In slave mode, it is used
as an input signal.
If unused, keep it open.

PCM_DIN 24 DI PCM data input 1.8 V power domain.

PCM_DOUT 25 DO PCM data output If unused, keep it open.

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 LTE Standard Module Series

Table 16: Pin Definition of I2C Interface

Pin Name Pin No. I/O Description Comment

I2C_SCL 41 OD I2C serial clock Used for external codec.

An external 1.8 V pull-up
I2C_SDA 42 OD I2C serial data resistor is needed.

Clock and mode can be configured by AT command, and the default configuration is short frame
synchronization format with 2048 kHz PCM_CLK and 8 kHz PCM_SYNC.

The following is a reference design for the PCM and I2C interfaces with external Codec chip.

33 pF 33 pF 33 pF MICBIAS

22R
INP

BIAS
PCM_CLK BCLK
22R INN
PCM_SYNC LRCK

22R
PCM_DOUT DAC
22R
PCM_DIN ADC
LOUTP
I2C_SCL SCL
I2C_SDA SDA LOUTN
4.7K

4.7K

Module Codec

1.8 V

Figure 23: PCM and I2C Interface Circuit Reference Design

NOTE

It is recommended to reserve the RC (R = 22 Ω, C = 33 pF) circuit on the PCM signal line and the
capacitor should be placed close to the module, especially on PCM_CLK.

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 LTE Standard Module Series

4.5. SPI Interface

The module provides one SPI interface that supports master mode. Maximum clock frequency of 52 MHz.

Table 17: Pin Definition of SPI Interface

Pin Name Pin No. I/O Description Comment

SPI_CLK 40 DO SPI clock

SPI_CS 37 DO SPI chip select 1.8 V power domain.

If unused, keep it
SPI_DIN 39 DI SPI data input open.

SPI_DOUT 38 DO SPI data output

NOTE

When used for SLIC IC SI32185, need module pin 3 as RESET_SLIC to connect SI32185 pin 18,
need module pin 4 as INT_SLIC to connect SI32185 pin 6, software changes module pin 3 and pin 4
GPIO configuration.

4.6. Analog Audio Interfaces

The module provides one analog audio input channel and one analog audio output channel. Pin definition
is shown in the following table.

Table 18: Pin Definition of Analog Audio Interfaces

Channel Pin Name Pin No. I/O Description

MICBIAS 140 PO Microphone bias voltage

AIN MIC_P 125 Microphone input channel (+)

AI
MIC_N 126 Microphone input channel (-)

SPK_P 124 Analog audio differential output channel (+)

AOUT AO
SPK_N 123 Analog audio differential output channel (-)

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 LTE Standard Module Series

⚫ AIN channels are differential inputs and are used for microphone input. Electret microphones are
usually used.
⚫ AOUT channel is a differential output, usually used for receiver.

4.6.1. Notes on Audio Interface Design

It is recommended to use the electret microphone with dual built-in capacitors (e.g. 10 pF and 33 pF) for
filtering out RF interference, thus reducing TDD noise. The 33 pF capacitor is applied for filtering out RF
interference when the module is transmitting at EGSM900. Without placing this capacitor, TDD noise
could be heard. The 10 pF capacitor here is used for filtering out RF interference at DCS1800. Please
note that the resonant frequency point of a capacitor largely depends on the material and production
technique. Therefore, you would have to discuss with their capacitor vendors to choose the most suitable
capacitor for filtering out high-frequency noises.

The severity degree of the RF interference in the voice channel during GSM transmitting largely depends
on the application design. In some cases, EGSM900 TDD noise is more severe; while in other cases,
DCS1800 TDD noise is more obvious. Therefore, a suitable capacitor can be selected based on the test
results. The filter capacitors on the PCB should be placed as close to the audio devices or audio
interfaces as possible, and the traces should be as short as possible. They should go through the filter
capacitors before arriving at other connection points.

In order to decrease radio or other signal interference, RF antennas should be placed away from audio
interfaces and audio traces. Power traces cannot be parallel with and also should be far away from the
audio traces.

The differential audio traces must be routed according to the differential signal layout rule.

4.6.2. Microphone Interface Circuit

The microphone interface reference circuit is shown below

Close to Module Close to

Microphone
MICBIAS
GND GND GND

510R
Differential
layout 10 pF 33 pF
Module 100 nF 2.2 µF ESD
0603 1.5K 0603 0603
0603
MIC_P

10 pF 33 pF
MIC_N 0603 0603
Electret
100 nF Microphone
1.5K 10 pF 33 pF
0603 ESD
0603 0603
510R

GND GND GND

GND

Figure 24: Microphone Interface Reference Circuit

EC200A_Series_Hardware_Design 47 / 97
 LTE Standard Module Series

NOTE

MIC channel is sensitive to ESD, so it is not recommended to remove the ESD components used for
protecting the MIC.

4.6.3. Handset Interface Circuit

Close to speaker
GND

10 pF 33 pF ESD
Differential layout 0603 0603

Module
SPK_P
10 pF 33 pF
0603 0603
SPK_N

10 pF 33 pF ESD
0603 0603

GND

Figure 25: Handset Interface Reference Circuit

4.7. UART Interface

The module provides two UART interfaces: the main UART interface and the debug UART interface. The
following shows their features.

⚫ The main UART interface supports 4800 bps, 9600 bps, 19200 bps, 38400 bps, 57600 bps,
115200 bps, 230400 bps, 460800 bps, 921600 bps baud rates, and the baud rate is 115200 bps by
default. This interface is used for data transmission and AT command communication. Also, it
supports RTS and CTS hardware flow control.
⚫ The debug UART interface supports 115200 bps baud rate. It is used for the output of partial logs.

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 LTE Standard Module Series

Table 19: Pin Definition of Main UART Interface

Pin Name Pin No. I/O Description Comment

MAIN_RI 62 DO Main UART ring indication

MAIN_DCD 63 DO Main UART data carrier detect

DTE clear to send signal from
MAIN_CTS 64 DO
DCE (Connect to DTE’s CTS)
1.8 V power domain.
DTE request to send signal to If unused, keep it
MAIN_RTS 65 DI
DCE (Connect to DTE’s RTS) open.
MAIN_DTR 66 DI Main UART data terminal ready

MAIN_RXD 68 DI Main UART receive

MAIN_TXD 67 DO Main UART transmit

Table 20: Pin Definition of Debug UART Interface

Pin Name Pin No. I/O Description Comment

DBG_RXD 11 DI Debug UART transmit 1.8 V power domain.

DBG_TXD 12 DO Debug UART receive If unused, keep it open.

The module provides a 1.8 V UART interface. A level translator should be used if the application is
equipped with a 3.3 V UART interface. A level translator TXS0108EPWR provided by Texas Instruments
is recommended. The following figure shows a reference design.

VDD_EXT VCCA VCCB VDD_MCU

0.1 μF 0.1 μF
10K

120K
OE GND
MAIN_RI A1 B1 RI_MCU
MAIN_DCD A2 B2 DCD_MCU
MAIN_CTS A3 Translator B3 CTS_MCU
MAIN_RTS A4 B4 RTS_MCU
MAIN_DTR A5 B5 DTR_MCU
MAIN_TXD A6 B6 RXD_MCU
MAIN_RXD A7 B7 TXD_MCU
51K 51K
A8 B8

Figure 26: Reference Circuit with Translator Chip

EC200A_Series_Hardware_Design 49 / 97
 LTE Standard Module Series

Please visit http://www.ti.com for more information.

Another example with transistor circuit is shown as below. For the design of circuits shown in dotted
lines, please refer to that shown in solid lines, but pay attention to the direction of connection.

4.7K
VDD_EXT VDD_EXT
1 nF
MCU/ARM Module
10K

TXD MAIN_RXD
RXD MAIN_TXD
1 nF
10K
VDD_EXT
VCC_MCU 4.7K
RTS MAIN_RTS
CTS MAIN_CTS
GPIO MAIN_DTR
EINT MAIN_RI
GPIO MAIN_DCD
GND GND

Figure 27: Reference Circuit with Transistor Circuit

NOTE

1. Transistor circuit solution is not suitable for applications with baud rates exceeding 460 kbps.
2. Please note that the module CTS is connected to the host CTS, and the module RTS is connected
to the host RTS.

4.8. SD card Interface

The module provides one SD card interface which supports SD 3.0 protocol.

Table 21: Pin Definition of SD Card Interface

Pin Name Pin No. I/O Description Comment

SD_SDIO_CLK 32 DO SD card SDIO clock 1.8/2.8 V power

SD card SDIO domain.
SD_SDIO_CMD 33 DIO If unused, keep it
command

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 LTE Standard Module Series

SD_SDIO_DATA0 31 DIO SD card SDIO bit 0 open.

SD_SDIO_DATA1 30 DIO SD card SDIO bit 1

SD_SDIO_DATA2 29 DIO SD card SDIO bit 2

SD_SDIO_DATA3 28 DIO SD card SDIO bit 3

SD card SDIO power
SD_SDIO_VDD 34 PO
supply
1.8 V power domain.
SD card hot-plug
SD_DET* 23 DI If unused, keep it
detect
open.

The following figure illustrates a reference design of SD card interface with the module.
Module VDD_3V SD Card Connector
SD_SDIO_VDD VDD
+
C10 C9 C8 C7
R7 R8 R9 R10 R11 100 uF 100 nF 33 pF 10 pF
NM NM NM NM NM
R1 0R
SD_SDIO_DATA3 CD/DAT3
R2 0R
SD_SDIO_DATA2 DAT2
R3 0R
SD_SDIO_DATA1 DAT1
R4 0R
SD_SDIO_DATA0 DAT0
R5 0R
SD_SDIO_CLK CLK
R6 0R
SD_SDIO_CMD CMD

SD_DET DETECTIVE
C1 D1 C2 D2 C3 D3 C4 D4 C5 D5 D7 C6 D6
NM NM NM NM NM NM VSS

Figure 28: Reference Circuit of SD Card Interface

In SD card interface design, in order to ensure good communication performance with SD card, the
following design principles should be complied with:

⚫ The voltage range of SD card power supply VDD_3V is 2.7–3.6 V and a sufficient current up to 0.8 A
should be provided. The maximum output current of SD_SDIO_VDD is 50 mA which can only be
used for SDIO pull-up resistors, an externally power supply is needed for SD card.
⚫ To avoid jitter of bus, resistors R7–R11 are needed to pull up the SDIO to SD_SDIO_VDD. Value of
these resistors is among 10 kΩ to 100 kΩ and the recommended value is 100 kΩ. SD_SDIO_VDD
should be used as the pull-up power.
⚫ In order to improve signal quality, it is recommended to add 0 Ω resistors R1 to R6 in series between
the module and the SD card. The bypass capacitors C1 to C6 are reserved and not mounted by
default. All resistors and bypass capacitors should be placed close to the module.
⚫ In order to offer good ESD protection, it is recommended to add a TVS diode on SD card pins near
the SD card connector with junction capacitance less than 15 pF.

EC200A_Series_Hardware_Design 51 / 97
 LTE Standard Module Series

⚫ It is important to route the SDIO signal traces with ground surrounded. The impedance of SDIO data
trace is 50 Ω (±10 %).
⚫ Keep SDIO signals far away from other sensitive circuits/signals such as RF circuits, analog signals,
etc., as well as noisy signals such as clock signals, DC-DC signals, etc.
⚫ It is recommended to keep the traces of SD_SDIO_CLK, SD_SDIO_DATA [0:3] and SD_SDIO_CMD
with equal length (the difference among them is less than 1 mm) and the total routing length needs to
be less than 50 mm.
⚫ Make sure the adjacent trace spacing is two times of the trace width and the load capacitance of
SDIO Bus should be less than 15 pF.

4.9. ADC Interface

The module provides two Analog-to-Digital Converter (ADC) interfaces. In order to improve the accuracy
of ADC, the trace of ADC interfaces should be surrounded by ground.

Table 22: Pin Definition of ADC Interface

Pin Name Pin No. I/O Description Comment

ADC0 45 AI General-purpose ADC

If unused, keep it open.
ADC1 44 AI interface

The voltage value on ADC pins can be read via AT+QADC=<port> command:

⚫ AT+QADC=0: read the voltage value on ADC0

⚫ AT+QADC=1: read the voltage value on ADC1

For more details about the AT command, please refer to document [2].

The resolution of the ADC is up to 12 bits. The following table describes the characteristic of the ADC
interface.

Table 23: Characteristics of ADC Interface

Name Min. Typ. Max. Unit

ADC0 Voltage Range 0 - VBAT_BB V

ADC1 Voltage Range 0 - VBAT_BB V

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 LTE Standard Module Series

ADC Resolution - 12 - bits

NOTE

1. The input voltage of ADC should not exceed its corresponding voltage range.
2. It is prohibited to supply any voltage to ADC pin when VBAT is removed.
3. It is recommended to use resistor divider circuit for ADC application and the divider resistance should
not exceed 100K.

4.10. RGMII/RMII Interface

The module provides one RGMII/RMII interface that can be used to connect 100/1000 Mbps Ethernet
PHYs.

Table 24: Pin Definition of RGMII/RMII Interface

Pin Name Pin No. I/O Description Comment

RGMII/RMII_RX_1 73 DI RGMII/RMII receive data bit 1

RGMII/RMII_CTL_RX 74 DI RGMII/RMII receive control

RGMII/RMII_CLK 75 DI RGMII/RMII clock

RGMII/RMII_RX_0 76 DI RGMII/RMII receive data bit 0

RGMII/RMII_TX_0 77 DO RGMII/RMII transmit data bit 0 1.8 V power

RGMII/RMII_TX_1 78 DO RGMII/RMII transmit data bit 1 domain for
RGMII.
RGMII_RX_2 79 DI RGMII receive data bit 2 1.8/3.3 V (default
3.3 V) power
RGMII_TX_2 80 DO RGMII transmit data bit 2 domain for RMII.
RGMII/RMII_CTL_TX 81 DO RGMII/RMII transmit control If unused, keep it
open.
RGMII_RX_3 82 DI RGMII receive data bit 3

RGMII_CK_TX 83 DO RGMII transmit clock

RGMII_TX_3 84 DO RGMII transmit data bit 3

RGMII/RMII_INT 120 DI RGMII/RMII interrupt input

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 LTE Standard Module Series

RGMII/RMII management
RGMII/RMII_MD_IO 121 IO
data input/output
RGMII/RMII management
RGMII/RMII_MD_CLK 122 DO
data clock
1.8 V power
domain.
Low level by
default.
RGMII/RMII_RST_N 119 DIO RGMII/RMII reset Cannot be pulled
high before
module’s
successful
power-on.

The following figure shows a reference circuit of RGMII MAC (3.3 V power domain) to PHY interface
(3.3 V power domain).

RGMII/RMII_MD_IO
RGMII/RMII_MD_CLK

M RGMII/RMII_CLK

Module A
RGMII/RMII_TX_[0:1] PHY
RGMII/RMII_RX_[0:1]
RGMII/RMII_CTL_TX
3.3 V
C
RGMII/RMII_CTL_RX

RGMII/RMII_INT

RGMII/RMII_RST_N

Figure 29: Reference Circuit of RMII to PHY Interface

The following figure shows a reference circuit of RGMII MAC (1.8 V power domain) to PHY (1.8 V power
domain) interface.

EC200A_Series_Hardware_Design 54 / 97
 LTE Standard Module Series

RGMII/RMII_MD_IO
RGMII/RMII_MD_CLK

RGMII/RMII_CLK

RGMII/RMII_TX_[0:1]
M
RGMII_TX_[2:3]

Module A RGMII/RMII_RX_[0:1] PHY

RGMII_RX_[2:3]

C RGMII/RMII_CTL_TX
1.8 V
RGMII/RMII_CTL_RX
RGMII_CK_TX

RGMII/RMII_INT

RGMII/RMII_RESET_N

Figure 30: Reference Circuit of RGMII to PHY Interface

To enhance the reliability and availability of application designs, please follow the criteria below for
RGMII/RMII circuit design:

⚫ Keep RMII and RGMII data and control signals away from other sensitive circuits/signals such as RF
circuits, analog signals, etc., as well as noisy signals such as clock signals, DC-DC signals, etc.
⚫ The single-ended impedance of RGMII data trace is 50 Ω ±10 %.
⚫ The length difference of RGMII/RMII_TX_[0:1], RGMII_TX_[2:3], RGMII/RMII_CTL_TX,
RGMII_CK_TX should be less than 2 mm, and the space between the signal traces should be larger
than 2 times of trace width. Similarly, The length difference of RGMII/RMII_RX_[0:1],
RGMII_RX_[2:3], RGMII/RMII_CTL_RX, RGMII/RMII_CLK should be less than 2 mm, and the space
between the signal traces should be larger than 2 times of trace width.
⚫ Spacing between Tx bus and Rx bus is larger than 2.5 times of the trace width.
⚫ Spacing between Tx bus or Rx bus is larger than 3 times of the trace width.

NOTE

Pay attention to the level match shown in dotted line.

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4.11. Indication Signal

The pin definition of indication signal is as follows:

Table 25: Pin Definition of Indication Signal

Pin Name Pin No. I/O Description Comment

Indicate the module’s 1.8 V power domain. If
NET_MODE 5 DO
network registration mode unused, keep it open.
Indicate the module's 1.8 V power domain.
NET_STATUS 6 DO
network activity status If unused, keep it open.

4.11.1. Network Status Indication

The network indication pins can be used to drive network status indication LEDs. The module provides
two network indication pins: NET_MODE and NET_STATUS. The following tables describe pin definition
and logic level changes in different network status.

Table 26: Working State of the Network Connection Status/Activity Indication

Pin Name Status Description

Always High Registered on LTE network

NET_MODE
Always Low Others

Flicker slowly (200 ms High/1800 ms Low) Network searching

Flicker slowly (1800 ms High/200 ms Low) Idle

NET_STATUS
Flicker quickly (125 ms High/125 ms Low) Data transfer is ongoing

Always High Voice calling

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VBAT DC_5V
Module Module

2.2 K 2.2 K

4.7 K 4.7 K
NET_STATUS NET_MODE
47 K 47 K

Figure 31: Reference Circuit of the Network Status Indication

4.11.2. STATUS

The STATUS pin is an open drain output for module’s operation status indication. It can be connected to a
GPIO of DTE with a pulled-up resistor, or as an LED indication circuit as below. When the module is
turned on normally, the STATUS will present the low state. Except for this, the STATUS will present
high-impedance state.

The following figure shows different circuit designs of STATUS, and you can choose either one according
to the application demands.

VDD_MCU VBAT

33 K

2.2 K

STATUS MCU_GPIO STATUS

Module Module

Figure 32: Reference Circuits of STATUS

NOTE

The status pin cannot be used as indication of module shutdown status when VBAT is removed.

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4.12. Behaviors of the MAIN_RI

AT+QCFG="risignaltype","physical" can be used to configure MAIN_RI behaviors.

No matter on which port a URC is presented, the URC will trigger the behaviors of MAIN_RI pin.

NOTE

The URC can be outputted via UART port, USB AT port and USB modem port, which can be set by
AT+QURCCFG. The default port is USB AT port.

In addition, MAIN_RI behavior can be configured flexibly. The default behavior of the MAIN_RI is shown
as below.

Table 27: Behaviors of the MAIN_RI

State Response

Idle MAIN_RI keeps at high level

URC MAIN_RI outputs 120 ms low pulse when a new URC returns

The MAIN_RI behavior can be changed via AT+QCFG. Please refer to document [2] for details.

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5 RF Specifications

5.1. Cellular Network

5.1.1. Antenna Interface & Frequency Bands

The pin definition of main antenna and Rx-diversity antenna interfaces is shown below.

Table 28: Pin Definition of Cellular Network Interface

Pin Name Pin No. I/O Description Comment

ANT_DRX 35 AI Diversity antenna interface

50 Ω impedance.
ANT_MAIN 49 AIO Main antenna interface

Table 29: Operating Frequency of EC200A-CN

Operating Frequency Transmit (MHz) Receive (MHz)

EGSM900 880–915 925–960

DCS1800 1710–1785 1805–1880

WCDMA B1 1922–1978 2112–2168

WCDMA B5 826–847 871–892

WCDMA B8 882–913 927–958

LTE-FDD B1 1920–1980 2110–2170

LTE-FDD B3 1710–1785 1805–1880

LTE-FDD B5 824–849 869–894

LTE-FDD B8 880–915 925–960

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LTE-TDD B34 2010–2025 2010–2025

LTE-TDD B38 2570–2620 2570–2620

LTE-TDD B39 1880–1920 1880–1920

LTE-TDD B40 2300–2400 2300–2400

LTE-TDD B41 2535–2675 2535–2675

⚫
NOTE

B41 only supports 140 MHz (2535–2675 MHz).

Table 30: Operating Frequency of EC200A-AU

Operating Frequency Transmit (MHz) Receive (MHz)

GSM850 824–849 869–894

EGSM900 880–915 925–960

DCS1800 1710–1785 1805–1880

PCS1900 1850–1910 1930–1990

WCDMA B1 1922–1978 2112–2168

WCDMA B2 1852–1908 1932–1988

WCDMA B4 1712–1753 2112–2153

WCDMA B5 826–847 871–892

WCDMA B8 882–913 927–958

LTE-FDD B1 1920–1980 2110–2170

LTE FDD B2 1850–1910 1930–1990

LTE-FDD B3 1710–1785 1805–1880

LTE FDD B4 1710–1755 2110–2155

LTE-FDD B5 824–849 869–894

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LTE-FDD B7 2500–2570 2620–2690

LTE-FDD B8 880–915 925–960

LTE-FDD B28 703–748 758–803

LTE-FDD B66 1710–1780 2110–2180

LTE-TDD B40 2300–2400 2300–2400

Table 31: Operating Frequency of EC200A-EU

Operating Frequency Transmit (MHz) Receive (MHz)

EGSM900 880–915 925–960

DCS1800 1710–1785 1805–1880

WCDMA B1 1922–1978 2112–2168

WCDMA B5 826–847 871–892

WCDMA B8 882–913 927–958

LTE-FDD B1 1920–1980 2110–2170

LTE-FDD B3 1710–1785 1805–1880

LTE-FDD B5 824–849 869–894

LTE-FDD B7 2500–2570 2620–2690

LTE-FDD B8 880–915 925–960

LTE-FDD B20 832–862 791–821

LTE-FDD B28 703–748 758–803

LTE-TDD B38 2570–2620 2570–2620

LTE-TDD B40 2300–2400 2300–2400

LTE-TDD B41 2535–2675 2535–2675

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5.1.2. Tx Power

The following table shows the RF output power of the module.

Table 32: Tx Power

Frequency Max. Tx Power Comments

GSM850 33 dBm ±2 dB 5 dBm ±5 dB

EGSM900 33 dBm ±2 dB 5 dBm ±5 dB

DCS1800 30 dBm ±2 dB 0 dBm ±5 dB

PCS1900 30 dBm ±2 dB 0 dBm ±5 dB

GSM850(8-PSK) 27 dBm ±3 dB 5 dBm ±5 dB

GSM900 (8-PSK) 27 dBm ±3 dB 5 dBm ±5 dB

DCS1800 (8-PSK) 26 dBm ±3 dB 0 dBm ±5 dB

PCS1900(8-PSK) 26 dBm ±3 dB 0 dBm ±5 dB

WCDMA B1/B2/B4/B5/B8 24 dBm +1/-3 dB < -49 dBm

LTE-FDD
23 dBm ±2 dB < -39 dBm
B1/B2/B3/B4/B5/B7/B8/B20/B28/B66

LTE-TDD B34/B38/B39/B40/B41 23 dBm ±2 dB < -39 dBm

. NOTE

In GPRS 4 slots Tx mode, the maximum output power is reduced by 4 dB. The design conforms to the
GSM specification as described in Chapter 13.16 of 3GPP TS 51.010-1.

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5.1.3. Rx Sensitivity

The following table shows conducted Rx sensitivity of the module.

Table 33: Conducted RF Receiving Sensitivity of EC200A-CN

Receiving Sensitivity (Typ.) 3GPP

Frequency Requirement
Primary Diversity SIMO (SIMO)

EGSM900 -109 - - -102dBm

DCS1800 -107 - - -102dBm

WCDMA B1 -109.4 - - -106.7dBm

WCDMA B5 -109.7 - - -104.7dBm

WCDMA B8 -110.2 - - -103.7dBm

LTE-FDD B1 -98.1 -98.4 -101.3 -96.3dBm

LTE-FDD B3 -97.1 -98.1 -100.8 -93.3dBm

LTE-FDD B5 -98.9 -99.7 -101.9 -94.3dBm

LTE-FDD B8 -97.4 -99.2 -101.9 -93.3dBm

LTE-TDD B34 -96.6 -98.7 -100.5 -96.3dBm

LTE-TDD B38 -96.7 -96.2 -98.9 -96.3dBm

LTE-TDD B39 -97.6 -98 -100.3 -96.3dBm

LTE-TDD B40 -97.4 -98.9 -101.4 -96.3dBm

LTE-TDD B41 -95 -95.8 -99.1 -94.3dBm

Table 34: Conducted RF Receiving Sensitivity of EC200A-AU

Receiving Sensitivity (Typ.) 3GPP

Frequency Requirement
Primary Diversity SIMO (SIMO)

GSM850 -109.3 - - -102dBm

EGSM900 -108.2 - - -102dBm

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DCS1800 -106.8 - - -102dBm

PCS1900 -107 - - -102dBm

WCDMA B1 -109.2 - - -106.7dBm

WCDMA B2 -107.7 - - -104.7dBm

WCDMA B4 -109.2 - - -106.7dBm

WCDMA B5 -110.7 - - -104.7dBm

WCDMA B8 -110.2 - - -103.7dBm

LTE-FDD B1 -97.8 -97.8 -101 -96.3dBm

LTE FDD B2 -96.1 -97.8 -100.2 -94.3dBm

LTE-FDD B3 -96.7 -97.5 -100.9 -93.3dBm

LTE FDD B4 -96.6 -97.4 -101.1 -96.3dBm

LTE-FDD B5 -98.2 -99.2 -101.7 -94.3dBm

LTE-FDD B7 -95.8 -97.3 -99.9 -94.3dBm

LTE-FDD B8 -96.9 -98.6 -100.2 -93.3dBm

LTE-FDD B28 -98.5 -99.3 -102.4 -94.8dBm

LTE-FDD B66 -95.5 -97.7 -100 -95.8dBm

LTE-TDD B40 -96.9 -98.5 -101.3 -96.3dBm

Table 35: Conducted RF Receiving Sensitivity of EC200A-EU

Receiving Sensitivity (Typ.) 3GPP

Frequency Requirement
Primary Diversity SIMO (SIMO)

EGSM900 -108.7 - - -102dBm

DCS1800 -107 - - -102dBm

WCDMA B1 -109.7 - - -106.7dBm

WCDMA B5 -111 - - -104.7dBm

WCDMA B8 -110.5 - - -103.7dBm

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LTE-FDD B1 -96.9 -97 -100.8 -96.3dBm

LTE-FDD B3 -95.9 -96.8 -100.4 -93.3dBm

LTE-FDD B5 -98.3 -99 -102.2 -94.3dBm

LTE-FDD B7 -94.4 -95.8 -98 -94.3dBm

LTE-FDD B8 -96.7 -98.9 -100.1 -93.3dBm

LTE-FDD B20 -98.1 -99.3 -101.4 -93.3dBm

LTE-FDD B28 -98.9 -99.5 -102.6 -94.8dBm

LTE-TDD B38 -96.5 -95.2 -99.3 -96.3dBm

LTE-TDD B40 -97.3 -97.3 -100.5 -96.3dBm

LTE-TDD B41 -94.9 -95.1 -97.8 -94.3dBm

5.1.4. Reference Design

The module provides two RF antenna interfaces for antenna connection.

It is recommended to reserve a π-type matching circuit for better RF performance, and the π-type
matching components (C1, R1, C2 and C3, R2, C4) should be placed as close to the antenna as possible.
The capacitors are not mounted by default.

Main
Module antenna
R1 0R
ANT_MAIN

C1 C2

NM NM

Diversity
antenna
R2 0R
ANT_DRX

C3 C4

NM NM

Figure 33: Reference Circuit for RF Antenna Interfaces

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5.2. Reference Design of RF Routing

For user’s PCB, the characteristic impedance of all RF traces should be controlled to 50 Ω. The
impedance of the RF traces is usually determined by the trace width (W), the materials’ dielectric constant,
the height from the reference ground to the signal layer (H), and the spacing between RF traces and
grounds (S). Microstrip or coplanar waveguide is typically used in RF layout to control characteristic
impedance. The following are reference designs of microstrip or coplanar waveguide with different PCB
structures.

Figure 34: Microstrip Design on a 2-layer PCB

Figure 35: Coplanar Waveguide Design on a 2-layer PCB

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Figure 36: Coplanar Waveguide Design on a 4-layer PCB (Layer 3 as Reference Ground)

Figure 37: Coplanar Waveguide Design on a 4-layer PCB (Layer 4 as Reference Ground)

In order to ensure RF performance and reliability, the following principles should be complied with in RF
layout design:

⚫ Use an impedance simulation tool to accurately control the characteristic impedance of RF traces to
50 Ω.
⚫ The GND pins adjacent to RF pins should not be designed as thermal relief pads, and should be fully
connected to ground.
⚫ The distance between the RF pins and the RF connector should be as short as possible, and all the
right-angle traces should be changed to curved ones.
⚫ There should be clearance under the signal pin of the antenna connector or solder joint.
⚫ The reference ground of RF traces should be complete. Meanwhile, ground vias around RF traces
and the reference ground improves RF performance. The distance between the ground vias and RF
traces should be more than two times the width of RF signal traces (2 × W).
⚫ Keep RF traces away from interference sources, and avoid intersection and paralleling between
traces on adjacent layers.

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For more details about RF layout, please refer to document [3].

5.3. Requirements for Antenna Design

Table 36: Requirements for Antenna Design

Antenna Type Requirements

VSWR: ≤ 2
Efficiency: > 30 %
Gain: 1dBi
Max. input power: 50 W
GSM/UMTS/LTE Input impedance: 50 Ω
Cable insertion loss:
< 1 dB：LB（< 1 GHz）
< 1.5 dB：MB（1~2.3 GHz）
< 2 dB：HB（> 2.3 GHz）

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5.4. RF Connector Recommendation

If RF connector is used for antenna connection, it is recommended to use U.FL-R-SMT connector

provided by Hirose.

Figure 38: Dimensions of U.FL-R-SMT Connector (Unit: mm)

U.FL-LP serial connectors listed in the following figure can be used to match the U.FL-R-SMT.

Figure 39: Mechanicals of U.FL-LP Connectors

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The following figure describes the space factor of mated connector.

Figure 40: Space Factor of Mated Connector (Unit: mm)

For more details, please visit http://hirose.com.

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6 Electrical Characteristics &

Reliability

6.1. Absolute Maximum Ratings

Absolute maximum ratings for power supply and voltage on digital and analog pins of the module are
listed in the following table.

Table 37: Absolute Maximum Ratings

Parameter Min. Max. Unit

VBAT_RF/VBAT_BB -0.3 5.5 V

USB_VBUS -0.3 5.5 V

Peak Current of VBAT_BB - 0.8 A

Peak Current of VBAT_RF - 1.8 A

Voltage on Digital Pins -0.3 2.3 V

Voltage at ADC0 0 VBAT_BB V

Voltage at ADC1 0 VBAT_BB V

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6.2. Power Supply Ratings

Table 38: The Module’s Power Supply Ratings

Parameter Description Conditions Min. Typ. Max. Unit

The actual input voltages

VBAT_BB and must stay between the
3.4 3.8 4.5 V
VBAT_RF minimum and maximum
VBAT values.
Voltage drop
Maximum power control
during 0 0 400 mV
level at EGSM 900
transmitting burst
Peak supply
Maximum power control
IVBAT current (during - 1.8 2.0 A
level at EGSM 900
transmission slot)
USB connection
USB_VBUS 3.0 5.0 5.25 V
detection

6.3. Power Consumption

Table 39: EC200A-CN Current Consumption

Description Conditions Typ. Unit

OFF state Power down 11 uA

AT+CFUN=0 (USB disconnected) 0.86 mA

EGSM900 @ DRX = 2 (USB disconnected) 1.71 mA

EGSM900 @ DRX = 5 (USB disconnected) 1.27 mA

EGSM900 @ DRX = 5 (USB suspend) 1.43 mA

Sleep state
EGSM900 @ DRX = 9 (USB disconnected) 1.14 mA

DCS1800 @ DRX = 2 (USB disconnected) 1.70 mA

DCS1800 @ DRX = 5 (USB disconnected) 1.26 mA

DCS1800 @ DRX = 5 (USB suspend) 1.41 mA

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DCS1800 @ DRX = 9 (USB disconnected) 1.13 mA

WCDMA @ PF = 64 (USB disconnected) 2.37 mA

WCDMA @ PF = 64 (USB suspend) 2.53 mA

WCDMA @ PF = 128 (USB disconnected) 1.66 mA

WCDMA @ PF = 256 (USB disconnected) 1.31 mA

WCDMA @ PF = 512 (USB disconnected) 1.14 mA

LTE-FDD @ PF = 32 (USB disconnected) 2.04 mA

LTE-FDD @ PF = 64 (USB disconnected) 1.46 mA

LTE-FDD @ PF = 64 (USB suspend) 1.60 mA

LTE-FDD @ PF = 128 (USB disconnected) 1.19 mA

LTE-FDD @ PF = 256 (USB disconnected) 1.06 mA

LTE-TDD @ PF = 32 (USB disconnected) 2.09 mA

LTE-TDD @ PF = 64 (USB disconnected) 1.48 mA

LTE-TDD @ PF = 64 (USB suspend) 1.64 mA

LTE-TDD @ PF = 128 (USB disconnected) 1.20 mA

LTE-TDD @ PF = 256 (USB disconnected) 1.06 mA

EGSM900 @ DRX = 5 (USB disconnected) 20.35 mA

EGSM900 @ DRX = 5 (USB connected) 36.52 mA

WCDMA @ PF = 64 (USB disconnected) 20.99 mA

WCDMA @ PF = 64 (USB connected) 37.15 mA

Idle state
LTE-FDD @ PF = 64 (USB disconnected) 20.52 mA

LTE-FDD @ PF = 64 (USB connected) 36.69 mA

LTE-TDD @ PF = 64 (USB disconnected) 20.51 mA

LTE-TDD @ PF = 64 (USB connected) 36.66 mA

GPRS data transfer EGSM900 4DL/1UL @ 32.34 dBm 197.6 mA

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EGSM900 3DL/2UL @ 32.31 dBm 364.8 mA

EGSM900 2DL/3UL @ 31.08 dBm 468.8 mA

EGSM900 1DL/4UL @ 29.28 dBm 523.2 mA

DCS1800 4DL/1UL @ 29.65 dBm 134.3 mA

DCS1800 3DL/2UL @ 29.58 dBm 242.3 mA

DCS1800 2DL/3UL @ 28.03 dBm 281.8 mA

DCS1800 1DL/4UL @ 26.16 dBm 298.5 mA

EGSM900 4DL/1UL @ 27.06 dBm 136.6 mA

EGSM900 3DL/2UL @ 26.87 dBm 243.3 mA

EGSM900 2DL/3UL @ 25.01 dBm 314.2 mA

EGSM900 1DL/4UL @ 22.87 dBm 359.2 mA

EDGE data
transfer
DCS1800 4DL/1UL @ 25.66 dBm 119.4 mA

DCS1800 3DL/2UL @ 25.50 dBm 214.1 mA

DCS1800 2DL/3UL @ 23.95 dBm 289.1 mA

DCS1800 1DL/4UL @ 21.93 dBm 344.8 mA

WCDMA B1 HSDPA @ 22.06 dBm 511.97 mA

WCDMA B5 HSDPA @ 21.68 dBm 443.02 mA

WCDMA B8 HSDPA @ 21.64 dBm 483.22 mA

WCDMA data transfer
WCDMA B1 HSUPA @ 21.30 dBm 489.72 mA

WCDMA B5 HSUPA @ 20.02 dBm 405.29 mA

WCDMA B8 HSUPA @ 21.03 dBm 451.78 mA

LTE-FDD B1 @ 22.78 dBm 563.82 mA

LTE-FDD B3 @ 23.39 dBm 583.24 mA

LTE data transfer
LTE-FDD B5 @ 23.19 dBm 530.15 mA

LTE-FDD B8 @ 23.87 dBm 578.26 mA

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LTE-TDD B34 @ 22.83 dBm 228.47 mA

LTE-TDD B38 @ 23.55 dBm 357.07 mA

LTE-TDD B39 @ 23.09 dBm 236.27 mA

LTE-TDD B40 @ 23.19 dBm 333.39 mA

LTE-TDD B41 @ 23.44 dBm 381.70 mA

EGSM900 PCL = 5 @ 32.24 dBm 202.3 mA

EGSM900 PCL = 12 @ 19.09 dBm 74.5 mA

EGSM900 PCL = 19 @ 5.82 dBm 47.2 mA

GSM voice call
DCS1800 PCL = 0 @ 29.40 dBm 134.9 mA

DCS1800 PCL = 7 @ 15.75 dBm 59.4 mA

DCS1800 PCL = 15 @ -0.43 dBm 46.8 mA

WCDMA B1 @ 22.77 dBm 557.69 mA

WCDMA voice call WCDMA B5 @ 22.42 dBm 483.34 mA

WCDMA B8 @ 22.43 dBm 529.50 mA

Table 40: EC200A-AU Current Consumption

Description Conditions Typ. Unit

OFF state Power down 10 uA

AT+CFUN=0 (USB disconnected) 0.95 mA

EGSM900 @ DRX = 2 (USB disconnected) 1.67 mA

EGSM900 @ DRX = 5 (USB disconnected) 1.29 mA

Sleep state EGSM900 @ DRX = 5 (USB suspend) TBD mA

EGSM900 @ DRX = 9 (USB disconnected) 1.28 mA

DCS1800 @ DRX = 2 (USB disconnected) 1.66 mA

DCS1800 @ DRX = 5 (USB disconnected) 1.30 mA

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DCS1800 @ DRX = 5 (USB suspend) TBD mA

DCS1800 @ DRX = 9 (USB disconnected) 1.19 mA

WCDMA @ PF = 64 (USB disconnected) 2.30 mA

WCDMA @ PF = 64 (USB suspend) TBD mA

WCDMA @ PF = 128 (USB disconnected) 2.29 mA

WCDMA @ PF = 256 (USB disconnected) 1.67 mA

WCDMA @ PF = 512 (USB disconnected) 1.36 mA

LTE-FDD @ PF = 32 (USB disconnected) TBD mA

LTE-FDD @ PF = 64 (USB disconnected) TBD mA

LTE-FDD @ PF = 64 (USB suspend) TBD mA

LTE-FDD @ PF = 128 (USB disconnected) TBD mA

LTE-FDD @ PF = 256 (USB disconnected) TBD mA

LTE-TDD @ PF = 32 (USB disconnected) TBD mA

LTE-TDD @ PF = 64 (USB disconnected) TBD mA

LTE-TDD @ PF = 64 (USB suspend) TBD mA

LTE-TDD @ PF = 128 (USB disconnected) TBD mA

LTE-TDD @ PF = 256 (USB disconnected) TBD mA

EGSM900 @ DRX = 5 (USB disconnected) 62.62 mA

EGSM900 @ DRX = 5 (USB connected) 38.93 mA

WCDMA @ PF = 64 (USB disconnected) 14.55 mA

WCDMA @ PF = 64 (USB connected) 39.48 mA

Idle state
LTE-FDD @ PF = 64 (USB disconnected) TBD mA

LTE-FDD @ PF = 64 (USB connected) TBD mA

LTE-TDD @ PF = 64 (USB disconnected) TBD mA

LTE-TDD @ PF = 64 (USB connected) TBD mA

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GSM850 4DL/1UL @ 31.77 dBm 231 mA

GSM850 3DL/2UL @ 31.79 dBm 389 mA

GSM850 2DL/3UL @ 30.80 dBm 497 mA

GSM850 1DL/4UL @ 29.19 dBm 548 mA

EGSM900 4DL/1UL @ 31.61 dBm 189 mA

EGSM900 3DL/2UL @ 31.59 dBm 357 mA

EGSM900 2DL/3UL @ 30.58 dBm 466 mA

EGSM900 1DL/4UL @ 28.99 dBm 522 mA

GPRS data transfer
DCS1800 4DL/1UL @ 28.53 dBm 144 mA

DCS1800 3DL/2UL @ 28.42 dBm 270 mA

DCS1800 2DL/3UL @ 27.54 dBm 331 mA

DCS1800 1DL/4UL @ 25.85 dBm 351 mA

PCS1900 4DL/1UL @ 27.61 dBm 218 mA

PCS1900 3DL/2UL @ 27.33 dBm 361 mA

PCS1900 2DL/3UL @ 27.17 dBm 435 mA

PCS1900 1DL/4UL @ 26.20 dBm 427 mA

GSM850 4DL/1UL @ 26.38 dBm 133 mA

GSM850 3DL/2UL @ 24.64 dBm 217 mA

GSM850 2DL/3UL @ 22.53 dBm 283 mA

GSM850 1DL/4UL @ 20.50 dBm 350 mA

EDGE data transfer EGSM900 4DL/1UL @ 26.74 dBm 136 mA

EGSM900 3DL/2UL @ 24.71 dBm 223 mA

EGSM900 2DL/3UL @ 22.57 dBm 288 mA

EGSM900 1DL/4UL @ 20.29 dBm 351 mA

DCS1800 4DL/1UL @ 25.81 dBm 122 mA

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DCS1800 3DL/2UL @ 24.29 dBm 211 mA

DCS1800 2DL/3UL @ 22.24 dBm 282 mA

DCS1800 1DL/4UL @ 19.89 dBm 354 mA

PCS1900 4DL/1UL @ 25.93 dBm 121 mA

PCS1900 3DL/2UL @ 24.34 dBm 207 mA

PCS1900 2DL/3UL @ 22.31 dBm 280 mA

PCS1900 1DL/4UL @ 20.09 dBm 354 mA

WCDMA B1 HSDPA @ 21.98 dBm 530 mA

WCDMA B2 HSDPA @ 21.78 dBm 547 mA

WCDMA B4 HSDPA @ 21.96 dBm 552 mA

WCDMA B5 HSDPA @ 21.70 dBm 501 mA

WCDMA B8 HSDPA @ 21.64 dBm 534 mA

WCDMA data transfer
WCDMA B1 HSUPA @ 21.99 dBm 484 mA

WCDMA B2 HSUPA @ 21.61 dBm 535 mA

WCDMA B4 HSUPA @ 20.68 dBm 501 mA

WCDMA B5 HSUPA @ 21.42 dBm 481 mA

WCDMA B8 HSUPA @ 21.45 dBm 523 mA

LTE-FDD B1 @ 22.76 dBm 553.4 mA

LTE-FDD B2 @ 23.06 dBm 501.64 mA

LTE-FDD B3 @ 22.32 dBm 515.51 mA

LTE-FDD B4 @ 23.31 dBm 470.45 mA

LTE data transfer
LTE-FDD B5 @ 22.73 dBm 439.9 mA

LTE-FDD B7 @ 23.04 dBm 618.68 mA

LTE-FDD B8 @ 23.39 dBm 470.43 mA

LTE-FDD B28A @ 23.33 dBm 441.96 mA

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LTE-FDD B28B @ 22.44 dBm 436.96 mA

LTE-FDD B66 @ 23.59 dBm 510.83 mA

LTE-TDD B40 @ 22.64 dBm 228.16 mA

EGSM900 PCL = 5 @ 31.55 dBm 234 mA

EGSM900 PCL = 12 @ 18.87 dBm 111 mA

EGSM900 PCL = 19 @ 5.58 dBm 81 mA

GSM voice call
DCS1800 PCL = 0 @ 28.50 dBm 183 mA

DCS1800 PCL = 7 @ 15.62 dBm 97 mA

DCS1800 PCL = 15 @ 0.32 dBm 77 mA

WCDMA B1 @ 23.08 dBm 587 mA

WCDMA B2 @ 22.72 dBm 602 mA

WCDMA voice call WCDMA B4 @ 23.28 dBm 602 mA

WCDMA B5 @ 22.69 dBm 552 mA

WCDMA B8 @ 22.61 dBm 593 mA

Table 41: EC200A-EU Current Consumption

Description Conditions Typ. Unit

OFF state Power down 10 uA

AT+CFUN=0 (USB disconnected) 0.78 mA

EGSM900 @ DRX = 2 (USB disconnected) 1.50 mA

EGSM900 @ DRX = 5 (USB disconnected) 1.12 mA

Sleep state EGSM900 @ DRX = 5 (USB suspend) 1.28 mA

EGSM900 @ DRX = 9 (USB disconnected) 1.01 mA

DCS1800 @ DRX = 2 (USB disconnected) 1.50 mA

DCS1800 @ DRX = 5 (USB disconnected) 1.11 mA

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DCS1800 @ DRX = 5 (USB suspend) 1.28 mA

DCS1800 @ DRX = 9 (USB disconnected) 1.00 mA

WCDMA @ PF = 64 (USB disconnected) 2.11 mA

WCDMA @ PF = 64 (USB suspend) 2.25 mA

WCDMA @ PF = 128 (USB disconnected) 1.47 mA

WCDMA @ PF = 256 (USB disconnected) 1.15 mA

WCDMA @ PF = 512 (USB disconnected) 0.99 mA

LTE-FDD @ PF = 32 (USB disconnected) 1.85 mA

LTE-FDD @ PF = 64 (USB disconnected) 1.28 mA

LTE-FDD @ PF = 64 (USB suspend) 1.43 mA

LTE-FDD @ PF = 128 (USB disconnected) 1.02 mA

LTE-FDD @ PF = 256 (USB disconnected) 0.89 mA

LTE-TDD @ PF = 32 (USB disconnected) 1.88 mA

LTE-TDD @ PF = 64 (USB disconnected) 1.29 mA

LTE-TDD @ PF = 64 (USB suspend) 1.45 mA

LTE-TDD @ PF = 128 (USB disconnected) 1.02 mA

LTE-TDD @ PF = 256 (USB disconnected) 0.90 mA

EGSM900 @ DRX = 5 (USB disconnected) 18.06 mA

EGSM900 @ DRX = 5 (USB connected) 32.65 mA

WCDMA @ PF = 64 (USB disconnected) 18.57 mA

WCDMA @ PF = 64 (USB connected) 33.17 mA

Idle state
LTE-FDD @ PF = 64 (USB disconnected) 18.31 mA

LTE-FDD @ PF = 64 (USB connected) 33.11 mA

LTE-TDD @ PF = 64 (USB disconnected) 18.29 mA

LTE-TDD @ PF = 64 (USB connected) 33.10 mA

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EGSM900 4DL/1UL @ 32.44 dBm 199 mA

EGSM900 3DL/2UL @ 32.39 dBm 372 mA

EGSM900 2DL/3UL @ 31.23 dBm 478 mA

EGSM900 1DL/4UL @ 29.53 dBm 533 mA

GPRS data transfer
DCS1800 4DL/1UL @ 29.77 dBm 136 mA

DCS1800 3DL/2UL @ 29.65 dBm 244 mA

DCS1800 2DL/3UL @ 28.31 dBm 293 mA

DCS1800 1DL/4UL @ 26.40 dBm 309 mA

EGSM900 4DL/1UL @ 27.01 dBm 137 mA

EGSM900 3DL/2UL @ 26.98 dBm 246 mA

EGSM900 2DL/3UL @ 25.27 dBm 315 mA

EGSM900 1DL/4UL @ 23.13 dBm 375 mA

EDGE data transfer
DCS1800 4DL/1UL @ 25.96 dBm 121 mA

DCS1800 3DL/2UL @ 25.77 dBm 215 mA

DCS1800 2DL/3UL @ 24.24 dBm 289 mA

DCS1800 1DL/4UL @ 22.10 dBm 360 mA

WCDMA B1 HSDPA @ 21.99 dBm 520 mA

WCDMA B5 HSDPA @ 21.76 dBm 474 mA

WCDMA B8 HSDPA @ 21.81 dBm 496 mA

WCDMA data transfer
WCDMA B1 HSUPA @ 21.21 dBm 504 mA

WCDMA B5 HSUPA @ 21.13 dBm 454 mA

WCDMA B8 HSUPA @ 21.49 dBm 497 mA

LTE-FDD B1 @ 23.61 dBm 607 mA

LTE data transfer LTE-FDD B3 @ 23.71 dBm 636 mA

LTE-FDD B5 @ 23.70 dBm 568 mA

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LTE-FDD B7 @ 23.56 dBm 813 mA

LTE-FDD B8 @ 24.11 dBm 591 mA

LTE-FDD B20 @ 23.20 dBm 592 mA

LTE-FDD B28 @ 23.77 dBm 559 mA

LTE-TDD B38 @ 18.12 dBm 230 mA

LTE-TDD B40 @ 18.68 dBm 233 mA

LTE-TDD B41 @ 19.18 dBm 242 mA

EGSM900 PCL = 5 @ 32.34 dBm 206 mA

EGSM900 PCL = 12 @ 19.11 dBm 76 mA

EGSM900 PCL = 19 @ 6.05 dBm 48 mA

GSM voice call
DCS1800 PCL = 0 @ 29.50 dBm 136 mA

DCS1800 PCL = 7 @ 16.07 dBm 61 mA

DCS1800 PCL = 15 @ -1.14 dBm 48 mA

WCDMA B1 @ 22.29 dBm 543 mA

WCDMA B5 @ 22.26 dBm 496 mA

WCDMA voice call
WCDMA B8 @ 22.25 dBm 533 mA

6.4. Digital I/O Characteristic

Table 42: 1.8 V I/O Requirements

Parameter Description Min. Max. Unit

VIH Input high voltage 1.2 2.0 V

VIL Input low voltage -0.3 0.6 V

VOH Output high voltage 1.35 1.8 V

VOL Output low voltage -0.3 0.45 V

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Table 43: (U)SIM 1.8 V I/O Requirements

Parameter Description Min. Max. Unit

USIM_VDD Power supply 1.7 1.9 V

VIH Input high voltage 1.2 2.0 V

VIL Input low voltage -0.3 0.6 V

VOH Output high voltage 1.35 1.8 V

VOL Output low voltage -0.3 0.45 V

Table 44: (U)SIM 3.0 V I/O Requirements

Parameter Description Min. Max. Unit

USIM_VDD Power supply 2.7 3.05 V

VIH Input high voltage 1.95 3.05 V

VIL Input low voltage -0.3 1.0 V

VOH Output high voltage 2.55 3.0 V

VOL Output low voltage -0.3 0.45 V

6.5. ESD

If the static electricity generated by various ways discharges to the module, the module maybe damaged
to a certain extent. Thus, please take proper ESD countermeasures and handling methods. For example,
wearing anti-static gloves during the development, production, assembly and testing of the module;
adding ESD protective component to the ESD sensitive interfaces and points in the product design of the
module.

ESD characteristics of the module’s pins are as follows:

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Table 45: Electrostatics Discharge Characteristics (25 °C, 45 % Relative Humidity)

Tested Interfaces Contact Discharge Air Discharge Unit

VBAT, GND ±8 ±10 kV

All Antenna Interfaces ±8 ±10 kV

Other Interfaces ±0.5 ±1 kV

6.6. Operating and Storage Temperatures

Table 46: Operating and Storage Temperatures

Parameter Min. Typ. Max. Unit

Operating Temperature Range 3 -35 +25 +75 °C

Extended Operating Temperature
-40 - +85 °C
Range 4

Storage temperature range -40 - +95 °C

3 Within operating temperature range, the module is 3GPP compliant.

4 Within the extended temperature range, the module remains the ability to establish and maintain functions such as voice,
SMS, data transmission, etc., without any unrecoverable malfunction. Radio spectrum and radio network are not influenced,
while one or more specifications, such as Pout, may exceed the specified tolerances of 3GPP. When the temperature
returns to the operating temperature range, the module meets 3GPP specifications again.

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7 Mechanical Information
This chapter describes the mechanical dimensions of the module. All dimensions are measured in
millimeter (mm), and the dimensional tolerances are ±0.2 mm unless otherwise specified.

7.1. Mechanical Dimensions

Figure 41: Module Top and Side Dimensions (Unit: mm)

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Figure 42: Module Bottom Dimensions View (Unit: mm)

⚫
NOTE

The flatness of EC200A series module of Remote Communication meets the requirements of JEITA
ED-7306 standard.

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7.2. Recommended Footprint

Figure 43: Recommended Footprint (Perspective View)

. NOTE

For convenient maintenance of the module, please keep about 3 mm between the module and other
components on the host PCB.

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7.3. Top and Bottom Views

Figure 44: Top and Bottom Views of the Module

NOTE

These are renderings of the module. For authentic appearance, please refer to the module that you
receive from Quectel.

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8 Storage, Manufacturing & Packaging

8.1. Storage Conditions

The module is provided with vacuum-sealed package. MSL of the module is rated as 3, and its storage
restrictions are shown as below.

1. Recommended Storage Condition: The temperature should be 23 ±5 °C and the relative humidity
should be 35–60 %.

2. The storage life (in vacuum-sealed packaging) is 12 months in Recommended Storage Condition.

3. The floor life of the module is 168 hours 5 in a plant where the temperature is 23 ±5 °C and relative
humidity is below 60 %. After the vacuum-sealed packaging is removed, the module must be
processed in reflow soldering or other high-temperature operations within 24 hours. Otherwise, the
module should be stored in an environment where the relative humidity is less than 10 % (e.g. a
drying cabinet).

4. The module should be pre-baked to avoid blistering, cracks and inner-layer separation in PCB under
the following circumstances:

⚫ The module is not stored in Recommended Storage Condition;

⚫ Violation of the third requirement above occurs;
⚫ Vacuum-sealed packaging is broken, or the packaging has been removed for over 24 hours;
⚫ Before module repairing.

5. If needed, the pre-baking should follow the requirements below:

⚫ The module should be baked for 8 hours at 120 ±5 °C;

⚫ All modules must be soldered to PCB within 24 hours after the baking, otherwise they should be
put in a dry environment such as in a drying oven.

5 This floor life is only applicable when the environment conforms to IPC/JEDEC J-STD-033. It is recommended to start the
solder reflow process within 24 hours after the package is removed if the temperature and moisture do not conform to, or
are not sure to conform to IPC/JEDEC J-STD-033. And do not remove the packages of tremendous modules if they are not
ready for soldering.

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NOTE

1. To avoid blistering, layer separation and other soldering issues, extended exposure of the module to
the air is forbidden.
2. Take out the module from the package and put it on high-temperature-resistant fixtures before
baking. All modules must be soldered to PCB within 24 hours after the baking, otherwise put them
in the drying oven. If shorter baking time is desired, see IPC/JEDEC J-STD-033 for the baking
procedure.
3. Pay attention to ESD protection, such as wearing anti-static gloves, when touching the modules.

8.2. Manufacturing and Soldering

Push the squeegee to apply the solder paste on the surface of stencil, thus making the paste fill the
stencil openings and then penetrate to the PCB. The force on the squeegee should be adjusted properly
to produce a clean stencil surface on a single pass. To ensure the module soldering quality, the thickness
of stencil for the module is recommended to be 0.18 – 0.20 mm. For more details, please refer to
document [4].

It is suggested that the peak reflow temperature is 235–246 °C, and the absolute maximum reflow
temperature is 246 °C. To avoid damage to the module caused by repeated heating, it is strongly
recommended that the module should be mounted after reflow soldering for the other side of PCB has
been completed. The recommended reflow soldering thermal profile (lead-free reflow soldering) and
related parameters are shown below.

Temp. (°C)
Reflow Zone
Max slope: Cooling down slope:
2 to 3°C/s C -1.5 to -3°C/s
246
235
217
B D
200
Soak Zone

150 A

100
Max slope: 1 to 3°C/s

Figure 45: Recommended Reflow Soldering Thermal Profile

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Table 47: Recommended Thermal Profile Parameters

Factor Recommendation

Soak Zone

Max slope 1 to 3 °C/s

Soak time (between A and B: 150 °C and 200 °C) 70 to 120 s

Reflow Zone

Max slope 2 to 3 °C/s

Reflow time (D: over 217 °C) 45 to 70 s

Max temperature 235 to 246 °C

Cooling down slope -1.5 ~ -3 °C/s

Reflow Cycle

Max reflow cycle 1

NOTE

1. During manufacturing and soldering, or any other processes that may contact the module directly,
NEVER wipe the module’s shielding can with organic solvents, such as acetone, ethyl alcohol,
isopropyl alcohol, trichloroethylene, etc. Otherwise, the shielding can may become rusted.
2. The shielding can for the module is made of Cupro-Nickel base material. It is tested that after 12
hours’ Neutral Salt Spray test, the laser engraved label information on the shielding can is still clearly
identifiable and the QR code is still readable, although white rust may be found.
3. If a conformal coating is necessary for the module, do NOT use any coating material that may
chemically react with the PCB or shielding cover, and prevent the coating material from flowing into
the module.
4. Avoid using ultrasonic technology for module cleaning since it can damage crystals inside the
module.
5. Due to the complexity of the SMT process, please contact Quectel Technical Supports in advance for
any situation that you are not sure about, or any process (e.g. selective soldering, ultrasonic
soldering) that is not mentioned in document [4].

8.3. Packaging Specifications

The module adopts carrier tape packaging and details are as follow:

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8.3.1. Carrier Tape

Dimension details are as follow:

Figure 46: Carrier Tape Dimension Drawing

Table 48: Carrier Tape Dimension Table (Unit: mm)

W P T A0 B0 K0 K1 F E

44 44 0.35 32.5 29.5 3.0 3.8 20.2 1.75

8.3.2. Plastic Reel

Figure 47: Plastic Reel Dimension Drawing

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Table 49: Plastic Reel Dimension Table (Unit: mm)

øD1 øD2 W

330 100 44.5

8.3.3. Packaging Process

Place the module into the carrier tape and use

the cover tape to cover them; then wind the
heat-sealed carrier tape to the plastic reel and
use the protective tape for protection. One
plastic reel can load 250 modules.

Place the packaged plastic reel, humidity

indicator card and desiccant bag into a
vacuum bag, then vacuumize it.

Place the vacuum-packed plastic reel into a

pizza box.

Put 4 pizza boxes into 1 carton and seal it. One

carton can pack 1000 modules.

Figure 48: Packaging Process

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9 Appendix References

Table 50: Related Documents

Document Name

[1] Quectel_UMTS&LTE_EVB_User_Guide

[2] Quectel_EC200x&EG912Y_Series_AT_Commands_Manual

[3] Quectel_RF_Layout_Application_Note

[4] Quectel_Module_Secondary_SMT_Application_Note

Table 51: Terms and Abbreviations

Abbreviation Description

AMR Adaptive Multi-Rate

BeiDou BeiDou Navigation Satellite System

bps Bytes per second

CDMA Code Division Multiple Access

CS Coding Scheme

CTS Clear To Send

DRX Discontinuous Reception

DTE Data Terminal Equipment

EFR Enhanced Full Rate

EGSM Enhanced GSM

ESD Electrostatic Discharge

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EVB Evaluation Board

FDD Frequency Division Duplexing

FR Full Rate

FTP File Transfer Protocol

FTPS FTP over SSL

GMSK Gaussian Filtered Minimum Shift Keying

GND Ground

GNSS Global Navigation Satellite System

GPS Global Positioning System

GSM Global System for Mobile Communications

HR Half Rate

HSDPA High Speed Downlink Packet Access

HTTPS Hypertext Transfer Protocol Secure

LGA Land Grid Array

LTE Long Term Evolution

MCS Modulation and Coding Scheme

MMS Multimedia Messaging Service

NTP Network Time Protocol

PAP Password Authentication Protocol

PCB Printed Circuit Board

PCM Pulse Code Modulation

PHY Physical Layer Transceiver

PING Packet Internet Groper

PPP Point-to-Point Protocol

PSK Phase Shift Keying

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QAM Quadrature Amplitude Modulation

QPSK Quadrature Phase Shift Keying

RF Radio Frequency

RoHS Restriction of Hazardous Substances

RTS Request To Send

SDIO Secure Digital Input and Output Card

SMS Short Message Service

SMTP Simple Mail Transfer Protocol

SMTPS Simple Mail Transfer Protocol Secure

SSL Secure Sockets Layer

TCP Transmission Control Protocol

TDD Time Division Duplexing

UDP User Datagram Protocol

UMTS Universal Mobile Telecommunications System

USB Universal Serial Bus

(U)SIM (Universal) Subscriber Identity Module

Vmax Maximum Voltage Value

Vnom Nominal Voltage Value

Vmin Minimum Voltage Value

VIHmax Maximum Input High Level Voltage Value

VIHmin Minimum Input High Level Voltage Value

VILmax Maximum Input Low Level Voltage Value

VILmin Minimum Input Low Level Voltage Value

VOHmin Minimum Output High Level Voltage Value

VOLmax Maximum Output Low Level Voltage Value

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VSWR Voltage Standing Wave Ratio

WCDMA Wideband Code Division Multiple Access

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