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Xilinx Rfsoc Product Brief

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49 views2 pages

Xilinx Rfsoc Product Brief

Uploaded by

yuviyuvaraj2244
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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PRODUCT BRIEF

> Integrated RF-Class Analog and Error Correction Technology


Zynq™ UltraScale+™ RFSoC > Delivering 50-75% Power & Footprint Reduction
> Full Programmability across the RF Signal Chain

OVERVIEW
ZynqTM UltraScale+TM RFSoCs integrate gigasample RF data converters and
soft-decision forward error correction (SD-FEC) into an SoC architecture.
The Zynq UltraScale+ RFSoC family simplifies system design with fewer
components and provides platform hardware and software flexibility.

HIGHLIGHTS
Industry’s Only Adaptable Single-Chip Radio Platform
> Integrated direct RF-sampling moves RF design to the digital domain

> User configurable SD-FEC integrated cores

> Programmable logic for diverse requirements and emerging standards TARGET APPLICATIONS
> 4G and 5G Remote Wireless Infrastructure
Cost Effective and Power Efficient Devices
> Remote Radio for Massive MIMO
> Lower power by eliminating JESD204 interfaces
> Fixed Wireless Access
> Over 50% PCB area reduction vs. discrete solutions
> 5G Baseband
> 80% more power efficient SD-FEC vs. a soft implementation
> Mobile Backhaul

Future-Proof Comprehensive Solution > Phased Array Radar

> Fulfilling 3G, 4G, and multiband 5G requirements > Remote-PHY for Cable Access DOCSIS 3.1

> Wide bandwidth for sub-6GHz and mmWave radio applications > Test and Measurement

> Fully integrated Remote-PHY solution for DOCSIS 3.1 standards > Satellite Communications

> L-Band, S-Band, and C-Band direct sampling > LiDAR

Broad Portfolio for Diverse Use Cases


> Gen 1 devices for breakthrough Integration of RF Data Converters
on a hardware programmable SoC

> Gen 2 devices support the latest 5G wireless bands

> Gen 3 devices for full sub-6GHz support with extended millimeter wave
interfacing and multi-band support

> Scalability and package migration across the portfolio

READY TO CONNECT? VISIT xilinx.com/rfsoc


Zynq UltraScale+ RFSoC
FE ATURES
GEN 1 GEN 2 GEN 3

RF DATA CONVERTER SUBSYSTEM

Maximum RF Input Frequency 4GHz 5GHz 6GHz

16x 2.058GSPS
12-bit RF-ADCs 16x 2.220GSPS -
8x 4.096GSPS

8x 5.0GSPS
14-bit RF-ADCs - -
16x 2.5GSPS

14-bit RF-DACs 16x 6.554GSPS 16x 6.554GSPS 16x 10.0GSPS

User Configurable SD-FEC Blocks 8 0 8

LDPC Encode Throughput 19.8Gb/s - 19.8Gb/s

LDPC Decode Throughput 2.84Gb/s @8 iterations - 2.84Gb/s @8 iterations

Turbo Decode Throughput 1.78Gb/s @6 iterations - 1.78Gb/s @6 iterations

PROGRAMMABLE LOGIC

System Logic Cells (K) 930 930 930

DSP Slices 4,272 4,272 4,272

33G GTY Transceivers 16 16 16

Memory (Mb) 60.5 60.5 60.5

PCIe® Gen3 x16 2 2 -

PCIe Gen3 x16/Gen4 x8/CCIX - - 2

100G Ethernet Blocks with RS-FEC 2 2 2

150G Interlaken 1 1 1

PROCESSING SYSTEM

Application Processor Core Quad-core Arm Cortex®-A53 MPCore up to 1.33GHz

Real-Time Processor Core Dual-core Arm Cortex-R5 MPCore up to 533MHz

Embedded and External Memory 256KB On-Chip Memory w/ECC; External DDR4/3/3L; LPDDR4/3; External Quad-SPI; NAND; eMMC

Note: All numbers are maximum capabilities


TAKE THE NEXT STEP
Zynq UltraScale+ RFSoCs are supported by comprehensive developments tools, reference designs, an IP catalog, and evaluation platforms.

For more information about AMD Zynq UltraScale+ RFSoCs, go to www.xilinx.com/rfsoc. Evaluation kits can be ordered separately.
Visit Zynq UltraScale+ RFSoC Boards, Kits, and Modules for details and to place an order today.

DISCLAIMERS
The information contained herein is for informational purposes only and is subject to change without notice. While every precaution has been taken in the preparation of this document, it may contain technical
inaccuracies, omissions and typographical errors, and AMD is under no obligation to update or otherwise correct this information. Advanced Micro Devices, Inc. makes no representations or warranties with
respect to the accuracy or completeness of the contents of this document, and assumes no liability of any kind, including the implied warranties of noninfringement, merchantability or fitness for purposes, with
respect to the operation or use of AMD hardware, software or other products described herein. No license, including implied or arising by estoppel, to any intellectual property rights is granted by this document.
Terms and limitations applicable to the purchase or use of AMD’s products are as set forth in a signed agreement between the parties or in AMD’s Standard Terms and Conditions of Sale.

COPYRIGHT NOTICE
© Copyright 2023 Advanced Micro Devices, Inc. All rights reserved. Xilinx, the Xilinx logo, AMD, the AMD Arrow logo, Alveo, Artix, Kintex, Kria, Spartan, Versal, Vitis, Virtex, Vivado, Zynq, and other designated
brands included herein are trademarks of Advanced Micro Devices, Inc. Other product names used in this publication are for identification purposes only and may be trademarks of their respective compa-
nies. AMBA, AMBA Designer, ARM, ARM1176JZ-S, CoreSight, Cortex, and PrimeCell are trademarks of ARM in the EU and other countries. PCIe, and PCI Express are trademarks of PCI-SIG and used under license.
PID1846750

READY TO CONNECT? VISIT xilinx.com/rfsoc

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