CT 321: MICROCONTROLLER SYSTEMS

4/5/24 By Dr. R.J. Mwifunyi 1

8051 Microcontroller architecture
q Introduction to MCS -51 Family microcontrollers,
q Architectural block Diagram,
q Pin diagram and Pin Functions,
q General Purpose and Special Function Registers,
q Oscillator and clock circuit,
q Reset circuit,
q I/O Port circuits,
q Memory organization: Program memory and data memory.

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8051 Microcontroller architecture
Introduction to MCS -51 Family microcontrollers

q The MCS-51 is a family of microcontroller ICs developed,

manufactured, and marked by Intel Corporation.
q Other ICs Manufacturers are Siemens, Advanced Micro Devices,
Philips etc.
q The generic MCS-51 IC is the 8051, the first device in the family
offered commercially .
q Its features are summarized as follows.
n 4K bytes ROM
n 128 bytes RAM
n Four 8-bit I/O ports
n Two 16-bit timers
n Serial Interface

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8051 Microcontroller architecture
Introduction to MCS -51 Family microcontrollers

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8051 Microcontroller architecture
Architectural block Diagram

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 8051 Microcontroller architecture
Architectural block Diagram
q Architecture of 8051 microcontroller has following features
n 4 Kb of ROM is not much at all.
n 128 bytes of RAM (including SFRs) satisfies the user's basic needs.
n 4 ports having in total of 32 input/output lines are in most cases sufficient to
make all necessary connections to peripheral environment.
q The whole configuration is obviously thought of as to satisfy the
needs of most programmers working on development of
automation devices.
q Advantages:
n Nothing is missing and nothing is too much. In other words, it is

created exactly in accordance to the average user‘s taste and

needs.
n RAM organization, the operation of Central Processor Unit (CPU)

and ports which completely use all resources and enable further
upgrade.

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 8051 Microcontroller architecture
Pin diagram and Pin Functions

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 8051 Microcontroller architecture
Pin diagram and Pin Functions
n Pin out Description
n Pins 1-8: Port 1 each of these pins can be configured as an
input or an output.
n Pin 9: RESET A logic one on this pin disables the
microcontroller and clears the contents of most registers. In
other words, the positive voltage on this pin resets the
microcontroller. By applying logic zero to this pin, the program
starts execution from the beginning.
n Pins10-17: Port 3 Similar to port 1, each of these pins can
serve as general input or output. Besides, all of them have
alternative functions:

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 8051 Microcontroller architecture
Pin diagram and Pin Functions
n Pin out Description
n Pin 10: RXD Serial asynchronous communication input or
Serial synchronous communication output.
n Pin 11: TXD Serial asynchronous communication output or
Serial synchronous communication clock output.
n Pin 12: INT0 Interrupt 0 inputs.
n Pin 13: INT1 Interrupt 1 input.
n Pin 14: T0 Counter 0 clock input.
n Pin 15: T1 Counter 1 clock input.
n Pin 16: WR Write to external (additional) RAM.
n Pin 17: RD Read from external RAM.

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 8051 Microcontroller architecture
Pin diagram and Pin Functions
n Port 3

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 8051 Microcontroller architecture
Pin diagram and Pin Functions
n Pin 18, 19: X2, X1 Internal oscillator input and
output.
q A quartz crystal which specifies operating frequency
(normally 12 MHz) is usually connected to these pins.
q

q Instead of it, miniature ceramics resonators can also be

used for frequency stability.

q Later versions of microcontrollers operate at a

frequency of 0 Hz up to over 50 Hz.

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 8051 Microcontroller architecture
Pin diagram and Pin Functions
n Pin 20: GND Ground.
n Pin 21-28: Port 2 If there is no intention to use
external memory then these port pins are
configured as general inputs/outputs.
q In case external memory is used, the higher address
byte, i.e. addresses A8-A15 will appear on this port.
q Even though memory with capacity of 64Kb is not used,

which means that not all eight port bits are used for its
addressing, the rest of them are not available as
inputs/outputs.

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 8051 Microcontroller architecture
Pin diagram and Pin Functions
n Pin out Description
n Pin 29: PSEN If external ROM is used for storing program then
a logic zero (0) appears on it every time the microcontroller
reads a byte from memory.
n Pin 30: ALE(Address Latch Enable). Prior to reading from
external memory, the microcontroller puts the lower address
byte (A0-A7) on P0 and activates the ALE output. After
receiving signal from the ALE pin, P0 used as a memory chip
address. Immediately after that, the ALE pin is returned its
previous logic state and P0 is now used as a Data Bus.
n In other words, this port is used for both data and address
transmission.
n Generally , it is used for demultiplexing the address and data
signal of Port 0.

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 8051 Microcontroller architecture
Pin diagram and Pin Functions
n Pin out Description
n Pin 31: EA-External Access input is used to enable or disable
external memory interfacing. If there is no external memory
requirement, this pin is always held high.
n Pin 32-39: Port 0 Similar to P2, if external memory is not used,
these pins can be used as general inputs/outputs.
n Otherwise, P0 is configured as address output (A0-A7) when
the ALE pin is driven high (1) or as data output (Data Bus)
when the ALE pin is driven low (0).
n Pin 40: VCC +5V power supply.

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8051 Microcontroller architecture--Registers
q Register are used to store information temporarily, while the
information could be
n a byte of data to be processed, or
n an address pointing to the data to be fetched
q The vast majority of 8051 register are 8-bit registers
n There is only one data type, 8 bits
q The 8 bits of a register are shown from MSB D7 to the LSB
D0
n With an 8-bit data type, any data larger than 8 bits must be
broken into 8-bit chunks before it is processed

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8051 Microcontroller architecture--Registers
q Types
n General Purpose Registers
n Special Purpose Registers

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8051 Microcontroller architecture
Special Function Registers
q Special Function Registers (SFRs) are a sort of control table used
for running and monitoring the operation of the microcontroller.

q Access to registers for 8051 microcontroller is the same as the one

used in most of microprocessors.

q E.g. “INC A” on 6809 microprocessor , increments the contents of

the Accumulator.

q “INC A” in the 8051 perform the same operation.

q The 8051 internal registers are configured as part of the on-chip

RAM, therefore each register has an address.

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8051 Microcontroller architecture
Special Function Registers
q Each of these registers as well as each bit they include,
has its name, address in the scope of RAM and
precisely defined purpose such as timer control,
interrupt control, serial communication control etc.

q Even though there are 128 memory locations intended to

be occupied by them, the basic core, shared by all types of
8051 microcontrollers, has only 21 such registers at the
top of internal RAM, from addresses 80H to FFH.

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8051 Microcontroller architecture
Special Function Registers
q Most of the 128 addresses from 80H to FFH are not
defined except 21.
q Rest of locations is intentionally left unoccupied in order to

enable the manufacturers to further develop

microcontrollers keeping them compatible with the
previous versions.
q It also enables programs written a long time ago for

microcontrollers which are out of production now to be

used today.
q SFRs are both bit-addressable and byte-addressable.

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8051 Microcontroller architecture
Special Function Registers
q Example
q SETB 0EOH

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8051 Microcontroller architecture
Special Function Registers
n Program Status Word (PSW) Register

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8051 Microcontroller architecture
Special Function Registers
n Program Status Word (PSW) Register
n PSW register is one of the most important SFRs.
n PSW is at address D0H contains status bits.
n It contains several status bits that reflect the current state of the
CPU.
n Besides, this register contains Carry bit, Auxiliary Carry, two register
bank select bits, Overflow flag, parity bit and user-definable status
flag.
n P - Parity bit. If a number stored in the accumulator has odd number
of 1s then this bit will be automatically set (1), otherwise it will be
cleared (0).
n It is mainly used during data transmit and receive via serial
communication.
n Bit 1. This bit is intended to be used in the future versions of
microcontrollers.

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8051 Microcontroller architecture
Special Function Registers
n Program Status Word (PSW) Register
n OV Overflow occurs when the result of an arithmetical operation is
larger than 255 and cannot be stored in one register. Overflow
condition causes the OV bit to be set (1). Otherwise, it will be cleared
(0).

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8051 Microcontroller architecture
Special Function Registers
n Program Status Word (PSW) Register
n RS0, RS1 - Register bank select bits. These two bits are used to
select one of four register banks of RAM. By setting and clearing
these bits, registers R0-R7 are stored in one of four banks of RAM.
Enabling register bank 3

n F0 - Flag 0. This is a general-purpose bit available for use.

n AC - Auxiliary Carry Flag is used for BCD operations only.

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8051 Microcontroller architecture
Special Function Registers
n Program Status Word (PSW) Register
n CY - Carry Flag is the (ninth) auxiliary bit used for all arithmetical
operations and shift instructions.

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8051 Microcontroller architecture
Special Function Registers

n Data Pointer Register (DPTR)

n DPTR register is not a true one because it doesn't physically
exist.
n It is used to access external code or data memory
n It consists of two separate registers: DPH (Data Pointer High)
and (Data Pointer Low).
n For this reason it may be treated as a 16-bit register or as two
independent 8-bit registers.
n Their 16 bits are primarly used for external memory
addressing.
n Besides, the DPTR Register is usually used for storing data
and intermediate results.

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8051 Microcontroller architecture
Special Function Registers

n Data Pointer Register (DPTR)

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8051 Microcontroller architecture
Special Function Registers
n Stack Pointer (SP) Register

n A value stored in the Stack Pointer, points to the first free stack
address and permits stack availability.
n Stack operations includes “pushing” data on the stack and “popping”
data off the stack
n Pushing increment the value in the Stack Pointer by 1 before writing
data.
n Likewise, Popping from the stack reads data and then decrement
the SP.
n Upon any reset and power-on, the value 7 is stored in the Stack
Pointer, which means that the space of RAM reserved for the stack
starts at this location.
n If another value is written to this register, the entire Stack is moved to
the new memory location.

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8051 Microcontroller architecture
Special Function Registers
n Stack Pointer (SP) Register
n The 8051 stack is kept in internal RAM and is limited to addresses
accessible by indirect addressing modes.
n Example: Initialize the stack at 60H, the following instruction is used
n MOV SP, #5FH

n The value of 5FH is used because, SP increment to 60H before the

first push operation.
n If the application software does not reinitialize the SP, then register
bank 1 (and perhaps 2 and 3) is not available, since this area of
internal RAM is the stack.

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8051 Microcontroller architecture
Special Function Registers

n P0, P1, P2, P3 - Input/Output Registers

n If neither external memory nor serial communication system

are used then 4 ports with in total of 32 input/output pins are
available for connection to peripheral environment.
n Each bit within these ports affects the state and performance
of appropriate pin of the microcontroller.
n Thus, bit logic state is reflected on appropriate pin as a voltage
(0 or 5 V) and vice versa, voltage on a pin reflects the state of
appropriate port bit.

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8051 Microcontroller architecture
Special Function Registers

n P0, P1, P2, P3 - Input/Output Registers

n Port bit state affects performance of port pins, i.e. whether they will
be configured as inputs or outputs.
n If a bit is cleared (0), the appropriate pin will be configured as an
output, while if it is set (1), the appropriate pin will be configured as
an input.
n Upon reset and power-on, all port bits are set (1), which means that
all appropriate pins will be configured as inputs.
n Port 0 is at address 80H, Port 1 is at 90H , port 2 is at A0H and port 3
is at B0H.
n Port 0, 2 and 3 may not be available for I/O if external memory is
used.
n All ports are bit addressable. This provides a powerful
interfacing possibility.
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8051 Microcontroller architecture
Special Function Registers

n P0, P1, P2, P3 - Input/Output Registers

n If a motor si connected through a solenoid and transistor driver to
port 1 bit 7, it could be turned on and off using a single 8051
instruction.

n SETB P1.7
n Might turn the motor on , and
n CLR P1.7
n Might turn off
n These instructions the same

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8051 Microcontroller architecture
Special Function Registers

n Timer Registers
n The 8051 microcontroller has 2 timers/counters (16-bit) called T0 and
T1.
n Their main purpose is to measure time and count external events
and also for generating clock pulses to be used in serial
communication, so called Baud Rate.
n If the timer is properly programmed, the value stored in its register
will be incremented (or decremented) with each coming pulse, i.e.
once per each machine cycle.

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8051 Microcontroller architecture
Special Function Registers

n Serial Port Registers

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8051 Microcontroller architecture
Special Function Registers

n Interrupt Registers

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8051 Microcontroller architecture
Special Function Registers

n The A Register (Accumulator)

q Prior to executing an instruction upon any number or operand it
is necessary to store it in the accumulator first.
q All results obtained from arithmetical operations performed by
the ALU are stored in the accumulator.
q Data to be moved from one register to another must go through
the accumulator.
n The B Register
q Multiplication and division can be performed only upon numbers
stored in A and B registers.

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8051 Microcontroller architecture
Special Function Registers
n The R Registers (R0-R7)
q This is a name for 8 general-purpose registers (R0, R1, R2
...R7).
q They occupy 4 banks within RAM and are used for temporary
storing variables and intermediate results during operation.
q The active banks depend on two bits of the PSW Register.
q Active bank is a bank the registers of which are currently used.

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8051 Microcontroller architecture
Special Function Registers
n The R Registers (R0-R7)
q Suppose it is necessary to perform some arithmetical
operations upon numbers previously stored in the R registers:
(R1+R2) - (R3+R4). A register for temporary storing results of
addition is needed.
q This is how it looks in the program:
n MOV A,R3; Means: move number from R3 into accumulator
n ADD A,R4; Means: add number from R4 to accumulator (result remains
in accumulator)
n MOV R5,A; Means: temporarily move the result from accumulator into
R5
n MOV A,R1; Means: move number from R1 to accumulator
n ADD A,R2; Means: add number from R2 to accumulator
n SUBB A,R5; Means: subtract number from R5 (there are R3+R4)

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8051 Microcontroller architecture
Special Function Registers
n The R Registers (R0-R7)
q Example: The following three instructions enable the register
bank3 and then move the contents of R7 to the accumulator

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8051 Microcontroller architecture-Oscillator and clock circuit
n The 8051 requires an external oscillator circuit.
n The oscillator circuit usually runs around 12 MHz, although the

8051 (depending on which specific model) is capable of running at

a maximum of 40 MHz.
n Each machine cycle in the 8051 is 12 clock cycles, giving an

effective cycle rate at 1 MHz (for a 12 MHz clock) to 3.33 MHz (for
the maximum 40 MHz clock).
n The oscillator circuit generates the clock pulses so that all

internal operations are synchronized.

n One machine cycle has 6 states. One state is 2 T-states.

Therefore one machine cycle is 12 T-states. Time to execute an

instruction is found by multiplying C by 12 and dividing product by
Crystal frequency. T=(C*12d)/crystal frequency

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8051 Microcontroller architecture--Reset circuit
q The 8051 is reset by holding RST high for at least two machine
cycles and then returning it low.
q RST may be manually activated using a switch, or may be
activated upon power-up using a R-C (Resister-capacitor) network

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8051 Microcontroller architecture--Reset circuit
q The state of all the 8051 registers after a system reset is as follows

q The most important of these registers, perhaps, is the program counter, which
is loaded with 000H.
q When RST returns low, program execution always begins at the first location
in code memory: address 000H.
q The content of on-chip RAM is not affected by reset operation.

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8051 Microcontroller architecture--I/O Port circuits
q All 8051 microcontrollers have 4 I/O ports each comprising
8 bits which can be configured as inputs or outputs.
q Accordingly, in total of 32 input/output pins enabling the

microcontroller to be connected to peripheral devices are

available for use.
q Pin configuration, i.e. whether it is to be configured as an

input (1) or an output (0), depends on its logic state.

q In order to configure a microcontroller pin as an output, it is

necessary to apply a logic zero (0) to appropriate I/O port

bit.
q In this case, voltage level on appropriate pin will be 0.

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8051 Microcontroller architecture--I/O Port circuits
q Similarly, in order to configure a microcontroller pin as an
input, it is necessary to apply a logic one (1) to appropriate
port.
q In this case, voltage level on appropriate pin will be 5V (as

is the case with any TTL input).

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8051 Microcontroller architecture-- Memory organization
q Most microprocessors implements a shared memory
space for data and programs.
q This is reasonable, since programs are usually stored on a

disk and loaded into RAM for execution; thus the data and
programs resides in the system RAM
q Microcontrollers on the other hand are rarely used as the

CPU in computer systems

q Instead , they are employed as the central components in

control-oriented design.
q There is limited memory, and there is no disk drive or disk

operating system.
q The control program must reside in ROM.

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8051 Microcontroller architecture-- Memory organization
q The 8051 has two types of memory and these are Program
Memory and Data Memory.
q Program Memory (ROM) is used to permanently save the
program being executed, while Data Memory (RAM) is used for
temporarily storing data and intermediate results created and
used during the operation of the microcontroller.
q Depending on the model in use (we are still talking about the 8051
microcontroller family in general) at most a few Kb of ROM and 128
or 256 bytes of RAM is used.
q However…All 8051 microcontrollers have a 16-bit addressing bus
and are capable of addressing 64 kb memory.
q It is neither a mistake nor a big ambition of engineers who were
working on basic core development.
q It is a matter of smart memory organization which makes these
microcontrollers a real “programmers’ goody“.
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8051 Microcontroller architecture-- Memory organization
q Program Memory (ROM)
n All models have a few Kbyte ROM embedded though a memory

sufficient for writing most of the programs.

n How it handles external memory depends on the EA pin logic

state:
n EA= 0 -; the microcontroller ignores internal program memory and executes
only the program stored in external memory.
n EA = 1; the microcontroller executes first the program from built-in ROM
and then the program stored in external memory.

Program Memory of 8051

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8051 Microcontroller architecture-- Memory Organization

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8051 Microcontroller architecture-- Memory organization
q Data memory: is used to store data temporarily.
q RAM in 8051 family has many registers such as hardware counters
and timers, input/output ports, serial data buffers etc.
q The first block consists of 4 banks each including 8 registers denoted
by R0-R7.
q The next memory block (address 20h-2Fh) is bit- addressable which
means that each bit has its own address (0-7Fh).
q Since there are 16 such registers, this block contains in total of 128
bits with separate addresses.
q The third group of registers occupies addresses 2Fh-7Fh.

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8051 Microcontroller architecture-- Memory organization
q Data memory.

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8051 Microcontroller architecture-- Memory organization
q Internal memory
q The internal memory consists of on-chip ROM and on-chip RAM.
q The on-chip RAM contains a rich arrangement of general purpose
storage, bit-addressable storage, register banks and special
function registers.

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8051 Microcontroller architecture-- Memory organization
q Internal memory---- 8031 Memory Space

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8051 Microcontroller architecture-- Memory organization
q Internal memory---- 8051 On-chip data memory

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8051 Microcontroller architecture-- Memory organization
q Internal memory----General Purpose RAM

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8051 Microcontroller architecture-- Memory organization
q Internal memory----Bit Addressable RAM

q Not that “bit address 67H” is the MSB at “byte address 2CH”

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8051 Microcontroller architecture-- Memory organization
q Internal memory----Register Banks

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8051 Microcontroller architecture-- Memory organization
q Memory expansion—External memory
q It is important that microcontrollers have expansion

capabilities beyond the on-chip resources to avoid a

potential design bottleneck.
q If any resources must be expanded (memory, I/O) then the

capability must be available

q The MCS-51 architecture provides a 64K external code

memory space and a 64K external data memory space.

q Extra ROM and RAM can be added as needed.

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8051 Microcontroller architecture-- Memory organization
q Memory expansion—External memory
q Peripheral interface ICs can also be added to expand the

I/O capability.
q When external memory is used, Port 0 is unavailable as an

I/O port.
q It becomes multiplexed address (A0-A7) and data (D0-D7)

bus, with ALE latching the low-byte of the address at the

beginning of each external memory cycle.
q Port 2 is usually (but not always) employed for the high-

byte of the address bus.

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8051 Microcontroller architecture-- Memory organization
q Memory expansion—External memory
q Multiplexing the address and data buses

q A non multiplexed arrangement uses 16 dedicated

address lines and eight dedicated data lines for a total of
24 pins.
q The multiplexed arrangement combines eight lines for the

data bus and low-byte of the address bus, with another

eight lines for the high-byte of the address bus-a total of
16pins
q Saving in pins allows other functions to be offered in a 40-

pin DIP (dual inline package)

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8051 Microcontroller architecture-- Memory organization
q Memory expansion—External memory
q Multiplexing the address and data buses

q
• During first half of the cycle,
the low-byte of the address is
provided on Port 0 and is
latched using ALE.
• A 74HC373 latch holds the
low-byte of the address stable
for the duration of the memory
cycle.
• During second half of the
memory cycle, Port 0 is used
as data bus and data are read
or written depending on the
operation.

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8051 Microcontroller architecture-- Memory organization
q Memory expansion

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8051 Microcontroller architecture-- Memory organization
q Memory expansion--- accessing the external Code Memory
q External code memory is read-only memory enabled by the PSEN signal.
q When external EPROM is used, ports 0 and 2 are unavailable as general
purpose I/O ports.
q The hardware connections for external EPROM memory is as follows

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8051 Microcontroller architecture-- Memory organization
n

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8051 Microcontroller architecture-- Memory organization
q Memory expansion--- accessing the external Code Memory

Read timing for external code memory

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8051 Microcontroller architecture-- Memory organization
q Memory expansion--- accessing the external Data Memory
q External Data memory is read/write memory enabled by RD and
WR-the alternative pin functions for P3.7 and P3.6.
q The only access to external memory is with the MOVX instruction,
using the 16-bit data pointer (DPTR), R0 or R1 as address register.
q RAMs may be interfaced to the 8051 the same way as EPROM
except thar RD line connect to the RAM’s output enable OE line
and WR connect to the RAM’s write W line.
q The connectios for the address and data bus are the same as for
EPROMs.
q Using Ports 0 and 2, up to 64K bytes data RAM can be connected
to 8051.

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8051 Microcontroller architecture-- Memory organization
q Memory expansion--- accessing the external Data Memory
q Example: a 1K byte RAM interfaced to the 8051

Interface to 1K RAM

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8051 Microcontroller architecture-- Memory organization
q Memory expansion--- accessing the external Data Memory
q A timing diagram for a read operation to external data memory is
as follows

Timing for MOVX instruction

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8051 Microcontroller architecture-- Memory organization
q Memory expansion--- Address decoding

q Typically , a decoder IC such as 74HC138 is used with its outputs

connected to the chip select (CS) inputs on the memory ICs.
q Due to the separable enable line (PSEN) for code memory and RD
and WR for data memory, the 8051 can accommodate up to 64K
each of EPROM and RAM.
q Example of system with multiple 2764 EPROMs and 6264 8K
RAMs

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8051 Microcontroller architecture-- Memory organization
q Memory expansion--- Address decoding
q Example of system with multiple 2764 EPROMs and 6264 8K
RAMs

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8051 Microcontroller architecture
q Reading Assignment
q General Purpose Registers
q Power Control Registers
q Overlapping the External Code and Data Spaces

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 End!!!!

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