ELEC512

Digital Electronics

Project Report

Done By

Student Name Student ID

Ziad Sefelnasr 202050895
Saad Alharairi 202050293
Sami Meetani 201950081
Saud Alyassi 201810264
Ammar Alharairi 202050863

Instructor: Prof.Falah Awwad

 TABLE OF CONTENTS

The Objective ................................................................................................................................ 3

The Theory part............................................................................................................................. 4
The Simulation Part........................................................................................................................9
Reference .....................................................................................................................................13
The Objective:

This project aims to analyze and simulate a given circuit containing two n-type MOSFETs using
LTspice software. The analysis will focus on determining the operating regions and drain-source
currents (IDS) of the transistors under the following conditions:
• Technology: 180 nm TSMC process
• Supply Voltage (VDD): 1.8 V
• Transistor Length (L): Fixed at 180 nm (for both)
• Threshold Voltage (Vth): 0.5 V
• Parameter (μnCox): 70 μA/V²
• Bias Voltage (VB): 0.7 V
• Drain Resistor (R): 1 kΩ

The project will be divided into two main tasks:

1. Simulation: The circuit will be simulated in LTspice using the provided 180 nm TSMC
technology model.
2. Analysis the circuit By hand calculation, the operating regions (cut-off, saturation, or
linear) of each MOSFET will be identified based on the simulated voltages and currents.

The final outcome of this project will be a comparison of the calculated operating regions and
drain-source currents with the results obtained from the LTspice simulation. This comparison
will validate the theoretical understanding of MOSFET behavior and the chosen model
parameters.
The Theory part

Let us begin with analysis of the circuit shown in figure 1. We can analyze its behavior
mathematically to figure out how the two transistors (MOSFETs) are operating. We will assume
both transistors are currently turned on. We are given the threshold voltage (Vth) of the MOSFETs
(0.5V), a parameter called Mu-n-Cox (70 μA/V^2), a bias voltage of 0.7V, and a resistor value of 1
kilohm. Based on this information, we can determine the region of operation (cut-off, triode, or
saturation) for each transistor and calculate the current flowing through them (drain-source
current or IDS).

Figure 1: The circuit.

At the beginning we wrote the given information as shown in figure 2.

Figure 2:The Given Information

The next step is to identify the drain and source terminals for both NMOS transistors (Q1 and Q2).
In NMOS devices, current flows from the higher voltage terminal (drain) to the lower voltage
terminal (source). For Q1, VDD is connected to the top terminal, so thats means the drain will be
under the resister because it will have the higher volatge. And the other end will be the source
for Q1. For Q2, the bottom terminal is connected to ground, which establishes it as the source
and the other end will be the drain for Q2. As shown in figure 3. Moreover the Length and width
had been taken from Simulation part.

Figure 3: The circuit with the Drain and Source locations.

Next step is to compare Vds with Vgs-Vtn. And since both NMOS are on so VGs is bigger than Vtn.
So we will do the compartion and we will decided in which region. But since the drain volatges
are unknown we need to assume that both NMOS are in saturation mode as shown in figure 4.

Figure 4: The comparison for Q1 and Q2.

Since we have assumed both transistors are in saturation mode, their drain currents (Ids) will be
equal. This allows us to utilize the drain current equation for transistors in saturation. We can
then substitute the known values to solve for the common drain current of Q1 and Q2.
 Figure 5: Equating the equations and simplify it

Our analysis yielded two possible values for Vs1, but only one satisfies the given condition.
The first value, Vs1 = 1.5 V, leads to Vgs being less than Vth. resulting in the NMOS being in the
cut-off region. Since we're given that the NMOS is ON, we can discard this value.

The second value, Vs1 = 1.1 V, produces a Vgs that allows the NMOS to operate in the saturation
region. To verify our initial assumption of both NMOS being in saturation, we compared) with Vgs
- Vth. The result confirms that Vd2 is indeed greater than the adjusted gate voltage, validating our
assumption that both NMOS transistors are in saturation mode. as shown in figure 6.

Figure 6: validating our assumption

Now we need to find the drain current by putting all the vaule in the saturation mode equation
for the cuurent as shown in figure 7. And we found that the current equal to 1.05 uA.

Figure 7: Finding the current

Next since we found the drain current we can find the drain volatge for Q1 and we found that the
drain volatge is equal to 1.79V. As shown in figure 8. And to check for our assumption and our
assumption is correct we are in the saturation mode.

Figure 8: Finding the VD2 and verify the assumption.

At the end we found that both NMOS working in saturation mode and we found that the drain
current is equal to 1.05uA.
The Simulation Part

Fig1: V1 Fig2 : Schematic of the

circuit

Fig3 : case 1 MOSFETs

values
 Fig4 : case 1
graph

ID vs Vds for M2 transistor (the lower transistor) for 9 different widths (0.18um to 100um) while
M1 width ( the top transistor) is fixed at 0.24um.

Justification for case 1 graphs

• Impact of Transistor Width (W):
• Increasing Width: As the width (W) of the lower transistor (M2) increases in your simulations,
the drain current (ID) is expected to increase proportionally in each curve.
• Wider Channel: Wider transistors provide a larger cross-sectional area for the conducting
channel, allowing more current carriers (electrons) to flow when biased in saturation. This results
in a higher drain current for wider transistors compared to narrower ones at the same gate-source
voltage (VGS).
• Observations on the Graphs:
• The nine curves in the plot should visually confirm this trend. Wider transistors (larger W values)
should correspond to higher ID values across the VDS range (assuming they are all biased in
saturation).
• The curves might start diverging from each other at lower VDS values (linear region) and
become more pronounced as VDS increases (saturation region).
• Additional Factors:
• Aspect Ratio (W/L): While the width is varied, keep in mind that the length (L) of the transistor
might also play a role. The aspect ratio (W/L) can influence the transistor's characteristics.
• Model Parameters: The specific model parameters used for the NMOS transistor in your
simulation can also affect the exact shapes and slopes of the curves.
• Overall Justification:
• The expected behavior is that the drain current (ID) will increase with increasing width (W) of
the transistor for a given gate-source voltage (VGS) in saturation just as shown in the graph.
 Fig5 : case two MOSFETs values

Id vs Vds for M1 transistor (the top transistor) for 9 different widths (0.18um to 100um) while
the lower transistor m2 is fixed at width 0.24um.

Fig6 : case 2
graph
Justification for case 2 graphs
• Impact of Top Transistor Width (W):
• Unlike the case with the lower transistor (M2), the impact of varying the top transistor's width
(W) on the drain current (ID) of the lower transistor (M2) is less direct. Here's why:
• In this configuration, the top transistor (M1) primarily acts as a current source for the lower
transistor (M2). It sets the current that can flow through M2, assuming both transistors are biased
in saturation.
• If the gate-source voltage (VGS) of M1 remains constant across different width variations, the
current it allows to flow will also remain relatively constant (assuming the model operates in
saturation).
• Observations on the Graphs:
• The nine curves representing different widths of M1 should ideally overlap or show minimal
variations in the drain current (ID) of M2 across the VDS range.
• There might be slight variations due to model complexities or non-idealities, but the overall
trend is a relatively constant ID for all width values of M1.

References :
1- https://en.wikipedia.org/wiki/180_nm_process
2- Course lecture