VLSI Design Automation ?

(VLSI (Very Large Scale Integration) Design Automation refers to the use of

computer-aided design (CAD) tools and methodologies to automate the design process of complex integrated

circuits (ICs) or microchips. VLSI design encompasses the creation of integrated circuits with millions or even

billions of transistors packed onto a single chip.)

The VLSI design process involves several key steps:

1.System Specification: This initial phase establishes the high-level requirements and constraints
of the system. It involves understanding market demands, technological capabilities, and economic
considerations to define what the product needs to achieve.

2.Architectural Design: Once the system requirements are understood, architectural decisions are
made. This involves choosing between different architectures (such as Reduced Instruction Set
Computing - RISC, or Complex Instruction Set Computing - CISC), designing Arithmetic Logic Units
(ALUs), configuring pipelines for data processing, and determining cache sizes to optimize
performance. The output of this stage is a Micro-Architectural Specification (MAS) which predicts
system performance based on architectural choices.

3.Behavioral Design: In this stage, the focus shifts to defining the behavior of the system without
getting into the internal structure. It involves identifying functional units, specifying interconnects
between these units, and estimating parameters like timing. Timing diagrams are often used to
visualize how different components interact over time.

4.Logic Design: This stage dives deeper into the internal workings of the system. Designers develop
the control flow, determine word widths for data representation, and specify logic operations using
Hardware Description Languages (HDL) like Verilog or VHDL. The design is then simulated and
tested to ensure correctness before proceeding further.
5. Circuit Design: Converts logic into a circuit layout, considering speed and power requirements,
verified through simulation using a netlist.

Netlist consists of a list of the electronic components in a circuit and a list of the nodes they are
connected to

6. Physical Design: Turns netlist into a geometric representation, automating where possible, using
multiple layers for logic components.

7. Fabrication: Involves creating masks, processing silicon wafers, and multiple fabrication steps to
produce integrated circuits (IC) based on physical design.

8. Packaging, Testing, and Debugging: Dices, packages, and tests chips to ensure they meet
design specs and function correctly.
New Trends in VLSI Design Cycle:

1. Interconnect Challenges:
● Issue: Interconnect delay[wire delay](it is the time difference between when a signal is
first applied to a net and when it reaches other devices connected to that net) increases
due to slower scaling compared to devices.
● Solution: Insert repeaters in long wires to address delay and signal integrity concerns.

2. Interconnect Area Expansion:

● Challenge: Only 60%-70% of microprocessor dies allocated for active devices; rest for
interconnect.
● Development: Introduction of a second metal layer reduces interconnect area.
● Note: More metal layers don't always mean less interconnect area due to via space on
lower layers.

3. Metal Layer Increase:

● Trend: Growing number of metal layers for interconnect.
● Usage: Three-layer process common; four or five layers mainly for microprocessors.

4. Planning Complexity Rise:

● Implication: Interconnect delay, dedicated area, and multiple metal layers highlight device
location importance.
● Steps:
● Block Planning: Assigns shapes and locations to main functional blocks.
● Signal Planning: Assigns three-dimensional regions for major buses and signal
routing.

5. Synthesis for Efficiency:

● Objective: Reduce design time by generating layout from higher-level description.
● Process: Map design to process technology using pre-designed logic cells in the library.
● Drawback: Synthesized blocks occupy larger areas than hand-crafted blocks.
● Types: Logic Block Synthesis and High-Level Synthesis, depending on design level.

I. Logic Block
● Function: Converts HDL (Hardware Description Language) to schematics and produces layout.
● Limitations: Not suitable for large, regular blocks like RAMs, ROMs, PLAs, and Data paths due
to inefficiencies in speed and area.

II. High-Level Synthesis

● Function: Converts a functional or microarchitectural description into a layout or RTL (Register
Transfer Level) description.
● Also Known As: C synthesis, ESL (Electronic System Level) synthesis, algorithmic synthesis, or
behavioral synthesis.
● Process: Automated transformation of abstract behavioral specifications into layout or RTL
descriptions.
● Input: Captures only the behavioral aspects of the system.
Physical Design Cycle :-

I. Partitioning

● Function: Divides VLSI circuit into sub-circuits with minimal interconnections.

II. Floorplanning and Placement

Function: Plans layout alternatives for blocks and places modules considering shape and I/O
pins.

Objectives: Minimize area, arrange blocks, decide I/O pad locations, manage power distribution,
and place clock locations.

● Aspect Ratio Consideration: This step sets up a plan for good layout alternatives for
each block, considering different aspect ratios.
● Aspect Ratio Definition: The aspect ratio of a module ( M ) is defined as ( h/w ), where (
h ) is the height and ( w ) is the width of the rectangular-shaped module.
III. Routing

● Function: Draws interconnection lines for nets.

● Considerations: Critical path, clock skew, crosstalk, and wire spacing.
● Goals: Achieve 100% routing, minimize wire length, chip area, and net delay.

IV. Compaction

● Function: Compresses layout to minimize chip area.

● Benefit: Reduces wire lengths, decreasing signal delay between components.

V. Extraction and Verification

● DRC(Design Rule Checking): Verifies geometric patterns against fabrication rules.

● Circuit Extraction: Generates a circuit for comparison with the netlist.
● Performance Verification: Computes resistance, capacitance, and delay.
● Reliability Verification: Ensures layout won't fail due to various effects.
New Trends in Physical Design Cycle

Interconnect Delay Challenge:

● Issue: In deep sub-micron ranges, interconnect delay doesn't scale as fast as gate delay.
● Solutions: Chip-level signal planning and Over-the-Cell (OTC) routing to reduce
interconnect delay.

1) Chip Level Signal Planning

● Early Planning: Routing of major signals and buses must be planned early to minimize
interconnect distances.
● Goal: Minimize interconnect distances to improve performance and reduce delays.
● Key Signals: Carefully plan key signals (e.g., clock signals, data buses, control lines) for
efficient communication.
● Top Metal Layers: Route global signals in the top metal layers to utilize their low delay per
unit length.

Considerations in Signal Planning:

● Global Signals: Critical signals like clock signals and reset lines that span large chip
areas.
● Routing Layers: Use top metal layers for global signals to minimize delay.
● Minimizing Distance: Plan routing early to reduce signal travel distances and propagation
delays.

2) Over-the-Cell (OTC) Routing

● Description: Routing over blocks and active areas.
● Efficient Interconnections: Determines precise paths for interconnecting standard cells,
macros, and I/O pins.
● Reduced Block Routing: Routing over cells reduces the number of blocks that need
routing within channels.
● Decreased Chip Area: Fewer tracks in channels lead to reduced chip area, making
routing a three-dimensional problem.
● Arbitrary Terminal Model (ATM): Pins are brought to the top of the block as a sea-of-pins
rather than to the block boundaries.
Design Styles :-

1) Full Custom Layout

● Advantages: Precise control, high performance, efficient area usage.
● Disadvantages: Time-consuming, expensive.
● Usage: Mass-produced chips for optimized speed and power.

2) Standard Layout
● Features: Predesigned modules for quick design, less optimized for mass production.
● Usage: Quick design turnaround for ASICs(Application-Specific Integrated Circuit).
3) Gate Array
● Overview: Uses a prefabricated chip with components (e.g., NAND gates, flip-flops)
interconnected by adding metal interconnect layers in the factory.
● Characteristics: All cells are identical, separated by vertical and horizontal channels.

Advantages:

● Reduces design time.

● Simplifies routability.
● Fewer errors.
● Lower production costs.
● Faster production time.

Disadvantages:

● Limited flexibility.
● Requires a moderately high area.
4) Field Programmable Gate Arrays (FPGAs)
● Overview: A new approach to ASIC design, featuring thousands of logic gates that can be
connected to implement any logic function.

Characteristics:

● Prefabricated cells and interconnect.

● Users "program" the interconnect.
● Provides large-scale integration and user programmability.

Components:

● I/O Blocks: Interface between FPGA and external devices.

● Configurable Logic Blocks (CLBs): Implement various logic functions.
● Programmable Routing Interconnects: Configurable pathways for signal flow.

Advantages:

● Reprogrammable.
● Reusable.
● Faster time to market.
● Low cost.

Disadvantages:

● Volatile.
● Less efficient.
● Limited size options.
● Not suitable for high-volume applications.

5) Sea of Gates
● Overview: Uses a prefabricated array of transistors to fabricate complex circuits, such as
RAMs.
Characteristics:

● Higher package density due to the use of transistors.

● Routing interconnects through gates or additional metal/polysilicon layers.

Disadvantages:

● Metal layer routing reduces gate utilization.

● Polysilicon routing increases mask count and fabrication time and cost.