IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 29, NO.

8, AUGUST 2014 4219

A Cascaded Multilevel Inverter Based

on Switched-Capacitor for High-Frequency
AC Power Distribution System
Junfeng Liu, K. W. E. Cheng, Senior Member, IEEE, and Yuanmao Ye

Abstract—The increase of transmission frequency reveals more is made up of a high-frequency (HF) inverter, an HF transmis-
merits than low- or medium-frequency distribution among differ- sion track, and numerous voltage-regulation modules (VRM).
ent kinds of power applications. High-frequency inverter serves as HF inverter accomplishes the power conversion to accommo-
source side in high-frequency ac (HFAC) power distribution sys-
tem (PDS). However, it is complicated to obtain a high-frequency date the requirement of point of load (POL). In order to increase
inverter with both simple circuit topology and straightforward the power capacity, the most popular method is to connect the
modulation strategy. A novel switched-capacitor-based cascaded inverter output in series or in parallel. However, it is impracti-
multilevel inverter is proposed in this paper, which is constructed cal for HF inverter, because it is complicated to simultaneously
by a switched-capacitor frontend and H-Bridge backend. Through synchronize both amplitude and phase with HF dynamics. Mul-
the conversion of series and parallel connections, the switched-
capacitor frontend increases the number of voltage levels. The out- tilevel inverter is an effective solution to increase power capacity
put harmonics and the component counter can be significantly without synchronization consideration, so the higher power ca-
reduced by the increasing number of voltage levels. A symmetrical pacity is easy to be achieved by multilevel inverter with lower
triangular waveform modulation is proposed with a simple analog switch stress. Nonpolluted sinusoidal waveform with the lower
implementation and low modulation frequency comparing with total harmonic distortion (THD) is critically caused by long
traditional multicarrier modulation. The circuit topology, sym-
metrical modulation, operation cycles, Fourier analysis, parame- track distribution in HFAC PDS. The higher number of voltage
ter determination, and topology enhancement are examined. An levels can effectively decrease total harmonics content of stair-
experimental prototype with a rated output frequency of 25 kHz is case output, thus significantly simplifying the filter design [7].
implemented to compare with simulation results. The experimen- HF power distribution is applicable for small-scale and internal
tal results agreed very well with the simulation that confirms the closed electrical network in electric vehicle (EV) due to mod-
feasibility of proposed multilevel inverter.
erate size of distribution network and effective weight reduc-
Index Terms—Cascaded H-Bridge, high-frequency ac (HFAC), tion [8]. The consideration of operation frequency has to make
multilevel inverter, switched capacitor (SC), symmetrical phase- compromise between the ac inductance and resistance [9], so
shift modulation (PSM).
multilevel inverter with the output frequency of about 20 kHz is
a feasible trial to serve as power source for HF EV application.
The traditional topologies of multilevel inverter mainly are
I. INTRODUCTION diode-clamped and capacitor-clamped type [10], [11]. The for-
IGH-FREQUENCY ac (HFAC) power distribution sys- mer uses diodes to clamp the voltage level, and the latter uses
H tem (PDS) potentially becomes an alternative to tradi-
tional dc distribution due to the fewer components and lower
additional capacitors to clamp the voltage. The higher number
of voltage levels can then be obtained; however, the circuit be-
cost. The existing applications can be found in computer [1], comes extremely complex in these two topologies. Another kind
telecom [2], electric vehicle [3], and renewable energy micro- of multilevel inverter is cascaded H-Bridge constructed by the
grid [4], [5]. However, HFAC PDS has to confront the challenges series connection of H-Bridges [12], [13]. The basic circuit is
from large power capacity, high electromagnetic interference similar to the classical H-bridge DC–DC converter [14]. The
(EMI), and severe power losses [6]. A traditional HFAC PDS cascaded structure increases the system reliability because of
the same circuit cell, control structure and modulation. How-
ever, the disadvantages confronted by cascaded structure are
more switches and a number of inputs. In order to increase two
voltage levels in staircase output, an H-Bridge constructed by
Manuscript received April 11, 2013; revised July 22, 2013 and September
27, 2013; accepted November 2, 2013. Date of current version March 26, 2014.
four power switches and an individual input are needed. The-
This work was supported by the Research Grants Council (RGC) of The Hong oretically, cascaded H-Bridge can obtain staircase output with
Kong SAR under the project reference PolyU 5133/10E. Recommended for any number of voltage levels, but it is inappropriate to the ap-
publication by Associate Editor R. N. Raju.
The authors are with the Department of Electrical Engineering, Power
plications of cost saving and input limitation.
Electronics Research Centre, The Hong Kong Polytechnic University, A number of studies have been performed to increase the
Kowloon, Hong Kong (e-mail: [email protected]; [email protected]. number of voltage levels. A switched-capacitor (SC) based mul-
hk; [email protected]).
Color versions of one or more of the figures in this paper are available online
tilevel circuit can effectively increase the number of voltage
at http://ieeexplore.ieee.org. levels. However, the control strategy is complex, and EMI issue
Digital Object Identifier 10.1109/TPEL.2013.2291514 becomes worse due to the discontinuous input current [15]. A

0885-8993 © 2013 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications standards/publications/rights/index.html for more information.
4220 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 29, NO. 8, AUGUST 2014

single-phase five-level pulsewidth-modulated (PWM) inverter

is constituted by a full bridge of diodes, two capacitors and a
switch. However, it only provides output with five voltage levels,
and higher number of voltage levels is limited by circuit struc-
ture [16]. An SC-based cascaded inverter was presented with SC
frontend and full bridge backend. However, both complicated
control and increased components limit its application [17]. The
further study was presented using series/parallel conversion of
SC. However, it is inappropriate to the applications with HF out-
put because of multicarrier PWM (MPWM) [18], [19]. If output
frequency is around 20 kHz, the carrier frequency reaches a
couple of megahertz. Namely, the carrier frequency in MPWM
is dozens times of the output frequency. Since the carrier fre-
quency determines the switching frequency, a high switching
loss is inevitable for the sake of high-frequency output. A boost
multilevel inverter based in partial charging of SC can increase
the number of voltage levels theoretically. However, the con-
trol strategy is complicated to implement partial charging [20].
Therefore, it is a challenging task to present an SC-based multi- Fig. 1. Circuit topology of cascaded nine-level inverter (N 1 = 2, N 2 = 2).
level inverter with high-frequency output, low-output harmon-
ics, and high conversion efficiency [21].
Based on the study situation aforementioned, a novel multi-
level inverter and simple modulation strategy are presented to
serve as HF power source. The rest of this paper is organized
as follows. The discussions of nine-level inverter are presented
in Section II, including circuit topology, modulation strategy,
operation cycle, and Fourier analysis. The parameter determi-
nation and loss analysis are discussed in Section III. The further Fig. 2. Circuit and operational waveforms of symmetrical PSM. (a) Circuit of
enhancement of 13-level inverter is studied in Section IV. The symmetrical PSM. (b) Operational waveforms of symmetrical PSM.
performance evaluation accomplished by simulation and experi-
ment is described in Section V followed by concluding remarks. B. Symmetrical Modulation
There are many modulation methods to regulate the mul-
II. SC-BASED CASCADED INVERTER
tilevel inverter, the popular modulations are the space vector
WITH NINE-LEVEL OUTPUT
modulation [22], the multicarrier PWM [23], and the selective
The proposed circuit is made up of the SC frontend and harmonic elimination [24], [25], subharmonic pulsewidth mod-
cascaded H-Bridge backend. If the numbers of voltage levels ulation [26], etc. However, most of them greatly increase the
obtained by SC frontend and cascaded H-Bridge backend are carrier frequency that is dozens times the frequency of refer-
N1 and N2 , respectively, the number of voltage levels is 2 × ence or output. A symmetrical phase-shift modulation (PSM)
N1 ×N2 +1 in the entire operation cycle. is introduced into the proposed multilevel inverter. The sym-
metrical PSM ensures the output voltage of full bridge is sym-
A. Circuit Topology metrical to the carrier, so voltage levels can be superimposed
symmetrically and carrier frequency is twice as that of the out-
Fig. 1 shows the circuit topology of nine-level inverter (N1 =
put frequency [27]. The structure of symmetrical PSM is shown
2, N2 = 2), where S1 , S2 , S1 , S2 as the switching devices of SC
in Fig. 2(a), and the operational waveform of symmetrical PSM
circuits (SC1 and SC2) are used to convert the series or parallel
is shown in Fig. 2(b).
connection of C1 and C2 . S1a , S1b , S1c , S1d , S2a , S2b , S2c , S2d
The logic operations of gate signals are
are the switching devices of cascaded H-Bridge. Vdc1 and Vdc2
are input voltage. D1 and D2 are diodes to restrict the current −
gate1 = XOR{Q(RS), Q(D)}
direction. iout and vo are the output current and the output
voltage, respectively. gate2 = XOR{Q(RS), Q(D)} (1)
It is worth noting that the backend circuit of the proposed
gate3 = XOR{AN D{Q(RS), N OT (P W M )}, Q(D)}
inverter is cascaded H-Bridges in series connection. It is signifi-
cant for H-Bridge to ensure the circuit conducting regardless of gate4 = XOR{AN D{Q(RS), N OT (P W M )}, Q̄(D)}.
the directions of output voltage and current. In other words, H-
(2)
Bridge has four conducting modes in the conditions of inductive
and resistive load, i.e., forward conducting, reverse conducting, A controlled PWM with pulsewidth δ is symmetrically gener-
forward freewheeling, and reverse freewheeling. ated by the comparisons of the triangle carrier Vc and modulation
LIU et al.: CASCADED MULTILEVEL INVERTER BASED ON SWITCHED-CAPACITOR 4221

signal Vm . The rising edge matching of Vc and Vm triggers the

polarity inversion of the leading bridge, while the falling edge
matching of Vc and Vm triggers the polarity inversion of the
lagging bridge. When Vm has a change ΔVm , this modulation
simultaneously moves gate1 and gate3 in the opposite direction.
Thus, the derived Vab is symmetrical with respect to Vc .

C. Operation Cycles
Fig. 3 demonstrates the ideal waveforms of proposed inverter.
Vc is the triangular carrier, and Vpp is the peak value of Vc . The
modulation signals of triangular carrier are Vm 1c , Vm 1b , Vm 2c
and Vm 2b . Vm 1b and Vm 2b are used to control phase-shift
angles of H-Bridge 1 and H-Bridge 2, respectively, and δi is
the duration of voltage levels controlled by them. Vm 1c and
Vm 2c are used to control the alternative operations of SC1
and SC2, respectively, and αi is the duration of voltage levels
controlled by them. Thus, the drive signals of H-Bridge switches
(S1a , S1b , S1c , S1d , S2a , S2b , S2c , S2d ) are phase-shifted pulse
signals, while the drive signals of SC switches (S1 , S2 , S1 , S2 )
are complementary pulse signals. Two operational modes are
presented as shown in Fig. 3(a) and (b). Mode 1 is similar to
mode 2 apart from the different positions of modulation signals
(Vm 1c , Vm 1b , Vm 2c , Vm 2b ). Consequently, the durations of
each voltage level are controlled by modulation signals in both
mode 1 and mode 2.
Active circuits of the operational mode 1 are demonstrated
in Fig. 4. Re is the equivalent load. When t satisfies t0 ≤ t
< t1 in Fig. 3(a), the switches S1a , S1b , S2a , S2b are driven by
the gate-source voltage, respectively. H-Bridges 1 and 2 are in
freewheeling state, and output voltage equals 0. Because S1
and S2 are on, the capacitors C1 and C2 are charged to Vin
(Vdc1 = Vdc2 = Vin ). The voltages on Bus 1 and Bus 2 are
Vin as well. The current flow of this time interval is shown in
Fig. 4(a).
When t satisfies t1 ≤ t < t2 in Fig. 3(a), the switches
S1a , S1b , S2a , S2c are driven by the gate-source voltage, respec-
tively. H-Bridge 1 is in freewheeling state, and H-Bridge 2 is in
positive conducting state. Output voltage equals Vin . Because
S1 and S2 are on, the capacitors C1 and C2 keep charged to
Vin (Vdc1 = Vdc2 = Vin ). The voltages on Bus 1 and Bus 2 are
Vin as well. The current flow of this time interval is shown in
Fig. 4(b).
When t satisfies t2 ≤ t < t3 in Fig. 3(a), the switches
S1a , S1c , S2a , S2c are driven by the gate-source voltage, respec-
tively. H-Bridges 1 and 2 are in positive conducting state. Output
voltage equals 2Vin . Because S1 and S2 are on, the capacitors
C1 and C2 keep charged to Vin (Vdc1 = Vdc2 = Vin ). The volt- Fig. 3. Operational waveforms of the proposed multilevel inverter. (a) Oper-
ages on Bus 1 and Bus 2 are Vin as well. The current flow of ational mode 1. (b) Operational mode 2.
this time interval is shown in Fig. 4(c).
When t satisfies t3 ≤ t < t4 in Fig. 3(a), the switches
S1a , S1c , S2a , S2c are driven by the gate-source voltage, respec- When t satisfies t4 ≤ t < t5 in Fig. 3(a), the switches
tively. H-Bridges 1 and 2 are in positive conducting state. Output S1a , S1c , S2a , S2c are driven by the gate-source voltage, respec-
voltage equals 3Vin . Because S1 and S2 are on, the capacitor C1 tively. H-Bridges 1 and 2 are in positive conducting state. Output
keeps charged to Vin (Vdc1 = Vdc2 = Vin ), and the capacitor C2 voltage equals 4Vin . Because S1 and S2 are on, the capacitor
is discharged. The voltages on Bus 1 and Bus 2 are Vin and 2Vin , C1 and C2 are discharged. The voltages on Bus 1 and Bus 2
respectively. The current flow of this time interval is shown in both are 2Vin . The current flow of this time interval is shown in
Fig. 4(d). Fig. 4(e).
4222 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 29, NO. 8, AUGUST 2014

Fig. 5. Active circuits for different operation intervals in the operational mode
2: (a) t2 − t3 ; (b) t6 − t7 .

positive conducting state. Output voltage equals 2Vin . Because

S1 and S2 are on, the capacitor C1 keeps charged to Vin and
capacitor C2 is discharged. The voltages on Bus 1 and Bus 2 are
Vin and 2Vin , respectively. The current flow of this time interval
is shown in Fig. 5(a). Similarly, the active circuit of t6 ≤ t < t7
is shown in Fig. 5(b) that has the same operations as t2 ≤ t <
t3 .
The second half-cycle (from t8 on) has the similar active
circuits as the first half-cycle (t1 − t8 ), but the current will
be circulated in the opposite direction to provide the negative
output voltage. The relations of on-state switches and output
voltage level are described in Table I, as well as operations of
two modes are compared closely. Table I has ten working states
for nine voltage levels. When the operation enters a new state
from an adjacent state, only one power switch changes between
on and off. The device stress in switching devices of H-bridge
circuit is higher than that in SC circuit. It can also be found that
the output voltage in Mode 1 is more stable than Mode 2 due to
less discharging period of switching capacitor.
Along with the up-down movement of modulation signals
(Vm 1c , Vm 1b , Vm 2c , Vm 2b ), the output voltage of the pro-
posed inverter is a controllable nine-level staircase. The dura-
tion of each voltage level is determined by the duty-cycle of SC
circuit and the phase-shifted angle of H-Bridge circuit.

D. Operation Cycles
In aforementioned nine-level inverter, the staircase out-
put vo can be divided into four components v01 , v02 , v03 ,
and v04 , as shown in Fig. 6. The durations of each com-
ponent are decided by the comparisons of reference sig-
Fig. 4. Active circuits for different operation intervals in the operational mode
1: (a) t0 − t1 ; (b) t1 − t2 ; (c) t2 − t3 ; (d) t3 − t4 ; (e) t4 − t5 ; (f) t5 − t6 ; nal (Vm 1c , Vm 1b , Vm 2c , Vm 2b ) and triangular carrier (Vc ).
(g) t6 − t7 ; (h) t7 − t8 . If pulsewidths of the constituted component are defined as
δ1 , δ2 , α1 , and α2 , Fourier analysis is accomplished for this
nine-level staircase.
The operations in t5 ≤ t < t6 , t6 ≤ t < t7 , and t7 ≤ t < t8 , are The magnitude of the harmonics is derived by
the same as the operations in t3 ≤ t < t4 , t2 ≤ t < t3 , and t1 ≤ t       
< t2 , respectively. The active circuits are shown in Fig. 4(f)–(h). 4Vin π − α1 π − δ1
Vn = cos n + cos n
Comparing with operational mode 1, the mode 2 has the dif- nπ 2 2
ferent active circuits in two time intervals. When t satisfies t2 ≤      
π − α2 π − δ2
t < t3 in operational mode 2 as shown in Fig. 3(b), the switches + cos n + cos n ,
S1a , S1b , S2a , S2c are driven by the gate-source voltage, respec- 2 2
tively. H-Bridge 1 is in freewheeling state, and H-Bridge 2 is in n = 1, 3, 5, . . . (3)
LIU et al.: CASCADED MULTILEVEL INVERTER BASED ON SWITCHED-CAPACITOR 4223

TABLE I
RELATIONS OF ON-STATE SWITCHES AND OUTPUT VOLTAGE

Fig. 7. Relation curves of output THD versus x1 , x2 (unit, rad): (a) k 1 = 0.6,
k 2 = 0.4; (b) k 1 = 0.5, k 2 = 0.5.

Fig. 6. Output voltage decomposition for Fourier analysis in mode 1. It can be found from Fig. 7 that THD is easy to be regulated by
the duration width of voltage levels. At the suitable scope of x1
and x2 , THD of output voltage is less than 10%. When k1 = 0.6
In operational mode 1
and k2 = 0.4, THD can be less than 10% within the scope of 0.05
Vm 2b Vm 1b < x1 < 0.5 and 0.4 < x2 < 0.6. When k1 = 0.5 and k2 = 0.5,
δ1 = π, α1 = π, THD can be less than 10% within the scope of 0 < x1 < 0.4 and
Vpp Vpp
0.4 < x2 < 0.6. Furthermore, THD becomes less along with
Vm 2c Vm 1c the increasing number of voltage levels. The output magnitude
δ2 = π, α2 = π. (4)
Vpp Vpp of multilevel inverter can be regulated by the duration width
of voltage levels as well. Two patterns are available to perform
In operation mode 2
the regulations of THD and magnitude simultaneously. One is to
Vm 2b Vm 2c regulate x1 , x2 with the fixed k1 , k2 . The other one is to regulate
δ1 = π, α1 = π, k1 , k2 with the fixed x1 , x2 . The numerical benchmark and THD
Vpp Vpp
optimization will be examined in the future study, and a fixed
Vm 1b Vm 1c ratio (k1 = k2 = 0.5, x1 = π/8, x2 = π/4) is adopted to evaluate
δ2 = π, α2 = π. (5)
Vpp Vpp output harmonics in subsequent simulation and experiment.
If the proposed dc–ac inverter is used as second stage of
To further describe the relations of output THD and
ac–ac conversion, an ac–dc controlled rectifier is introduced as
pulsewidths α1 , α2 , δ1 , δ2 , four parameters are predefined
preceding stage of ac–ac conversion. Power factor correction
α1 α2 π − δ1 π − δ2 (PFC) implemented by dc–dc converter can improve the power
k1 = , k2 = , x1 = , x2 = . (6) factor in ac–dc conversion. In this case, both SC and H-bridge
δ1 δ2 2 2
generate the optimized pulsewidth to minimize output THD.
The output waveforms can be characterized by these The magnitude regulation of output voltage can be performed
four
constants. According to the definitions as (THD = by controllable ac–dc stage in input side. The minimized THD
∞ 2 /V ) × 100%), THD of output voltage can be
( V
n =2... n 1 is achieved by this two-stage power circuit, namely, ac–dc stage
calculated by the harmonic magnitudes. The relations of output is used to regulate magnitude, and dc–ac stage formed by the
THD to x1 , x2 are given in Fig. 7 with the fixed k1 and k2 . proposed inverter is used to minimize THD.
4224 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 29, NO. 8, AUGUST 2014

III. DETERMINATION OF CAPACITANCE It can be seen from the equations that the operational mode
2 needs larger C2 than that in operational mode 1. When the
As shown in Fig. 4, the capacitors are charged when they are
in parallel with power source, and the capacitors are discharged load is resistive, the phase of load current is agreed with the
load voltage. The maximum discharging amount of capacitor is
when they are in series with power source. The switch Si and Si
obtained in resistive load, because the peak load current is the
are driven alternatively during the half of output cycle. There-
fore, the driven frequency of Si and Si is twice the frequency midpoint of integration period. In other words, if the capacitance
of Ci is derived in pure resistive load, it also maintains the less
of output voltage, as well as the driven frequency of Sia − Sid
voltage ripples in inductive load.
is the same as the frequency of output voltage.
The capacitance of Ci is determined by the voltage ripple The peak current of the capacitor Ci is derived by
of Ci that denotes the voltage fluctuation of multilevel output. Vin − VC i − VdF
The larger capacitance has the fewer ripple voltage. The voltage Ici = (14)
rc + ron + rd
fluctuation over a narrow scope has a smaller power losses and
higher capacitor efficiency. The appropriated method of capac- where VC i is the voltage on the capacitors Ci , VdF is the forward
itance calculation is that the maximum voltage ripple is 10% of voltage drop of diode, rc is the equivalent series resistance (ESR)
the maximum capacitor voltage [28]. of the capacitors, ron is the internal on-state resistance of the
Before obtaining the capacitance of Ci , two assumptions are switching device, and rd is the internal on-state resistance of
given to simplify the derivations: 1) the output load is pure the diode. Because of a small voltage difference of Vin and VC i ,
resistive load, and 2) the same duration is given in each level of the peak current Ici is fewer for the larger Ci . Thus, the larger
staircase output. Therefore, the time points in Fig. 3 are capacitor is needed to cut down undesirable peak current and
1 1 3 1 prolong the capacitor lifetime.
t0 = 0, t1 = t s , t2 = t s , t3 = t s , t4 = t s The analysis of switching loss is similar to the traditional cas-
20 10 20 5
caded H-bridge, while the capacitor losses consisting of ripple
3 7 2 9
t5 = t s , t6 = t s , t7 = t s , t8 = ts (7) loss Prip and conduction loss Pcond are newly introduced by
10 20 5 20
the proposed inverter. When the capacitor Ci is connected from
where ts is the period of the output voltage derived by series to parallel, the ripple is derived by the difference between
1 the input voltage Vin and the capacitor voltage Vc i . The voltage
ts = (8) ripple of Ci is
fs
where fs is the frequency of the output voltage. In the opera-  t+
1
tional mode 1, as shown in Fig. 3(a), the longest discharging ΔVrip = iC i dt (15)
Ci t−
cycle of C1 is between t4 and t5 , and the longest discharging
cycle of C2 is between t3 and t6 . In the operational mode 2, where iC i is the transient current of the capacitor Ci , and the
as shown in Fig. 3(b), the longest discharging cycle of C1 is discharging interval is denoted by t− and t+ . For C1 in opera-
the same as the operational mode 1, while the longest discharg- tional mode 1, t− and t+ are t4 and t5 , respectively. For C2 in
ing cycle of C2 is between t2 and t7 . Therefore, the maximum operational mode 1, t− and t+ are t3 and t6 , respectively. Thus,
discharging amount of C1 is Qc1 and is defined as the loss from voltage ripple is resulted by
 t5
Qc1 = Iout sin(2πfs t − Φ)dt (9) 
k
2
t4 Prip = Ci ΔVrip fs (16)
where Iout is the amplitude of the output current iout and Φ is i=1

the phase difference between the output voltage vo and current

where k is the number of switched capacitors (SCs), and fs is
iout . If 10% ripple voltage is considered, Qc1 should be less
the frequency of the output voltage. It can be found that the
than 10% of the maximum charge of C1 , i.e.
ripple loss is inversely proportional to the capacitor Ci . The
Qc1 conduction losses can be further calculated by
C1 ≥ . (10)
0.1Vin
k 
 t+
Furthermore, the maximum discharging amount of C2 is Qc2 Pcond = 2fs rc i2ci dt. (17)
and is defined as i=1 t−
 t6
Qc2 = Iout sin(2πfs t − Φ)dt, mode 1 (11) The larger capacitor current leads to a large conduction loss.
t3 Lastly, the losses from SCs are denoted by
 t7
Qc2 = Iout sin(2πfs t − Φ)dt, mode 2. (12) Psc = Prip + Pcond . (18)
t2

Then Both ripple loss and conduction loss are proportional to the
Qc2 frequency of the output voltage and number of capacitors. It
C2 ≥ . (13) is concluded that a larger capacitor can improve efficiency and
0.1Vin
LIU et al.: CASCADED MULTILEVEL INVERTER BASED ON SWITCHED-CAPACITOR 4225

Fig. 8. Capacitance determination. (a) Curves of frontend capacitor versus

voltage ripple with 25 kHz output frequency. (b) Curves of frontend capacitor
versus output frequency with 10% voltage ripple.

prolong capacitor lifetime. However, the larger capacitor leads

to the higher cost. Thus, a tradeoff of cost and efficiency need
to be taken into account.
According to (10), (13), and (15), the relation curves of SCs
(Ci ) and ripple voltage are illustrated in Fig. 8(a) with the fixed
25 kHz output frequency, and relation curves of SC (Ci ) and
output frequency are illustrated in Fig. 8(b) with the fixed 10%
ripple voltage.
It can be found from Fig. 8(a) that the less capacitance leads
to larger ripple voltage. Operational mode 2 needs larger ca-
pacitance than mode 1 to keep the ripples low. The gradient of
capacitor to ripple is larger in low-ripple zone, and the gradient
of capacitor to ripple is lower in high-ripple zone. The gradient
variation is caused by inversely proportional relation between
capacitance with ripple voltage. It can be found from Fig. 8(b)
that the less capacitance is required for higher frequency ap-
plications to maintain 10% ripple voltage. Thus, capacitor cost
can be greatly saved for HF application compared with low-
frequency counterpart.

IV. FURTHER ENHANCEMENTS

The number of voltage levels can be further increased via two
Fig. 9. Circuit topology of 13-level inverter. (a) 3 × 2 with two dc inputs.
approaches. One is to increase the level number generated by SC (b) 2 × 3 with three dc inputs.
circuit; the other one is to increase level number generated by
cascaded H-Bridge. Thirteen-level inverters, as shown in Fig. 9, TABLE II
explain these two methods. COMPONENTS COMPARISON OF PROPOSED INVERTER AND
A 3 × 2 structure, as shown in Fig. 9(a), is derived by the CASCADED H-BRIDGE
enhancement of SC circuit, which needs 6 diodes, 4 capacitors,
14 switches, and 2 dc inputs. 2 × 3 structure as shown in Fig. 9(b)
is derived by the enhancement of H-Bridge circuit, which needs
3 diodes, 3 capacitors, 18 switches, and 3 dc inputs. It can be
found that 3 × 2 structure requires more diodes and capacitors
than 2 × 3 structure. However, the number of power switches in
3 × 2 structure is less than that in 2 × 3 structure. Because the
traditional cascaded H-bridge needs 24 switches and 6 inputs to
produce 13 voltage levels, the numbers of power switches and
inputs are greatly decreased by proposed inverter. In order to
accomplish the staircase output with 4n + 1 voltage levels, the
component counts are compared in Table II.
4226 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 29, NO. 8, AUGUST 2014

Fig. 10. Simulation waveforms of nine-level SC-based cascaded inverter, output frequency fs = 25 kHz (k 1 = k 2 = 0.5, x1 = π/8, x2 = π/4, mode 1).
(a) Low power at 50 W. (b) High power at 4 kW.

An n × 2 topology needs 2n – 2 capacitors, 2n + 8 switches, V. PERFORMANCE EVALUATION

and 2 dc inputs; 2 × n topology needs n capacitors, 6n switches,
A. Simulation Evaluation
and n dc inputs. The traditional cascaded H-Bridge needs 8n
switches and 2n dc inputs. With the same number of voltage The simulation based on PSIM is performed for the proposed
levels, the proposed inverter needs less switching devices and inverter. The waveforms of output voltage vo , capacitor cur-
inputs than the traditional cascaded H-Bridge. Considering the rents (iC 1 , iC 2 ) and capacitor voltages (vC 1 , vC 2 ) are shown in
power losses, the traditional cascaded H-bridge has the higher Fig. 10. The following parameters are used for low power sim-
switching losses caused by more switch devices. However, the ulation. The input voltage is Vin = 12 V, the module 1 capacitor
proposed inverter newly introduces the capacitor loss that has is C1 = 100 μF with 80 mΩ ESR, the module 2 capacitor is C2
already been examined in last section. Moreover, a flexible cir- = 220 μF with 50 mΩ ESR, the diodes D1 and D2 have 0.6 V
cuit structure becomes possible. It is feasible for the proposed forward voltage drop and 50 mΩ internal on-state resistance,
multilevel inverter to select suitable enhancement that can ac- and the load resistance is Ro = 12 Ω. The following parameters
commodate the requirements from different applications. For are used for high-power simulation. The input voltage is Vin =
example, 2 × n topology can be used for the power application 100 V, the module 1 capacitor is C1 = 300 μF with 30 mΩ
sourced by multiple solar panels or batteries, and n × 2 topology ESR, the module 2 capacitor is C2 = 560 μF with 20 mΩ ESR,
can be used for the power application sourced by dual power and the load resistance is Ro = 12 Ω. The output frequency fs
sources. is 25 kHz. The waveforms of low power and high power are
LIU et al.: CASCADED MULTILEVEL INVERTER BASED ON SWITCHED-CAPACITOR 4227

TABLE III
HARMONICS OF THE PROPOSED 9-LEVEL AND 13-LEVEL INVERTER

Fig. 11(c) that the voltage drop is indistinctive in each step of

staircase output because the discharging periods of SCs become
shorter for 13-level inverter.
Fig. 11. Simulation waveforms of 9-level and 13-level inverter, output fre-
quency fs = 25 kHz. (a) Output voltage of nine-level inverter (k 1 = k 2 = 0.5, The output spectrums of 9-level and 13-level inverter are il-
x1 = π/8, x2 = π/4). (b) Spectrum of nine-level output. (c) Output voltage of lustrated in Fig. 11(b) and (d), respectively. The fundamental
13-level inverter (same duration of each voltage level). (d) Spectrum of 13-level frequency is 25 kHz that is the same as output frequency. It
output.
can be observed that the fundamental harmonic is significantly
higher than the other harmonics. The magnitude of fundamen-
tal component is below 40 V for nine-level inverter, while the
demonstrated in Fig. 10(a) and (b), respectively. It can be seen
magnitude of fundamental component is 55 V for a 13-level
that the proposed inverter can work at higher power. C1 and
inverter. The dominating harmonics are compared in Table III.
C2 can be converted to resonant switched-capacitor topology
The calculated THD is 19.1% for 9-level inverter and 14.1%
easily [29], [30] and hence the less power loss can be achieved
for 13-level inverter. A 13-level inverter has fewer high order
in the frontend SC stage.
harmonics than nine-level inverter. It can be estimated that the
The simulation waveforms are accorded with theoretical anal-
harmonics can be further cut down along with the increasing
ysis. C1 is discharged at the interval of t4 to t5 , and C2 is dis-
number of voltage levels. Thus, the proposed inverter produces
charged at the interval of t3 to t6 . Both capacitors are charged
near sinusoidal staircase output, and two methods can make
and discharged once every half cycle. Because of the internal
it more sinusoidal. One is to optimize the duration of voltage
resistance of diodes D1 and D2 , the charging current can be
levels; the other one is to increase the number of voltage levels.
divided into several subintervals that are in accordance with
operational analysis in Fig. 4. Considering the charging cycle
B. Experimental Evaluation
and RC time constant, the peak current of charging period and
voltage drop of discharging period are rational at the given con- An experimental prototype was implemented with output fre-
ditions. Theoretically, low power can obtain amplitude of ±4 quency of 25 kHz and output power of 50 W. The schematic
× 12 V, and high power can obtain amplitude of ±4 × 100 V. of modulation circuit is shown in Fig. 12 that is made up of
However, an amplitude difference emerges between theoreti- DFF, RSFF, NOT, and XOR. LM393 is a dual comparator oper-
cal results and simulation waveforms. In low power simulation, ated at single voltage mode. The LOCMOS logic components
the voltage of the capacitors C1 varies between 11 and 11.3 V, consisting of HEF4013 (dual D flip-flop), HEF4070 (Quad 2-
while the voltage of the capacitors C2 varies between 10.8 and input XOR), HEF4081 (Quad 2-input AND gate), and HEF4069
11.1 V. In high power simulation, the voltage of the capacitors (Hex Inverters) accomplish the symmetrical PSM. 5 V out-
C1 varies between 91 and 95 V, while the voltage of the ca- put in CMOS logic is magnified by boot-strap IC IR2113 to
pacitors C2 varies between 89 and 91 V. Thus, the amplitude drive power switches. The schematic of power circuit is same as
of simulation waveform is less than the theoretical amplitude shown in Fig. 1. The switching devices are IRF540 MOSFETs
caused by forward voltage drop and inner resistance. with about 50 mΩ on-state resistances. Capacitor C1 is 100 μF
The output voltage and voltage spectrum are compared in electrolytic capacitor with ESR 80 mΩ, while C2 is 220 μF
Fig. 11, including 9- and 13-level inverter. Fig. 11(a) is output electrolytic capacitor with ESR 50 mΩ. Vin is 12 V supplied by
waveform of nine-level inverter at condition of k1 = k2 = 0.5, dc power supply KIKUSUI PAS40-9. The switching frequency
x1 = π/8, and x2 = π/4. The voltage step in staircase output has of H-bridge backend is 25 kHz, while the switching frequency
a slightly drop at t = 0.00465–0.00475 due to the discharging of SC frontend is 50 kHz. Ro is 12 Ω resistive load.
cycle of SC. Fig. 11(c) is output waveform of 13-level inverter Fig. 13 shows the observed waveforms of gate drivers
with the same duration of each voltage level. A thirteen-level (gs1 , gs1a ), input currents (Iin1 , Iin2 ), and output voltage (vo ).
inverter adopts 3 × 2 structure, and the following circuit param- The switching frequency of S1 , S1 , S2 , and S2 is twice the
eters are used. The input voltage is Vin = 12 V, the module 1 output frequency, and the switching frequency of S1a − S1d
capacitors are C1 = 100 μF C1 = 120 μF with 80 mΩ ESR, the and S2a − S2d is the same as the output frequency. Thus, the
module 2 capacitor are C2 = 220 μF C2 = 250 μF with 50 mΩ switching frequency is so much less than that in multicarrier
ESR, and the load resistance is Ro = 12 Ω. It can be found from modulation. Iin2 is greater than Iin1 , so Vdc2 provides more
4228 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 29, NO. 8, AUGUST 2014

Fig. 12. Schematic of modulation circuit.

Fig. 13. Observed waveforms of output voltage, gate drivers, input currents
with 25 kHz frequency and 12 Ω load (k 1 = k 2 = 0.5, x1 = π/8, x2 = π/4). Fig. 14. Observed waveforms of output voltage, capacitor currents and capac-
(a) Upper trace: output voltage v o ; second trace: S 1 gate driver gs 1 ; third trace: itor voltages with 25 kHz output frequency, and 12 Ω load (k 1 = k 2 = 0.5, x1
S 1 a gate driver of gs 1 a ; lower trace: input current Iin 1 . (b) Upper trace: output = π/8, x2 = π/4). (a) Upper trace: output voltage v o ; middle trace: capacitor
voltage v o ; second trace: S 2 gate driver gs 2 ; third trace: S 2 a gate driver gs 2 a ; current ic 1 ; lower trace: capacitor voltage v c 1 . (b) Upper trace: output voltage
lower trace: input current Iin 2 . v o ; middle trace: capacitor current ic 2 ; lower trace: capacitor voltage v c 2 .

energy than Vdc1 . There is an energy unbalance in each cell

with cascaded connection, and the further study is required for theoretical amplitude 48 V caused by the voltage drop from
power balance. THD of output voltage is 19.7% for nine-level the internal resistance of MOSFETs, diode, and capacitor. The
inverter, which is close to simulation results and theoretical charging cycle is divided into several subintervals, and capac-
analysis. itor C1 has a shorter discharging cycle than capacitor C2 . The
Fig. 14 shows the observed waveforms of output voltage (vo ), capacitor voltages vc1 and vc2 alternatively increase and drop
capacitor currents (ic1 , ic2 ), and capacitor voltages (vc1 , vc2 ). along with charging and discharging operations, respectively.
The observed amplitude of output voltage is lower than the vc1 has the lower ripple voltage than vc2 due to the shorter
LIU et al.: CASCADED MULTILEVEL INVERTER BASED ON SWITCHED-CAPACITOR 4229

of simulation and experiment due to the discrepancy between

the simulation model and the experimental prototype. However,
the curvature varied with the output current is almost similar.
The main power losses contain switching losses, conduction
losses of the switches, conduction losses of capacitors, and rip-
ple losses of capacitors. It can be found that the proposed inverter
can achieve more than 83% conversion efficiency over a wide
range of output current. Meanwhile, total efficiency slightly falls
off along with the increase in the output power. The root cause
is the increase of conduction losses due to on-resistance of the
power MOSFET.
With the same circuit parameters, the smooth output is seen
Fig. 15. Observed output and capacitor voltage at condition of k 1 = k 2 = in high-frequency scenario. Meanwhile, the capacitor cost of
0.5, x1 = π/8, x2 = π/4, and 12 Ω load. (a) Output waveforms of 25 kHz
frequency. Upper trace: output voltage v o ; lower trace: capacitor voltage v c 1 . high-frequency scenario can be significantly saved compared
(b) Output waveforms of 500 Hz frequency. Upper trace: output voltage v o ; with low frequency counterpart. Thus, the proposed modula-
lower trace: capacitor voltage v c 1 . tion and topology are more suitable for high-frequency appli-
cations. Furthermore, the charging and discharging frequencies
of SCs are twice the output frequency, which is significantly
less than the charging and discharging frequencies in multi-
carrier pulsewidth modulation [18]. Thus, the capacitor life-
time is prolonged by the reduced times of charging and dis-
charging. Meanwhile, the system reliability is increased due to
the same circuit cell and modulation strategy. It is concluded
from simulation and experiment that the proposed multilevel
inverter and symmetrical modulation are an effective approach
to serve as high-frequency power source with higher conversion
efficiency.
Fig. 16. Output waveforms after LC filter and conversion efficiency. (a) Upper
trace: staircase output v o ; middle trace: output voltage after LC filter v o f ; lower
trace: output current after LC filter io f . (b) Conversion efficiency comparisons VI. CONCLUSION
of nine-level inverter with 25 kHz output under the condition of k 1 = k 2 = 0.5,
x1 = π/8, x2 = π/4.
In this paper, a novel SC-based cascaded multilevel inverter
was proposed. Both 9-level and 13-level circuit topology are
examined in depth. Compared with conventional cascaded mul-
discharging period. The experimental results are in accord with tilevel inverter, the proposed inverter can greatly decrease the
the simulation waveforms as shown in Fig. 10. number of switching devices. A single carrier modulation named
Fig. 15 shows the observed waveforms at the different output by symmetrical PSM, was presented with the low switching
frequencies with the operational condition of k1 = k2 = 0.5, x1 frequency and simple implementation. The accordant results
= π/8, x2 = π/4. The same circuit parameters are adopted for of simulation and experiment further confirm the feasibility of
comparisons of 25 kHz and 500 Hz. The output and capacitor proposed circuit and modulation method.
voltage are demonstrated in Fig. 15(a) with the output frequency Comparing with traditional cascade H-bridge, the number
of 25 kHz; the output and capacitor voltage are demonstrated in of voltage levels can be further increased by SC frontend. For
Fig. 15(b) with the output frequency of 500 Hz. It can be found instance, the number of voltage levels increases twice in half
that the voltage drop is indistinct in each step of 25 kHz staircase cycle of 9-level circuit, and the number of voltage levels in-
output caused by a shorter discharging cycle. However, a larger creases three times in half cycle of 13-level circuit. With the
voltage drop occurs in each step of 500 Hz staircase output due exponential increase in the number of voltage levels, the har-
to a longer discharging cycle. Likewise, the larger ripple can be monics are significantly cut down in staircase output, which is
found in capacitor voltage vc1 with output frequency of 500 Hz. particularly remarkable due to simple and flexible circuit topol-
A small LC filter is added in front of resistive load to improve ogy. Meanwhile, the magnitude control can be accomplished
the output harmonics. The filter inductor and capacitor are 50 μH by pulsewidth regulation of voltage level, so the proposed mul-
and 0.5 μF, respectively. Output voltage and current after filter tilevel inverter can serve as HF power source with controlled
are vof and iof , both of which are demonstrated in Fig. 16(a). magnitude and fewer harmonics. This paper mainly analyzes
It can be found that the LC filter smoothes the staircase output nine-level and 13-level inverters. The method of analysis and
and more sinusoidal output is obtained for power distribution. design is also applicable to other members of the proposed in-
The efficiency curves of the simulation and experiment are il- verter. The proposed inverter can be applied to grid-connected
lustrated in Fig. 16(b). Both simulation and experiment adopt the photovoltaic system and electrical network of EV, because the
same circuit parameters with the output frequency of 25 kHz. multiple dc sources are available easily from solar panel, batter-
There are some small differences existed between the results ies, ultracapacitors, and fuel cells.
4230 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 29, NO. 8, AUGUST 2014

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pp. 2763–2770, Dec. 2005. best teaching in 2003 from the Hong Kong Polytechnic University, the Faculty
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