Int. J. Elec&Electr.Eng&Telecoms.

2013 K Venkata Subba Reddy and K Bala, 2013

ISSN 2319 – 2518 www.ijeetc.com

Vol. 2, No. 4, October 2013
© 2013 IJEETC. All Rights Reserved

Research Paper

IMPLEMENTATION OF 64-POINT FFT/IFFT

BY USING RADIX-8 ALGORITHM
K Venkata Subba Reddy1* and K Bala1

*Corresponding Author: K Venkata Subba Reddy,  [email protected]

Fast Fourier Transform (FFT) processing is one of the key procedure in popular Orthogonal
Frequency Division Multiplexing (OFDM) communication systems. Structured pipeline
architectures, low power consumption, high speed and reduced chip area are the main concerns
in this VLSI implementation. In this paper, the efficient implementation of FFT/IFFT processor
for OFDM applications is presented. The processor can be used in various OFDM-based
communication systems, such as Worldwide interoperability for Microwave access (Wi-Max),
Digital Audio Broadcasting (DAB), Digital Video Broadcasting-Terrestrial (DVB-T). We adopt
single-path delay feedback architecture. To eliminate the Read Only Memories (ROM’s) used to
store the twiddle factors, this proposed architecture applies a reconfigurable complex multiplier
to achieve a ROM-less FFT/IFFT processor and to reduce the truncation error we adopt the
fixed width modified booth multiplier. The three Processing Elements (PE’s), Delay-Line (DL)
buffers are used for computing IFFT. Thus we consume the low power, lower hardware cost,
high efficiency and reduced chip size.

Keywords: FFT/IFFT, Single delay feedback path, OFDM, Pipelined architectures, High power
consumption

INTRODUCTION of operation, low power consumption, reduced

The Fast Fourier Transform (FFT) and its truncation error and reduced chip size. By
Inverse Fast Fourier Transform (IFFT) are considering these facts, we proposed the
essential in the field of digital signal ROM-less processor with Single-path Delay
processing (DSP), widely used in Feedback (SDF) pipeline architecture and
communication systems, especially in modified booth width multiplier. The SDF
Orthogonal Rrequency Division Multiplexing pipelined architecture is used for the high-
(OFDM) systems, wireless-LAN, ADSL, VDSL throughput in FFT processor. There are three
systems and W i-MAX. Apart from the types of pipeline structures; they are Single-
applications, the system demands high speed path Delay Feedback (SDF), Single-path
1
SRTS College of Engineering, Ukkayapalli Road, Kadapa 516002, AP, India.

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Int. J. Elec&Electr.Eng&Telecoms. 2013 K Venkata Subba Reddy and K Bala, 2013

Delay Commutator (SDC) and Multi-path equation essentially combines two stages of
Delay Commutator. The advantages of Single- a radix-2 FFT into one, so that half as many
path Delay Feedback (SDF) are (1) This SDF stages are required. To calculate 16-point FFT,
architecture is very simple to implement the the radix-2 takes log216 = 4 stages but the
different length FFT. (2) The required registers radix-4 takes only log416 = 2 stages. A 16-
in SDF architecture is less than MDC and point, radix-4 decimation-in-frequency FFT
SDC architectures. (3) The control unit of SDF algorithm is shown in Figure 1. Its input is in
architecture is easier. We implement the normal order and its output is in digit-reversed
processor in SDF architecture with radix-8 order. It has exactly the same computational
algorithm. There are various algorithms to complexity as the decimation-in-time radix-4
implement FFT, such as radix-2, radix-4 and FFT algorithm.
split-radix with arbitrary sizes, radix-2 algorithm
Figure 1: Flow Graph of a 16-Point
is the simplest one, but its calculation of Radix-4 FFT Algorithm
addition and multiplication is more than radix-
4’s. Though being more efficient than radix-2,
radix-8 only can process 8 n-point FFT. The
radix-8 FFT equation essentially combines
three stages of a radix-2 FFT into one, so that
one third as many stages are required. Since
the radix-8 FFT requires fewer stages and
butterflies than the radix 2 FFT, the
computations of FFT can be further improved.
Using radix-8 algorithm, we propose a 64-
point FFT/IFFT processor with ROM
architecture.

FFT/IFFT ALGORITMH EXISTING ARCHITECTURE

In last three decades, various FFT In this paper, low power techniques are
architectures such as single-memory employed for power consumption using
architecture, dual memory architecture, reconfigurable complex multiplier. Using
pipelined architecture, array architecture and radix-4 algorithm, increase the
cache memory architecture have been computational speed, further reduce the chip
proposed. In order to improve the power area by three different Processing Elements
reduction, we propose a radix-4 64-point (PE’s) were proposed in this radix-4 64-point
pipeline FFT/IFFT processor. In order to speed FFT/IFFT processor. Our proposed
up the FFT computations, more advanced architecture uses a low complexity
solutions have been proposed using an reconfigurable complex multiplier instead of
increase of the radix. The radix-4 FFT ROM tables to generate twiddle factors and
algorithm is most popular and has the potential fixed width modified booth multiplier to
to satisfy the current need. The radix-4 FFT reduce the truncation error.

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Int. J. Elec&Electr.Eng&Telecoms. 2013 K Venkata Subba Reddy and K Bala, 2013

Figure 2: Existing Radix-4 64-Point PROPOSED ARCHITECTURE

Pipeline FFT/IFFT Processor In the R2SDF pipelined architecture, we can
find that relationship between the PE
numbered and different radix agorithams
shown in Figures 3 and 4; presents a
complex multiplier, denotes a constant
multiplier and denotes a complex multiplier..
The radix-2 PE, radix-22 PE and radix-23 PE
respectively map to one time stage of Signal
Flow Graph (SFG) of radix-2 butterfly, two
time stage of SFG of radix-4 butterfly and

Figure 3: Relationship Between the PE Number and Different Radix Algorithm

(a) R2SDF PE in Radix-2 Butterfly (b) R22SDF PE in Radix-4 Butterfly

Figure 4: R23SDF PE in Radix-8 Butterfly

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Int. J. Elec&Electr.Eng&Telecoms. 2013 K Venkata Subba Reddy and K Bala, 2013

three time stage of SFG of radix-8 butterfly. R2SDF at the last time stage can redeem the
When R2SDF performs a N-point DFT, where R22SDF to Implement all time stage. When
N is a power of 2, every PE of R2SDF the R23SDF implements N- point D FT, where
includes a complex multiplier except the PE N is a power of 8, employing PEs of R23SDF
of penultimate time stage employs a “–j” can completely implement all time stage.
complex multiplier. W hen the R2 2 SDF Except N isn’t a power of 8, adding extra
implements N-point DFT, where N is a power R2SDF PE at the last one remainder time
of 4, employing PEs o f R2 2 SDF can stage or R22SDF PE at two remainder time
completely implement all time stage. Except stage can completely implement operation of
N isn’t a power of 4, adding a extra PE of all time stages.

Table 1: Analyze the Number of Complex Multiplications in SDF with Different Radix

R2SDF
FFT point 64 128 256 512 1024 2048 4096 8192
Constant mul 0 0 0 0 0 0 0 0
Complex mul 4 5 6 7 8 9 10 11
Multiplierarea 131459.2 164324 197188.8 230053.6 262918.4 295783.2 328648 361512.8
R22SDF
FFT point 64 128 256 512 1024 2048 4096 8192
Constant mul 0 0 0 0 0 0 0 0
Complex mul 2 3 3 4 4 5 5 6
Multiplierarea 65729.6 98594.4 98594.4 131459.2 131459.2 164324 164324 197188.8
3
R2 SDF
FFT point 64 128 256 512 1024 2048 4096 8192
Constant mul 2 2 2 3 3 3 4 4
Complex mul 1 2 2 2 3 3 3 4
Multiplierarea 53275.6 86140.4 86140.4 96345.8 129210.6 129210.6 139416 172280.8
Note: Constant and Complex Multiplier bit width: 20 bit, process: umc. 18. Complex Multiplier: 32864.8 um . Constant Multiplier: 10205.4 um2.
2

Figure 5: Simulation Results

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Int. J. Elec&Electr.Eng&Telecoms. 2013 K Venkata Subba Reddy and K Bala, 2013

CONCLUSION Complex Fourier Series”, Math. Comput.,

A low power pipelined 64-point FFT/IFFT Vol. 5, No. 5, pp. 87-109.
processor for OFDM applications has been 4. Despain A M (1974), “Fourier Transform
described in this paper. Computer Using CORDIC Iterations”,
We present an efficient FFT/IFFT compiler IEEE Trans. Comput., Vol. C-23,
which consists of three IP cores, R23SDF, October, pp. 993-1001.
R2 3MDC and memory-based FFT
5. Jia L, Gao Y, Isoaho J and Tenhunen H
architectures. The inputs to our developed
(1998), “A New VLSI-Oriented FFT
generator are a set of user-defined parameters.
Algorithm and Implementation”, Proc.
Since our design requires low-cost and
Eleventh Annu. IEEE Int. ASIC Conf.,
consumes low power, as well as reduced SQNR
pp. 337-341.
and highly efficient. Hence it can be applied as
a powerful FFT/IFFT processor in wireless 6. Oppenheim A V, Schafer R W and John
communication systems. R Buck (1999), Discrete-Time Signal
Processing, 2nd Edition, Prentice-Hill.
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