TRIBHUVAN UNIVERSITY

INSTITUTE OF ENGINEERING
PULCHOWK CAMPUS

A REPORT ON
64 BIT PROCESSOR

SUBMITTED BY:
PRAHARSHA ADHIKARI (PUL078BCT061)

SUBMITTED TO:
PROF. DR. SUBARNA SHAKYA
DEPARTMENT OF ELECTRONICS & COMPUTER ENGINEERING

MAY 31, 2024

Contents
1 Introduction 1

2 Internal Architecture 2
2.1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2.1.1 General-Purpose Registers (GPRs) . . . . . . . . . . . . . . . . . . . 2
2.1.2 Floating-Point Registers . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.1.3 Special-Purpose Registers . . . . . . . . . . . . . . . . . . . . . . . . 3
2.2 Arithmetic Logic Unit (ALU) . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.3 Control Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.3.1 Fetch Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.3.2 Decode Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.3.3 Execute Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.4 Cache Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.5 Instruction Set Architecture (ISA) . . . . . . . . . . . . . . . . . . . . . . . 4
2.6 Memory Management Unit (MMU) . . . . . . . . . . . . . . . . . . . . . . . 5
2.7 Bus Interface Unit (BIU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.8 Pipeline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.9 Branch Predictor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.10 Integrated Graphics Processor (IGP) . . . . . . . . . . . . . . . . . . . . . . 6

3 Comparison between 32 bit and 64 bit processor 7

3.1 Memory Addressing Capacity . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.2 Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.3 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.4 Compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.5 Applications and Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.6 Security Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.7 Operating Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.8 Use cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

4 Limitations 10
4.1 Increased Memory Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

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 4.2 Compatibility Issues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.3 Software Overhead . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.4 Increased Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.5 No Performance Gain for Certain Applications . . . . . . . . . . . . . . . . . 10
4.6 Larger Binary Sizes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.7 Driver Availability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.8 Increased Development and Testing Requirements . . . . . . . . . . . . . . . 11

References 11
1. Introduction
The transition to 64-bit processors represents a pivotal advancement in the field of computer
architecture, fundamentally enhancing the capabilities and performance of contemporary
computing systems. This report aims to provide a detailed analysis of 64-bit processors,
tracing architectural design as well as the profound implications they hold for computational
efficiency and capacity. By exploring the theoretical foundations and practical implementa-
tions of 64-bit processors, this report seeks to offer an in-depth understanding of their role
as a cornerstone in the evolution of modern computing.

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2. Internal Architecture
These details highlight the sophisticated architecture and capabilities of 64-bit processors,
emphasizing their role in enhancing computational performance and efficiency across various
applications.

Figure 2.1: Block Diagram of 64-bit internal architechure

2.1 Registers
2.1.1 General-Purpose Registers (GPRs)
General-purpose registers (GPRs) in 64-bit processors are designed to hold 64-bit values and
are utilized for a wide range of operations including arithmetic, logic, and data transfer.
Examples of these registers in the x86-64 architecture include RAX, RBX, RCX, and RDX.

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2.1.2 Floating-Point Registers
Floating-point registers are used for performing floating-point calculations and typically
support 64-bit double-precision operations. Modern 64-bit processors often incorporate ad-
ditional registers for SIMD (Single Instruction, Multiple Data) operations, such as those
provided by SSE (Streaming SIMD Extensions) and AVX (Advanced Vector Extensions) in
Intel processors.

2.1.3 Special-Purpose Registers

Special-purpose registers include the Instruction Pointer (IP), Stack Pointer (SP), Base
Pointer (BP), and various flags or status registers that control and monitor the proces-
sor’s operations. These registers play a critical role in managing the execution flow and the
state of the processor.

2.2 Arithmetic Logic Unit (ALU)

The Arithmetic Logic Unit (ALU) in a 64-bit processor performs arithmetic and logical
operations on data held in the registers. With the capability to operate on 64-bit integers
directly, the ALU enables faster computations involving large numbers. Modern processors
often contain multiple ALUs to perform parallel computations, thereby increasing processing
speed and efficiency.

2.3 Control Unit

The control unit orchestrates the operation of the processor, managing the fetching, decoding,
and executing of instructions. It coordinates the activities of the ALU, registers, and other
components, ensuring that the processor executes instructions correctly and efficiently.

2.3.1 Fetch Stage

In the fetch stage, instructions are retrieved from memory. The Program Counter (PC),
which is 64 bits wide, holds the address of the next instruction. This address is translated
from virtual to physical by the Memory Management Unit (MMU). The fetched instruction is
placed into the Instruction Register (IR), and the PC is incremented to point to the following
instruction. Modern processors use a multi-level cache hierarchy (L1, L2, and L3 caches)
to store frequently accessed instructions, minimizing delays from main memory access and
ensuring a continuous flow of instructions into the pipeline.

2.3.2 Decode Stage

During the decode stage, the fetched instruction is decoded to extract the opcode, which
specifies the operation to be performed, and the operands, which may include 64-bit registers

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or memory addresses. The control unit generates the necessary control signals based on the
opcode to direct various CPU components such as the ALU, registers, and memory.

2.3.3 Execute Stage

In the execute stage, the processor performs the operation specified by the decoded instruc-
tion. For arithmetic and logical operations, the ALU executes the required computation
on 64-bit data. Memory-related instructions involve calculated addresses and data transfer
between the registers and memory. Branch instructions update the PC to the target address
if the branch condition is met, supported by branch prediction mechanisms to minimize
pipeline stalls. The result of the execution is written back to the designated register or
memory location, completing the instruction cycle.

2.4 Cache Memory

Cache memory is a small, high-speed memory located close to the CPU, storing frequently
accessed data and instructions to reduce fetch times from main memory. The multi-level
cache system improves overall performance by minimizing memory access latency.

• L1 Cache: The fastest and smallest cache, located closest to the CPU cores, typically
divided into separate instruction (I-cache) and data (D-cache) caches.

• L2 Cache: Larger and slightly slower than L1 cache, often shared by multiple cores
in some architectures.

• L3 Cache: The largest and slowest cache, shared across all cores in multi-core pro-
cessors.

2.5 Instruction Set Architecture (ISA)

The ISA defines the set of instructions the processor can execute and serves as the interface
between software and hardware. It includes instruction formats, addressing modes, and
operational codes (opcodes).

• x86-64 ISA: Extends the x86 architecture to support 64-bit computing, with addi-
tional registers and instructions.

• ARM64 ISA: Designed for efficiency in power and performance, used in many mobile
and embedded devices, including instructions for SIMD and advanced floating-point
operations.

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2.6 Memory Management Unit (MMU)
The MMU translates virtual addresses used by software into physical addresses used by
hardware. It manages memory protection, cache control, and paging.

• Paging: Divides virtual memory into fixed-size pages and maps them to physical
memory frames.

• Virtual to Physical Address Translation: Uses page tables to map virtual ad-
dresses to physical addresses.

• Memory Protection: Enforces access control to protect different processes’ memory

spaces.

2.7 Bus Interface Unit (BIU)

The BIU manages communication between the CPU and other system components such
as memory, input/output devices, and other peripherals. It handles the transfer of data
between the CPU and memory or I/O devices, manages access to the system bus to prevent
conflicts, and performs address translation by converting virtual addresses from the CPU to
physical addresses on the system bus.

2.8 Pipeline
Pipelining is a technique that allows multiple instruction phases to overlap, improving CPU
throughput and performance. The pipeline in a 64-bit processor’s internal architecture en-
ables more efficient instruction execution by allowing multiple instructions to be processed
simultaneously in different pipeline stages. Typical pipelining stages include fetch, decode,
execute, memory access, and write-back. The wider data paths and registers in a 64-bit
processor enhance the performance of the pipeline by enabling the processor to handle larger
data sizes and more complex operations.

2.9 Branch Predictor

The branch predictor in a 64-bit processor enhances instruction execution by predicting
the outcome of branch instructions, such as if-else conditions. It employs both static and
dynamic prediction techniques to optimize branch prediction accuracy. Static prediction
relies on predefined rules, while dynamic prediction uses historical data and heuristics to
predict branch outcomes more accurately. Additionally, the processor uses a Branch Target
Buffer (BTB) to store the target addresses of recently taken branches, speeding up branch
resolution by providing quick access to branch targets.

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2.10 Integrated Graphics Processor (IGP)
Some 64-bit CPUs include an integrated graphics processor to handle graphics rendering
tasks, reducing the need for a separate graphics card. The Graphics Execution Units perform
rendering, shading, and other graphics tasks, accelerating video playback and recording.

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3. Comparison between 32 bit and 64
bit processor
The following points show the contrast between 32 bit and 64 bit processor and help us
understand them.

3.1 Memory Addressing Capacity

• 32-bit processors: Can address up to 4 GB of RAM directly. This limitation is due
to the 32-bit address space, which allows for 232 unique addresses.

• 64-bit processors: Can theoretically address up to 16 exabytes of RAM, although

practical limitations are currently much lower. The 64-bit address space allows for 264
unique addresses.

3.2 Performance
• 32-bit processors: Generally have lower performance in handling large data sets and
applications requiring significant computational power.

• 64-bit processors: Offer higher performance due to the ability to handle more data
per clock cycle and access more memory, which is beneficial for tasks such as video
editing, 3D rendering, and complex scientific calculations.

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3.3 Registers

Figure 3.1: Size comparision of registers in 64 bit and 32 bit processors

• 32-bit processors: Typically have 32-bit wide registers, which limit the amount of
data processed in a single instruction.

• 64-bit processors: Have 64-bit wide registers, allowing them to process larger chunks
of data per instruction, improving efficiency in data-intensive applications.

3.4 Compatibility
• 32-bit processors: Can only run 32-bit operating systems and applications.

• 64-bit processors: Can run both 64-bit and 32-bit operating systems and applica-
tions, offering greater flexibility and future-proofing.

3.5 Applications and Software

• 32-bit processors: Limited to 32-bit software, which can be a constraint for modern
applications that demand more memory and processing power.

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 • 64-bit processors: Support 64-bit software, which can utilize more memory and
provide better performance for demanding applications.

3.6 Security Features

• 32-bit processors: Lack some of the advanced security features available in 64-bit
processors.

• 64-bit processors: Include enhanced security features such as hardware-based Data

Execution Prevention (DEP) and support for Address Space Layout Randomization
(ASLR), making them more secure against certain types of attacks.

3.7 Operating Systems

• 32-bit processors: Limited to 32-bit operating systems, which restrict the use of
modern software that requires more memory and processing power.

• 64-bit processors: Can run 64-bit operating systems, which are optimized to handle
more memory and provide better performance for modern applications.

3.8 Use cases

• 32-bit processors: Suitable for basic computing tasks such as word processing, brows-
ing, and running simple applications.

• 64-bit processors: Ideal for advanced computing tasks including gaming, video edit-
ing, running virtual machines, and scientific computing, where higher performance and
more memory are crucial.

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4. Limitations
Even though 64 bit processors sound so great, they are not prefect at all. Below are some
limitations of 64 bit processors:

4.1 Increased Memory Usage

64-bit applications often consume more memory than 32-bit applications because pointers
and certain data structures are larger. This results in higher memory requirements and
potential inefficiencies, especially in environments with limited RAM.

4.2 Compatibility Issues

Some older software and hardware may not be compatible with 64-bit processors. This can
pose challenges in running legacy applications or using older peripheral devices that do not
have 64-bit drivers available.

4.3 Software Overhead

Developing and maintaining 64-bit software can be more complex and resource-intensive.
This complexity results in increased development costs and longer timeframes for software
updates and bug fixes.

4.4 Increased Power Consumption

64-bit processors can consume more power compared to 32-bit processors, especially in high-
performance scenarios. This can lead to shorter battery life for mobile devices and higher
energy costs for data centers.

4.5 No Performance Gain for Certain Applications

Not all applications benefit from the 64-bit architecture. Programs that do not require
large amounts of memory or intensive computations may not see significant performance
improvements, making the switch to 64-bit less beneficial in some cases.

4.6 Larger Binary Sizes

64-bit executables and libraries are generally larger than their 32-bit counterparts. This can
lead to increased disk space usage and longer load times for applications.

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4.7 Driver Availability
Finding 64-bit drivers for certain hardware, especially older devices, can be challenging. This
may restrict the use of certain peripherals or require users to seek alternative solutions or
newer hardware.

4.8 Increased Development and Testing Requirements

Developing 64-bit applications requires thorough testing to ensure compatibility and per-
formance across different hardware configurations. This adds to the complexity and cost of
software development, requiring more robust testing environments and resources.

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References
• An Introduction to 64-bit Computing and x86-64 by Jon Stokes, Arstechnica,
https://arstechnica.com/gadgets/2002/03/an-introduction-to-64-bit-computing-and-
x86-64/ - (accessed: 30.05.2024)

• 64-bit computing, Wikipedia, https://en.wikipedia.org/wiki/64-bit_computing

(accessed: 30.05.2024)

• 64 - Bit Processor | Computer Architecture & Organisation (CAO) - Computer

Science Engineering (CSE), Edurev, https://edurev.in/t/97497/64-Bit-Processor -
(accessed: 30.05.2024)

• x64 Architecture, Microsoft Learn, https://learn.microsoft.com/en-us/windows-

hardware/drivers/debugger/x64-architecture - (accessed: 30.05.2024)

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