RM0360

Reference manual
STM32F030x4/x6/x8/xC and STM32F070x6/xB
advanced Arm®-based 32-bit MCUs

Introduction
This reference manual targets application developers. It provides complete information on
how to use the STM32F030x4/x6/x8/xC and STM32F070x6/xB microcontroller memory and
peripherals.
It applies to STM32F030x4/x6/x8/xC and STM32F070x6/xB devices.
For the purpose of this manual, STM32F030x4/x6/x8/xC and STM32F070x6/xB
microcontrollers are referred to as STM32F0x0.
The STM32F0x0 is a family of microcontrollers with different memory sizes, packages and
peripherals.
For ordering information, mechanical and electrical device characteristics, please refer to
the corresponding datasheet.
For information on the Arm® Cortex®-M0 core, please refer to the Arm® Cortex®-M0
technical reference manual.
STM32F030x4/x6/x8/xC and STM32F070x6/xB microcontrollers include ST state-of-the-art
patented technology.

Related documents
• Arm® Cortex®-M0 technical reference manual, available from Arm website at
www.arm.com
• STM32F0xx Cortex-M0 programming manual (PM0215)
• STM32F030x4/x6/x8/xC and STM32F070x6/xB datasheets available from
STMicroelectronics website at www.st.com
• STM32F030x4/x6/x8/xC and STM32F070x6/xB errata sheets available from
STMicroelectronics website at www.st.com

May 2023 RM0360 Rev 5 1/775

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Contents RM0360

Contents

1 Documentation conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
1.1 General information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
1.2 List of abbreviations for registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
1.3 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
1.4 Availability of peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

2 System and memory overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

2.1 System architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
2.2 Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
2.2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
2.2.2 Memory map and register boundary addresses . . . . . . . . . . . . . . . . . . 38
2.3 Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
2.4 Flash memory overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
2.5 Boot configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

3 Embedded flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

3.1 Flash main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
3.2 Flash memory functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
3.2.1 Flash memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
3.2.2 Flash program and erase operations . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
3.3 Memory protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
3.3.1 Read protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
3.3.2 Write protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
3.3.3 Option byte write protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
3.4 Flash interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
3.5 Flash register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
3.5.1 Flash access control register (FLASH_ACR) . . . . . . . . . . . . . . . . . . . . 59
3.5.2 Flash key register (FLASH_KEYR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
3.5.3 Flash option key register (FLASH_OPTKEYR) . . . . . . . . . . . . . . . . . . . 60
3.5.4 Flash status register (FLASH_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
3.5.5 Flash control register (FLASH_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
3.5.6 Flash address register (FLASH_AR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
3.5.7 Flash Option byte register (FLASH_OBR) . . . . . . . . . . . . . . . . . . . . . . . 63

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3.5.8 Write protection register (FLASH_WRPR) . . . . . . . . . . . . . . . . . . . . . . . 64

3.5.9 Flash register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

4 Option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
4.1 Option byte description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
4.1.1 User and read protection option byte . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
4.1.2 User data option byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
4.1.3 Write protection option byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
4.1.4 Option byte map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

5 Cyclic redundancy check calculation unit (CRC) . . . . . . . . . . . . . . . . . 70

5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
5.2 CRC main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
5.3 CRC functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
5.3.1 CRC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
5.3.2 CRC internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
5.3.3 CRC operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
5.4 CRC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
5.4.1 CRC data register (CRC_DR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
5.4.2 CRC independent data register (CRC_IDR) . . . . . . . . . . . . . . . . . . . . . 73
5.4.3 CRC control register (CRC_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
5.4.4 CRC initial value (CRC_INIT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
5.4.5 CRC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

6 Power control (PWR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

6.1 Power supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
6.1.1 Independent A/D converter supply and reference voltage . . . . . . . . . . . 76
6.1.2 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
6.2 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
6.2.1 Power on reset (POR) / power down reset (PDR) . . . . . . . . . . . . . . . . . 77
6.3 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
6.3.1 Slowing down system clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
6.3.2 Peripheral clock gating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
6.3.3 Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
6.3.4 Stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
6.3.5 Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

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6.3.6 RTC wakeup from low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

6.4 Power control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
6.4.1 Power control register (PWR_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
6.4.2 Power control/status register (PWR_CSR) . . . . . . . . . . . . . . . . . . . . . . 86
6.4.3 PWR register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

7 Reset and clock control (RCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

7.1 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
7.1.1 Power reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
7.1.2 System reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
7.1.3 RTC domain reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
7.2 Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
7.2.1 HSE clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
7.2.2 HSI clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
7.2.3 PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
7.2.4 LSE clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
7.2.5 LSI clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
7.2.6 System clock (SYSCLK) selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
7.2.7 Clock security system (CSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
7.2.8 ADC clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
7.2.9 RTC clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
7.2.10 Independent watchdog clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
7.2.11 Clock-out capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
7.2.12 Internal/external clock measurement with TIM14 . . . . . . . . . . . . . . . . . 98
7.3 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
7.4 RCC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
7.4.1 Clock control register (RCC_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
7.4.2 Clock configuration register (RCC_CFGR) . . . . . . . . . . . . . . . . . . . . . 101
7.4.3 Clock interrupt register (RCC_CIR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
7.4.4 APB peripheral reset register 2 (RCC_APB2RSTR) . . . . . . . . . . . . . . 107
7.4.5 APB peripheral reset register 1 (RCC_APB1RSTR) . . . . . . . . . . . . . . 108
7.4.6 AHB peripheral clock enable register (RCC_AHBENR) . . . . . . . . . . . 110
7.4.7 APB peripheral clock enable register 2 (RCC_APB2ENR) . . . . . . . . . 111
7.4.8 APB peripheral clock enable register 1 (RCC_APB1ENR) . . . . . . . . . 113
7.4.9 RTC domain control register (RCC_BDCR) . . . . . . . . . . . . . . . . . . . . . 115
7.4.10 Control/status register (RCC_CSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
7.4.11 AHB peripheral reset register (RCC_AHBRSTR) . . . . . . . . . . . . . . . . 118

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7.4.12 Clock configuration register 2 (RCC_CFGR2) . . . . . . . . . . . . . . . . . . . 119

7.4.13 Clock configuration register 3 (RCC_CFGR3) . . . . . . . . . . . . . . . . . . . 120
7.4.14 Clock control register 2 (RCC_CR2) . . . . . . . . . . . . . . . . . . . . . . . . . . 121
7.4.15 RCC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

8 General-purpose I/Os (GPIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
8.2 GPIO main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
8.3 GPIO functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
8.3.1 General-purpose I/O (GPIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
8.3.2 I/O pin alternate function multiplexer and mapping . . . . . . . . . . . . . . . 127
8.3.3 I/O port control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
8.3.4 I/O port data registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
8.3.5 I/O data bitwise handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
8.3.6 GPIO locking mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
8.3.7 I/O alternate function input/output . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
8.3.8 External interrupt/wake-up lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
8.3.9 Input configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
8.3.10 Output configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
8.3.11 Alternate function configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
8.3.12 Analog configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
8.3.13 Using the HSE or LSE oscillator pins as GPIOs . . . . . . . . . . . . . . . . . 133
8.3.14 Using the GPIO pins in the RTC supply domain . . . . . . . . . . . . . . . . . 133
8.4 GPIO registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
8.4.1 GPIO port mode register (GPIOx_MODER)
(x =A to D, F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
8.4.2 GPIO port output type register (GPIOx_OTYPER)
(x = A to D, F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
8.4.3 GPIO port output speed register (GPIOx_OSPEEDR)
(x = A to D, F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
8.4.4 GPIO port pull-up/pull-down register (GPIOx_PUPDR)
(x = A to ,D, F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
8.4.5 GPIO port input data register (GPIOx_IDR)
(x = A to D, F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
8.4.6 GPIO port output data register (GPIOx_ODR)
(x = A to D, F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
8.4.7 GPIO port bit set/reset register (GPIOx_BSRR)
(x = A to D, F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

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8.4.8 GPIO port configuration lock register (GPIOx_LCKR)

(x = A to B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
8.4.9 GPIO alternate function low register (GPIOx_AFRL)
(x = A to D, ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
8.4.10 GPIO alternate function high register (GPIOx_AFRH)
(x = A to D, F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
8.4.11 GPIO port bit reset register (GPIOx_BRR) (x = A to D, F) . . . . . . . . . . 139
8.4.12 GPIO register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140

9 System configuration controller (SYSCFG) . . . . . . . . . . . . . . . . . . . . 142

9.1 SYSCFG registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
9.1.1 SYSCFG configuration register 1 (SYSCFG_CFGR1) . . . . . . . . . . . . 142
9.1.2 SYSCFG external interrupt configuration register 1
(SYSCFG_EXTICR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
9.1.3 SYSCFG external interrupt configuration register 2
(SYSCFG_EXTICR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
9.1.4 SYSCFG external interrupt configuration register 3
(SYSCFG_EXTICR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
9.1.5 SYSCFG external interrupt configuration register 4
(SYSCFG_EXTICR4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
9.1.6 SYSCFG configuration register 2 (SYSCFG_CFGR2) . . . . . . . . . . . . 147
9.1.7 SYSCFG register maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148

10 Direct memory access controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . 149

10.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
10.2 DMA main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
10.3 DMA implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
10.3.1 DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
10.3.2 DMA request mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
10.4 DMA functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
10.4.1 DMA block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
10.4.2 DMA transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
10.4.3 DMA arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
10.4.4 DMA channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
10.4.5 DMA data width, alignment and endianness . . . . . . . . . . . . . . . . . . . . 159
10.4.6 DMA error management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
10.5 DMA interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
10.6 DMA registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161

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10.6.1 DMA interrupt status register (DMA_ISR) . . . . . . . . . . . . . . . . . . . . . . 161

10.6.2 DMA interrupt flag clear register (DMA_IFCR) . . . . . . . . . . . . . . . . . . 163
10.6.3 DMA channel x configuration register (DMA_CCRx) . . . . . . . . . . . . . . 164
10.6.4 DMA channel x number of data to transfer register (DMA_CNDTRx) . 166
10.6.5 DMA channel x peripheral address register (DMA_CPARx) . . . . . . . . 167
10.6.6 DMA channel x memory address register (DMA_CMARx) . . . . . . . . . 168
10.6.7 DMA channel selection register (DMA_CSELR) . . . . . . . . . . . . . . . . . 168
10.6.8 DMA register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169

11 Interrupts and events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171

11.1 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 171
11.1.1 NVIC main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
11.1.2 SysTick calibration value register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
11.1.3 Interrupt and exception vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
11.2 Extended interrupts and events controller (EXTI) . . . . . . . . . . . . . . . . . 173
11.2.1 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
11.2.2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
11.2.3 Event management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
11.2.4 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
11.2.5 External and internal interrupt/event line mapping . . . . . . . . . . . . . . . 176
11.3 EXTI registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
11.3.1 Interrupt mask register (EXTI_IMR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
11.3.2 Event mask register (EXTI_EMR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
11.3.3 Rising trigger selection register (EXTI_RTSR) . . . . . . . . . . . . . . . . . . 177
11.3.4 Falling trigger selection register (EXTI_FTSR) . . . . . . . . . . . . . . . . . . 178
11.3.5 Software interrupt event register (EXTI_SWIER) . . . . . . . . . . . . . . . . 179
11.3.6 Pending register (EXTI_PR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
11.3.7 EXTI register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181

12 Analog-to-digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182

12.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
12.2 ADC main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
12.3 ADC functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
12.3.1 ADC pins and internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
12.3.2 Calibration (ADCAL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
12.3.3 ADC on-off control (ADEN, ADDIS, ADRDY) . . . . . . . . . . . . . . . . . . . . 186
12.3.4 ADC clock (CKMODE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188

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12.3.5 Configuring the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189

12.3.6 Channel selection (CHSEL, SCANDIR) . . . . . . . . . . . . . . . . . . . . . . . . 189
12.3.7 Programmable sampling time (SMP) . . . . . . . . . . . . . . . . . . . . . . . . . . 190
12.3.8 Single conversion mode (CONT = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . 190
12.3.9 Continuous conversion mode (CONT = 1) . . . . . . . . . . . . . . . . . . . . . . 191
12.3.10 Starting conversions (ADSTART) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
12.3.11 Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
12.3.12 Stopping an ongoing conversion (ADSTP) . . . . . . . . . . . . . . . . . . . . . 193
12.4 Conversion on external trigger and trigger polarity (EXTSEL, EXTEN) . 193
12.4.1 Discontinuous mode (DISCEN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
12.4.2 Programmable resolution (RES) - Fast conversion mode . . . . . . . . . . 194
12.4.3 End of conversion, end of sampling phase (EOC, EOSMP flags) . . . . 195
12.4.4 End of conversion sequence (EOS flag) . . . . . . . . . . . . . . . . . . . . . . . 195
12.4.5 Example timing diagrams (single/continuous modes
hardware/software triggers) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
12.5 Data management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
12.5.1 Data register and data alignment (ADC_DR, ALIGN) . . . . . . . . . . . . . 198
12.5.2 ADC overrun (OVR, OVRMOD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
12.5.3 Managing a sequence of data converted without using the DMA . . . . 199
12.5.4 Managing converted data without using the DMA without overrun . . . 199
12.5.5 Managing converted data using the DMA . . . . . . . . . . . . . . . . . . . . . . 199
12.6 Low-power features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
12.6.1 Wait mode conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
12.6.2 Auto-off mode (AUTOFF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
12.7 Analog window watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
12.7.1 Description of the analog watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
12.7.2 ADC_AWD1_OUT output signal generation . . . . . . . . . . . . . . . . . . . . 204
12.7.3 Analog watchdog threshold control . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
12.8 Temperature sensor and internal reference voltage . . . . . . . . . . . . . . . . 207
12.9 ADC interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
12.10 ADC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .211
12.10.1 ADC interrupt and status register (ADC_ISR) . . . . . . . . . . . . . . . . . . . 211
12.10.2 ADC interrupt enable register (ADC_IER) . . . . . . . . . . . . . . . . . . . . . . 212
12.10.3 ADC control register (ADC_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
12.10.4 ADC configuration register 1 (ADC_CFGR1) . . . . . . . . . . . . . . . . . . . 216
12.10.5 ADC configuration register 2 (ADC_CFGR2) . . . . . . . . . . . . . . . . . . . 220

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12.10.6 ADC sampling time register (ADC_SMPR) . . . . . . . . . . . . . . . . . . . . . 220

12.10.7 ADC watchdog threshold register (ADC_TR) . . . . . . . . . . . . . . . . . . . 221
12.10.8 ADC channel selection register (ADC_CHSELR) . . . . . . . . . . . . . . . . 221
12.10.9 ADC data register (ADC_DR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
12.10.10 ADC common configuration register (ADC_CCR) . . . . . . . . . . . . . . . . 223
12.11 ADC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223

13 Advanced-control timers (TIM1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225

13.1 TIM1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
13.2 TIM1 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
13.3 TIM1 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
13.3.1 Time-base unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
13.3.2 Counter modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
13.3.3 Repetition counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
13.3.4 Clock sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
13.3.5 Capture/compare channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244
13.3.6 Input capture mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
13.3.7 PWM input mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
13.3.8 Forced output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
13.3.9 Output compare mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
13.3.10 PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
13.3.11 Complementary outputs and dead-time insertion . . . . . . . . . . . . . . . . 254
13.3.12 Using the break function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256
13.3.13 Clearing the OCxREF signal on an external event . . . . . . . . . . . . . . . 259
13.3.14 6-step PWM generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261
13.3.15 One-pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262
13.3.16 Encoder interface mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263
13.3.17 Timer input XOR function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266
13.3.18 Interfacing with Hall sensors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266
13.3.19 TIMx and external trigger synchronization . . . . . . . . . . . . . . . . . . . . . . 268
13.3.20 Timer synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271
13.3.21 Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271
13.4 TIM1 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272
13.4.1 TIM1 control register 1 (TIM1_CR1) . . . . . . . . . . . . . . . . . . . . . . . . . . 272
13.4.2 TIM1 control register 2 (TIM1_CR2) . . . . . . . . . . . . . . . . . . . . . . . . . . 273
13.4.3 TIM1 slave mode control register (TIM1_SMCR) . . . . . . . . . . . . . . . . 275
13.4.4 TIM1 DMA/interrupt enable register (TIM1_DIER) . . . . . . . . . . . . . . . 278

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13.4.5 TIM1 status register (TIM1_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280

13.4.6 TIM1 event generation register (TIM1_EGR) . . . . . . . . . . . . . . . . . . . 281
13.4.7 TIM1 capture/compare mode register 1 (TIM1_CCMR1) . . . . . . . . . . 283
13.4.8 TIM1 capture/compare mode register 2 (TIM1_CCMR2) . . . . . . . . . . 286
13.4.9 TIM1 capture/compare enable register (TIM1_CCER) . . . . . . . . . . . . 288
13.4.10 TIM1 counter (TIM1_CNT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291
13.4.11 TIM1 prescaler (TIM1_PSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292
13.4.12 TIM1 auto-reload register (TIM1_ARR) . . . . . . . . . . . . . . . . . . . . . . . . 292
13.4.13 TIM1 repetition counter register (TIM1_RCR) . . . . . . . . . . . . . . . . . . . 292
13.4.14 TIM1 capture/compare register 1 (TIM1_CCR1) . . . . . . . . . . . . . . . . . 293
13.4.15 TIM1 capture/compare register 2 (TIM1_CCR2) . . . . . . . . . . . . . . . . . 293
13.4.16 TIM1 capture/compare register 3 (TIM1_CCR3) . . . . . . . . . . . . . . . . . 294
13.4.17 TIM1 capture/compare register 4 (TIM1_CCR4) . . . . . . . . . . . . . . . . . 295
13.4.18 TIM1 break and dead-time register (TIM1_BDTR) . . . . . . . . . . . . . . . 295
13.4.19 TIM1 DMA control register (TIM1_DCR) . . . . . . . . . . . . . . . . . . . . . . . 297
13.4.20 TIM1 DMA address for full transfer (TIM1_DMAR) . . . . . . . . . . . . . . . 298
13.4.21 TIM1 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299

14 General-purpose timers (TIM3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301

14.1 TIM3 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301
14.2 TIM3 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301
14.3 TIM3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302
14.3.1 Time-base unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302
14.3.2 Counter modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304
14.3.3 Clock sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315
14.3.4 Capture/compare channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318
14.3.5 Input capture mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320
14.3.6 PWM input mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322
14.3.7 Forced output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323
14.3.8 Output compare mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323
14.3.9 PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324
14.3.10 One-pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328
14.3.11 Clearing the OCxREF signal on an external event . . . . . . . . . . . . . . . 329
14.3.12 Encoder interface mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330
14.3.13 Timer input XOR function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332
14.3.14 Timers and external trigger synchronization . . . . . . . . . . . . . . . . . . . . 333
14.3.15 Timer synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336

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14.3.16 Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342

14.4 TIM3 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343
14.4.1 TIM3 control register 1 (TIM3_CR1) . . . . . . . . . . . . . . . . . . . . . . . . . . 343
14.4.2 TIM3 control register 2 (TIM3_CR2) . . . . . . . . . . . . . . . . . . . . . . . . . . 345
14.4.3 TIM3 slave mode control register (TIM3_SMCR) . . . . . . . . . . . . . . . . 346
14.4.4 TIM3 DMA/Interrupt enable register (TIM3_DIER) . . . . . . . . . . . . . . . 348
14.4.5 TIM3 status register (TIM3_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349
14.4.6 TIM3 event generation register (TIM3_EGR) . . . . . . . . . . . . . . . . . . . 352
14.4.7 TIM3 capture/compare mode register 1 (TIM3_CCMR1) . . . . . . . . . . 353
14.4.8 TIM3 capture/compare mode register 2 (TIM3_CCMR2) . . . . . . . . . . 356
14.4.9 TIM3 capture/compare enable register (TIM3_CCER) . . . . . . . . . . . . 357
14.4.10 TIM3 counter (TIM3_CNT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 359
14.4.11 TIM3 prescaler (TIM3_PSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 359
14.4.12 TIM3 auto-reload register (TIM3_ARR) . . . . . . . . . . . . . . . . . . . . . . . . 359
14.4.13 TIM3 capture/compare register 1 (TIM3_CCR1) . . . . . . . . . . . . . . . . . 360
14.4.14 TIM3 capture/compare register 2 (TIM3_CCR2) . . . . . . . . . . . . . . . . . 360
14.4.15 TIM3 capture/compare register 3 (TIM3_CCR3) . . . . . . . . . . . . . . . . . 360
14.4.16 TIM3 capture/compare register 4 (TIM3_CCR4) . . . . . . . . . . . . . . . . . 362
14.4.17 TIM3 DMA control register (TIM3_DCR) . . . . . . . . . . . . . . . . . . . . . . . 362
14.4.18 TIM3 DMA address for full transfer (TIM3_DMAR) . . . . . . . . . . . . . . . 363
14.4.19 TIM3 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 365

15 Basic timer (TIM6/TIM7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367

15.1 TIM6/TIM7 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367
15.2 TIM6/TIM7 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367
15.3 TIM6/TIM7 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 368
15.3.1 Time-base unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 368
15.3.2 Counter modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 370
15.3.3 Clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 374
15.3.4 Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 374
15.4 TIM6/TIM7 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 375
15.4.1 TIM6/TIM7 control register 1 (TIMx_CR1) . . . . . . . . . . . . . . . . . . . . . . 375
15.4.2 TIM6/TIM7 DMA/Interrupt enable register (TIMx_DIER) . . . . . . . . . . . 376
15.4.3 TIM6/TIM7 status register (TIMx_SR) . . . . . . . . . . . . . . . . . . . . . . . . . 377
15.4.4 TIM6/TIM7 event generation register (TIMx_EGR) . . . . . . . . . . . . . . . 377
15.4.5 TIM6/TIM7 counter (TIMx_CNT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 377
15.4.6 TIM6/TIM7 prescaler (TIMx_PSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378

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15.4.7 TIM6/TIM7 auto-reload register (TIMx_ARR) . . . . . . . . . . . . . . . . . . . 378

15.4.8 TIM6/TIM7 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 379

16 General-purpose timer (TIM14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 380

16.1 TIM14 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 380
16.2 TIM14 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 380
16.3 TIM14 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381
16.3.1 Time-base unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381
16.3.2 Counter operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 382
16.3.3 Clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 385
16.3.4 Capture/compare channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 385
16.3.5 Input capture mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 387
16.3.6 Forced output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 388
16.3.7 Output compare mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 388
16.3.8 PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 390
16.3.9 Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 391
16.4 TIM14 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 391
16.4.1 TIM14 control register 1 (TIM14_CR1) . . . . . . . . . . . . . . . . . . . . . . . . 391
16.4.2 TIM14 interrupt enable register (TIM14_DIER) . . . . . . . . . . . . . . . . . . 392
16.4.3 TIM14 status register (TIM14_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 393
16.4.4 TIM14 event generation register (TIM14_EGR) . . . . . . . . . . . . . . . . . 393
16.4.5 TIM14 capture/compare mode register 1 [alternate] (TIM14_CCMR1) 394
16.4.6 TIM14 capture/compare mode register 1 [alternate] (TIM14_CCMR1) 395
16.4.7 TIM14 capture/compare enable register (TIM14_CCER) . . . . . . . . . . 396
16.4.8 TIM14 counter (TIM14_CNT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397
16.4.9 TIM14 prescaler (TIM14_PSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 398
16.4.10 TIM14 auto-reload register (TIM14_ARR) . . . . . . . . . . . . . . . . . . . . . . 398
16.4.11 TIM14 capture/compare register 1 (TIM14_CCR1) . . . . . . . . . . . . . . . 398
16.4.12 TIM14 option register (TIM14_OR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 399
16.4.13 TIM14 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 399

17 General-purpose timers (TIM15/16/17) . . . . . . . . . . . . . . . . . . . . . . . . 401

17.1 TIM15/16/17 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 401
17.2 TIM15 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 401
17.3 TIM16 and TIM17 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 403
17.4 TIM15/16/17 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 404

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17.4.1 Time-base unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 404

17.4.2 Counter operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 406
17.4.3 Repetition counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 410
17.4.4 Clock sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 411
17.4.5 Capture/compare channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 413
17.4.6 Input capture mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 416
17.4.7 PWM input mode (only for TIM15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 417
17.4.8 Forced output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 417
17.4.9 Output compare mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 418
17.4.10 PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 419
17.4.11 Complementary outputs and dead-time insertion . . . . . . . . . . . . . . . . 420
17.4.12 Using the break function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 422
17.4.13 One-pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 425
17.4.14 TIM15 external trigger synchronization . . . . . . . . . . . . . . . . . . . . . . . . 426
17.4.15 Timer synchronization (TIM15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 429
17.4.16 Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 429
17.5 TIM15 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 430
17.5.1 TIM15 control register 1 (TIM15_CR1) . . . . . . . . . . . . . . . . . . . . . . . . 430
17.5.2 TIM15 control register 2 (TIM15_CR2) . . . . . . . . . . . . . . . . . . . . . . . . 431
17.5.3 TIM15 slave mode control register (TIM15_SMCR) . . . . . . . . . . . . . . 432
17.5.4 TIM15 DMA/interrupt enable register (TIM15_DIER) . . . . . . . . . . . . . 434
17.5.5 TIM15 status register (TIM15_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 435
17.5.6 TIM15 event generation register (TIM15_EGR) . . . . . . . . . . . . . . . . . 437
17.5.7 TIM15 capture/compare mode register 1 [alternate] (TIM15_CCMR1) 438
17.5.8 TIM15 capture/compare mode register 1 [alternate] (TIM15_CCMR1) 439
17.5.9 TIM15 capture/compare enable register (TIM15_CCER) . . . . . . . . . . 441
17.5.10 TIM15 counter (TIM15_CNT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 444
17.5.11 TIM15 prescaler (TIM15_PSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 444
17.5.12 TIM15 auto-reload register (TIM15_ARR) . . . . . . . . . . . . . . . . . . . . . . 444
17.5.13 TIM15 repetition counter register (TIM15_RCR) . . . . . . . . . . . . . . . . . 445
17.5.14 TIM15 capture/compare register 1 (TIM15_CCR1) . . . . . . . . . . . . . . . 445
17.5.15 TIM15 capture/compare register 2 (TIM15_CCR2) . . . . . . . . . . . . . . . 445
17.5.16 TIM15 break and dead-time register (TIM15_BDTR) . . . . . . . . . . . . . 446
17.5.17 TIM15 DMA control register (TIM15_DCR) . . . . . . . . . . . . . . . . . . . . . 448
17.5.18 TIM15 DMA address for full transfer (TIM15_DMAR) . . . . . . . . . . . . . 449
17.5.19 TIM15 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 449
17.6 TIM16/TIM17 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 450

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17.6.1 TIMx control register 1 (TIMx_CR1)(x = 16 to 17) . . . . . . . . . . . . . . . . 450

17.6.2 TIMx control register 2 (TIMx_CR2)(x = 16 to 17) . . . . . . . . . . . . . . . . 452
17.6.3 TIMx DMA/interrupt enable register (TIMx_DIER)(x = 16 to 17) . . . . . 452
17.6.4 TIMx status register (TIMx_SR)(x = 16 to 17) . . . . . . . . . . . . . . . . . . . 453
17.6.5 TIMx event generation register (TIMx_EGR)(x = 16 to 17) . . . . . . . . . 454
17.6.6 TIMx capture/compare mode register 1 [alternate]
(TIMx_CCMR1)(x = 16 to 17) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 455
17.6.7 TIMx capture/compare mode register 1 [alternate]
(TIMx_CCMR1)(x = 16 to 17) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 456
17.6.8 TIMx capture/compare enable register (TIMx_CCER)(x = 16 to 17) . . 458
17.6.9 TIMx counter (TIMx_CNT)(x = 16 to 17) . . . . . . . . . . . . . . . . . . . . . . . 461
17.6.10 TIMx prescaler (TIMx_PSC)(x = 16 to 17) . . . . . . . . . . . . . . . . . . . . . . 461
17.6.11 TIMx auto-reload register (TIMx_ARR)(x = 16 to 17) . . . . . . . . . . . . . 461
17.6.12 TIMx repetition counter register (TIMx_RCR)(x = 16 to 17) . . . . . . . . . 462
17.6.13 TIMx capture/compare register 1 (TIMx_CCR1)(x = 16 to 17) . . . . . . 462
17.6.14 TIMx break and dead-time register (TIMx_BDTR)(x = 16 to 17) . . . . . 462
17.6.15 TIMx DMA control register (TIMx_DCR)(x = 16 to 17) . . . . . . . . . . . . . 464
17.6.16 TIMx DMA address for full transfer (TIMx_DMAR)(x = 16 to 17) . . . . . 465
17.6.17 TIM16/TIM17 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 466

18 Infrared interface (IRTIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 468

19 Independent watchdog (IWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 469

19.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 469
19.2 IWDG main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 469
19.3 IWDG functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 469
19.3.1 IWDG block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 469
19.3.2 Window option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 470
19.3.3 Hardware watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 471
19.3.4 Register access protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 471
19.3.5 Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 471
19.4 IWDG registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 472
19.4.1 IWDG key register (IWDG_KR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 472
19.4.2 IWDG prescaler register (IWDG_PR) . . . . . . . . . . . . . . . . . . . . . . . . . 473
19.4.3 IWDG reload register (IWDG_RLR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 474
19.4.4 IWDG status register (IWDG_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 475
19.4.5 IWDG window register (IWDG_WINR) . . . . . . . . . . . . . . . . . . . . . . . . 476

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19.4.6 IWDG register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 477

20 System window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . 478

20.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 478
20.2 WWDG main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 478
20.3 WWDG functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 478
20.3.1 WWDG block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 479
20.3.2 Enabling the watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 479
20.3.3 Controlling the down-counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 479
20.3.4 How to program the watchdog timeout . . . . . . . . . . . . . . . . . . . . . . . . 479
20.3.5 Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 480
20.4 WWDG interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 481
20.5 WWDG registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 481
20.5.1 WWDG control register (WWDG_CR) . . . . . . . . . . . . . . . . . . . . . . . . . 481
20.5.2 WWDG configuration register (WWDG_CFR) . . . . . . . . . . . . . . . . . . . 482
20.5.3 WWDG status register (WWDG_SR) . . . . . . . . . . . . . . . . . . . . . . . . . 482
20.5.4 WWDG register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 483

21 Real-time clock (RTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 484

21.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 484
21.2 RTC main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 485
21.3 RTC implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 485
21.4 RTC functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 486
21.4.1 RTC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 486
21.4.2 GPIOs controlled by the RTC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 488
21.4.3 Clock and prescalers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 489
21.4.4 Real-time clock and calendar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 490
21.4.5 Programmable alarm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 490
21.4.6 Periodic auto-wake-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 491
21.4.7 RTC initialization and configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 491
21.4.8 Reading the calendar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 493
21.4.9 Resetting the RTC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 494
21.4.10 RTC synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 494
21.4.11 RTC reference clock detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 495
21.4.12 RTC smooth digital calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 496
21.4.13 Time-stamp function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 498

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21.4.14 Tamper detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 498

21.4.15 Calibration clock output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500
21.4.16 Alarm output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500
21.5 RTC low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 501
21.6 RTC interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 501
21.7 RTC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 501
21.7.1 RTC time register (RTC_TR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 501
21.7.2 RTC date register (RTC_DR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 502
21.7.3 RTC control register (RTC_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 504
21.7.4 RTC initialization and status register (RTC_ISR) . . . . . . . . . . . . . . . . . 507
21.7.5 RTC prescaler register (RTC_PRER) . . . . . . . . . . . . . . . . . . . . . . . . . 509
21.7.6 RTC wake-up timer register (RTC_WUTR) . . . . . . . . . . . . . . . . . . . . . 510
21.7.7 RTC alarm A register (RTC_ALRMAR) . . . . . . . . . . . . . . . . . . . . . . . . 511
21.7.8 RTC write protection register (RTC_WPR) . . . . . . . . . . . . . . . . . . . . . 512
21.7.9 RTC sub second register (RTC_SSR) . . . . . . . . . . . . . . . . . . . . . . . . . 512
21.7.10 RTC shift control register (RTC_SHIFTR) . . . . . . . . . . . . . . . . . . . . . . 513
21.7.11 RTC timestamp time register (RTC_TSTR) . . . . . . . . . . . . . . . . . . . . . 514
21.7.12 RTC timestamp date register (RTC_TSDR) . . . . . . . . . . . . . . . . . . . . 515
21.7.13 RTC time-stamp sub second register (RTC_TSSSR) . . . . . . . . . . . . . 516
21.7.14 RTC calibration register (RTC_CALR) . . . . . . . . . . . . . . . . . . . . . . . . . 517
21.7.15 RTC tamper and alternate function configuration register
(RTC_TAFCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 518
21.7.16 RTC alarm A sub second register (RTC_ALRMASSR) . . . . . . . . . . . . 521
21.7.17 RTC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 521

22 Inter-integrated circuit (I2C) interface . . . . . . . . . . . . . . . . . . . . . . . . . 524

22.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 524
22.2 I2C main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 524
22.3 I2C implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 525
22.4 I2C functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 525
22.4.1 I2C block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 526
22.4.2 I2C2 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 526
22.4.3 I2C pins and internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 527
22.4.4 I2C clock requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 527
22.4.5 Mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 528
22.4.6 I2C initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 529
22.4.7 Software reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 533

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22.4.8 Data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 534

22.4.9 I2C slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 536
22.4.10 I2C master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 545
22.4.11 I2C_TIMINGR register configuration examples . . . . . . . . . . . . . . . . . . 556
22.4.12 SMBus specific features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 558
22.4.13 SMBus initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 561
22.4.14 SMBus: I2C_TIMEOUTR register configuration examples . . . . . . . . . 563
22.4.15 SMBus slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 563
22.4.16 Error conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 570
22.4.17 DMA requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 572
22.4.18 Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 573
22.5 I2C low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 573
22.6 I2C interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 574
22.7 I2C registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 575
22.7.1 I2C control register 1 (I2C_CR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 575
22.7.2 I2C control register 2 (I2C_CR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 577
22.7.3 I2C own address 1 register (I2C_OAR1) . . . . . . . . . . . . . . . . . . . . . . . 579
22.7.4 I2C own address 2 register (I2C_OAR2) . . . . . . . . . . . . . . . . . . . . . . . 580
22.7.5 I2C timing register (I2C_TIMINGR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 581
22.7.6 I2C timeout register (I2C_TIMEOUTR) . . . . . . . . . . . . . . . . . . . . . . . . 582
22.7.7 I2C interrupt and status register (I2C_ISR) . . . . . . . . . . . . . . . . . . . . . 583
22.7.8 I2C interrupt clear register (I2C_ICR) . . . . . . . . . . . . . . . . . . . . . . . . . 585
22.7.9 I2C PEC register (I2C_PECR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 586
22.7.10 I2C receive data register (I2C_RXDR) . . . . . . . . . . . . . . . . . . . . . . . . 587
22.7.11 I2C transmit data register (I2C_TXDR) . . . . . . . . . . . . . . . . . . . . . . . . 587
22.7.12 I2C register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 588

23 Universal synchronous/asynchronous receiver

transmitter (USART/UART) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 590
23.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 590
23.2 USART main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 590
23.3 USART implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 592
23.4 USART functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 593
23.4.1 USART character description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 594
23.4.2 USART transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 595
23.4.3 USART receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 598

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23.4.4 USART baud rate generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 604

23.4.5 Tolerance of the USART receiver to clock deviation . . . . . . . . . . . . . . 606
23.4.6 USART auto baud rate detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 607
23.4.7 Multiprocessor communication using USART . . . . . . . . . . . . . . . . . . . 607
23.4.8 USART parity control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 610
23.4.9 USART synchronous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 610
23.4.10 USART Single-wire Half-duplex communication . . . . . . . . . . . . . . . . . 613
23.4.11 USART continuous communication in DMA mode . . . . . . . . . . . . . . . . 613
23.4.12 RS232 hardware flow control and RS485 driver enable
using USART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 616
23.5 USART in low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 618
23.6 USART interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 619
23.7 USART registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 620
23.7.1 USART control register 1 (USART_CR1) . . . . . . . . . . . . . . . . . . . . . . 620
23.7.2 USART control register 2 (USART_CR2) . . . . . . . . . . . . . . . . . . . . . . 623
23.7.3 USART control register 3 (USART_CR3) . . . . . . . . . . . . . . . . . . . . . . 626
23.7.4 USART baud rate register (USART_BRR) . . . . . . . . . . . . . . . . . . . . . 628
23.7.5 USART receiver timeout register (USART_RTOR) . . . . . . . . . . . . . . . 628
23.7.6 USART request register (USART_RQR) . . . . . . . . . . . . . . . . . . . . . . . 629
23.7.7 USART interrupt and status register (USART_ISR) . . . . . . . . . . . . . . 630
23.7.8 USART interrupt flag clear register (USART_ICR) . . . . . . . . . . . . . . . 633
23.7.9 USART receive data register (USART_RDR) . . . . . . . . . . . . . . . . . . . 634
23.7.10 USART transmit data register (USART_TDR) . . . . . . . . . . . . . . . . . . . 635
23.7.11 USART register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 635

24 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 637

24.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 637
24.2 SPI main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 637
24.3 SPI implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 638
24.4 SPI functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 638
24.4.1 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 638
24.4.2 Communications between one master and one slave . . . . . . . . . . . . . 639
24.4.3 Standard multislave communication . . . . . . . . . . . . . . . . . . . . . . . . . . 642
24.4.4 Multimaster communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 642
24.4.5 Slave select (NSS) pin management . . . . . . . . . . . . . . . . . . . . . . . . . . 643
24.4.6 Communication formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 644
24.4.7 Configuration of SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 646

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24.4.8 Procedure for enabling SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 647

24.4.9 Data transmission and reception procedures . . . . . . . . . . . . . . . . . . . 647
24.4.10 SPI status flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 657
24.4.11 SPI error flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 658
24.4.12 NSS pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 659
24.4.13 TI mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 659
24.4.14 CRC calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 660
24.5 SPI interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 662
24.6 SPI registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 663
24.6.1 SPI control register 1 (SPIx_CR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 663
24.6.2 SPI control register 2 (SPIx_CR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 665
24.6.3 SPI status register (SPIx_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 667
24.6.4 SPI data register (SPIx_DR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 668
24.6.5 SPI CRC polynomial register (SPIx_CRCPR) . . . . . . . . . . . . . . . . . . . 669
24.6.6 SPI Rx CRC register (SPIx_RXCRCR) . . . . . . . . . . . . . . . . . . . . . . . . 669
24.6.7 SPI Tx CRC register (SPIx_TXCRCR) . . . . . . . . . . . . . . . . . . . . . . . . 669
24.6.8 SPI register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 671

25 Universal serial bus full-speed device interface (USB) . . . . . . . . . . . 672

25.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 672
25.2 USB main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 672
25.3 USB implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 672
25.4 USB functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 673
25.4.1 Description of USB blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 674
25.5 Programming considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 675
25.5.1 Generic USB device programming . . . . . . . . . . . . . . . . . . . . . . . . . . . 675
25.5.2 System and power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 676
25.5.3 Double-buffered endpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 681
25.5.4 Isochronous transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 683
25.5.5 Suspend/Resume events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 684
25.6 USB and USB SRAM registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 687
25.6.1 Common registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 687
25.6.2 Buffer descriptor table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 700
25.6.3 USB register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 703

26 Debug support (DBG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 705

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26.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 705

26.2 Reference Arm documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 706
26.3 Pinout and debug port pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 706
26.3.1 SWD port pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 707
26.3.2 SW-DP pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 707
26.3.3 Internal pull-up and pull-down on SWD pins . . . . . . . . . . . . . . . . . . . . 707
26.4 ID codes and locking mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 707
26.4.1 MCU device ID code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 708
26.5 SWD port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 708
26.5.1 SWD protocol introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 708
26.5.2 SWD protocol sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 709
26.5.3 SW-DP state machine (reset, idle states, ID code) . . . . . . . . . . . . . . . 710
26.5.4 DP and AP read/write accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 710
26.5.5 SW-DP registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 711
26.5.6 SW-AP registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 712
26.6 Core debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 712
26.7 BPU (Break Point Unit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 713
26.7.1 BPU functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 713
26.8 DWT (Data Watchpoint) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 713
26.8.1 DWT functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 713
26.8.2 DWT Program Counter Sample Register . . . . . . . . . . . . . . . . . . . . . . . 713
26.9 MCU debug component (DBGMCU) . . . . . . . . . . . . . . . . . . . . . . . . . . . 713
26.9.1 Debug support for low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . 714
26.9.2 Debug support for timers, watchdog and I2C . . . . . . . . . . . . . . . . . . . . 714
26.9.3 Debug MCU configuration register (DBGMCU_CR) . . . . . . . . . . . . . . 715
26.9.4 Debug MCU APB1 freeze register (DBGMCU_APB1_FZ) . . . . . . . . . 716
26.9.5 Debug MCU APB2 freeze register (DBGMCU_APB2_FZ) . . . . . . . . . 718
26.9.6 DBG register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 718

27 Device electronic signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 720

27.1 Flash memory size data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 720

Appendix A Code examples. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 721

A.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 721
A.2 FLASH operation code examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 721
A.2.1 Flash memory unlocking sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . 721

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A.2.2 Main flash memory programming sequence. . . . . . . . . . . . . . . . . . . . . 721

A.2.3 Page erase sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 722
A.2.4 Mass erase sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 723
A.2.5 Option byte unlocking sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 723
A.2.6 Option byte programming sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . 724
A.2.7 Option byte erasing sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 724
A.3 Clock controller code examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 725
A.3.1 HSE start sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 725
A.3.2 PLL configuration modification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 726
A.3.3 MCO selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 726
A.3.4 Clock measurement configuration with TIM14 . . . . . . . . . . . . . . . . . . . 727
A.4 GPIO code examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 728
A.4.1 Lock sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 728
A.4.2 Alternate function selection sequence . . . . . . . . . . . . . . . . . . . . . . . . . 728
A.4.3 Analog GPIO configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 729
A.5 DMA code examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 729
A.5.1 DMA channel configuration sequence . . . . . . . . . . . . . . . . . . . . . . . . . 729
A.6 Interrupts and event code examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . 730
A.6.1 NVIC initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 730
A.6.2 External interrupt selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 730
A.7 ADC code examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 731
A.7.1 ADC calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 731
A.7.2 ADC enable sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 731
A.7.3 ADC disable sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 732
A.7.4 ADC clock selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 732
A.7.5 Single conversion sequence - software trigger. . . . . . . . . . . . . . . . . . . 733
A.7.6 Continuous conversion sequence - software trigger. . . . . . . . . . . . . . . 733
A.7.7 Single conversion sequence - hardware trigger . . . . . . . . . . . . . . . . . . 734
A.7.8 Continuous conversion sequence - hardware trigger . . . . . . . . . . . . . . 734
A.7.9 DMA one shot mode sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 735
A.7.10 DMA circular mode sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 735
A.7.11 Wait mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 735
A.7.12 Auto Off and no wait mode sequence. . . . . . . . . . . . . . . . . . . . . . . . . . 736
A.7.13 Auto Off and wait mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . 736
A.7.14 Analog watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 736
A.7.15 Temperature configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 737

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A.7.16 Temperature computation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 737

A.8 Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 738
A.8.1 Upcounter on TI2 rising edge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 738
A.8.2 Up counter on each 2 ETR rising edges. . . . . . . . . . . . . . . . . . . . . . . . 739
A.8.3 Input capture configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 739
A.8.4 Input capture data management. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 740
A.8.5 PWM input configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 741
A.8.6 PWM input with DMA configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 741
A.8.7 Output compare configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 742
A.8.8 Edge-aligned PWM configuration example. . . . . . . . . . . . . . . . . . . . . . 742
A.8.9 Center-aligned PWM configuration example . . . . . . . . . . . . . . . . . . . . 743
A.8.10 ETR configuration to clear OCxREF. . . . . . . . . . . . . . . . . . . . . . . . . . . 744
A.8.11 Encoder interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 744
A.8.12 Reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 745
A.8.13 Gated mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 745
A.8.14 Trigger mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 746
A.8.15 External clock mode 2 + trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . 746
A.8.16 One-Pulse mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 747
A.8.17 Timer prescaling another timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 747
A.8.18 Timer enabling another timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 748
A.8.19 Master and slave synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . 749
A.8.20 Two timers synchronized by an external trigger . . . . . . . . . . . . . . . . . . 750
A.8.21 DMA burst feature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 751
A.9 IRTIM code examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 752
A.9.1 TIM16 and TIM17 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 752
A.9.2 IRQHandler for IRTIM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 753
A.10 DBG code examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 754
A.10.1 DBG read device ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 754
A.10.2 DBG debug in Low-power mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 754
A.11 I2C code examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 754
A.11.1 I2C configured in master mode to receive . . . . . . . . . . . . . . . . . . . . . . 754
A.11.2 I2C configured in master mode to transmit . . . . . . . . . . . . . . . . . . . . . . 754
A.11.3 I2C configured in slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 755
A.11.4 I2C master transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 755
A.11.5 I2C master receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 755
A.11.6 I2C slave transmitter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 756
A.11.7 I2C slave receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 756

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A.11.8 I2C configured in master mode to transmit with DMA. . . . . . . . . . . . . . 756

A.11.9 I2C configured in slave mode to receive with DMA . . . . . . . . . . . . . . . 757
A.12 IWDG code examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 757
A.12.1 IWDG configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 757
A.12.2 IWDG configuration with window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 758
A.13 RTC code examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 758
A.13.1 RTC calendar configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 758
A.13.2 RTC alarm configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 759
A.13.3 RTC WUT configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 759
A.13.4 RTC read calendar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 759
A.13.5 RTC calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 760
A.13.6 RTC tamper and time stamp configuration . . . . . . . . . . . . . . . . . . . . . . 760
A.13.7 RTC tamper and time stamp. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 761
A.13.8 RTC clock output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 761
A.14 SPI code examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 761
A.14.1 SPI master configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 761
A.14.2 SPI slave configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 762
A.14.3 SPI full duplex communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 762
A.14.4 SPI interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 762
A.14.5 SPI master configuration with DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . 762
A.14.6 SPI slave configuration with DMA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 763
A.15 USART code examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 763
A.15.1 USART transmitter configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 763
A.15.2 USART transmit byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 763
A.15.3 USART transfer complete . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 763
A.15.4 USART receiver configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 764
A.15.5 USART receive byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 764
A.15.6 USART synchronous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 764
A.15.7 USART DMA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 765
A.15.8 USART hardware flow control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 765
A.16 WWDG code examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 765
A.16.1 WWDG configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 765

Important security notice . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 766

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 767

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List of tables RM0360

List of tables

Table 1. STM32F0x0 memory boundary addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Table 2. STM32F0x0 peripheral register boundary addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 3. Boot modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 4. Flash memory organization (STM32F030x4, STM32F030x6, STM32F070x6 and
STM32F030x8 devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 5. Flash memory organization (STM32F070xB, STM32F030xC devices) . . . . . . . . . . . . . . . 48
Table 6. Flash memory read protection status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Table 7. Access status versus protection level and execution modes . . . . . . . . . . . . . . . . . . . . . . . 57
Table 8. Flash interrupt request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Table 9. Flash interface - Register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Table 10. Option byte format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Table 11. Option byte organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Table 12. Option byte map and ST production values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Table 13. CRC internal input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Table 14. CRC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Table 15. Low-power mode summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Table 16. Sleep-now . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Table 17. Sleep-on-exit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Table 18. Stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Table 19. Standby mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Table 20. PWR register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Table 21. RCC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Table 22. Port bit configuration table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Table 23. GPIO register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
Table 24. SYSCFG register map and reset values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Table 25. DMA implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
Table 26. DMA requests for each channel
on STM32F030x4/x6/x8 and STM32F070x6/xB devices . . . . . . . . . . . . . . . . . . . . . . . . . 151
Table 27. DMA requests for each channel on STM32F030xC devices . . . . . . . . . . . . . . . . . . . . . . 152
Table 28. Programmable data width and endian behavior (when PINC = MINC = 1) . . . . . . . . . . . 159
Table 29. DMA interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
Table 30. DMA register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
Table 31. Vector table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
Table 32. External interrupt/event controller register map and reset values. . . . . . . . . . . . . . . . . . . 181
Table 33. ADC input/output pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
Table 34. ADC internal input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
Table 35. External triggers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
Table 36. Latency between trigger and start of conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
Table 37. Configuring the trigger polarity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
Table 38. tSAR timings depending on resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
Table 39. Analog watchdog comparison. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
Table 40. Analog watchdog channel selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
Table 41. ADC interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
Table 42. ADC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
Table 43. Counting direction versus encoder signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264
Table 44. TIMx Internal trigger connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277
Table 45. Output control bits for complementary OCx and OCxN channels with
break feature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290

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Table 46. TIM1 register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299

Table 47. Counting direction versus encoder signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331
Table 48. TIM3 internal trigger connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348
Table 49. Output control bit for standard OCx channels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 358
Table 50. TIM3 register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 365
Table 51. TIM6/TIM7 register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 379
Table 52. Output control bit for standard OCx channels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397
Table 53. TIM14 register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 399
Table 54. TIMx Internal trigger connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 433
Table 55. Output control bits for complementary OCx and OCxN channels with break feature . . . . 443
Table 56. TIM15 register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 449
Table 57. Output control bits for complementary OCx and OCxN channels with break feature . . . . 460
Table 58. TIM16/TIM17 register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 466
Table 59. IWDG register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 477
Table 60. WWDG register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 483
Table 61. STM32F0x0 RTC implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 485
Table 62. RTC pin PC13 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 488
Table 63. LSE pin PC14 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 489
Table 64. LSE pin PC15 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 489
Table 65. Effect of low-power modes on RTC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 501
Table 66. Interrupt control bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 501
Table 67. RTC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 521
Table 68. STM32F0x0 I2C implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 525
Table 69. I2C input/output pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 527
Table 70. I2C internal input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 527
Table 71. Comparison of analog vs. digital filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 529
Table 72. I2C-SMBus specification data setup and hold times . . . . . . . . . . . . . . . . . . . . . . . . . . . . 532
Table 73. I2C configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 536
Table 74. I2C-SMBus specification clock timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 547
Table 75. Examples of timing settings for fI2CCLK = 8 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 557
Table 76. Examples of timing settings for fI2CCLK = 16 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 557
Table 77. Examples of timing settings for fI2CCLK = 48 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 558
Table 78. SMBus timeout specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 560
Table 79. SMBus with PEC configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 561
Table 80. Examples of TIMEOUTA settings (max tTIMEOUT = 25 ms) . . . . . . . . . . . . . . . . . . . . . . . 563
Table 81. Examples of TIMEOUTB settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 563
Table 82. Examples of TIMEOUTA settings (max tIDLE = 50 µs) . . . . . . . . . . . . . . . . . . . . . . . . . . . 563
Table 83. Effect of low-power modes on the I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 573
Table 84. I2C interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 574
Table 85. I2C register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 588
Table 86. STM32F0x0 USART features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 592
Table 87. Noise detection from sampled data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 603
Table 88. Error calculation for programmed baud rates at fCK = 48 MHz in both cases of
oversampling by 16 or by 8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 605
Table 89. Tolerance of the USART receiver when BRR [3:0] = 0000. . . . . . . . . . . . . . . . . . . . . . . . 606
Table 90. Tolerance of the USART receiver when BRR [3:0] is different from 0000 . . . . . . . . . . . . 606
Table 91. Frame formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 610
Table 92. Effect of low-power modes on the USART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 618
Table 93. USART interrupt requests. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 619
Table 94. USART register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 635
Table 95. STM32F0x0 SPI implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 638
Table 96. SPI interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 662

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Table 97. SPI register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 671

Table 98. STM32F0x0 USB implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 672
Table 99. Double-buffering buffer flag definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 682
Table 100. Bulk double-buffering memory buffers usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 682
Table 101. Isochronous memory buffers usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 684
Table 102. Resume event detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 685
Table 103. Reception status encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 698
Table 104. Endpoint type encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 698
Table 105. Endpoint kind meaning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 698
Table 106. Transmission status encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 699
Table 107. Definition of allocated buffer memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 702
Table 108. USB register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 703
Table 109. SW debug port pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 707
Table 110. DEV_ID and REV_ID field values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 708
Table 111. Packet request (8-bits) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 709
Table 112. ACK response (3 bits). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 709
Table 113. DATA transfer (33 bits) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 710
Table 114. SW-DP registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 711
Table 115. 32-bit debug port registers addressed through the shifted value A[3:2] . . . . . . . . . . . . . . 712
Table 116. Core debug registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 712
Table 117. DBG register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 719
Table 118. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 767

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List of figures

Figure 1. System architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Figure 2. Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 3. Programming procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Figure 4. Flash memory Page erase procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Figure 5. Flash memory mass erase procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Figure 6. CRC calculation unit block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Figure 7. Power supply overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Figure 8. Power on reset/power down reset waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Figure 9. Simplified diagram of the reset circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Figure 10. Clock tree (STM32F030x4, STM32F030x6 and STM32F030x8 devices) . . . . . . . . . . . . . 91
Figure 11. Clock tree (STM32F070x6, STM32F070xB and STM32F030xC). . . . . . . . . . . . . . . . . . . . 92
Figure 12. HSE/ LSE clock sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Figure 13. Frequency measurement with TIM14 in capture mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Figure 14. Basic structure of an I/O port bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Figure 15. Input floating / pull up / pull down configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Figure 16. Output configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Figure 17. Alternate function configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Figure 18. High impedance-analog configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Figure 19. DMA request mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Figure 20. DMA block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
Figure 21. Extended interrupts and events controller (EXTI) block diagram . . . . . . . . . . . . . . . . . . . 174
Figure 22. External interrupt/event GPIO mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
Figure 23. ADC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
Figure 24. ADC calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
Figure 25. Enabling/disabling the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
Figure 26. ADC clock scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
Figure 27. Analog to digital conversion time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
Figure 28. ADC conversion timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
Figure 29. Stopping an ongoing conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
Figure 30. Single conversions of a sequence, software trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
Figure 31. Continuous conversion of a sequence, software trigger . . . . . . . . . . . . . . . . . . . . . . . . . . 196
Figure 32. Single conversions of a sequence, hardware trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
Figure 33. Continuous conversions of a sequence, hardware trigger . . . . . . . . . . . . . . . . . . . . . . . . 197
Figure 34. Data alignment and resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
Figure 35. Example of overrun (OVR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
Figure 36. Wait mode conversion (continuous mode, software trigger). . . . . . . . . . . . . . . . . . . . . . . 201
Figure 37. Behavior with WAIT = 0, AUTOFF = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
Figure 38. Behavior with WAIT = 1, AUTOFF = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
Figure 39. Analog watchdog guarded area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
Figure 40. ADC_AWD1_OUT signal generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
Figure 41. ADC_AWD1_OUT signal generation (AWD flag not cleared by software) . . . . . . . . . . . . 206
Figure 42. ADC1_AWD_OUT signal generation (on a single channel) . . . . . . . . . . . . . . . . . . . . . . . 206
Figure 43. Analog watchdog threshold update . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
Figure 44. Temperature sensor and VREFINT channel block diagram . . . . . . . . . . . . . . . . . . . . . . 208
Figure 45. Advanced-control timer block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
Figure 46. Counter timing diagram with prescaler division change from 1 to 2 . . . . . . . . . . . . . . . . . 228
Figure 47. Counter timing diagram with prescaler division change from 1 to 4 . . . . . . . . . . . . . . . . . 228
Figure 48. Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230

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Figure 49. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230

Figure 50. Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
Figure 51. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
Figure 52. Counter timing diagram, update event when ARPE=0
(TIMx_ARR not preloaded) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232
Figure 53. Counter timing diagram, update event when ARPE=1
(TIMx_ARR preloaded) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232
Figure 54. Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
Figure 55. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
Figure 56. Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
Figure 57. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
Figure 58. Counter timing diagram, update event when repetition counter is not used . . . . . . . . . . . 235
Figure 59. Counter timing diagram, internal clock divided by 1, TIMx_ARR = 0x6 . . . . . . . . . . . . . . 236
Figure 60. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
Figure 61. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 . . . . . . . . . . . . . . 237
Figure 62. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
Figure 63. Counter timing diagram, update event with ARPE=1 (counter underflow) . . . . . . . . . . . . 238
Figure 64. Counter timing diagram, Update event with ARPE=1 (counter overflow) . . . . . . . . . . . . . 239
Figure 65. Update rate examples depending on mode and TIMx_RCR register settings . . . . . . . . . 240
Figure 66. Control circuit in normal mode, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . 241
Figure 67. TI2 external clock connection example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242
Figure 68. Control circuit in external clock mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
Figure 69. External trigger input block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
Figure 70. Control circuit in external clock mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244
Figure 71. Capture/compare channel (example: channel 1 input stage) . . . . . . . . . . . . . . . . . . . . . . 245
Figure 72. Capture/compare channel 1 main circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245
Figure 73. Output stage of capture/compare channel (channel 1 to 3) . . . . . . . . . . . . . . . . . . . . . . . 246
Figure 74. Output stage of capture/compare channel (channel 4). . . . . . . . . . . . . . . . . . . . . . . . . . . 246
Figure 75. PWM input mode timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
Figure 76. Output compare mode, toggle on OC1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
Figure 77. Edge-aligned PWM waveforms (ARR=8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252
Figure 78. Center-aligned PWM waveforms (ARR=8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
Figure 79. Complementary output with dead-time insertion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
Figure 80. Dead-time waveforms with delay greater than the negative pulse. . . . . . . . . . . . . . . . . . 255
Figure 81. Dead-time waveforms with delay greater than the positive pulse. . . . . . . . . . . . . . . . . . . 255
Figure 82. Output behavior in response to a break . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258
Figure 83. Clearing TIMx OCxREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260
Figure 84. 6-step generation, COM example (OSSR=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261
Figure 85. Example of one pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262
Figure 86. Example of counter operation in encoder interface mode. . . . . . . . . . . . . . . . . . . . . . . . . 265
Figure 87. Example of encoder interface mode with TI1FP1 polarity inverted. . . . . . . . . . . . . . . . . . 265
Figure 88. Example of hall sensor interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267
Figure 89. Control circuit in reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268
Figure 90. Control circuit in gated mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269
Figure 91. Control circuit in trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270
Figure 92. Control circuit in external clock mode 2 + trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . . 271
Figure 93. General-purpose timer block diagram (TIM3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302
Figure 94. Counter timing diagram with prescaler division change from 1 to 2 . . . . . . . . . . . . . . . . . 303
Figure 95. Counter timing diagram with prescaler division change from 1 to 4 . . . . . . . . . . . . . . . . . 304
Figure 96. Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305
Figure 97. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305
Figure 98. Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306

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Figure 99. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306

Figure 100. Counter timing diagram, Update event when ARPE=0
(TIMx_ARR not preloaded) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307
Figure 101. Counter timing diagram, Update event when ARPE=1
(TIMx_ARR preloaded) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307
Figure 102. Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308
Figure 103. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309
Figure 104. Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309
Figure 105. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310
Figure 106. Counter timing diagram, Update event when repetition counter is not used . . . . . . . . . . 310
Figure 107. Counter timing diagram, internal clock divided by 1, TIMx_ARR=0x6 . . . . . . . . . . . . . . . 312
Figure 108. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312
Figure 109. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 . . . . . . . . . . . . . . 313
Figure 110. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313
Figure 111. Counter timing diagram, Update event with ARPE=1 (counter underflow). . . . . . . . . . . . 314
Figure 112. Counter timing diagram, Update event with ARPE=1 (counter overflow) . . . . . . . . . . . . . 314
Figure 113. Control circuit in normal mode, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . 315
Figure 114. TI2 external clock connection example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316
Figure 115. Control circuit in external clock mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317
Figure 116. External trigger input block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317
Figure 117. Control circuit in external clock mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318
Figure 118. Capture/compare channel (example: channel 1 input stage) . . . . . . . . . . . . . . . . . . . . . . 319
Figure 119. Capture/compare channel 1 main circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319
Figure 120. Output stage of capture/compare channel (channel 1). . . . . . . . . . . . . . . . . . . . . . . . . . . 320
Figure 121. PWM input mode timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322
Figure 122. Output compare mode, toggle on OC1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324
Figure 123. Edge-aligned PWM waveforms (ARR=8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325
Figure 124. Center-aligned PWM waveforms (ARR=8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327
Figure 125. Example of one-pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328
Figure 126. Clearing TIMx OCxREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330
Figure 127. Example of counter operation in encoder interface mode . . . . . . . . . . . . . . . . . . . . . . . . 332
Figure 128. Example of encoder interface mode with TI1FP1 polarity inverted . . . . . . . . . . . . . . . . . 332
Figure 129. Control circuit in reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333
Figure 130. Control circuit in gated mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 334
Figure 131. Control circuit in trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335
Figure 132. Control circuit in external clock mode 2 + trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . . 336
Figure 133. Master/Slave timer example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337
Figure 134. Gating timer 3 with OC1REF of timer 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338
Figure 135. Gating timer 3 with Enable of timer 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339
Figure 136. Triggering timer 3 with update of timer 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 340
Figure 137. Triggering timer 3 with Enable of timer 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341
Figure 138. Triggering timer 1 and 3 with timer 1 TI1 input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342
Figure 139. Basic timer block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367
Figure 140. Counter timing diagram with prescaler division change from 1 to 2 . . . . . . . . . . . . . . . . . 369
Figure 141. Counter timing diagram with prescaler division change from 1 to 4 . . . . . . . . . . . . . . . . . 369
Figure 142. Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 370
Figure 143. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 371
Figure 144. Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 371
Figure 145. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 372
Figure 146. Counter timing diagram, update event when ARPE = 0
(TIMx_ARR not preloaded) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 372
Figure 147. Counter timing diagram, update event when ARPE=1

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(TIMx_ARR preloaded) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373

Figure 148. Control circuit in normal mode, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . 374
Figure 149. General-purpose timer block diagram (TIM14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381
Figure 150. Counter timing diagram with prescaler division change from 1 to 2 . . . . . . . . . . . . . . . . . 382
Figure 151. Counter timing diagram with prescaler division change from 1 to 4 . . . . . . . . . . . . . . . . . 382
Figure 152. Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383
Figure 153. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383
Figure 154. Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 384
Figure 155. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 384
Figure 156. Counter timing diagram, update event when ARPE=0
(TIMx_ARR not preloaded) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 384
Figure 157. Counter timing diagram, update event when ARPE=1
(TIMx_ARR preloaded) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 385
Figure 158. Control circuit in normal mode, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . 385
Figure 159. Capture/compare channel (example: channel 1 input stage) . . . . . . . . . . . . . . . . . . . . . . 386
Figure 160. Capture/compare channel 1 main circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 386
Figure 161. Output stage of capture/compare channel (channel 1). . . . . . . . . . . . . . . . . . . . . . . . . . . 387
Figure 162. Output compare mode, toggle on OC1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 390
Figure 163. Edge-aligned PWM waveforms (ARR=8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 391
Figure 164. TIM15 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 402
Figure 165. TIM16 and TIM17 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 404
Figure 166. Counter timing diagram with prescaler division change from 1 to 2 . . . . . . . . . . . . . . . . . 405
Figure 167. Counter timing diagram with prescaler division change from 1 to 4 . . . . . . . . . . . . . . . . . 406
Figure 168. Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 407
Figure 169. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 408
Figure 170. Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 408
Figure 171. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 409
Figure 172. Counter timing diagram, update event when ARPE=0
(TIMx_ARR not preloaded) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 409
Figure 173. Counter timing diagram, update event when ARPE=1
(TIMx_ARR preloaded) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 410
Figure 174. Update rate examples depending on mode and TIMx_RCR register settings . . . . . . . . . 411
Figure 175. Control circuit in normal mode, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . 412
Figure 176. TI2 external clock connection example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 412
Figure 177. Control circuit in external clock mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 413
Figure 178. Capture/compare channel (example: channel 1 input stage) . . . . . . . . . . . . . . . . . . . . . . 414
Figure 179. Capture/compare channel 1 main circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 414
Figure 180. Output stage of capture/compare channel (channel 1). . . . . . . . . . . . . . . . . . . . . . . . . . . 415
Figure 181. Output stage of capture/compare channel (channel 2 for TIM15) . . . . . . . . . . . . . . . . . . 415
Figure 182. PWM input mode timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 417
Figure 183. Output compare mode, toggle on OC1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 419
Figure 184. Edge-aligned PWM waveforms (ARR=8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 420
Figure 185. Complementary output with dead-time insertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 421
Figure 186. Dead-time waveforms with delay greater than the negative pulse . . . . . . . . . . . . . . . . . . 421
Figure 187. Dead-time waveforms with delay greater than the positive pulse. . . . . . . . . . . . . . . . . . . 421
Figure 188. Output behavior in response to a break . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 424
Figure 189. Example of One-pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 425
Figure 190. Control circuit in reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 427
Figure 191. Control circuit in gated mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 428
Figure 192. Control circuit in trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 429
Figure 193. IRTIM internal hardware connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 468
Figure 194. Independent watchdog block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 469

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Figure 195. Watchdog block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 479

Figure 196. Window watchdog timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 480
Figure 197. RTC block diagram in STM32F030x4/6,
STM32F070x6 and STM32F030x8 devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 486
Figure 198. RTC block diagram for STM32F070xB
and STM32F030xC devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 487
Figure 199. I2C block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 526
Figure 200. I2C2 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 527
Figure 201. I2C bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 529
Figure 202. Setup and hold timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 530
Figure 203. I2C initialization flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 533
Figure 204. Data reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 534
Figure 205. Data transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 535
Figure 206. Slave initialization flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 538
Figure 207. Transfer sequence flow for I2C slave transmitter, NOSTRETCH = 0. . . . . . . . . . . . . . . . 540
Figure 208. Transfer sequence flow for I2C slave transmitter, NOSTRETCH = 1. . . . . . . . . . . . . . . . 541
Figure 209. Transfer bus diagrams for I2C slave transmitter (mandatory events only) . . . . . . . . . . . . 542
Figure 210. Transfer sequence flow for slave receiver with NOSTRETCH = 0 . . . . . . . . . . . . . . . . . 543
Figure 211. Transfer sequence flow for slave receiver with NOSTRETCH = 1 . . . . . . . . . . . . . . . . . 544
Figure 212. Transfer bus diagrams for I2C slave receiver
(mandatory events only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 544
Figure 213. Master clock generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 546
Figure 214. Master initialization flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 548
Figure 215. 10-bit address read access with HEAD10R = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 548
Figure 216. 10-bit address read access with HEAD10R = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 549
Figure 217. Transfer sequence flow for I2C master transmitter for N ≤ 255 bytes . . . . . . . . . . . . . . . 550
Figure 218. Transfer sequence flow for I2C master transmitter for N > 255 bytes . . . . . . . . . . . . . . . 551
Figure 219. Transfer bus diagrams for I2C master transmitter
(mandatory events only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 552
Figure 220. Transfer sequence flow for I2C master receiver for N ≤ 255 bytes . . . . . . . . . . . . . . . . . 554
Figure 221. Transfer sequence flow for I2C master receiver for N > 255 bytes . . . . . . . . . . . . . . . . . 555
Figure 222. Transfer bus diagrams for I2C master receiver
(mandatory events only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 556
Figure 223. Timeout intervals for tLOW:SEXT, tLOW:MEXT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 560
Figure 224. Transfer sequence flow for SMBus slave transmitter N bytes + PEC. . . . . . . . . . . . . . . . 564
Figure 225. Transfer bus diagrams for SMBus slave transmitter (SBC = 1) . . . . . . . . . . . . . . . . . . . . 564
Figure 226. Transfer sequence flow for SMBus slave receiver N bytes + PEC. . . . . . . . . . . . . . . . . . 566
Figure 227. Bus transfer diagrams for SMBus slave receiver (SBC = 1). . . . . . . . . . . . . . . . . . . . . . . 567
Figure 228. Bus transfer diagrams for SMBus master transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . 568
Figure 229. Bus transfer diagrams for SMBus master receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 570
Figure 230. USART block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 594
Figure 231. Word length programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 595
Figure 232. Configurable stop bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 596
Figure 233. TC/TXE behavior when transmitting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 598
Figure 234. Start bit detection when oversampling by 16 or 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 599
Figure 235. Data sampling when oversampling by 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 602
Figure 236. Data sampling when oversampling by 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 603
Figure 237. Mute mode using Idle line detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 608
Figure 238. Mute mode using address mark detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 609
Figure 239. USART example of synchronous transmission. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 611
Figure 240. USART data clock timing diagram (M=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 612
Figure 241. USART data clock timing diagram (M=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 612

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Figure 242. RX data setup/hold time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 613

Figure 243. Transmission using DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 615
Figure 244. Reception using DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 616
Figure 245. Hardware flow control between 2 USARTs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 616
Figure 246. RS232 RTS flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 617
Figure 247. RS232 CTS flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 618
Figure 248. USART interrupt mapping diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 619
Figure 249. SPI block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 639
Figure 250. Full-duplex single master/ single slave application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 640
Figure 251. Half-duplex single master/ single slave application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 640
Figure 252. Simplex single master/single slave application (master in transmit-only/
slave in receive-only mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 641
Figure 253. Master and three independent slaves. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 642
Figure 254. Multimaster application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 643
Figure 255. Hardware/software slave select management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 644
Figure 256. Data clock timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 645
Figure 257. Data alignment when data length is not equal to 8-bit or 16-bit . . . . . . . . . . . . . . . . . . . . 646
Figure 258. Packing data in FIFO for transmission and reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . 650
Figure 259. Master full-duplex communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 653
Figure 260. Slave full-duplex communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 654
Figure 261. Master full-duplex communication with CRC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 655
Figure 262. Master full-duplex communication in packed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 656
Figure 263. NSSP pulse generation in Motorola SPI master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 659
Figure 264. TI mode transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 660
Figure 265. USB peripheral block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 673
Figure 266. Packet buffer areas with examples of buffer description table locations . . . . . . . . . . . . . 677
Figure 267. Block diagram of STM32F0x0 MCU and Arm® Cortex®-M0-level debug support . . . . . . 705

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1 Documentation conventions

1.1 General information

The STM32F0x0 devices have an Arm®(a) Arm® Cortex®-M0 core.

1.2 List of abbreviations for registers

The following abbreviations(b) are used in register descriptions:

read/write (rw) Software can read and write to this bit.

read-only (r) Software can only read this bit.
write-only (w) Software can only write to this bit. Reading this bit returns the reset value.
read/clear write0 (rc_w0) Software can read as well as clear this bit by writing 0. Writing 1 has no
effect on the bit value.
read/clear write1 (rc_w1) Software can read as well as clear this bit by writing 1. Writing 0 has no
effect on the bit value.
read/clear write (rc_w) Software can read as well as clear this bit by writing to the register. The
value written to this bit is not important.
read/clear by read (rc_r) Software can read this bit. Reading this bit automatically clears it to 0.
Writing this bit has no effect on the bit value.
read/set by read (rs_r) Software can read this bit. Reading this bit automatically sets it to 1.
Writing this bit has no effect on the bit value.
read/set (rs) Software can read as well as set this bit. Writing 0 has no effect on the bit
value.
read/write once (rwo) Software can only write once to this bit and can also read it at any time.
Only a reset can return the bit to its reset value.
toggle (t) The software can toggle this bit by writing 1. Writing 0 has no effect.
read-only write trigger (rt_w1) Software can read this bit. Writing 1 triggers an event but has no effect on
the bit value.
Reserved (Res.) Reserved bit, must be kept at reset value.

a. Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.
b. This is an exhaustive list of all abbreviations applicable to STMicroelectronics microcontrollers, some of
them may not be used in the current document.

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1.3 Glossary
This section gives a brief definition of acronyms and abbreviations used in this document:
• Word: data of 32-bit length.
• Half-word: data of 16-bit length.
• Byte: data of 8-bit length.
• SWD-DP (SWD DEBUG PORT): SWD-DP provides a 2-pin (clock and data) interface
based on the Serial Wire Debug (SWD) protocol. Please refer to the Arm® Cortex®-M0
technical reference manual.
• IAP (in-application programming): IAP is the ability to re-program the flash memory
of a microcontroller while the user program is running.
• ICP (in-circuit programming): ICP is the ability to program the flash memory of a
microcontroller using the JTAG protocol, the SWD protocol or the bootloader while the
device is mounted on the user application board.
• Option bytes: product configuration bits stored in the flash memory.
• OBL: option byte loader.
• AHB: advanced high-performance bus.
• APB: advanced peripheral bus.

1.4 Availability of peripherals

For availability of peripherals and their number across all sales types, refer to the particular
device datasheet.

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2 System and memory overview

2.1 System architecture

The main system consists of:
• Two masters:
– Arm® Cortex®-M0 core
– General-purpose DMA
• Four slaves:
– Internal SRAM
– Internal flash memory
– AHB1 with AHB to APB bridge, which connects all the APB peripherals
– AHB2 dedicated to GPIO ports
These are interconnected using a multilayer AHB bus architecture, as shown in Figure 1:

Figure 1. System architecture

FLITF
Flash memory
ARM® Flash interface
Cortex®-M0 System bus
core
SRAM
Bus matrix
DMA1 GPIO Ports
DMA bus AHB2 bus
channels 1 to 5 A,B,C,D,F
AHB to APB
AHB1 bus APB bus
bridge

SYSCFG,
Reset and ADC,
clock TIM1, TIM3,
controller CRC TIM6, TIM7,
(RCC) TIM14 to TIM17,
IWDG, WWDG,
RTC, PWR,
I2C1, I2C2,
USART1 to USART6,
SPI1, SPI2,
DBGMCU
DMA requests

MSv36431V1

System bus
This bus connects the system bus of the Arm® Cortex®-M0 core (peripherals bus) to a
BusMatrix which manages the arbitration between the core and the DMA.

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DMA bus
This bus connects the AHB master interface of the DMA to the BusMatrix which manages
the access of CPU and DMA to SRAM, flash memory and peripherals.

BusMatrix
The BusMatrix manages the access arbitration between the core system bus and the DMA
master bus. The arbitration uses a Round Robin algorithm. The BusMatrix is composed of
two masters (CPU, DMA) and four slaves (FLITF, SRAM, AHB1 with AHB to APB bridge
and AHB2).
AHB peripherals are connected on system bus through a BusMatrix to allow DMA access.

AHB to APB bridge (APB)

The AHB to APB bridge provides full synchronous connections between the AHB and the
APB bus.
Refer to Section 2.2.2: Memory map and register boundary addresses for the address
mapping of the peripherals connected to this bridge.
After each device reset, all peripheral clocks are disabled (except for the SRAM and flash).
Before using a peripheral you have to enable its clock in the RCC_AHBENR,
RCC_APB2ENR or RCC_APB1ENR register.
Note: When a 16- or 8-bit access is performed on an APB register, the access is transformed into
a 32-bit access: the bridge duplicates the 16- or 8-bit data to feed the 32-bit vector.

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2.2 Memory organization

2.2.1 Introduction
Program memory, data memory, registers and I/O ports are organized within the same linear
4-Gbyte address space.
The bytes are coded in memory in Little Endian format. The lowest numbered byte in a word
is considered the word’s least significant byte and the highest numbered byte the most
significant.
The addressable memory space is divided into eight main blocks, of 512 Mbytes each.

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2.2.2 Memory map and register boundary addresses

Figure 2. Memory map

0xFFFF FFFF
7 0x4800 17FF
AHB2
0xE010 0000
Cortex-M0 0x4800 0000
peripherals
0xE000 0000

0xC000 0000

0x4002 43FF
5 AHB1
0x4002 0000

0xA000 0000

0x4001 8000
4 0x1FFF FFFF
Option bytes APB
0x8000 0000 0x4001 0000

System memory

3 0x4000 8000

APB
0x6000 0000 0x4000 0000

Peripherals
0x4000 0000

1 Main
Flash memory
SRAM 0x0800 0000
0x2000 0000

CODE
0
Flash, system
memory or SRAM,
0x0000 0000 depending on
BOOT configuration
Reserved
0x0000 0000 MS33181V5

All the memory map areas not allocated to on-chip memories and peripherals are
considered “Reserved”. For the detailed mapping of available memory and register areas,
refer to the following table, which gives the boundary addresses of the available peripherals.

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Table 1. STM32F0x0 memory boundary addresses

Device Boundary address Size Memory Area Register description

0x2000 1000 - 0x3FFF FFFF ~512 MB Reserved -

0x2000 0000 - 0x2000 0FFF 4 KB SRAM Section 2.3 on page 42
0x1FFF FC00 - 0x1FFF FFFF 1 KB Reserved -
0x1FFF F800 - 0x1FFF FBFF 1 KB Option bytes Section 4 on page 66
0x1FFF EC00 - 0x1FFF F7FF 3 KB System memory -
STM32F030x4, 0x0800 8000 - 0x1FFF EBFF ~384 MB Reserved -
STM32F030x6
0x0800 0000 - 0x0800 7FFF 32 KB(1) Main flash memory Section 3 on page 46
0x0000 8000 - 0x07FF FFFF ~128 MB Reserved -
Main flash memory,
(1) system memory or SRAM
0x0000 0000 - 0x0000 7FFF 32 KB -
depending on BOOT
configuration
0x2000 1800 - 0x3FFF FFFF ~512 MB Reserved -
0x2000 0000 - 0x2000 17FF 6 KB SRAM Section 2.3 on page 42
0x1FFF FC00 - 0x1FFF FFFF 1 KB Reserved -
0x1FFF F800 - 0x1FFF FBFF 1 KB Option bytes Section 4 on page 66
0x1FFF C400 - 0x1FFF F7FF 13 KB System memory -
0x0801 8000- 0x1FFF C7FF ~384 MB Reserved -
STM32F070x6
0x0800 0000 - 0x0801 7FFF 32 KB Main flash memory Section 3 on page 46
0x0001 8000 - 0x07FF FFFF ~128 MB Reserved -
Main flash memory,
system memory or SRAM
0x0000 0000 - 0x0000 7FFF 32 KB -
depending on BOOT
configuration
0x2000 2000 - 0x3FFF FFFF ~512 MB Reserved -
0x2000 0000 - 0x2000 1FFF 8 KB SRAM Section 2.3 on page 42
0x1FFF FC00 - 0x1FFF FFFF 1 KB Reserved -
0x1FFF F800 - 0x1FFF FBFF 1 KB Option bytes Section 4 on page 66
0x1FFF EC00 - 0x1FFF F7FF 3 KB System memory -
0x0801 0000 - 0x1FFF EBFF ~384 MB Reserved -
STM32F030x8
0x0800 0000 - 0x0800 FFFF 64 KB Main flash memory Section 3 on page 46
0x0001 0000 - 0x07FF FFFF ~128 MB Reserved -
Main flash memory,
system memory or SRAM
0x0000 0000 - 0x0000 FFFF 64 KB -
depending on BOOT
configuration

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Table 1. STM32F0x0 memory boundary addresses (continued)

Device Boundary address Size Memory Area Register description

0x2000 4000 - 0x3FFF FFFF ~512 MB Reserved -

0x2000 0000 - 0x2000 3FFF 16 KB SRAM Section 2.3 on page 42
0x1FFF F800 - 0x1FFF FFFF 2 KB Option bytes Section 4 on page 66
0x1FFF C800 - 0x1FFF F7FF 12 KB System memory -
0x0802 0000 - 0x1FFF C7FF ~384 MB Reserved -
STM32F070xB 0x0800 0000 - 0x0801 FFFF 128 KB Main flash memory Section 3 on page 46
0x0002 0000 - 0x07FF FFFF ~128 MB Reserved -
Main flash memory,
system memory or SRAM
0x0000 0000 - 0x0001 FFFF 128 KB -
depending on BOOT
configuration
0x2000 8000 - 0x3FFF FFFF ~512 MB Reserved -
0x2000 0000 - 0x2000 7FFF 32 KB SRAM Section 2.3 on page 42
0x1FFF F800 - 0x1FFF FFFF 2 KB Option bytes Section 4 on page 66
0x1FFF D800 - 0x1FFF F7FF 8 KB System memory -
0x0804 0000 - 0x1FFF D7FF ~384 MB Reserved -
STM32F030xC 0x0800 0000 - 0x0803 FFFF 256 KB Main flash memory Section 3 on page 46
0x0004 0000 - 0x07FF FFFF ~128 MB Reserved -
Main flash memory,
system memory or SRAM
0x0000 0000 - 0x0003 FFFF 256 KB -
depending on BOOT
configuration
1. Limited to 16 KB on STM32F030x4 devices.

Table 2. STM32F0x0 peripheral register boundary addresses

Bus Boundary address Size Peripheral Peripheral register map

Cortex®-M0 internal
- 0xE000 0000 - 0xE00F FFFF 1MB -
peripherals
- 0x4800 1800 - 0x5FFF FFFF ~384 MB Reserved -
0x4800 1400 - 0x4800 17FF 1KB GPIOF Section 8.4.11 on page 139
0x4800 1000 - 0x4800 13FF 1KB Reserved -
0x4800 0C00 - 0x4800 0FFF 1KB GPIOD Section 8.4.11 on page 139
AHB2
0x4800 0800 - 0x4800 0BFF 1KB GPIOC Section 8.4.11 on page 139
0x4800 0400 - 0x4800 07FF 1KB GPIOB Section 8.4.11 on page 139
0x4800 0000 - 0x4800 03FF 1KB GPIOA Section 8.4.11 on page 139
- 0x4002 4400 - 0x47FF FFFF ~128 MB Reserved -

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Table 2. STM32F0x0 peripheral register boundary addresses (continued)

Bus Boundary address Size Peripheral Peripheral register map

0x4002 3400 - 0x4002 43FF 4 KB Reserved -

0x4002 3000 - 0x4002 33FF 1 KB CRC Section 5.4.5 on page 75
0x4002 2400 - 0x4002 2FFF 3 KB Reserved -
0x4002 2000 - 0x4002 23FF 1 KB FLASH interface Section 3.5.9 on page 65
AHB1
0x4002 1400 - 0x4002 1FFF 3 KB Reserved -
0x4002 1000 - 0x4002 13FF 1 KB RCC Section 7.4.15 on page 123
0x4002 0400 - 0x4002 0FFF 3 KB Reserved -
0x4002 0000 - 0x4002 03FF 1 KB DMA Section 10.6.8 on page 169
- 0x4001 8000 - 0x4001 FFFF 32 KB Reserved -
0x4001 5C00 - 0x4001 7FFF 9 KB Reserved -
0x4001 5800 - 0x4001 5BFF 1 KB DBGMCU -
0x4001 4C00 - 0x4001 57FF 3 KB Reserved -
0x4001 4800 - 0x4001 4BFF 1 KB TIM17 Section 17.6.17 on page 466
0x4001 4400 - 0x4001 47FF 1 KB TIM16 Section 17.6.17 on page 466
0x4001 4000 - 0x4001 43FF 1 KB TIM15 Section 17.5.19 on page 449
0x4001 3C00 - 0x4001 3FFF 1 KB Reserved -
0x4001 3800 - 0x4001 3BFF 1 KB USART1 Section 23.7.11 on page 635
0x4001 3400 - 0x4001 37FF 1 KB Reserved -
APB
0x4001 3000 - 0x4001 33FF 1 KB SPI1 Section 24.6.8 on page 671
0x4001 2C00 - 0x4001 2FFF 1 KB TIM1 Section 13.4.21 on page 299
0x4001 2800 - 0x4001 2BFF 1 KB Reserved -
0x4001 2400 - 0x4001 27FF 1 KB ADC Section 12.11 on page 223
0x4001 1800 - 0x4001 23FF 4 KB Reserved -
0x4001 1400 - 0x4001 17FF 1 KB USART6 Section 23.7.11 on page 635
0x4001 0800 - 0x4001 23FF 7 KB Reserved -
0x4001 0400 - 0x4001 07FF 1 KB EXTI Section 11.3.7 on page 181
0x4001 0000 - 0x4001 03FF 1 KB SYSCFG Section 9.1.7 on page 148
- 0x4000 8000 - 0x4000 FFFF 32 KB Reserved -

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Table 2. STM32F0x0 peripheral register boundary addresses (continued)

Bus Boundary address Size Peripheral Peripheral register map

0x4000 7400 - 0x4000 7FFF 3 KB Reserved -

0x4000 7000 - 0x4000 73FF 1 KB PWR Section 6.4.3 on page 87
0x4000 63FF - 0x4000 6FFF 3 KB Reserved -
0x4000 6000 - 0x4000 63FF 1 KB USB/SRAM Section 25.6.3 on page 703
0x4000 5C00 - 0x4000 5FFF 1 KB USB Section 25.6.3 on page 703
0x4000 5800 - 0x4000 5BFF 1 KB I2C2 Section 22.7.12 on page 588
0x4000 5400 - 0x4000 57FF 1 KB I2C1 Section 22.7.12 on page 588
0x4000 5000 - 0x4000 53FF 1 KB USART5 Section 23.7.11 on page 635
0x4000 4C00 - 0x4000 4FFF 1 KB USART4 Section 23.7.11 on page 635
0x4000 4800 - 0x4000 4BFF 1 KB USART3 Section 23.7.11 on page 635
0x4000 4400 - 0x4000 47FF 1 KB USART2 Section 23.7.11 on page 635
0x4000 3C00 - 0x4000 43FF 2 KB Reserved -
APB 0x4000 3800 - 0x4000 3BFF 1 KB SPI2 Section 24.6.8 on page 671
0x4000 3400 - 0x4000 37FF 1 KB Reserved -
0x4000 3000 - 0x4000 33FF 1 KB IWDG Section 19.4.6 on page 477
0x4000 2C00 - 0x4000 2FFF 1 KB WWDG Section 20.5.4 on page 483
0x4000 2800 - 0x4000 2BFF 1 KB RTC Section 21.7.17 on page 521
0x4000 2400 - 0x4000 27FF 1 KB Reserved -
0x4000 2000 - 0x4000 23FF 1 KB TIM14 Section 16.4.13 on page 399
0x4000 1800 - 0x4000 1FFF 2 KB Reserved -
0x4000 1400 - 0x4000 17FF 1 KB TIM7 Section 15.4.8 on page 379
0x4000 1000 - 0x4000 13FF 1 KB TIM6 Section 15.4.8 on page 379
0x4000 0800 - 0x4000 0FFF 2 KB Reserved -
0x4000 0400 - 0x4000 07FF 1 KB TIM3 Section 14.4.19 on page 365
0x4000 0000 - 0x4000 03FF 1 KB Reserved -

2.3 Embedded SRAM

STM32F030x4 and STM32F030x6 devices feature 4 Kbytes of SRAM. STM32F030x8
devices feature 8 Kbytes of SRAM. STM32F030xC devices feature 32 Kbytes of SRAM.
STM32F070x6 devices feature 6 Kbytes of SRAM. STM32F070xB devices feature
16 Kbytes of SRAM.
The SRAM can be accessed by bytes, half-words (16 bits) or full words (32 bits), at
maximum system clock frequency without wait state and thus by both CPU and DMA.
Parity check
The user can enable the parity check using the option bit RAM_PARITY_CHECK in the user
option byte (refer to Section 4: Option bytes).

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The data bus width is 36 bits because 4 bits are available for parity check (1 bit per byte) in
order to increase memory robustness, as required for instance by Class B or SIL norms.
The parity bits are computed and stored when writing into the SRAM. Then, they are
automatically checked when reading. If one bit fails, an NMI is generated. In addition, to get
the SRAM parity error at the same cycle time that it is occurring, a bus error is generated
(triggering a HardFault exception) together with the NMI. This avoids the use of corrupted
data by the application, but with the side effect of having both NMI and HardFault interrupts
generated. The same error can also be linked to the BRK_IN Break input of TIM1/15/16/17,
with the SRAM_PARITY_LOCK control bit in the SYSCFG configuration register 2
(SYSCFG_CFGR2). The SRAM Parity Error flag (SRAM_PEF) is available in the SYSCFG
configuration register 2 (SYSCFG_CFGR2).
Note: When enabling the RAM parity check, it is advised to initialize by software the whole RAM
memory at the beginning of the code, to avoid getting parity errors when reading non-
initialized locations.

2.4 Flash memory overview

The flash memory is composed of two distinct physical areas:
• The main flash memory block. It contains the application program and user data if
necessary.
• The information block. It is composed of two parts:
– option bytes for hardware and memory protection user configuration
– system memory which contains the proprietary boot loader code
(refer to Section 3: Embedded flash memory for more details.)
The flash interface implements instruction access and data access based on the AHB
protocol. It implements the prefetch buffer that speeds up CPU code execution. It also
implements the logic necessary to carry out the flash memory operations (Program/Erase)
controlled through the flash registers.

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2.5 Boot configuration

In the STM32F0x0, three different boot modes can be selected through the BOOT0 pin and
boot configuration bits nBOOT1 in the User option byte, as shown in the following table.

Table 3. Boot modes

Boot mode configuration
Mode
nBOOT1 bit BOOT0 pin

x 0 Main Flash memory is selected as boot area(1)

1 1 System memory is selected as boot area
0 1 Embedded SRAM is selected as boot area
1. For STM32F070x6 and STM32F030xC devices, see also Empty check description.

The boot mode configuration is latched on the 4th rising edge of SYSCLK after a reset. It is
up to the user to set boot mode configuration related to the required boot mode.
The boot mode configuration is also re-sampled when exiting from Standby mode.
Consequently they must be kept in the required Boot mode configuration in Standby mode.
After this startup delay has elapsed, the CPU fetches the top-of-stack value from address
0x0000 0000, then starts code execution from the boot memory at 0x0000 0004.
Depending on the selected boot mode, main flash memory, system memory or SRAM is
accessible as follows:
• Boot from main flash memory: the main flash memory is aliased in the boot memory
space (0x0000 0000), but still accessible from its original memory space
(0x0800 0000). In other words, the flash memory contents can be accessed starting
from address 0x0000 0000 or 0x0800 0000.
• Boot from system memory: the system memory is aliased in the boot memory space
(0x0000 0000), but still accessible from its original memory space(0x1FFF EC00 on
STM32F030x4, STM32F030x6 and STM32F030x8 devices, 0x1FFF C400 on
STM32F070x6 devices, 0x1FFF C800 on STM32F070xB and 0x1FFF D800 on
STM32F030xC devices).
• Boot from the embedded SRAM: the SRAM is aliased in the boot memory space
(0x0000 0000), but it is still accessible from its original memory space (0x2000 0000).

Empty check
On STM32F070x6 and STM32F030xC devices only, internal empty check flag is
implemented to allow easy programming of virgin devices by the boot loader. This flag is
used when BOOT0 pin is defining Main flash memory as the target boot area. When the flag
is set, the device is considered as empty and System memory (boot loader) is selected
instead of the main flash as a boot area to allow user to program the flash memory.
Therefore, some of the GPIOs are be reconfigured from the High-Z state. Refer to AN2606
for more details concerning the boot loader and GPIO configuration in System memory boot
mode. It is possible to disable this feature by configuring the option bytes, to force boot from
the Main flash memory (nSWBOOT0 = 0, nBOOT0 = 1).
The empty check flag is updated only during the loading of option bytes: it is set when the
content of the address 0x0800 0000 is read as 0xFFFF FFFF, otherwise it is cleared. It

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means a power reset or setting of OBL_LAUNCH bit in FLASH_CR register is needed to

clear this flag after programming of a virgin device to execute user code after System reset.
Note: If the device is programmed for a first time but the option bytes are not reloaded, the device
still selects System memory as a boot area after a System reset. In the STM32F070x6, the
boot loader code is able to detect this situation. It then changes the boot memory mapping
to main flash and performs a jump to user code programmed there. In the STM32F030xC, a
POR must be performed or the Option bytes reloaded before applying the system reset.

Physical remap
Once the boot mode is selected, the application software can modify the memory accessible
in the code area. This modification is performed by programming the MEM_MODE bits in
the SYSCFG configuration register 1 (SYSCFG_CFGR1). Unlike Cortex® M3 and M4, the
M0 CPU does not support the vector table relocation. For application code which is located
in a different address than 0x0800 0000, some additional code must be added in order to be
able to serve the application interrupts. A solution is to relocate by software the vector table
to the internal SRAM:
• Copy the vector table from the flash (mapped at the base of the application load
address) to the base address of the SRAM at 0x2000 0000.
• Remap SRAM at address 0x0000 0000, using SYSCFG configuration register 1.
• Then once an interrupt occurs, the Cortex®-M0 processor fetches the interrupt handler
start address from the relocated vector table in SRAM, then it jumps to execute the
interrupt handler located in the flash.
This operation should be done at the initialization phase of the application. Please refer to
AN4065 and attached IAP code from www.st.com for more details.

Embedded boot loader

The embedded boot loader is located in the System memory, programmed by ST during
production. It is used to reprogram the flash memory using one of the following serial
interfaces:
• USART on pins PA14/PA15 or PA9/PA10
• I2C on pins PB6/PB7 ( STM32F070xx and STM32F030xC devices only)
• USB DFU interface (STM32F070xx devices only)
For further details, refer to the application note AN2606.

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3 Embedded flash memory

3.1 Flash main features

• Up to 256 Kbyte of flash memory
• Memory organization:
– Main flash memory block:
Up to 64 Kword (64 K × 32 bits)
– Information block:
Up to 3 Kword (3 K × 32 bits) for the system memory
– Up to 2 x 8 byte for the option byte
Flash memory interface features:
• Read interface with prefetch buffer
• Option byte loader
• Flash program / erase operation
• Read / write protection
• Low-power mode

3.2 Flash memory functional description

3.2.1 Flash memory organization

The flash memory is organized as 32-bit wide memory cells that can be used for storing
both code and data constants.
The memory organization of STM32F030x4, STM32F030x6, STM32F070x6 and
STM32F030x8 devices is based on a main flash memory block containing up to 64 pages of
1 Kbyte or up to 16 sectors of 4 Kbytes (4 pages). The sector is the granularity of the write
protection (see Section 3.3).
The memory organization of STM32F070xB and STM32F030xC devices is based on a main
flash memory block containing up to 128 pages of 2 Kbytes or up to 64 sectors of 4 Kbytes
(2 pages). The sector is the granularity of the write protection (see Section 3.3).
The information block is divided into two parts:
1. System memory: used to boot the device in System memory boot mode. The area is
reserved for use by STMicroelectronics and contains the boot loader, which is used to
reprogram the flash memory through the selected communication interface. It is
programmed by ST when the device is manufactured, and protected against spurious
write/erase operations. For further details refer to AN2606.
2. Option byte

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Table 4. Flash memory organization (STM32F030x4, STM32F030x6, STM32F070x6 and

STM32F030x8 devices)
Flash area Flash memory addresses Size (byte) Name Description(1)

0x0800 0000 - 0x0800 03FF 1 Kbyte Page 0

0x0800 0400 - 0x0800 07FF 1 Kbyte Page 1
Sector 0
0x0800 0800 - 0x0800 0BFF 1 Kbyte Page 2
0x0800 0C00 - 0x0800 0FFF 1 Kbyte Page 3
. . . .
. . . .
. . . .
0x0800 7000 - 0x0800 73FF 1 Kbyte Page 28

Main flash 0x0800 7400 - 0x0800 77FF 1 Kbyte Page 29

Sector 7 (1)
memory 0x0800 7800 - 0x0800 7BFF 1 Kbyte Page 30
0x0800 7C00 - 0x0800 7FFF 1 Kbyte Page 31
. . . .
. . . .
. . . .
0x0800 F000 - 0x0800 F3FF 1 Kbyte Page 60
0x0800 F400 - 0x0800 F7FF 1 Kbyte Page 61
Sector 15
0x0800 F800 - 0x0800 FBFF 1 Kbyte Page 62
0x0800 FC00 - 0x0800 FFFF 1 Kbyte Page 63
0x1FFF EC00 - 0x1FFF F7FF 3 Kbyte(2) - System memory
Information
0x1FFF C400 -0x1FFF F7FF 13 Kbyte(3) - System memory
block
0x1FFF F800 - 0x1FFF F80F 2 x 8 byte - Option byte
1. On STM32F030x4 devices, the main Flash memory space is limited to sector 3. On STM32F030x6 and STM32F070x6
devices, the main Flash memory is limited to sector 7.
2. STM32F030x4, STM32F030x6 and STM32F030x8 devices.
3. STM32F070x6 devices.

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Table 5. Flash memory organization (STM32F070xB, STM32F030xC devices)

Flash area Flash memory addresses Size (byte) Name Description

0x0800 0000 - 0x0800 07FF 2 Kbytes Page 0

Sector 0
0x0800 0800 - 0x0800 0FFF 2 Kbytes Page 1
. . . .
. . . .
. . . .

Main flash 0x0801 F000 - 0x0801 F7FF 2 Kbytes Page 62

Sector 31(1)
memory 0x0801 F800 - 0x0801 FFFF 2 Kbytes Page 63
. . . .
. . . .
. . . .
0x0803 F000 - 0x0803 F7FF 2 Kbytes Page 126 -
0x0803 F800 - 0x0803 FFFF 2 Kbytes Page 127 -
(2)
0x1FFF C800 - 0x1FFF F7FF 12 Kbytes - System memory
Information (3)
0x1FFF D800 - 0x1FFF F7FF 8 Kbytes - System memory
block
0x1FFF F800 - 0x1FFF F80F 2 x 8 byte - Option byte
1. The main flash memory space of STM32F070xB is limited to sector 31.
2. STM32F070xB devices only.
3. STM32F030xC devices only.

Read operations
The embedded flash module can be addressed directly, as a common memory space. Any
data read operation accesses the content of the flash module through dedicated read
senses and provides the requested data.
The instruction fetch and the data access are both done through the same AHB bus. Read
accesses can be performed with the following options managed through the flash access
control register (FLASH_ACR):
• Instruction fetch: Prefetch buffer enabled for a faster CPU execution
• Latency: number of wait states for a correct read operation (from 0 to 1)

Instruction fetch
The Arm® Cortex®-M0 fetches the instruction over the AHB bus. The prefetch block aims at
increasing the efficiency of instruction fetching.

Prefetch buffer
The prefetch buffer is 3-block wide where each block consists of 4 bytes. The prefetch
blocks are direct-mapped. A block can be completely replaced on a single read to the flash
memory as the size of the block matches the bandwidth of the flash memory.
The implementation of this prefetch buffer makes a faster CPU execution possible as the
CPU fetches one word at a time with the next word readily available in the prefetch buffer.
This implies that the acceleration ratio is of the order of 2, assuming that the code is aligned
at a 32-bit boundary for the jumps.

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However the prefetch buffer has an impact on the performance only when the wait state
number is 1. In the other case (no wait state) the performance remains the same whatever
the prefetch buffer status. There could be some impacts on the power consumption but this
is strongly dependent from the actual application code.

Prefetch controller
The prefetch controller decides to access the flash memory depending on the available
space in the prefetch buffer. The Controller initiates a read request when there is at least
one block free in the prefetch buffer.
After reset, the state of the prefetch buffer is on.
The prefetch buffer is usually switched on/off during the initialization routine, while the
microcontroller is running on the internal 8 MHz RC (HSI) oscillator.

Access latency
In order to maintain the control signals to read the flash memory, the ratio of the prefetch
controller clock period to the access time of the flash memory has to be programmed in the
flash access control register with the LATENCY[2:0] bits. This value gives the number of
cycles needed to maintain the control signals of the flash memory and correctly read the
required data. After reset, the value is zero and only one cycle without additional wait states
is required to access the flash memory.

3.2.2 Flash program and erase operations

The STM32F0x0 embedded flash memory can be programmed using in-circuit
programming or in-application programming.
The in-circuit programming (ICP) method is used to update the entire contents of the flash
memory, using the SWD protocol or the boot loader to load the user application into the
microcontroller. ICP offers quick and efficient design iterations and eliminates unnecessary
package handling or socketing of devices.
In contrast to the ICP method, in-application programming (IAP) can use any
communication interface supported by the microcontroller (I/Os, USB, USART, I2C, SPI,
etc.) to download programming data into memory. IAP allows the user to re-program the
flash memory while the application is running. Nevertheless, part of the application has to
have been previously programmed in the flash memory using ICP.
The program and erase operations can be performed over the whole product voltage range.
They are managed through the following seven flash registers:
• Key register (FLASH_KEYR)
• Option byte key register (FLASH_OPTKEYR)
• Flash control register (FLASH_CR)
• Flash status register (FLASH_SR)
• Flash address register (FLASH_AR)
• Option byte register (FLASH_OBR)
• Write protection register (FLASH_WRPR)
An ongoing flash memory operation does not block the CPU as long as the CPU does not
access the flash memory.

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On the contrary, during a program/erase operation to the flash memory, any attempt to read
the flash memory stalls the bus. The read operation proceeds correctly once the
program/erase operation has completed. This means that code or data fetches cannot be
made while a program/erase operation is ongoing.
For program and erase operations on the flash memory (write/erase), the internal RC
oscillator (HSI) must be ON.

Unlocking the flash memory

After reset, the flash memory is protected against unwanted write or erase operations. The
FLASH_CR register is not accessible in write mode, except for the OBL_LAUNCH bit, used
to reload the option bits. An unlocking sequence should be written to the FLASH_KEYR
register to open the access to the FLASH_CR register. This sequence consists of two write
operations:
• Write KEY1 = 0x45670123
• Write KEY2 = 0xCDEF89AB
Any wrong sequence locks up the FLASH_CR register until the next reset.
In the case of a wrong key sequence, a bus error is detected and a Hard Fault interrupt is
generated. This is done after the first write cycle if KEY1 does not match, or during the
second write cycle if KEY1 has been correctly written but KEY2 does not match.
The FLASH_CR register can be locked again by user software by writing the LOCK bit in the
FLASH_CR register to 1.
For code example refer to the Appendix section A.2.1: Flash memory unlocking sequence.

Main flash memory programming

The main flash memory can be programmed 16 bits at a time. The program operation is
started when the CPU writes a half-word into a main flash memory address with the PG bit
of the FLASH_CR register set. Any attempt to write data that are not half-word long results
in a bus error generating a Hard Fault interrupt.

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Figure 3. Programming procedure

Read LOCK bit in

FLASH_CR

Yes
LOCK bit in FLASH_CR Perform unlock sequence
=1

No

Write PG bit in FLASH_CR to 1

Perform half-word write at the

desired address

Yes
BSY bit in FLASH_SR
=1

No
Check the programmed value
by reading the programmed
address
MS19220V1

The flash memory interface preliminarily reads the value at the addressed main flash
memory location and checks that it has been erased. If not, the program operation is
skipped and a warning is issued by the PGERR bit in FLASH_SR register. The only
exception to this is when 0x0000 is programmed. In this case, the location is correctly
programmed to 0x0000 and the PGERR bit is not set.
If the addressed main flash memory location is write-protected by the FLASH_WRPR
register, the program operation is skipped and a warning is issued by the WRPRTERR bit in
the FLASH_SR register. The end of the program operation is indicated by the EOP bit in the
FLASH_SR register.

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The main flash memory programming sequence in standard mode is as follows:

1. Check that no main flash memory operation is ongoing by checking the BSY bit in the
FLASH_SR register.
2. Set the PG bit in the FLASH_CR register.
3. Perform the data write (half-word) at the desired address.
4. Wait until the BSY bit is reset in the FLASH_SR register.
5. Check the EOP flag in the FLASH_SR register (it is set when the programming
operation has succeeded), and then clear it by software.
Note: The registers are not accessible in write mode when the BSY bit of the FLASH_SR register
is set.
For code example refer to the Appendix section A.2.2: Main flash memory programming
sequence.

Flash memory erase

The flash memory can be erased page by page or completely (mass erase).

Page erase
To erase a page, the procedure below should be followed:
1. Check that no flash memory operation is ongoing, by checking the BSY bit in the
FLASH_CR register.
2. Set the PER bit in the FLASH_CR register.
3. Program the FLASH_AR register to select a page to erase.
4. Set the STRT bit in the FLASH_CR register (see note below).
5. Wait for the BSY bit to be reset.
6. Check the EOP flag in the FLASH_SR register (it is set when the erase operation has
succeeded).
7. Clear the EOP flag.
Note: The software should start checking if the BSY bit equals “0” at least one CPU cycle after
setting the STRT bit.
For code example refer to the Appendix section A.2.3: Page erase sequence.

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Figure 4. Flash memory Page erase procedure

Read LOCK bit in

FLASH_CR

Yes
LOCK bit in FLASH_CR Perform unlock sequence
=1

No

Write PER bit in FLASH_CR

Write into FAR an address

within the page to erase

Write STRT bit in FLASH_CR

to 1

BSY bit in FLASH_SR Yes

=1

No

Check the page is erased by

reading all the addresses in
the page
MS19221V1

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Mass erase
The mass erase command can be used to completely erase the pages of the main flash
memory. The information block is unaffected by this procedure. The following sequence is
recommended:
1. Check that no flash memory operation is ongoing by checking the BSY bit in the
FLASH_SR register.
2. Set the MER bit in the FLASH_CR register.
3. Set the STRT bit in the FLASH_CR register.
4. Wait until the BSY bit is reset in the FLASH_SR register.
5. Check the EOP flag in the FLASH_SR register (it is set when the programming
operation has succeeded).
6. Clear the EOP flag.
Note: The software should start checking if the BSY bit equals “0” at least one CPU cycle after
setting the STRT bit.
For code example refer to the Appendix section A.2.4: Mass erase sequence.

Figure 5. Flash memory mass erase procedure

Read LOCK bit in

FLASH_CR

Yes
LOCK bit in FLASH_CR Perform unlock sequency
=1

No

Write MER bit

in FLASH_CR to 1

Write STRT bit in FLASH_CR

to 1

BSY bit in Yes

FLASH_SR
=1

No

Check the erase operation by

reading all the addresses in
the user memory
MS19222V1

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Option byte programming

The option byte are programmed differently from normal user addresses. The number of
option byte is limited to 8 (1, 2 or 4 for write protection, 1 for read protection, 1 for hardware
configuration and 2 free byte for user data). After unlocking the flash access, the user has to
authorize the programming of the option byte by writing the same set of KEYS (KEY1 and
KEY2) to the FLASH_OPTKEYR register to set the OPTWRE bit in the FLASH_CR register
(refer to Unlocking the flash memory for key values). Then the user has to set the OPTPG
bit in the FLASH_CR register and perform a half-word write operation at the desired flash
address.
The value of the addressed option byte is first read to check it is really erased. If not, the
program operation is skipped and a warning is issued by the PGERR bit in the FLASH_SR
register. The end of the program operation is indicated by the EOP bit in the FLASH_SR
register.
The option byte is automatically complemented into the next flash memory address before
the programming operation starts. This guarantees that the option byte and its complement
are always correct.
The sequence is as follows:
1. Check that no flash memory operation is ongoing by checking the BSY bit in the
FLASH_SR register.
2. Unlock the OPTWRE bit in the FLASH_CR register.
3. Set the OPTPG bit in the FLASH_CR register.
4. Write the data (half-word) to the desired address.
5. Wait for the BSY bit to be reset.
6. Read the programmed value and verify.
For code example refer to the Appendix section A.2.6: Option byte programming sequence.
When the flash memory read protection option is changed from protected to unprotected, a
mass erase of the main flash memory is performed before reprogramming the read
protection option. If the user wants to change an option other than the read protection
option, then the mass erase is not performed. The erased state of the read protection option
byte protects the flash memory.

Erase procedure
The option byte erase sequence is as follows:
1. Check that no flash memory operation is ongoing by reading the BSY bit in the
FLASH_SR register
2. Unlock the OPTWRE bit in the FLASH_CR register
3. Set the OPTER bit in the FLASH_CR register
4. Set the STRT bit in the FLASH_CR register
5. Wait for the BSY bit to be reset
6. Read the erased option byte and verify
For code example refer to the Appendix section A.2.7: Option byte erasing sequence.

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3.3 Memory protection

The user area of the flash memory can be protected against read by untrusted code. The
pages of the flash memory can also be protected against unwanted write due to loss of
program counter contexts. The write-protection granularity is one sector (four pages).

3.3.1 Read protection

The read protection is activated by setting the RDP option byte then by applying the system
reset to reload the new RDP option byte.
Note: Instead of the system reset, apply the power-on reset (POR) to reload the new RDP option
byte if the debugger connection occurred since the last POR. If the read protection is
programmed through software, do not set the OBL_LAUNCH bit (FLASH_CR register) but
perform a POR to reload the option bytes. This can be done by Standby or Shutdown mode
entry followed by a wakeup.
There are three levels of read protection from no protection (level 0) to maximum protection
or no debug (level 2). Refer to Table 7: Access status versus protection level and execution
modes.
The flash memory is protected when the RDP option byte and its complement contain the
pair of values shown in Table 6.

Table 6. Flash memory read protection status

RDP byte value RDP complement value Read protection level

Level 0 (ST production

0xAA 0x55
configuration)
Any value
Any value
(not necessarily complementary) Level 1
except 0xAA or 0xCC
except 0x55 and 0x33
0xCC 0x33 Level 2

The System memory area is read accessible whatever the protection level. It is never
accessible for program/erase operation

Level 0: no protection
Read, program and erase operations into the main flash memory area are possible.
The option byte are as well accessible by all operations.

Level 1: read protection

This is the default protection level when RDP option byte is erased. It is defined as well
when RDP value is at any value different from 0xAA and 0xCC, or even if the complement is
not correct.
• User mode: Code executing in user mode can access main flash memory and option
byte with all operations.
• Debug, boot RAM and boot loader modes: In debug mode (with SWD) or when code
is running from boot RAM or boot loader, the main flash memory is totally inaccessible.
In these modes, even a simple read access generates a bus error and a Hard Fault
interrupt. The main flash memory is program/erase protected to prevent malicious or

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unauthorized users from reprogramming any of the user code with a dump routine. Any
attempted program/erase operation sets the PGERR flag of flash status register
(FLASH_SR).
When the RPD is reprogrammed to the value 0xAA to move back to Level 0, a mass
erase of the main flash memory is performed.

Level 2: no debug
In this level, the protection level 1 is guaranteed. In addition, the CortexM0 debug
capabilities are disabled. Consequently, the debug port (SWD), the boot from RAM (boot
RAM mode) and the boot from System memory (boot loader mode) are no more available.
In user execution mode, all operations are allowed on the main flash memory. On the
contrary, only read and program operations can be performed on the option byte. Option
byte are not accessible for erase operations.
Moreover, the RDP byte cannot be programmed. Thus, the level 2 cannot be removed at all:
it is an irreversible operation. When attempting to program the RDP byte, the protection
error flag WRPRTERR is set in the flash_SR register and an interrupt can be generated.
Note: The debug feature is also disabled under reset.
STMicroelectronics is not able to perform analysis on defective parts on which the level 2
protection has been set.

Table 7. Access status versus protection level and execution modes

Debug / Boot from RAM /
User execution
Protection Boot from System memory
Area
level
Read Write Erase Read Write Erase

Main flash 1 Yes Yes Yes No No No

memory 2 Yes Yes Yes N/A(1) N/A(1) N/A(1)

System 1 Yes No No Yes No No

memory(2) 2 Yes No No N/A(1) N/A(1) N/A(1)
1 Yes Yes(3) Yes Yes(4) Yes(4) Yes
Option byte
(5) N/A(1) N/A(1) N/A(1)
2 Yes Yes No
1. When the protection level 2 is active, the Debug port, the boot from RAM and the boot from System memory are
disabled.
2. The system memory is only read-accessible, whatever the protection level (0, 1 or 2) and execution mode.
3. The main flash memory is erased when the RDP option byte is changed from level 1 to level 0 (0xAA).
4. When the RDP level 1 is active, the embedded boot loader does not allow to read or write the Option byte, except to
remove the RDP protection (move from level 1 to level 0).
5. All option byte can be programmed, except the RDP byte.

Changing read protection level

It is easy to move from level 0 to level 1 by changing the value of the RDP byte to any value
(except 0xCC).
By programming the 0xCC value in the RDP byte, it is possible to go to level 2 either directly
from level 0 or from level 1.

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On the contrary, the change to level 0 (no protection) is not possible without a main flash
memory Mass erase operation. This Mass erase is generated as soon as 0xAA is
programmed in the RDP byte.
Note: To validate the protection level change, the option byte must be reloaded through the
"OBL_LAUNCH" bit in Flash control register.

3.3.2 Write protection

The write protection is implemented with a granularity of one sector. It is activated by
configuring the WRPx option byte, and then by reloading them by setting the OBL_LAUNCH
bit in the FLASH_CR register.
If a program or an erase operation is performed on a protected sector, the flash memory
returns a WRPRTERR protection error flag in the flash memory Status Register
(FLASH_SR).

Write unprotection
To disable the write protection, two application cases are provided:
• Case 1: Read protection disabled after the write unprotection:
– Erase the entire option byte area by using the OPTER bit in the flash memory
control register (FLASH_CR).
– Program the code 0xAA in the RDP byte to unprotect the memory. This operation
forces a mass erase of the main flash memory.
– Set the OBL_LAUNCH bit in the flash control register (FLASH_CR) to reload the
option byte (and the new WRP[1:0] byte), and to disable the write protection.
• Case 2: Read protection maintained active after the write unprotection, useful for in-
application programming with a user boot loader:
– Erase the entire option byte area by using the OPTER bit in the flash memory
control register (FLASH_CR).
– Set the OBL_LAUNCH bit in the flash control register (FLASH_CR) to reload the
option byte (and the new WRP[1:0] byte), and to disable the write protection.

3.3.3 Option byte write protection

The option byte are always read-accessible and write-protected by default. To gain write
access (Program/Erase) to the option byte, a sequence of keys (same as for lock) has to be
written into the OPTKEYR. A correct sequence of keys gives write access to the option byte
and this is indicated by OPTWRE in the FLASH_CR register being set. Write access can be
disabled by resetting the bit through software.

3.4 Flash interrupts

Table 8. Flash interrupt request
Interrupt event Event flag Enable control bit

End of operation EOP EOPIE

Write protection error WRPRTERR ERRIE
Programming error PGERR ERRIE

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3.5 Flash register description

The flash memory registers have to be accessed by 32-bit words (half-word and byte
accesses are not allowed).

3.5.1 Flash access control register (FLASH_ACR)

Address offset: 0x00
Reset value: 0x0000 0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRFT PRFT
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. LATENCY[2:0]
BS BE
r rw rw rw rw

Bits 31:6 Reserved, must be kept at reset value.

Bit 5 PRFTBS: Prefetch buffer status
This bit provides the status of the prefetch buffer.
0: Prefetch buffer is disabled
1: Prefetch buffer is enabled
Note: The prefetch status is set to 1 as soon a first fetch request is done
Bit 4 PRFTBE: Prefetch buffer enable
0: Prefetch is disabled
1: Prefetch is enabled
Bit 3 Reserved, must be kept at reset value.
Bits 2:0 LATENCY[2:0]: Latency
These bits represent the ratio of the SYSCLK (system clock) period to the flash access time.
000: Zero wait state, if SYSCLK ≤ 24 MHz
001: One wait state, if 24 MHz < SYSCLK ≤ 48 MHz

3.5.2 Flash key register (FLASH_KEYR)

Address offset: 0x04
Reset value: 0xXXXX XXXX
All these register bits are write-only and return a 0 when read.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FKEY[31:16]
w w w w w w w w w w w w w w w w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FKEY[15:0]
w w w w w w w w w w w w w w w w

Bits 31:0 FKEY: Flash key

These bits represent the keys to unlock the flash.

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3.5.3 Flash option key register (FLASH_OPTKEYR)

Address offset: 0x08
Reset value: 0xXXXX XXXX
All these register bits are write-only and return a 0 when read.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OPTKEY[31:16]
w w w w w w w w w w w w w w w w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OPTKEY[15:0]
w w w w w w w w w w w w w w w w

Bits 31:0 OPTKEY: Option byte key

These bits represent the keys to unlock the OPTWRE.

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3.5.4 Flash status register (FLASH_SR)

Address offset: 0x0C
Reset value: 0x0000 0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WRPRT PG
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. EOP Res. Res. BSY
ERR ERR
rc_w1 rc_w1 rc_w1 r

Bits 31:6 Reserved, must be kept at reset value.

Bit 5 EOP: End of operation
Set by hardware when a flash operation (programming / erase) is completed.
Reset by writing 1.
Note: EOP is asserted at the end of each successful program or erase operation
Bit 4 WRPRTERR: Write protection error
Set by hardware when programming a write-protected address of the flash memory.
Reset by writing 1.
Bit 3 Reserved, must be kept at reset value.
Bit 2 PGERR: Programming error
Set by hardware when an address to be programmed contains a value different from '0xFFFF'
before programming.
Reset by writing 1.
Note: The STRT bit in the FLASH_CR register should be reset before starting a programming
operation.
Bit 1 Reserved, must be kept at reset value.
Bit 0 BSY: Busy
This indicates that a flash operation is in progress. This is set on the beginning of a flash
operation and reset when the operation finishes or when an error occurs.

3.5.5 Flash control register (FLASH_CR)

Address offset: 0x10
Reset value: 0x0000 0080

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. OBL_LAUNCH EOPIE Res. ERRIE OPTWRE Res. LOCK STRT OPTER OPTPG Res. MER PER PG
rw rw rw rw rw rw rw rw rw rw rw

Bits 31:14 Reserved, must be kept at reset value.

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Bit 13 OBL_LAUNCH: Force option byte loading

When set to 1, this bit forces the option byte reloading. This operation generates a system
reset.
0: Inactive
1: Active
Bit 12 EOPIE: End of operation interrupt enable
This bit enables the interrupt generation when the EOP bit in the FLASH_SR register goes to 1.
0: Interrupt generation disabled
1: Interrupt generation enabled
Bit 11 Reserved, must be kept at reset value
Bit 10 ERRIE: Error interrupt enable
This bit enables the interrupt generation on an error when PGERR / WRPRTERR are set in the
FLASH_SR register.
0: Interrupt generation disabled
1: Interrupt generation enabled
Bit 9 OPTWRE: Option byte write enable
When set, the option byte can be programmed. This bit is set on writing the correct key
sequence to the FLASH_OPTKEYR register.
This bit can be reset by software
Bit 8 Reserved, must be kept at reset value.
Bit 7 LOCK: Lock
Write to 1 only. When it is set, it indicates that the flash is locked. This bit is reset by hardware
after detecting the unlock sequence.
In the event of unsuccessful unlock operation, this bit remains set until the next reset.
Bit 6 STRT: Start
This bit triggers an ERASE operation when set. This bit is set only by software and reset when
the BSY bit is reset.
Bit 5 OPTER: Option byte erase
Option byte erase chosen.
Bit 4 OPTPG: Option byte programming
Option byte programming chosen.
Bit 3 Reserved, must be kept at reset value.
Bit 2 MER: Mass erase
Erase of all user pages chosen.
Bit 1 PER: Page erase
Page erase chosen.
Bit 0 PG: Programming
Flash programming chosen.

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3.5.6 Flash address register (FLASH_AR)

Address offset: 0x14
Reset value: 0x0000 0000
This register is updated by hardware with the currently/last used address. For Page erase
operations, this should be updated by software to indicate the chosen page.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FAR[31:16]
w w w w w w w w w w w w w w w w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FAR[15:0]
w w w w w w w w w w w w w w w w

Bits 31:0 FAR: Flash address

Chooses the address to program when programming is selected, or a page to erase when Page
erase is selected.
Note: Write access to this register is blocked when the BSY bit in the FLASH_SR register is set.

3.5.7 Flash Option byte register (FLASH_OBR)

Address offset 0x1C
Reset value: 0xXXXX XX0X
The reset value of this register depends on the value programmed in the option byte.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA1 DATA0
r r r r r r r r r r r r r r r r

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RAM_
VDDA_ nRST_ nRST_
Res. PARITY_ nBOOT1 Res. WDG_SW Res. Res. Res. Res. Res. RDPRT[1:0] OPTERR
MONITOR STDBY STOP
CHECK
r r r r r r r r r

Bits 31:24 DATA1

Bits 23:16 DATA0
Bit 15 Reserved, must be kept at reset value
Bits 14:12 User option byte:
Bit 14: RAM_PARITY_CHECK
Bit 13: VDDA_MONITOR
Bit 12: nBOOT1
Bit 11 Reserved, must be kept at reset value
Bits 10:8 Bit 10: nRST_STDBY
Bit 9: nRST_STOP
Bit 8: WDG_SW

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Bits 7:3 Reserved, must be kept at reset value.

Bits 2:1 RDPRT[1:0]: Read protection level status
00: Read protection level 0 is enabled (ST production configuration)
01: Read protection level 1 is enabled
11: Read protection level 2 is enabled.
Bit 0 OPTERR: Option byte error
When set, this indicates that the loaded option byte and its complement do not match. The
corresponding byte is set to 0xFF in respective FLASH_OBR or FLASH_WRPR register.

3.5.8 Write protection register (FLASH_WRPR)

Address offset: 0x20
Reset value: 0xXXXX XXXX
The reset value of this register depends on the value programmed in the option byte.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WRP[31:16]

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WRP[15:0]

Bits 31:0 WRP: Write protect

This register contains the write-protection option byte loaded by the OBL.

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3.5.9 Flash register map

Table 9. Flash interface - Register map and reset values

Off- Register
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12

10
11

9
8
7
6
5
4
3
2
1
0
set

LATENCY
PRFTBS
PRFTBE
HLFCYA
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

[2:0]
FLASH_ACR
0x000

Reset value 0 0 0 0 0 0

FLASH_KEYR FKEY[31:0]
0x004
Reset value x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x

FLASH_
OPTKEY[31:0]
0x008 OPTKEYR

Reset value x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x

WRPRTERR

ERLYBSY
PGERR
EOP
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.

BSY
FLASH_SR
0x00C

Reset value 0 0 0 0 0

OBL_LAUNCH

OPTWRE

OPTPG
OPTER
EOPIE

ERRIE

LOCK
STRT

MER
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.

Res.

Res.

PER
PG
FLASH_CR
0x010

Reset value 0 0 0 0 1 0 0 0 0 0 0

FLASH_AR FAR[31:0]
0x014
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RAM_PARITY_CHECK
VDDA_MONITOR

nRST_STDBY
nRST_STOP

RDPRT[1:0]
WDG_SW

OPTERR
nBOOT1
Data1

Data0

Res.

Res.

Res.
Res.
Res.
Res.
Res.
FLASH_OBR
0x01C

Reset value X X X X X X X X X X X X X X X X X X X X X X X X X

FLASH_WRPR WRP[31:0]
0x020
Reset value X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X

Refer to Section 2.2 on page 37 for the register boundary addresses.

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4 Option bytes

There are up to 8 option bytes. They are configured by the end user depending on the
application requirements. As a configuration example, the watchdog may be selected in
hardware or software mode.
A 32-bit word is split up as follows in the option byte.

Table 10. Option byte format

31-24 23-16 15 -8 7-0

Complemented Complemented
Option byte 1 Option byte 0
option byte 1 option byte 0

The organization of these bytes inside the information block is as shown in Table 11.
The option byte can be read from the memory locations listed in Table 11 or from the Option
byte register (FLASH_OBR).
Note: The new programmed option byte (user, read/write protection) are not loaded after a system
reset. To reload them, either a POR or setting to '1' the OBL_LAUNCH bit is necessary.

Table 11. Option byte organization

Address [31:24] [23:16] [15:8] [7:0]

0x1FFF F800 nUSER USER nRDP RDP

0x1FFF F804 nData1 Data1 nData0 Data0
0x1FFF F808 nWRP1 WRP1 nWRP0 WRP0
0x1FFF F80C nWRP3 WRP3 nWRP2 WRP2

On every power-on reset, the option byte loader (OBL) reads the information block and
stores the data into the option byte register (FLASH_OBR) and the write protection register
(FLASH_WRPR). During option byte loading, the bit-wise complementarity of the option
byte and its corresponding complemented option byte is verified. In case of failure, an option
byte error (OPTERR) is generated and the corresponding option byte is considered as
0xFF. If the option byte and its complemented option byte are both equal to 0xFF (Electrical
Erase state) the option byte error is not generated.

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4.1 Option byte description

4.1.1 User and read protection option byte

Flash memory address: 0x1FFF F800
ST production value: 0x00FF 55AA

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
USER
RAM_
VDDA_ nRST_ nRST_ WDG_
nUSER Res. PARITY_ nBOOT1 Res.
MONITOR STDBY STOP SW
CHECK
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
nRDP RDP
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:24 nUSER: User option byte complement

Bit 23 Reserved, must be kept as “1”
Bits 22:20 USER: User option byte (stored in FLASH_OBR[15:8])
Bit 22: RAM_PARITY_CHECK
0: RAM parity check enabled
1: RAM parity check disabled
Bit 21: VDDA_MONITOR
0: VDDA power supply supervisor disabled
1: VDDA power supply supervisor enabled
Bit 20: nBOOT1
Together with the BOOT0 signal, it selects the device boot mode. Refer to Section 2.5: Boot
configuration for more details.
Section 2.5: Boot configuration
Bit 19 Reserved, must be kept as “1”

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Bits 18:16 Bit 18: nRST_STDBY

0: Reset generated when entering Standby mode.
1: No reset generated.
Bit 17: nRST_STOP
0: Reset generated when entering Stop mode
1: No reset generated
Bit 16: WDG_SW
0: Hardware watchdog
1: Software watchdog
Bits 15:8 nRDP: Read protection option byte complement
Bits 7:0 RDP: Read protection option byte
The value of this byte defines the flash memory protection level
0xAA: level 0 (ST production configuration)
0xXX (except 0xAA & 0xCC): Level 1
0xCC: Level 2
Note: Read protection level status is stored in bits RDPRT[1:0] of the Flash Option byte
register (FLASH_OBR). For more details about read protection, refer to Section 3.3.1:
Read protection.

4.1.2 User data option byte

Flash memory address: 0x1FFF F804
ST production value: 0x00FF 00FF

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
nData1 Data1
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
nData0 Data0
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:24 nData1: User data byte 1 complement

Bits 23:16 Data1: User data byte 1 value (stored in FLASH_OBR[31:24])
Bits 15:8 nData0: User data byte 0 complement
Bits 7:0 Data0: User data byte 0 value (stored in FLASH_OBR[23:16])

4.1.3 Write protection option byte

This set of registers is used to write-protect the flash memory. Clearing a bit in WRPx field
(and at the same time setting a corresponding bit in nWRPx field) write-protects the given
memory sector.
For STM32F030x4, STM32F030x6, STM32F070x6, STM32F030x8 and STM32F070xB
devices, WRP bits from 0 to 31 are protecting the flash memory by sector of 4 kB.
For STM32F030xC devices, WRP bits from 0 to 30 are protecting the first 124 kB by sector
of 4 kB and the bit 31 is protecting the last 132 kB.
Refer to Section 3.3.2: Write protection for more details.

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Flash memory address: 0x1FFF F808

ST production value: 0x00FF 00FF

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
nWRP1 WRP1
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
nWRP0 WRP0
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:24 nWRP1: Flash memory write protection option byte 1 complement
Bits 23:16 WRP1: Flash memory write protection option byte 1 value (stored in FLASH_WRPR[15:8])
Bits 15:8 nWRP0: Flash memory write protection option byte 0 complement
Bits 7:0 WRP0: Flash memory write protection option byte 0 value (stored in FLASH_WRPR[7:0])

Note: STM32F030x4, STM32F030x6 and STM32F070x6 devices embed WRP0 and nWRP0 only.
The following Option byte are available on STM32F070xB and STM32F030xC devices only.
Flash memory address: 0x1FFF F80C
ST production value: 0x00FF 00FF

4.1.4 Option byte map

The following table summarizes the option bytes.

Table 12. Option byte map and ST production values

Offset Option
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12

10
11

9
8
7
6
5
4
3
2
1
0
byte
USER
RAM_PARITY_CHECK
VDDA_MONITOR

nRST_STDBY
nRST_STOP

User and
WDG_SW
nBOOT1

read nUSER nRDP RDP

Res.

Res.

0x00 protection

ST production
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0
value

User data nData1 Data1 nData0 Data0

0x04 ST production
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
value

Write
nWRP1 WRP1 nWRP0 WRP0
protection
0x08
ST production
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
value

Write
nWRP3 WRP3 nWRP2 WRP2
protection
0x0C
ST production
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
value

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5 Cyclic redundancy check calculation unit (CRC)

5.1 Introduction
The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from 8-, 16-
or 32-bit data word and a generator polynomial.
Among other applications, CRC-based techniques are used to verify data transmission or
storage integrity. In the scope of the functional safety standards, they offer a means of
verifying the flash memory integrity. The CRC calculation unit helps compute a signature of
the software during runtime, to be compared with a reference signature generated at link
time and stored at a given memory location.

5.2 CRC main features

• Uses CRC-32 (Ethernet) polynomial: 0x4C11DB7
X32 + X26 + X23 + X22 + X16 + X12 + X11 + X10 +X8 + X7 + X5 + X4 + X2+ X +1
• Handles 8-,16-, 32-bit data size
• Programmable CRC initial value
• Single input/output 32-bit data register
• Input buffer to avoid bus stall during calculation
• CRC computation done in 4 AHB clock cycles (HCLK) for the 32-bit data size
• General-purpose 8-bit register (can be used for temporary storage)
• Reversibility option on I/O data
• Accessed through AHB slave peripheral by 32-bit words only, with the exception of
CRC_DR register that can be accessed by words, right-aligned half-words and right-
aligned bytes

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5.3 CRC functional description

5.3.1 CRC block diagram

Figure 6. CRC calculation unit block diagram

32-bit AHB bus

read access write access 32-bit accesses

Data register Data register

crc_hclk
(output) (input)
CRC_INIT

CRC_CR
CRC computation
CRC_POL

CRC_IDR

MS19882V3

5.3.2 CRC internal signals

Table 13. CRC internal input/output signals

Signal name Signal type Description

crc_hclk Digital input AHB clock

5.3.3 CRC operation

The CRC calculation unit has a single 32-bit read/write data register (CRC_DR). It is used to
input new data (write access), and holds the result of the previous CRC calculation (read
access).
Each write operation to the data register creates a combination of the previous CRC value
(stored in CRC_DR) and the new one. CRC computation is done on the whole 32-bit data
word or byte by byte depending on the format of the data being written.
The CRC_DR register can be accessed by word, right-aligned half-word and right-aligned
byte. For the other registers only 32-bit accesses are allowed.
The duration of the computation depends on data width:
• 4 AHB clock cycles for 32 bits
• 2 AHB clock cycles for 16 bits
• 1 AHB clock cycles for 8 bits
An input buffer allows a second data to be immediately written without waiting for any wait
states due to the previous CRC calculation.

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The data size can be dynamically adjusted to minimize the number of write accesses for a
given number of bytes. For instance, a CRC for 5 bytes can be computed with a word write
followed by a byte write.
The input data can be reversed to manage the various endianness schemes. The reversing
operation can be performed on 8 bits, 16 bits and 32 bits depending on the REV_IN[1:0] bits
in the CRC_CR register.
For example, 0x1A2B3C4D input data are used for CRC calculation as:
• 0x58D43CB2 with bit-reversal done by byte
• 0xD458B23C with bit-reversal done by half-word
• 0xB23CD458 with bit-reversal done on the full word
The output data can also be reversed by setting the REV_OUT bit in the CRC_CR register.
The operation is done at bit level. For example, 0x11223344 output data are converted to
0x22CC4488.
The CRC calculator can be initialized to a programmable value using the RESET control bit
in the CRC_CR register (the default value is 0xFFFFFFFF).
The initial CRC value can be programmed with the CRC_INIT register. The CRC_DR
register is automatically initialized upon CRC_INIT register write access.
The CRC_IDR register can be used to hold a temporary value related to CRC calculation. It
is not affected by the RESET bit in the CRC_CR register.

5.4 CRC registers

The CRC_DR register can be accessed by words, right-aligned half-words and right-aligned
bytes. For the other registers only 32-bit accesses are allowed.

5.4.1 CRC data register (CRC_DR)

Address offset: 0x00
Reset value: 0xFFFF FFFF

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

DR[31:16]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

DR[15:0]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:0 DR[31:0]: Data register bits

This register is used to write new data to the CRC calculator.
It holds the previous CRC calculation result when it is read.
If the data size is less than 32 bits, the least significant bits are used to write/read the correct
value.

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5.4.2 CRC independent data register (CRC_IDR)

Address offset: 0x04
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res. Res. Res. Res. Res. Res. Res. Res. IDR[7:0]

rw rw rw rw rw rw rw rw

Bits 31:8 Reserved, must be kept at reset value.

Bits 7:0 IDR[7:0]: General-purpose 8-bit data register bits
These bits can be used as a temporary storage location for one byte.
This register is not affected by CRC resets generated by the RESET bit in the CRC_CR
register

5.4.3 CRC control register (CRC_CR)

Address offset: 0x08
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REV_
Res. Res. Res. Res. Res. Res. Res. Res. REV_IN[1:0] Res. Res. Res. Res. RESET
OUT
rw rw rw rs

Bits 31:8 Reserved, must be kept at reset value.

Bit 7 REV_OUT: Reverse output data
This bit controls the reversal of the bit order of the output data.
0: Bit order not affected
1: Bit-reversed output format

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Bits 6:5 REV_IN[1:0]: Reverse input data

This bitfield controls the reversal of the bit order of the input data
00: Bit order not affected
01: Bit reversal done by byte
10: Bit reversal done by half-word
11: Bit reversal done by word
Bits 4:1 Reserved, must be kept at reset value.
Bit 0 RESET: RESET bit
This bit is set by software to reset the CRC calculation unit and set the data register to the
value stored in the CRC_INIT register. This bit can only be set, it is automatically cleared by
hardware

5.4.4 CRC initial value (CRC_INIT)

Address offset: 0x10
Reset value: 0xFFFF FFFF

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

CRC_INIT[31:16]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

CRC_INIT[15:0]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:0 CRC_INIT[31:0]: Programmable initial CRC value

This register is used to write the CRC initial value.

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5.4.5 CRC register map

Table 14. CRC register map and reset values

Offset Register

31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12

10
11

9
8
7
6
5
4
3
2
1
0
name

CRC_DR DR[31:0]
0x00
Reset value 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
CRC_IDR IDR[7:0]
0x04
Reset value 0 0 0 0 0 0 0 0

REV_IN[1:0]
REV_OUT

RESET
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.
Res.
Res.
Res.
CRC_CR
0x08

Reset value 0 0 0 0

CRC_INIT CRC_INIT[31:0]
0x10
Reset value 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

Refer to Section 2.2 on page 37 for the register boundary addresses.

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Power control (PWR) RM0360

6 Power control (PWR)

6.1 Power supplies

The STM32F030/STM32F070 subfamily embeds a voltage regulator in order to supply the
internal 1.8 V digital power domain.
• The STM32F030/STM32F070 devices require a 2.4 V - 3.6 V operating supply voltage
(VDD) and a 2.4 V - 3.6 V analog supply voltage (VDDA).

Figure 7. Power supply overview

STM32F030
VDDA domain STM32F070
VSSA A/D converter
Temp. sensor
VDDA Reset block
PLL

VDD domain
I/O ring
Core
VSS
Standby circuitry
Memories
VDD (Wakeup logic,
IWDG) Digital
peripherals
Voltage regulator

LSE crystal 32 K osc

RTC

MS32604V1

6.1.1 Independent A/D converter supply and reference voltage

To improve conversion accuracy and to extend the supply flexibility, the ADC has an
independent power supply that can be separately filtered and shielded from noise on the
PCB.
• The ADC voltage supply input is available on a separate VDDA pin.
• An isolated supply ground connection is provided on pin VSSA.
The VDDA supply/reference voltage must be equal or higher than VDD.
When a single supply is used, VDDA can be externally connected to VDD, through the
external filtering circuit in order to ensure a noise free VDDA reference voltage.
When VDDA is different from VDD, VDDA must always be higher or equal to VDD. To keep
safe potential difference in between VDDA and VDD during power-up/power-down, an
external Shottky diode may be used between VDD and VDDA. Refer to the datasheet for the
maximum allowed difference.

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6.1.2 Voltage regulator

The voltage regulator is always enabled after Reset. It works in three different modes
depending on the application modes.
• In Run mode, the regulator supplies full power to the 1.8 V domain (core, memories
and digital peripherals).
• In Stop mode the regulator supplies low-power to the 1.8 V domain, preserving
contents of registers and SRAM
• In Standby Mode, the regulator is powered off. The contents of the registers and SRAM
are lost except for the Standby circuitry.

6.2 Power supply supervisor

6.2.1 Power on reset (POR) / power down reset (PDR)

STM32F0x1xx and STM32F0x2xx devices feature integrated power-on reset (POR) and
power-down reset (PDR) circuits, which are always active and ensure proper operation
above a threshold of 2 V.
The device remains in Reset mode when the monitored supply voltage is below a specified
threshold, VPOR/PDR, without the need for an external reset circuit.
• The POR monitors only the VDD supply voltage. During the startup phase VDDA must
arrive first and be greater than or equal to VDD.
• The PDR monitors both the VDD and VDDA supply voltages. However, the VDDA power
supply supervisor can be disabled (by programming a dedicated option bit
VDDA_MONITOR) to reduce the power consumption if the application is designed to
make sure that VDDA is higher than or equal to VDD.
For more details on the power on / power down reset threshold, refer to the electrical
characteristics section in the datasheet.

Figure 8. Power on reset/power down reset waveform

VDD /VDDA

VPOR
40 mV
hysteresis
V PDR

Temporization
t RSTTEMPO

Reset
MS31444V2

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6.3 Low-power modes

By default, the microcontroller is in Run mode after a system or a power Reset. Several low-
power modes are available to save power when the CPU does not need to be kept running,
for example when waiting for an external event. It is up to the user to select the mode that
gives the best compromise between low-power consumption, short startup time and
available wake-up sources.
The device features three low-power modes:
• Sleep mode (CPU clock off, all peripherals including Arm® Cortex®-M0 core
peripherals like NVIC, SysTick, etc. are kept running)
• Stop mode (all clocks are stopped)
• Standby mode (1.8V domain powered-off)
In addition, the power consumption in Run mode can be reduce by one of the following
means:
• Slowing down the system clocks
• Gating the clocks to the APB and AHB peripherals when they are unused.

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Table 15. Low-power mode summary

Effect on
Effect on 1.8 V VDD Voltage
Mode name Entry Wake-up
domain clocks domain regulator
clocks

Sleep WFI Any interrupt CPU clock OFF

(Sleep now or no effect on other None ON
Sleep-on - WFE Wake-up event clocks or analog
exit) clock sources
ON or in low-
PDDS and LPDS power mode
Any EXTI line
bits + (depends on
Stop (configured in the
SLEEPDEEP bit Power control
EXTI registers) HSI and
+ WFI or WFE register
All 1.8V domain HSE (PWR_CR))
clocks OFF oscillators
WKUP pin rising OFF
PDDS bit + edge, RTC alarm,
Standby SLEEPDEEP bit external reset in OFF
+ WFI or WFE NRST pin,
IWDG reset

6.3.1 Slowing down system clocks

In Run mode the speed of the system clocks (SYSCLK, HCLK, PCLK) can be reduced by
programming the prescaler registers. These prescalers can also be used to slow down
peripherals before entering Sleep mode.
For more details refer to Section 7.4.2: Clock configuration register (RCC_CFGR).

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6.3.2 Peripheral clock gating

In Run mode, the AHB clock (HCLK) and the APB clock (PCLK) for individual peripherals
and memories can be stopped at any time to reduce power consumption.
To further reduce power consumption in Sleep mode the peripheral clocks can be disabled
prior to executing the WFI or WFE instructions.
Peripheral clock gating is controlled by the AHB peripheral clock enable register
(RCC_AHBENR), the APB peripheral clock enable register 2 (RCC_APB2ENR) and the
APB peripheral clock enable register 1 (RCC_APB1ENR).

6.3.3 Sleep mode

Entering Sleep mode
The Sleep mode is entered by executing the WFI (Wait For Interrupt) or WFE (Wait for
Event) instructions. Two options are available to select the Sleep mode entry mechanism,
depending on the SLEEPONEXIT bit in the Arm® Cortex®-M0 System Control register:
• Sleep-now: if the SLEEPONEXIT bit is cleared, the MCU enters Sleep mode as soon
as WFI or WFE instruction is executed.
• Sleep-on-exit: if the SLEEPONEXIT bit is set, the MCU enters Sleep mode as soon as
it exits the lowest priority ISR.
In the Sleep mode, all I/O pins keep the same state as in the Run mode.
Refer to Table 16 and Table 17 for details on how to enter Sleep mode.

Exiting Sleep mode

If the WFI instruction is used to enter Sleep mode, any peripheral interrupt acknowledged by
the nested vectored interrupt controller (NVIC) can wake up the device from Sleep mode.
If the WFE instruction is used to enter Sleep mode, the MCU exits Sleep mode as soon as
an event occurs. The wake-up event can be generated either by:
• enabling an interrupt in the peripheral control register but not in the NVIC, and enabling
the SEVONPEND bit in the Arm® Cortex®-M0 System Control register. When the MCU
resumes from WFE, the peripheral interrupt pending bit and the peripheral NVIC IRQ
channel pending bit (in the NVIC interrupt clear pending register) must be cleared.
• or configuring an external or internal EXTI line in event mode. When the CPU resumes
from WFE, it is not necessary to clear the peripheral interrupt pending bit or the NVIC
IRQ channel pending bit as the pending bit corresponding to the event line is not set.
This mode offers the lowest wake-up time as no time is wasted in interrupt entry/exit.
Refer to Table 16 and Table 17 for more details on how to exit Sleep mode.

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Table 16. Sleep-now

Sleep-now mode Description

WFI (Wait for Interrupt) or WFE (Wait for Event) while:

– SLEEPDEEP = 0 and
Mode entry
– SLEEPONEXIT = 0
Refer to the Arm® Cortex®-M0 System Control register.
If WFI was used for entry:
Interrupt: Refer to Table 31: Vector table
Mode exit
If WFE was used for entry
Wake-up event: Refer to Section 11.2.3: Event management
Wake-up latency None

Table 17. Sleep-on-exit

Sleep-on-exit Description

WFI (wait for interrupt) while:

– SLEEPDEEP = 0 and
Mode entry
– SLEEPONEXIT = 1
Refer to the Arm® Cortex®-M0 System Control register.
Mode exit Interrupt: Refer to Table 31: Vector table.
Wake-up latency None

6.3.4 Stop mode

The Stop mode is based on the Arm® Cortex®-M0 deep sleep mode combined with
peripheral clock gating. The voltage regulator can be configured either in normal or low-
power mode. In Stop mode, all clocks in the 1.8 V domain are stopped, the PLL, the HSI and
the HSE oscillators are disabled. SRAM and register contents are preserved.
In the Stop mode, all I/O pins keep the same state as in the Run mode.

Entering Stop mode

Refer to Table 18 for details on how to enter the Stop mode.
To further reduce power consumption in Stop mode, the internal voltage regulator can be put
in low-power mode. This is configured by the LPDS bit of the Power control register
(PWR_CR).
If Flash memory programming is ongoing, the Stop mode entry is delayed until the memory
access is finished.
If an access to the APB domain is ongoing, The Stop mode entry is delayed until the APB
access is finished.
In Stop mode, the following features can be selected by programming individual control bits:
• Independent watchdog (IWDG): the IWDG is started by writing to its Key register or by
hardware option. Once started it cannot be stopped except by a Reset. See
Section 19.3: IWDG functional description.

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• real-time clock (RTC): this is configured by the RTCEN bit in the RTC domain control
register (RCC_BDCR)
• Internal RC oscillator (LSI): this is configured by the LSION bit in the Control/status
register (RCC_CSR).
• External 32.768 kHz oscillator (LSE): this is configured by the LSEON bit in the RTC
domain control register (RCC_BDCR).
The ADC can also consume power during Stop mode, unless it is disabled before entering
this mode. Refer to ADC control register (ADC_CR) for details on how to disable it.
Exiting Stop mode
Refer to Table 18 for more details on how to exit Stop mode.
When exiting Stop mode by issuing an interrupt or a wake-up event, the HSI oscillator is
selected as system clock.
When the voltage regulator operates in low-power mode, an additional startup delay is
incurred when waking up from Stop mode. By keeping the internal regulator ON during Stop
mode, the consumption is higher although the startup time is reduced.

Table 18. Stop mode

Stop mode Description

WFI (Wait for Interrupt) or WFE (Wait for Event) while:

– Set SLEEPDEEP bit in Arm® Cortex®-M0 System Control register
– Clear PDDS bit in Power Control register (PWR_CR)
– Select the voltage regulator mode by configuring LPDS bit in PWR_CR

Note: To enter Stop mode, all EXTI line pending bits (in Pending register
(EXTI_PR)), all peripherals interrupt pending bits and RTC Alarm flag must
Mode entry be reset. Otherwise, the Stop mode entry procedure is ignored and
program execution continues.
If the application needs to disable the external oscillator (external clock)
before entering Stop mode, the system clock source must be first switched
to HSI and then clear the HSEON bit.
Otherwise, if before entering Stop mode the HSEON bit is kept at 1, the
security system (CSS) feature must be enabled to detect any external
oscillator (external clock) failure and avoid a malfunction when entering
Stop mode.
If WFI was used for entry:
– Any EXTI line configured in Interrupt mode (the corresponding EXTI
Interrupt vector must be enabled in the NVIC).
Mode exit Refer to Table 31: Vector table.
If WFE was used for entry:
Any EXTI line configured in event mode. Refer to Section 11.2.3: Event
management on page 174
Wake-up latency HSI wake-up time + regulator wake-up time from Low-power mode

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6.3.5 Standby mode

The Standby mode allows to achieve the lowest power consumption. It is based on the
Arm® Cortex®-M0 deepsleep mode, with the voltage regulator disabled. The 1.8 V domain
is consequently powered off. The PLL, the HSI oscillator and the HSE oscillator are also
switched off. SRAM and register contents are lost except for registers in the Standby
circuitry (see Figure 7).

Entering Standby mode

Refer to Table 19 for more details on how to enter Standby mode.
In Standby mode, the following features can be selected by programming individual control
bits:
• Independent watchdog (IWDG): the IWDG is started by writing to its Key register or by
hardware option. Once started it cannot be stopped except by a reset. See
Section 19.3: IWDG functional description.
• Real-time clock (RTC): this is configured by the RTCEN bit in the RTC domain control
register (RCC_BDCR).
• Internal RC oscillator (LSI): this is configured by the LSION bit in the Control/status
register (RCC_CSR).
• External 32.768 kHz oscillator (LSE): this is configured by the LSEON bit in the RTC
domain control register (RCC_BDCR).

Exiting Standby mode

The microcontroller exits the Standby mode when an external reset (NRST pin), an IWDG
reset, a rising edge on one of the enabled WKUPx pins or an RTC event occurs. All
registers are reset after wake-up from Standby except for Power control/status register
(PWR_CSR).
After waking up from Standby mode, program execution restarts in the same way as after a
Reset (boot pin sampling, option bytes loading, reset vector is fetched, etc.). The SBF status
flag in the Power control/status register (PWR_CSR) indicates that the MCU was in Standby
mode.
Refer to Table 19 for more details on how to exit Standby mode.

Table 19. Standby mode

Standby mode Description

WFI (Wait for Interrupt) or WFE (Wait for Event) while:

– Set SLEEPDEEP in Arm® Cortex®-M0 System Control register
Mode entry
– Set PDDS bit in Power Control register (PWR_CR)
– Clear WUF bit in Power Control/Status register (PWR_CSR)
WKUP pin rising edge, RTC alarm event’s rising edge, external Reset in
Mode exit
NRST pin, IWDG Reset.
Wake-up latency Reset phase

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I/O states in Standby mode

In Standby mode, all I/O pins are high impedance except:
• Reset pad (still available)
• PC13, PC14 and PC15 if configured by RTC or LSE
• WKUPx pins

Debug mode
By default, the debug connection is lost if the application puts the MCU in Stop or Standby
mode while the debug features are used. This is due to the fact that the Arm® Cortex®-M0
core is no longer clocked.
However, by setting some configuration bits in the DBGMCU_CR register, the software can
be debugged even when using the low-power modes extensively.

6.3.6 RTC wakeup from low-power mode

The RTC can be used to wake-up the MCU from low-power mode by means of the RTC
alarm. For this purpose, two of the three alternative RTC clock sources can be selected by
programming the RTCSEL[1:0] bits in the RTC domain control register (RCC_BDCR):
• Low-power 32.768 kHz external crystal oscillator (LSE OSC)
This clock source provides a precise time base with very low-power consumption (less
than 1 µA added consumption in typical conditions)
• Low-power internal RC oscillator (LSI)
This clock source has the advantage of saving the cost of the 32.768 kHz crystal. This
internal RC oscillator is designed to add minimum power consumption.
To wake-up from Stop mode with an RTC alarm event, it is necessary to:
• Configure the EXTI Line 17 to be sensitive to rising edge
• Configure the RTC to generate the RTC alarm
To wake-up from Standby mode, there is no need to configure the EXTI Line 17.

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6.4 Power control registers

The peripheral registers can be accessed by half-words (16-bit) or words (32-bit).

6.4.1 Power control register (PWR_CR)

Address offset: 0x00
Reset value: 0x0000 0000 (reset by wake-up from Standby mode)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res Res Res Res Res Res Res DBP Res Res Res Res CSBF CWUF PDDS LPDS

rw rc_w1 rc_w1 rw rw

Bits 31:9 Reserved, must be kept at reset value.

Bit 8 DBP: Disable RTC domain write protection.
In reset state, the RTC registers are protected against parasitic write access. This bit must be
set to enable write access to these registers.
0: Access to RTC disabled
1: Access to RTC enabled
Bits 7:4 Reserved, must be kept at reset value
Bit 3 CSBF: Clear standby flag.
This bit is always read as 0.
0: No effect
1: Clear the SBF standby flag (write).
Bit 2 CWUF: Clear wake-up flag.
This bit is always read as 0.
0: No effect
1: Clear the WUF wake-up Flag after 2 System clock cycles. (write)
Bit 1 PDDS: Power down deepsleep.
This bit is set and cleared by software. It works together with the LPDS bit.
0: Enter Stop mode when the CPU enters Deepsleep. The regulator status depends on the
LPDS bit.
1: Enter Standby mode when the CPU enters Deepsleep.
Bit 0 LPDS: Low-power deepsleep.
This bit is set and cleared by software. It works together with the PDDS bit.
0: Voltage regulator on during Stop mode
1: Voltage regulator in low-power mode during Stop mode
Note: When a peripheral that can work in STOP mode requires a clock, the Power controller
automatically switch the voltage regulator from Low-power mode to Normal mode and
remains in this mode until the request disappears.

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6.4.2 Power control/status register (PWR_CSR)

Address offset: 0x04
Reset value: 0x0000 000X (not reset by wake-up from Standby mode)
Additional APB cycles are needed to read this register versus a standard APB read.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

EWUP EWUP EWUP EWUP EWUP EWUP

Res. Res. Res Res Res Res Res Res SBF WUF
7 6 5 4 2 1

rw rw rw rw rw rw r r

Bits 31:15 Reserved, must be kept at reset value.

Bits 14:11 EWUPx: Enable WKUPx pin (available only on STM32F070xB and STM32F030xC devices)
These bits are set and cleared by software.
0: WKUPx pin is used for general purpose I/O. An event on the WKUPx pin does not wake-
up the device from Standby mode.
1: WKUPx pin is used for wake-up from Standby mode and forced in input pull down
configuration (rising edge on WKUPx pin wakes-up the system from Standby mode).
Note: These bits are reset by a system Reset.
Bit 10 Reserved, must be kept at reset value.
Bits 9:8 EWUPx: Enable WKUPx pin
These bits are set and cleared by software.
0: WKUPx pin is used for general purpose I/O. An event on the WKUPx pin does not wakeup
the device from Standby mode.
1: WKUPx pin is used for wakeup from Standby mode and forced in input pull down
configuration (rising edge on WKUPx pin wakes-up the system from Standby mode).
Note: These bits are reset by a system Reset.
Bits 7:2 Reserved, must be kept at reset value.
Bit 1 SBF: Standby flag
This bit is set by hardware when the device enters Standby mode and it is cleared only by a
POR/PDR (power on reset/power down reset) or by setting the CSBF bit in the Power control
register (PWR_CR)
0: Device has not been in Standby mode
1: Device has been in Standby mode
Bit 0 WUF: Wake-up flag
This bit is set by hardware to indicate that the device received a wake-up event. It is cleared by
a system reset or by setting the CWUF bit in the Power control register (PWR_CR)
0: No wake-up event occurred
1: A wake-up event was received from one of the enabled WKUPx pins or from the RTC
alarm.
Note: An additional wake-up event is detected if one WKUPx pin is enabled (by setting the
EWUPx bit) when its pin level is already high.

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6.4.3 PWR register map

The following table summarizes the PWR register map and reset values.

Table 20. PWR register map and reset values

Offset Register 31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12

10
11

9
8
7
6
5
4
3
2
1
0
CWUF
PDDS
CSBF

LPDS
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
PWR_CR
0x000
Reset value 0 0 0 0

(1)

(1)

(1)

EWUP4(1)

EWUP2
EWUP1
EWUP7
EWUP6
EWUP5

WUF
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.

Res.
Res.
Res.
Res.
Res.
Res.
SBF
PWR_CSR
0x004

Reset value 0 0 0 0 0 0 0 0

1. Available on STM32F070xB and STM32F030xC devices only.

Refer to Section 2.2 on page 37 for the register boundary addresses.

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7 Reset and clock control (RCC)

7.1 Reset
There are three types of reset, defined as system reset, power reset and RTC domain reset.

7.1.1 Power reset

A power reset is generated when one of the following events occurs:
1. Power-on/power-down reset (POR/PDR reset)
2. When exiting Standby mode
A power reset sets all registers to their reset values.

7.1.2 System reset

System reset sets each register to its reset value, unless otherwise specified in the register
description.
A system reset is generated when one of the following events occurs:
1. A low level on the NRST pin (external reset)
2. Window watchdog event (WWDG reset)
3. Independent watchdog event (IWDG reset)
4. A software reset (SW reset) (see Software reset)
5. Low-power management reset (see Low-power management reset)
6. Option byte loader reset (see Option byte loader reset)
7. A power reset
The reset source can be identified by checking the reset flags in the Control/Status register,
RCC_CSR (see Section 7.4.10: Control/status register (RCC_CSR)).
These sources act on the NRST pin and it is always kept low during the delay phase. The
RESET service routine vector is fixed at address 0x0000_0004 in the memory map.
The system reset signal provided to the device is output on the NRST pin. The pulse
generator guarantees a minimum reset pulse duration of 20 µs for each internal reset
source. In case of an external reset, the reset pulse is generated while the NRST pin is
asserted low.

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Figure 9. Simplified diagram of the reset circuit

V DD

R PU
External
reset Filter System reset
NRST

WWDG reset
IWDG reset
Pulse Power reset
generator Software reset
(min 20 μs) Low-power management reset
Option byte loader reset
Exit from Standby mode

MS19841V4

Software reset
The SYSRESETREQ bit in Arm® Cortex®-M0 Application Interrupt and Reset Control
Register must be set to force a software reset on the device. Refer to the Cortex™-M0
technical reference manual for more details.

Low-power management reset

There are two ways to generate a low-power management reset:
1. Reset generated when entering Standby mode:
This type of reset is enabled by resetting nRST_STDBY bit in User Option Bytes. In this
case, whenever a Standby mode entry sequence is successfully executed, the device
is reset instead of entering Standby mode.
2. Reset when entering Stop mode:
This type of reset is enabled by resetting nRST_STOP bit in User Option Bytes. In this
case, whenever a Stop mode entry sequence is successfully executed, the device is
reset instead of entering Stop mode.
For further information on the User Option Bytes, refer to Section 4: Option bytes.

Option byte loader reset

The option byte loader reset is generated when the OBL_LAUNCH bit (bit 13) is set in the
FLASH_CR register. This bit is used to launch the option byte loading by software.

7.1.3 RTC domain reset

An RTC domain reset only affects the LSE oscillator, the RTC and the RCC RTC domain
control register (RCC_BDCR). It is generated when one of the following events occurs.
1. Software reset, triggered by setting the BDRST bit in the RTC domain control register
(RCC_BDCR).
2. A POR reset.

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7.2 Clocks
Various clock sources can be used to drive the system clock (SYSCLK):
• HSI 8 MHz RC oscillator clock
• HSE oscillator clock
• PLL clock
The devices have the following additional clock sources:
• 40 kHz low speed internal RC (LSI RC) which drives the independent watchdog and
optionally the RTC used for Auto-wake-up from Stop/Standby mode.
• 32.768 kHz low speed external crystal (LSE crystal) which optionally drives the real-
time clock (RTCCLK)
• 14 MHz high speed internal RC (HSI14) dedicated for ADC.
Each clock source can be switched on or off independently when it is not used, to optimize
power consumption.
Several prescalers can be used to configure the frequency of the AHB and the APB
domains. The AHB and the APB domains maximum frequency is 48 MHz.
All the peripheral clocks are derived from their bus clock (HCLK for AHB or PCLK for APB)
except:
• The Flash memory programming interface clock (FLITFCLK) which is always the HSI
clock.
• The option byte loader clock which is always the HSI clock
• The ADC clock which is derived (selected by software) from one of the two following
sources:
– dedicated HSI14 clock, to run always at the maximum sampling rate
– APB clock (PCLK) divided by 2 or 4
• The USART1 clock which is derived (selected by software) from one of the four
following sources:
– system clock
– HSI clock
– LSE clock
– APB clock (PCLK)
• The I2C1 clock which is derived (selected by software) from one of the two following
sources:
– system clock
– HSI clock
• The USB clock which is derived (selected by software) from the following source:
– PLL clock
• The RTC clock which is derived from the LSE, LSI or from the HSE clock divided by 32.
• The timer clock frequencies are automatically fixed by hardware. There are two cases:
– if the APB prescaler is 1, the timer clock frequencies are set to the same
frequency as that of the APB domain;
– otherwise, they are set to twice (x2) the frequency of the APB domain.
• The IWDG clock which is always the LSI clock.

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The RCC feeds the Cortex System Timer (SysTick) external clock with the AHB clock
(HCLK) divided by 8. The SysTick can work either with this clock or directly with the Cortex
clock (HCLK), configurable in the SysTick Control and Status Register.

Figure 10. Clock tree (STM32F030x4, STM32F030x6 and STM32F030x8 devices)

FLITFCLK Flash memory

programming
I2C1SW interface
8 MHz HSI HSI HSI
HSI RC I2C1
SYSCLK

/2

AHB, core, memory, DMA,

HCLK Cortex FCLK free-run clock
SW SYSCLK
PLLSRC PLLMUL Cortex
/8
HSI system timer
PLL /1,/2,… /1,/2,/4, PCLK
PLLCLK APB
x2,x3,.. …/512 /8,/16
HSE peripherals
...x16
PREDIV
HPRE PPRE
/1,/2,..
CSS
../16 PPRE

x1, x2 TIM1,3,6(2)
OSC_OUT HSE 14,15(2),16,17
4-32 MHz CKMODE
HSE OSC
OSC_IN /2, /4
ADC
LSE 14 MHz (14 MHz max)
HSI14 RC
/32
OSC32_IN RTCCLK USART1SW
32.768 kHz LSE PCLK
LSE OSC SYSCLK
OSC32_OUT USART1
HSI
RTCSEL LSE
40 kHz LSI RTC
LSI RC
PLLNODIV IWDG
(1)
MCOPRE (1)
/1 ,/2 PLLCLK
Main clock HSI
output HSI14
/1,/2,/4,..
MCO ../128 HSE Legend
SYSCLK
LSI(1) black clock tree element
LSE(1)
white clock tree control element
MCO clock line
control line

MSv32138V3
1. Applies to STM32F030x4/x6 devices.
2. Applies to STM32F030x8 devices.

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Figure 11. Clock tree (STM32F070x6, STM32F070xB and STM32F030xC)

FLITFCLK Flash memory
programming
I2C1SW interface
8 MHz HSI HSI HSI
HSI RC I2C1
SYSCLK

AHB, core, memory, DMA,

HCLK Cortex FCLK free-run clock
PREDIV
SW SYSCLK
PLLSRC PLLMUL Cortex
/8
HSI system timer
PLL /1,/2,… /1,/2,/4, PCLK
/1,/2,.. PLLCLK APB
x2,x3,.. …/512 /8,/16
../16 HSE peripherals
...x16
HPRE PPRE

CSS
PPRE

x1, x2 TIM1,3,6,7
OSC_OUT HSE 14,15,16,17
4-32 MHz
HSE OSC USART1SW
OSC_IN PCLK
LSE SYSCLK
USART1
HSI
/32 LSE
OSC32_IN RTCCLK
32.768 kHz LSE RTC
LSE OSC
OSC32_OUT
RTCSEL USB

40 kHz LSI IWDG

LSI RC
PLLNODIV ADC
14 MHz HSI14
HSI14 RC asynchronous
MCOPRE PLLCLK clock input
/1,/2
Main clock HSI
output HSI14
/1,/2,/4,..
MCO ../128 HSE Legend
SYSCLK
LSI black clock tree element
LSE
white clock tree control element
to TIM14
MCO clock line
control line

MSv35598V2

FCLK acts as Arm® Cortex®-M0’s free-running clock. For more details refer to the Arm
Cortex-M0 r0p0 technical reference manual (TRM).

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7.2.1 HSE clock

The high speed external clock signal (HSE) can be generated from two possible clock
sources:
• HSE external crystal/ceramic resonator
• HSE user external clock
The resonator and the load capacitors have to be placed as close as possible to the
oscillator pins in order to minimize output distortion and startup stabilization time. The
loading capacitance values must be adjusted according to the selected oscillator.

Figure 12. HSE/ LSE clock sources

Clock source Hardware configuration

OSC_IN OSC_OUT
External clock

GPIO
External
source
MSv31915V1

OSC_IN OSC_OUT

Crystal/Ceramic
resonators
CL1 CL2
Load
capacitors
MSv31916V1

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External crystal/ceramic resonator (HSE crystal)

The 4 to 32 MHz external oscillator has the advantage of producing a very accurate rate on
the main clock.
The associated hardware configuration is shown in Figure 12. Refer to the electrical
characteristics section of the datasheet for more details.
The HSERDY flag in the Clock control register (RCC_CR) indicates if the HSE oscillator is
stable or not. At startup, the clock is not released until this bit is set by hardware. An
interrupt can be generated if enabled in the Clock interrupt register (RCC_CIR).
The HSE Crystal can be switched on and off using the HSEON bit in the Clock control
register (RCC_CR).
For code example refer to the Appendix section A.3.1: HSE start sequence.
Caution: To switch ON the HSE oscillator, 512 HSE clock pulses need to be seen by an internal
stabilization counter after the HSEON bit is set. Even in the case that no crystal or resonator
is connected to the device, excessive external noise on the OSC_IN pin may still lead the
oscillator to start. Once the oscillator is started, it needs another 6 HSE clock pulses to
complete a switching OFF sequence. If for any reason the oscillations are no more present
on the OSC_IN pin, the oscillator cannot be switched OFF, locking the OSC pins from any
other use and introducing unwanted power consumption. To avoid such situation, it is
strongly recommended to always enable the Clock Security System (CSS) which is able to
switch OFF the oscillator even in this case.

External source (HSE bypass)

In this mode, an external clock source must be provided. It can have a frequency of up to
32 MHz. You select this mode by setting the HSEBYP and HSEON bits in the Clock control
register (RCC_CR). The external clock signal (square, sinus or triangle) with ~40-60% duty
cycle depending on the frequency (refer to the datasheet) has to drive the OSC_IN pin while
the OSC_OUT pin can be used a GPIO. See Figure 12.

7.2.2 HSI clock

The HSI clock signal is generated from an internal 8 MHz RC oscillator and can be used
directly as a system clock or for PLL input
The HSI RC oscillator has the advantage of providing a clock source at low cost (no external
components). It also has a faster startup time than the HSE crystal oscillator however, even
with calibration the frequency is less accurate than an external crystal oscillator or ceramic
resonator.

Calibration
RC oscillator frequencies can vary from one chip to another due to manufacturing process
variations, this is why each device is factory calibrated by ST for 1% accuracy at TA=25°C.
After reset, the factory calibration value is loaded in the HSICAL[7:0] bits in the Clock control
register (RCC_CR).
If the application is subject to voltage or temperature variations this may affect the RC
oscillator speed. You can trim the HSI frequency in the application using the HSITRIM[4:0]
bits in the Clock control register (RCC_CR).

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For more details on how to measure the HSI frequency variation refer to Section 7.2.12:
Internal/external clock measurement with TIM14 on page 98.
The HSIRDY flag in the Clock control register (RCC_CR) indicates if the HSI RC is stable or
not. At startup, the HSI RC output clock is not released until this bit is set by hardware.
The HSI RC can be switched on and off using the HSION bit in the Clock control register
(RCC_CR).
The HSI signal can also be used as a backup source (Auxiliary clock) if the HSE crystal
oscillator fails. Refer to Section 7.2.7: Clock security system (CSS) on page 96.
Furthermore it is possible to drive the HSI clock to the MCO multiplexer. Then the clock
could be driven to the Timer 14 giving the ability to the user to calibrate the oscillator.

7.2.3 PLL
The internal PLL can be used to multiply the HSI and the HSE output clock frequency. Refer
to Figure 9: Simplified diagram of the reset circuit, Figure 12: HSE/ LSE clock sources and
Clock control register (RCC_CR).
The PLL configuration (selection of the input clock, predivider and multiplication factor) must
be done before enabling the PLL. Once the PLL is enabled, these parameters cannot be
changed.
To modify the PLL configuration, proceed as follows:
1. Disable the PLL by setting PLLON to 0.
2. Wait until PLLRDY is cleared. The PLL is now fully stopped.
3. Change the desired parameter.
4. Enable the PLL again by setting PLLON to 1.
5. Wait until PLLRDY is set.
An interrupt can be generated when the PLL is ready, if enabled in the Clock interrupt
register (RCC_CIR).
The PLL output frequency must be set in the range 16-48 MHz.
For code example refer to the Appendix section A.3.2: PLL configuration modification.

7.2.4 LSE clock

The LSE crystal is a 32.768 kHz Low Speed External crystal or ceramic resonator. It has the
advantage of providing a low-power but highly accurate clock source to the real-time clock
peripheral (RTC) for clock/calendar or other timing functions.
The LSE crystal is switched on and off using the LSEON bit in RTC domain control register
(RCC_BDCR). The crystal oscillator driving strength can be changed at runtime using the
LSEDRV[1:0] bits in the RTC domain control register (RCC_BDCR) to obtain the best
compromise between robustness and short start-up time on one side and low-power
consumption on the other.
The LSERDY flag in the RTC domain control register (RCC_BDCR) indicates whether the
LSE crystal is stable or not. At startup, the LSE crystal output clock signal is not released
until this bit is set by hardware. An interrupt can be generated if enabled in the Clock
interrupt register (RCC_CIR).

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Caution: To switch ON the LSE oscillator, 4096 LSE clock pulses need to be seen by an internal
stabilization counter after the LSEON bit is set. Even in the case that no crystal or resonator
is connected to the device, excessive external noise on the OSC32_IN pin may still lead the
oscillator to start. Once the oscillator is started, it needs another 6 LSE clock pulses to
complete a switching OFF sequence. If for any reason the oscillations are no more present
on the OSC_IN pin, the oscillator cannot be switched OFF, locking the OSC32 pins from any
other use and introducing unwanted power consumption. The only way to recover such
situation is to perform the RTC domain reset by software.

External source (LSE bypass)

In this mode, an external clock source must be provided. It can have a frequency of up to
1 MHz. You select this mode by setting the LSEBYP and LSEON bits in the RTC domain
control register (RCC_BDCR). The external clock signal (square, sinus or triangle) with
~50% duty cycle has to drive the OSC32_IN pin while the OSC32_OUT pin can be used as
GPIO. See Figure 12.

7.2.5 LSI clock

The LSI RC acts as a low-power clock source that can be kept running in Stop and Standby
mode for the independent watchdog (IWDG) and RTC. The clock frequency is around 40
kHz. For more details, refer to the electrical characteristics section of the datasheets.
The LSI RC can be switched on and off using the LSION bit in the Control/status register
(RCC_CSR).
The LSIRDY flag in the Control/status register (RCC_CSR) indicates if the LSI oscillator is
stable or not. At startup, the clock is not released until this bit is set by hardware. An
interrupt can be generated if enabled in the Clock interrupt register (RCC_CIR).

7.2.6 System clock (SYSCLK) selection

Various clock sources can be used to drive the system clock (SYSCLK):
• HSI oscillator
• HSE oscillator
• PLL
After a system reset, the HSI oscillator is selected as system clock. When a clock source is
used directly or through the PLL as a system clock, it is not possible to stop it.
A switch from one clock source to another occurs only if the target clock source is ready
(clock stable after startup delay or PLL locked). If a clock source which is not yet ready is
selected, the switch will occur when the clock source becomes ready. Status bits in the
Clock control register (RCC_CR) indicate which clock(s) is (are) ready and which clock is
currently used as a system clock.

7.2.7 Clock security system (CSS)

Clock security system can be activated by software. In this case, the clock detector is
enabled after the HSE oscillator startup delay, and disabled when this oscillator is stopped.
If a failure is detected on the HSE clock, the HSE oscillator is automatically disabled, a clock
failure event is sent to the break input of the advanced-control timers (TIM1) and general-
purpose timers (TIM15, TIM16 and TIM17) and an interrupt is generated to inform the
software about the failure (clock security system interrupt, or CSSI), allowing the MCU to

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perform rescue operations. The CSSI is linked to the Arm® Cortex®-M0 NMI (Non-Maskable
Interrupt) exception vector.
Note: Once the CSS is enabled and if the HSE clock fails, the CSS interrupt occurs and an NMI is
automatically generated. The NMI is executed indefinitely unless the CSS interrupt pending
bit is cleared. As a consequence, in the NMI ISR user must clear the CSS interrupt by
setting the CSSC bit in the Clock interrupt register (RCC_CIR).
If the HSE oscillator is used directly or indirectly as the system clock (indirectly means: it is
used as PLL input clock, and the PLL clock is used as system clock), a detected failure
causes a switch of the system clock to the HSI oscillator and the disabling of the HSE
oscillator. If the HSE clock (divided or not) is the clock entry of the PLL used as system clock
when the failure occurs, the PLL is disabled too.

7.2.8 ADC clock

The ADC clock selection is done inside the ADC_CFGR2 (refer to Section 12.10.5: ADC
configuration register 2 (ADC_CFGR2) on page 220). It can be either the dedicated 14 MHz
RC oscillator (HSI14) connected on the ADC asynchronous clock input or PCLK divided by
2 or 4. The 14 MHz RC oscillator can be configured by software either to be turned on/off
(“auto-off mode”) by the ADC interface or to be always enabled. The HSI 14 MHz RC
oscillator cannot be turned on by ADC interface when the APB clock is selected as an ADC
kernel clock.

7.2.9 RTC clock

The RTCCLK clock source can be either the HSE/32, LSE or LSI clocks. This is selected by
programming the RTCSEL[1:0] bits in the RTC domain control register (RCC_BDCR). This
selection cannot be modified without resetting the RTC domain. The system must be always
configured in a way that the PCLK frequency is greater then or equal to the RTCCLK
frequency for proper operation of the RTC.

7.2.10 Independent watchdog clock

If the Independent watchdog (IWDG) is started by either hardware option or software
access, the LSI oscillator is forced ON and cannot be disabled. After the LSI oscillator
temporization, the clock is provided to the IWDG.

7.2.11 Clock-out capability

The microcontroller clock output (MCO) capability allows the clock to be output onto the
external MCO pin. The configuration registers of the corresponding GPIO port must be
programmed in alternate function mode. One of the following clock signals can be selected
as the MCO clock:
• HSI14
• SYSCLK
• HSI
• HSE
• PLL clock divided by 2 or direct (direct connection is not available on STM32F030x8
devices)
• LSE
• LSI

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The selection is controlled by the MCO[3:0] bits of the Clock configuration register
(RCC_CFGR).
For code example refer to the Appendix section A.3.3: MCO selection.
On STM32F030x4, STM32F030x6, STM32F070x6, STM32F070xB and STM32F030xC
devices, the additional bit PLLNODIV of this register controls the divider bypass for a PLL
clock input to MCO. The MCO frequency can be reduced by a configurable binary divider,
controlled by the MCOPRE[2..0] bits of the Clock configuration register (RCC_CFGR).

7.2.12 Internal/external clock measurement with TIM14

It is possible to indirectly measure the frequency of all on-board clock sources by mean of
the TIM14 channel 1 input capture. As represented on Figure 13.

Figure 13. Frequency measurement with TIM14 in capture mode

TIM14

TI1_RMP[1:0]
GPIO
RTCCLK TI1
HSE/32
MCO

MS31046V1

The input capture channel of the Timer 14 can be a GPIO line or an internal clock of the
MCU. This selection is performed through the TI1_RMP [1:0] bits in the TIM14_OR register.
The possibilities available are the following ones.
• TIM14 Channel1 is connected to the GPIO. Refer to the alternate function mapping in
the device datasheets.
• TIM14 Channel1 is connected to the RTCCLK.
• TIM14 Channel1 is connected to the HSE/32 Clock.
• TIM14 Channel1 is connected to the microcontroller clock output (MCO). Refer to
Section 7.2.11: Clock-out capability for MCO clock configuration.
For code example refer to the Appendix section A.3.4: Clock measurement configuration
with TIM14.

Calibration of the HSI

The primary purpose of connecting the LSE, through the MCO multiplexer, to the channel 1
input capture is to be able to precisely measure the HSI system clocks (for this, the HSI
should be used as the system clock source). The number of HSI clock counts between
consecutive edges of the LSE signal provides a measure of the internal clock period. Taking
advantage of the high precision of LSE crystals (typically a few tens of ppm), it is possible to
determine the internal clock frequency with the same resolution, and trim the source to
compensate for manufacturing-process- and/or temperature- and voltage-related frequency
deviations.
The HSI oscillator has dedicated user-accessible calibration bits for this purpose.

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The basic concept consists in providing a relative measurement (e.g. the HSI/LSE ratio): the
precision is therefore closely related to the ratio between the two clock sources. The higher
the ratio is, the better the measurement is.
If LSE is not available, HSE/32 is the better option in order to reach the most precise
calibration possible.

Calibration of the LSI

The calibration of the LSI will follow the same pattern that for the HSI, but changing the
reference clock. It is necessary to connect LSI clock to the channel 1 input capture of the
TIM14. Then define the HSE as system clock source, the number of its clock counts
between consecutive edges of the LSI signal provides a measure of the internal low speed
clock period.
The basic concept consists in providing a relative measurement (e.g. the HSE/LSI ratio): the
precision is therefore closely related to the ratio between the two clock sources. The higher
the ratio is, the better the measurement is.

Calibration of the HSI14

For the HSI14, because of its high frequency, it is not possible to have a precise resolution.
However a solution could be to clock Timer 14 with HSE through PLL to reach 48 MHz, and
to use the input capture line with the HSI14 and the capture prescaler defined to the higher
value. In that configuration, we got a ratio of 27 events. It is still a bit low to have an accurate
calibration. In order to increase the measure accuracy, it is advised to count the HSI periods
after multiple cycles of Timer 14. Using polling to treat the capture event is necessary in this
case.

7.3 Low-power modes

APB peripheral clocks and DMA clock can be disabled by software.
Sleep mode stops the CPU clock. The memory interface clocks (Flash and RAM interfaces)
can be stopped by software during sleep mode. The AHB to APB bridge clocks are disabled
by hardware during Sleep mode when all the clocks of the peripherals connected to them
are disabled.
Stop mode stops all the clocks in the core supply domain and disables the PLL and the HSI,
HSI14 and HSE oscillators.
Standby mode stops all the clocks in the core supply domain and disables the PLL and the
HSI, HSI14 and HSE oscillators.
The CPU’s deepsleep mode can be overridden for debugging by setting the DBG_STOP or
DBG_STANDBY bits in the DBGMCU_CR register.
When waking up from deepsleep after an interrupt (Stop mode) or reset (Standby mode),
the HSI oscillator is selected as system clock.
If a Flash programming operation is on going, deepsleep mode entry is delayed until the
Flash interface access is finished. If an access to the APB domain is ongoing, deepsleep
mode entry is delayed until the APB access is finished.

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7.4 RCC registers

Refer to Section 1.2 on page 33 for a list of abbreviations used in register descriptions.

7.4.1 Clock control register (RCC_CR)

Address offset: 0x00
Reset value: 0x0000 XX83 where X is undefined.
Access: no wait state, word, half-word and byte access

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

PLL CSS HSE HSE HSE

Res. Res. Res. Res. Res. Res. PLLON Res. Res. Res. Res.
RDY ON BYP RDY ON

r rw rw rw r rw

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

HSI
HSICAL[7:0] HSITRIM[4:0] Res. HSION
RDY

r r r r r r r r rw rw rw rw rw r rw

Bits 31:26 Reserved, must be kept at reset value.

Bit 25 PLLRDY: PLL clock ready flag
Set by hardware to indicate that the PLL is locked.
0: PLL unlocked
1: PLL locked
Bit 24 PLLON: PLL enable
Set and cleared by software to enable PLL.
Cleared by hardware when entering Stop or Standby mode. This bit can not be reset if the PLL
clock is used as system clock or is selected to become the system clock.
0: PLL OFF
1: PLL ON
Bits 23:20 Reserved, must be kept at reset value.
Bit 19 CSSON: Clock security system enable
Set and cleared by software to enable the clock security system. When CSSON is set, the
clock detector is enabled by hardware when the HSE oscillator is ready, and disabled by
hardware if a HSE clock failure is detected.
0: Clock security system disabled (clock detector OFF).
1: Clock security system enabled (clock detector ON if the HSE is ready, OFF if not).
Bit 18 HSEBYP: HSE crystal oscillator bypass
Set and cleared by software to bypass the oscillator with an external clock. The external clock
must be enabled with the HSEON bit set, to be used by the device. The HSEBYP bit can be
written only if the HSE oscillator is disabled.
0: HSE crystal oscillator not bypassed
1: HSE crystal oscillator bypassed with external clock

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Bit 17 HSERDY: HSE clock ready flag

Set by hardware to indicate that the HSE oscillator is stable. This bit needs 6 cycles of the HSE
oscillator clock to fall down after HSEON reset.
0: HSE oscillator not ready
1: HSE oscillator ready
Bit 16 HSEON: HSE clock enable
Set and cleared by software.
Cleared by hardware to stop the HSE oscillator when entering Stop or Standby mode. This bit
cannot be reset if the HSE oscillator is used directly or indirectly as the system clock.
0: HSE oscillator OFF
1: HSE oscillator ON
Bits 15:8 HSICAL[7:0]: HSI clock calibration
These bits are initialized automatically at startup. They are adjusted by SW through the
HSITRIM setting.
Bits 7:3 HSITRIM[4:0]: HSI clock trimming
These bits provide an additional user-programmable trimming value that is added to the
HSICAL[7:0] bits. It can be programmed to adjust to variations in voltage and temperature that
influence the frequency of the HSI.
The default value is 16, which, when added to the HSICAL value, should trim the HSI to 8 MHz
± 1%. The trimming step is around 40 kHz between two consecutive HSICAL steps.
Note: Increased value in the register results to higher clock frequency.
Bit 2 Reserved, must be kept at reset value.
Bit 1 HSIRDY: HSI clock ready flag
Set by hardware to indicate that HSI oscillator is stable. After the HSION bit is cleared,
HSIRDY goes low after 6 HSI oscillator clock cycles.
0: HSI oscillator not ready
1: HSI oscillator ready
Bit 0 HSION: HSI clock enable
Set and cleared by software.
Set by hardware to force the HSI oscillator ON when leaving Stop or Standby mode or in case
of failure of the HSE crystal oscillator used directly or indirectly as system clock. This bit
cannot be reset if the HSI is used directly or indirectly as system clock or is selected to become
the system clock.
0: HSI oscillator OFF
1: HSI oscillator ON

7.4.2 Clock configuration register (RCC_CFGR)

Address offset: 0x04
Reset value: 0x0000 0000
Access: 0 ≤ wait state ≤ 2, word, half-word and byte access
1 or 2 wait states inserted only if the access occurs during clock source switch.

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31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

PLL PLL PLL

MCOPRE[2:0] MCO[3:0] Res. Res. PLLMUL[3:0]
NODIV XTPRE SRC[1]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

PLL ADC
Res. Res. Res. PPRE[2:0] HPRE[3:0] SWS[1:0] SW[1:0]
SRC[0] PRE

rw rw rw rw rw rw rw rw rw r r rw rw

Bit 31 PLLNODIV: PLL clock not divided for MCO (not available on STM32F030x8 devices)
This bit is set and cleared by software. It switches off divider by 2 for PLL connection to MCO.
0: PLL is divided by 2 for MCO
1: PLL is not divided for MCO
Bits 30:28 MCOPRE[2:0]: Microcontroller clock output prescaler (not available on STM32F030x8
devices)
These bits are set and cleared by software to select the MCO prescaler division factor. To
avoid glitches, it is highly recommended to change this prescaler only when the MCO output is
disabled.
000: MCO is divided by 1
001: MCO is divided by 2
010: MCO is divided by 4
.....
111: MCO is divided by 128
Bits 27:24 MCO[3:0]: Microcontroller clock output
Set and cleared by software.
0000: MCO output disabled, no clock on MCO
0001: Internal RC 14 MHz (HSI14) oscillator clock selected
0010: Internal low speed (LSI) oscillator clock selected
0011: External low speed (LSE) oscillator clock selected
0100: System clock selected
0101: Internal RC 8 MHz (HSI) oscillator clock selected
0110: External 4-32 MHz (HSE) oscillator clock selected
0111: PLL clock selected (divided by 1 or 2, depending on PLLNODIV)
1xxx: Reserved, must be kept at reset value.
Note: This clock output may have some truncated cycles at startup or during MCO clock
source switching.
Bits 23:22 Reserved, must be kept at reset value.

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Bits 21:18 PLLMUL[3:0]: PLL multiplication factor

These bits are written by software to define the PLL multiplication factor. These bits can be
written only when PLL is disabled.
Caution: The PLL output frequency must not exceed 48 MHz.
0000: PLL input clock x 2
0001: PLL input clock x 3
0010: PLL input clock x 4
0011: PLL input clock x 5
0100: PLL input clock x 6
0101: PLL input clock x 7
0110: PLL input clock x 8
0111: PLL input clock x 9
1000: PLL input clock x 10
1001: PLL input clock x 11
1010: PLL input clock x 12
1011: PLL input clock x 13
1100: PLL input clock x 14
1101: PLL input clock x 15
1110: PLL input clock x 16
1111: PLL input clock x 16
Bit 17 PLLXTPRE: HSE divider for PLL input clock
This bit is the same bit as bit PREDIV[0] from RCC_CFGR2. Refer to RCC_CFGR2 PREDIV
bits description for its meaning.
Bits 16:15 PLLSRC[1:0]: PLL input clock source
Set and cleared by software to select PLL or PREDIV clock source. These bits can be written
only when PLL is disabled.
00: HSI/2 selected as PLL input clock (PREDIV forced to divide by 2 on STM32F070xx and
STM32F030xC devices)
01: HSI/PREDIV selected as PLL input clock
10: HSE/PREDIV selected as PLL input clock
11: Reserved
Bit PLLSRC[0] is available only on STM32F070xx and STM32F030xC devices, otherwise it is
reserved (with value zero).
Bit 14 ADCPRE: ADC prescaler
Obsolete setting. Proper ADC clock selection is done inside the ADC_CFGR2 (refer to
Section 12.10.5: ADC configuration register 2 (ADC_CFGR2) on page 220).
Bits 13:11 Reserved, must be kept at reset value.
Bits 10:8 PPRE[2:0]: PCLK prescaler
Set and cleared by software to control the division factor of the APB clock (PCLK).
0xx: HCLK not divided
100: HCLK divided by 2
101: HCLK divided by 4
110: HCLK divided by 8
111: HCLK divided by 16

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Bits 7:4 HPRE[3:0]: HCLK prescaler

Set and cleared by software to control the division factor of the AHB clock.
0xxx: SYSCLK not divided
1000: SYSCLK divided by 2
1001: SYSCLK divided by 4
1010: SYSCLK divided by 8
1011: SYSCLK divided by 16
1100: SYSCLK divided by 64
1101: SYSCLK divided by 128
1110: SYSCLK divided by 256
1111: SYSCLK divided by 512
Bits 3:2 SWS[1:0]: System clock switch status
Set and cleared by hardware to indicate which clock source is used as system clock.
00: HSI oscillator used as system clock
01: HSE oscillator used as system clock
10: PLL used as system clock
11: Reserved, must be kept at reset value.
Bits 1:0 SW[1:0]: System clock switch
Set and cleared by software to select SYSCLK source.
Cleared by hardware to force HSI selection when leaving Stop and Standby mode or in case
of failure of the HSE oscillator used directly or indirectly as system clock (if the Clock Security
System is enabled).
00: HSI selected as system clock
01: HSE selected as system clock
10: PLL selected as system clock
11: Reserved, must be kept at reset value.

7.4.3 Clock interrupt register (RCC_CIR)

Address offset: 0x08
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

HSI14 PLL HSE HSI LSE LSI

Res. Res. Res. Res. Res. Res. Res. Res. CSSC Res.
RDYC RDYC RDYC RDYC RDYC RDYC

w w w w w w w

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

HSI14 PLL HSE HSI LSE LSI HSI14 PLL HSE HSI LSE LSI
Res. Res. CSSF Res.
RDYIE RDYIE RDYIE RDYIE RDYIE RDYIE RDYF RDYF RDYF RDYF RDYF RDYF

rw rw rw rw rw rw r r r r r r r

Bits 31:24 Reserved, must be kept at reset value.

Bit 23 CSSC: Clock security system interrupt clear
This bit is set by software to clear the CSSF flag.
0: No effect
1: Clear CSSF flag

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Bit 22
Reserved, must be kept at reset value.
Bit 21 HSI14RDYC: HSI14 ready interrupt clear
This bit is set by software to clear the HSI14RDYF flag.
0: No effect
1: Clear HSI14RDYF flag
Bit 20 PLLRDYC: PLL ready interrupt clear
This bit is set by software to clear the PLLRDYF flag.
0: No effect
1: Clear PLLRDYF flag
Bit 19 HSERDYC: HSE ready interrupt clear
This bit is set by software to clear the HSERDYF flag.
0: No effect
1: Clear HSERDYF flag
Bit 18 HSIRDYC: HSI ready interrupt clear
This bit is set software to clear the HSIRDYF flag.
0: No effect
1: Clear HSIRDYF flag
Bit 17 LSERDYC: LSE ready interrupt clear
This bit is set by software to clear the LSERDYF flag.
0: No effect
1: LSERDYF cleared
Bit 16 LSIRDYC: LSI ready interrupt clear
This bit is set by software to clear the LSIRDYF flag.
0: No effect
1: LSIRDYF cleared
Bits 15:14 Reserved, must be kept at reset value.
Bit 13 HSI14RDYIE: HSI14 ready interrupt enable
Set and cleared by software to enable/disable interrupt caused by the HSI14 oscillator
stabilization.
0: HSI14 ready interrupt disabled
1: HSI14 ready interrupt enabled
Bit 12 PLLRDYIE: PLL ready interrupt enable
Set and cleared by software to enable/disable interrupt caused by PLL lock.
0: PLL lock interrupt disabled
1: PLL lock interrupt enabled
Bit 11 HSERDYIE: HSE ready interrupt enable
Set and cleared by software to enable/disable interrupt caused by the HSE oscillator
stabilization.
0: HSE ready interrupt disabled
1: HSE ready interrupt enabled
Bit 10 HSIRDYIE: HSI ready interrupt enable
Set and cleared by software to enable/disable interrupt caused by the HSI oscillator
stabilization.
0: HSI ready interrupt disabled
1: HSI ready interrupt enabled

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Bit 9 LSERDYIE: LSE ready interrupt enable

Set and cleared by software to enable/disable interrupt caused by the LSE oscillator
stabilization.
0: LSE ready interrupt disabled
1: LSE ready interrupt enabled
Bit 8 LSIRDYIE: LSI ready interrupt enable
Set and cleared by software to enable/disable interrupt caused by the LSI oscillator
stabilization.
0: LSI ready interrupt disabled
1: LSI ready interrupt enabled
Bit 7 CSSF: Clock security system interrupt flag
Set by hardware when a failure is detected in the HSE oscillator.
Cleared by software setting the CSSC bit.
0: No clock security interrupt caused by HSE clock failure
1: Clock security interrupt caused by HSE clock failure
Bit 6
Reserved, must be kept at reset value.
Bit 5 HSI14RDYF: HSI14 ready interrupt flag
Set by hardware when the HSI14 becomes stable and HSI14RDYDIE is set in a response to
setting the HSI14ON bit in Clock control register 2 (RCC_CR2). When HSI14ON is not set
but the HSI14 oscillator is enabled by the peripheral through a clock request, this bit is not set
and no interrupt is generated.
Cleared by software setting the HSI14RDYC bit.
0: No clock ready interrupt caused by the HSI14 oscillator
1: Clock ready interrupt caused by the HSI14 oscillator
Bit 4 PLLRDYF: PLL ready interrupt flag
Set by hardware when the PLL locks and PLLRDYDIE is set.
Cleared by software setting the PLLRDYC bit.
0: No clock ready interrupt caused by PLL lock
1: Clock ready interrupt caused by PLL lock
Bit 3 HSERDYF: HSE ready interrupt flag
Set by hardware when the HSE clock becomes stable and HSERDYDIE is set.
Cleared by software setting the HSERDYC bit.
0: No clock ready interrupt caused by the HSE oscillator
1: Clock ready interrupt caused by the HSE oscillator
Bit 2 HSIRDYF: HSI ready interrupt flag
Set by hardware when the HSI clock becomes stable and HSIRDYDIE is set in a response to
setting the HSION (refer to Clock control register (RCC_CR)). When HSION is not set but the
HSI oscillator is enabled by the peripheral through a clock request, this bit is not set and no
interrupt is generated.
Cleared by software setting the HSIRDYC bit.
0: No clock ready interrupt caused by the HSI oscillator
1: Clock ready interrupt caused by the HSI oscillator

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Bit 1 LSERDYF: LSE ready interrupt flag

Set by hardware when the LSE clock becomes stable and LSERDYDIE is set.
Cleared by software setting the LSERDYC bit.
0: No clock ready interrupt caused by the LSE oscillator
1: Clock ready interrupt caused by the LSE oscillator
Bit 0 LSIRDYF: LSI ready interrupt flag
Set by hardware when the LSI clock becomes stable and LSIRDYDIE is set.
Cleared by software setting the LSIRDYC bit.
0: No clock ready interrupt caused by the LSI oscillator
1: Clock ready interrupt caused by the LSI oscillator

7.4.4 APB peripheral reset register 2 (RCC_APB2RSTR)

Address offset: 0x0C
Reset value: 0x00000 0000
Access: no wait state, word, half-word and byte access

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

DBGMCU TIM17 TIM16 TIM15

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
RST RST RST RST

rw rw rw rw

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

USART1 SPI1 TIM1 ADC USART6 SYSCFG

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
RST RST RST RST RST RST

rw rw rw rw rw rw

Bits 31:23 Reserved, must be kept at reset value.

Bit 22 DBGMCURST: Debug MCU reset
Set and cleared by software.
0: No effect
1: Reset Debug MCU
Bits 21:19 Reserved, must be kept at reset value.
Bit 18 TIM17RST: TIM17 timer reset
Set and cleared by software.
0: No effect
1: Reset TIM17 timer
Bit 17 TIM16RST: TIM16 timer reset
Set and cleared by software.
0: No effect
1: Reset TIM16 timer
Bit 16 TIM15RST: TIM15 timer reset
Set and cleared by software.
0: No effect
1: Reset TIM15 timer
Bit 15 Reserved, must be kept at reset value.

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Bit 14 USART1RST: USART1 reset

Set and cleared by software.
0: No effect
1: Reset USART1
Bit 13 Reserved, must be kept at reset value.
Bit 12 SPI1RST: SPI1 reset
Set and cleared by software.
0: No effect
1: Reset SPI1
Bit 11 TIM1RST: TIM1 timer reset
Set and cleared by software.
0: No effect
1: Reset TIM1 timer
Bit 10 Reserved, must be kept at reset value.
Bit 9 ADCRST: ADC interface reset
Set and cleared by software.
0: No effect
1: Reset ADC interface
Bits 8:6 Reserved, must be kept at reset value.
Bit 5 USART6RST: USART6 reset
Set and cleared by software
0: No effect
1: Reset USART6
Bits 4:1 Reserved, must be kept at reset value.
Bit 0 SYSCFGRST: SYSCFG reset
Set and cleared by software.
0: No effect
1: Reset SYSCFG

7.4.5 APB peripheral reset register 1 (RCC_APB1RSTR)

Address offset: 0x10
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

PWR USB I2C2 I2C1 USART5 USART4 USART3 USART2

Res. Res. Res. Res. Res. Res. Res. Res.
RST RST RST RST RST RST RST RST

rw rw rw rw rw rw rw rw

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

SPI2 WWDG TIM14 TIM7 TIM6 TIM3

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
RST RST RST RST RST RST

rw rw rw rw rw rw

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Bits 31:29 Reserved, must be kept at reset value.

Bit 28 PWRRST: Power interface reset
Set and cleared by software.
0: No effect
1: Reset power interface
Bits 27:24 Reserved, must be kept at reset value.
Bit 23 USBRST: USB interface reset
Set and cleared by software.
0: No effect
1: Reset USB interface
Bit 22 I2C2RST: I2C2 reset
Set and cleared by software.
0: No effect
1: Reset I2C2
Bit 21 I2C1RST: I2C1 reset
Set and cleared by software.
0: No effect
1: Reset I2C1
Bit 20 USART5RST: USART5 reset
Set and cleared by software.
0: No effect
1: Reset USART4
Bit 19 USART4RST: USART4 reset
Set and cleared by software.
0: No effect
1: Reset USART4
Bit 18 USART3RST: USART3 reset
Set and cleared by software.
0: No effect
1: Reset USART3
Bit 17 USART2RST: USART2 reset
Set and cleared by software.
0: No effect
1: Reset USART2
Bits 16:15 Reserved, must be kept at reset value.
Bit 14 SPI2RST: SPI2 reset
Set and cleared by software.
0: No effect
1: Reset SPI2
Bits 13:12 Reserved, must be kept at reset value.
Bit 11 WWDGRST: Window watchdog reset
Set and cleared by software.
0: No effect
1: Reset window watchdog

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Reset and clock control (RCC) RM0360

Bits 10:9 Reserved, must be kept at reset value.

Bit 8 TIM14RST: TIM14 timer reset
Set and cleared by software.
0: No effect
1: Reset TIM14
Bits 7:6 Reserved, must be kept at reset value.
Bit 5 TIM7RST: TIM7 timer reset
Set and cleared by software.
0: No effect
1: Reset TIM7
Bit 4 TIM6RST: TIM6 timer reset
Set and cleared by software.
0: No effect
1: Reset TIM6
Bits 3:2 Reserved, must be kept at reset value.
Bit 1 TIM3RST: TIM3 timer reset
Set and cleared by software.
0: No effect
1: Reset TIM3
Bit 0 Reserved, must be kept at reset value.

7.4.6 AHB peripheral clock enable register (RCC_AHBENR)

Address offset: 0x14
Reset value: 0x0000 0014
Access: no wait state, word, half-word and byte access
Note: When the peripheral clock is not active, the peripheral register values may not be readable
by software and the returned value is always 0x0.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

GPIOF GPIOD GPIOC GPIOB GPIOA

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
EN EN EN EN EN

rw rw rw rw rw

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

CRC FLITF SRAM DMA

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
EN EN EN EN

rw rw rw rw

Bits 31:23 Reserved, must be kept at reset value.

Bit 22 GPIOFEN: I/O port F clock enable
Set and cleared by software.
0: I/O port F clock disabled
1: I/O port F clock enabled
Bit 21 Reserved, must be kept at reset value.

110/775 RM0360 Rev 5

RM0360 Reset and clock control (RCC)

Bit 20 GPIODEN: I/O port D clock enable

Set and cleared by software.
0: I/O port D clock disabled
1: I/O port D clock enabled
Bit 19 GPIOCEN: I/O port C clock enable
Set and cleared by software.
0: I/O port C clock disabled
1: I/O port C clock enabled
Bit 18 GPIOBEN: I/O port B clock enable
Set and cleared by software.
0: I/O port B clock disabled
1: I/O port B clock enabled
Bit 17 GPIOAEN: I/O port A clock enable
Set and cleared by software.
0: I/O port A clock disabled
1: I/O port A clock enabled
Bits 16:7 Reserved, must be kept at reset value.
Bit 6 CRCEN: CRC clock enable
Set and cleared by software.
0: CRC clock disabled
1: CRC clock enabled
Bit 5 Reserved, must be kept at reset value.
Bit 4 FLITFEN: FLITF clock enable
Set and cleared by software to disable/enable FLITF clock during Sleep mode.
0: FLITF clock disabled during Sleep mode
1: FLITF clock enabled during Sleep mode
Bit 3 Reserved, must be kept at reset value.
Bit 2 SRAMEN: SRAM interface clock enable
Set and cleared by software to disable/enable SRAM interface clock during Sleep mode.
0: SRAM interface clock disabled during Sleep mode.
1: SRAM interface clock enabled during Sleep mode
Bit 1 Reserved, must be kept at reset value.
Bit 0 DMAEN: DMA clock enable
Set and cleared by software.
0: DMA clock disabled
1: DMA clock enabled

7.4.7 APB peripheral clock enable register 2 (RCC_APB2ENR)

Address: 0x18
Reset value: 0x0000 0000
Access: word, half-word and byte access
No wait states, except if the access occurs while an access to a peripheral in the APB
domain is on going. In this case, wait states are inserted until the access to APB peripheral
is finished.

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Reset and clock control (RCC) RM0360

Note: When the peripheral clock is not active, the peripheral register values may not be readable
by software and the returned value is always 0x0.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

DBG TIM17 TIM16 TIM15

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
MCUEN EN EN EN

rw rw rw rw

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

USART1 SPI1 TIM1 ADC USART6 SYSCFG

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
EN EN EN EN EN COMPEN

rw rw rw rw rw rw

Bits 31:23 Reserved, must be kept at reset value.

Bit 22 DBGMCUEN MCU debug module clock enable
Set and reset by software.
0: MCU debug module clock disabled
1: MCU debug module enabled
Bits 21:19 Reserved, must be kept at reset value.
Bit 18 TIM17EN: TIM17 timer clock enable
Set and cleared by software.
0: TIM17 timer clock disabled
1: TIM17 timer clock enabled
Bit 17 TIM16EN: TIM16 timer clock enable
Set and cleared by software.
0: TIM16 timer clock disabled
1: TIM16 timer clock enabled
Bit 16 TIM15EN: TIM15 timer clock enable
Set and cleared by software.
0: TIM15 timer clock disabled
1: TIM15 timer clock enabled
Bit 15 Reserved, must be kept at reset value.
Bit 14 USART1EN: USART1 clock enable
Set and cleared by software.
0: USART1clock disabled
1: USART1clock enabled
Bit 13 Reserved, must be kept at reset value.
Bit 12 SPI1EN: SPI1 clock enable
Set and cleared by software.
0: SPI1 clock disabled
1: SPI1 clock enabled
Bit 11 TIM1EN: TIM1 timer clock enable
Set and cleared by software.
0: TIM1 timer clock disabled
1: TIM1P timer clock enabled

112/775 RM0360 Rev 5

RM0360 Reset and clock control (RCC)

Bit 10 Reserved, must be kept at reset value.

Bit 9 ADCEN: ADC interface clock enable
Set and cleared by software.
0: ADC interface disabled
1: ADC interface clock enabled
Bits 8:6 Reserved, must be kept at reset value.
Bit 5 USART6EN: USART6 clock enable
Set and cleared by software.
0: USART6clock disabled
1: USART6clock enabled
Bits 4:1 Reserved, must be kept at reset value.
Bit 0 SYSCFGEN: SYSCFG clock enable
Set and cleared by software.
0: SYSCFG clock disabled
1: SYSCFG clock enabled

7.4.8 APB peripheral clock enable register 1 (RCC_APB1ENR)

Address: 0x1C
Reset value: 0x0000 0000
Access: word, half-word and byte access
No wait state, except if the access occurs while an access to a peripheral on APB domain is
on going. In this case, wait states are inserted until this access to APB peripheral is finished.
Note: When the peripheral clock is not active, the peripheral register values may not be readable
by software and the returned value is always 0x0.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

PWR USB I2C2 I2C1 USART5 USART4 USART3 USART2

Res. Res. Res. Res. Res. Res. Res. Res.
EN EN EN EN EN EN EN EN

rw rw rw rw rw rw rw rw

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

SPI2 WWDG TIM14 TIM7 TIM6 TIM3

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
EN EN EN EN EN EN

rw rw rw rw rw rw

Bits 31:29 Reserved, must be kept at reset value.

Bit 28 PWREN: Power interface clock enable
Set and cleared by software.
0: Power interface clock disabled
1: Power interface clock enabled
Bits 27:24 Reserved, must be kept at reset value.

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Reset and clock control (RCC) RM0360

Bit 23 USBEN: USB interface clock enable

Set and cleared by software.
0: USB interface clock disabled
1: USB interface clock enabled
Bit 22 I2C2EN: I2C2 clock enable
Set and cleared by software.
0: I2C2 clock disabled
1: I2C2 clock enabled
Bit 21 I2C1EN: I2C1 clock enable
Set and cleared by software.
0: I2C1 clock disabled
1: I2C1 clock enabled
Bit 20 USART5EN: USART5 clock enable
Set and cleared by software.
0: USART5 clock disabled
1: USART5 clock enabled
Bit 19 USART4EN: USART4 clock enable
Set and cleared by software.
0: USART4 clock disabled
1: USART4 clock enabled
Bit 18 USART3EN: USART3 clock enable
Set and cleared by software.
0: USART3 clock disabled
1: USART3 clock enabled
Bit 17 USART2EN: USART2 clock enable
Set and cleared by software.
0: USART2 clock disabled
1: USART2 clock enabled
Bits 16:15 Reserved, must be kept at reset value.
Bit 14 SPI2EN: SPI2 clock enable
Set and cleared by software.
0: SPI2 clock disabled
1: SPI2 clock enabled
Bits 13:12 Reserved, must be kept at reset value.
Bit 11 WWDGEN: Window watchdog clock enable
Set and cleared by software.
0: Window watchdog clock disabled
1: Window watchdog clock enabled
Bits 10:9 Reserved, must be kept at reset value.
Bit 8 TIM14EN: TIM14 timer clock enable
Set and cleared by software.
0: TIM14 clock disabled
1: TIM14 clock enabled
Bits 7:6 Reserved, must be kept at reset value.

114/775 RM0360 Rev 5

RM0360 Reset and clock control (RCC)

Bit 5 TIM7EN: TIM7 timer clock enable (not available on STM32F070x6, nor STM32F030x4/6/8/C
devices).
Set and cleared by software.
0: TIM7 clock disabled
1: TIM7 clock enabled
Bit 4 TIM6EN: TIM6 timer clock enable
Set and cleared by software.
0: TIM6 clock disabled
1: TIM6 clock enabled
Bits 3:2 Reserved, must be kept at reset value.
Bit 1 TIM3EN: TIM3 timer clock enable
Set and cleared by software.
0: TIM3 clock disabled
1: TIM3 clock enabled
Bit 0
Reserved, must be kept at reset value.

7.4.9 RTC domain control register (RCC_BDCR)

Address offset: 0x20
Reset value: 0x0000 0018, reset by RTC domain reset.
Access: 0 ≤ wait state ≤ 3, word, half-word and byte access
Wait states are inserted in case of successive accesses to this register.
Note: The LSEON, LSEBYP, RTCSEL and RTCEN bits of the RTC domain control register
(RCC_BDCR) are in the RTC domain. As a result, after reset, these bits are write-protected
and the DBP bit in the Power control register (PWR_CR) has to be set before they can be
modified. Refer to Section 6.1.2: Voltage regulator for further information. These bits are
only reset after a RTC domain reset (see Section 7.1.3: RTC domain reset). Any internal or
external reset does not have any effect on these bits.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. BDRST

rw

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RTC LSE LSE

Res. Res. Res. Res. Res. RTCSEL[1:0] Res. Res. Res. LSEDRV[1:0] LSEON
EN BYP RDY

rw rw rw rw rw rw r rw

Bits 31:17 Reserved, must be kept at reset value.

Bit 16 BDRST: RTC domain software reset
Set and cleared by software.
0: Reset not activated
1: Resets the entire RTC domain

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Reset and clock control (RCC) RM0360

Bit 15 RTCEN: RTC clock enable

Set and cleared by software.
0: RTC clock disabled
1: RTC clock enabled
Bits 14:10 Reserved, must be kept at reset value.
Bits 9:8 RTCSEL[1:0]: RTC clock source selection
Set by software to select the clock source for the RTC. Once the RTC clock source has been
selected, it cannot be changed anymore unless the RTC domain is reset. The BDRST bit can
be used to reset them.
00: No clock
01: LSE oscillator clock used as RTC clock
10: LSI oscillator clock used as RTC clock
11: HSE oscillator clock divided by 32 used as RTC clock
Bits 7:5 Reserved, must be kept at reset value.
Bits 4:3 LSEDRV LSE oscillator drive capability
Set and reset by software to modulate the LSE oscillator’s drive capability. A reset of the RTC
domain restores the default value.
00: ‘Xtal mode’ low drive capability
01: ‘Xtal mode’ medium-high drive capability
10: ‘Xtal mode’ medium-low drive capability
11: ‘Xtal mode’ high drive capability (reset value)
Note: The oscillator is in Xtal mode when it is not in bypass mode.
Bit 2 LSEBYP: LSE oscillator bypass
Set and cleared by software to bypass oscillator in debug mode. This bit can be written only
when the external 32 kHz oscillator is disabled.
0: LSE oscillator not bypassed
1: LSE oscillator bypassed
Bit 1 LSERDY: LSE oscillator ready
Set and cleared by hardware to indicate when the external 32 kHz oscillator is stable. After the
LSEON bit is cleared, LSERDY goes low after 6 external low-speed oscillator clock cycles.
0: LSE oscillator not ready
1: LSE oscillator ready
Bit 0 LSEON: LSE oscillator enable
Set and cleared by software.
0: LSE oscillator OFF
1: LSE oscillator ON

7.4.10 Control/status register (RCC_CSR)

Address: 0x24
Reset value: 0xXXX0 0000, reset by system Reset, except reset flags by power Reset only.
Access: 0 ≤ wait state ≤ 3, word, half-word and byte access
Wait states are inserted in case of successive accesses to this register.

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RM0360 Reset and clock control (RCC)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

LPWR WWDG IWDG SFT POR PIN OB V18PWR

RMVF Res. Res. Res. Res. Res. Res. Res.
RSTF RSTF RSTF RSTF RSTF RSTF LRSTF RSTF

r r r r r r r rt_w r

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

LSI
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. LSION
RDY

r rw

Bit 31 LPWRRSTF: Low-power reset flag

Set by hardware when a Low-power management reset occurs.
Cleared by writing to the RMVF bit.
0: No Low-power management reset occurred
1: Low-power management reset occurred
For further information refer to Low-power management reset.
Bit 30 WWDGRSTF: Window watchdog reset flag
Set by hardware when a window watchdog reset occurs.
Cleared by writing to the RMVF bit.
0: No window watchdog reset occurred
1: Window watchdog reset occurred
Bit 29 IWDGRSTF: Independent watchdog reset flag
Set by hardware when an independent watchdog reset from VDD domain occurs.
Cleared by writing to the RMVF bit.
0: No watchdog reset occurred
1: Watchdog reset occurred
Bit 28 SFTRSTF: Software reset flag
Set by hardware when a software reset occurs.
Cleared by writing to the RMVF bit.
0: No software reset occurred
1: Software reset occurred
Bit 27 PORRSTF: POR/PDR reset flag
Set by hardware when a POR/PDR reset occurs.
Cleared by writing to the RMVF bit.
0: No POR/PDR reset occurred
1: POR/PDR reset occurred
Bit 26 PINRSTF: PIN reset flag
Set by hardware when a reset from the NRST pin occurs.
Cleared by writing to the RMVF bit.
0: No reset from NRST pin occurred
1: Reset from NRST pin occurred
Bit 25 OBLRSTF: Option byte loader reset flag
Set by hardware when a reset from the OBL occurs.
Cleared by writing to the RMVF bit.
0: No reset from OBL occurred
1: Reset from OBL occurred

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Reset and clock control (RCC) RM0360

Bit 24 RMVF: Remove reset flag

Set by software to clear the reset flags including RMVF.
0: No effect
1: Clear the reset flags
Bit 23 V18PWRRSTF: Reset flag of the 1.8 V domain.
Set by hardware when a POR/PDR of the 1.8 V domain occurred.
Cleared by writing to the RMVF bit.
0: No POR/PDR reset of the 1.8 V domain occurred
1: POR/PDR reset of the 1.8 V domain occurred
Bits 22:2 Reserved, must be kept at reset value.
Bit 1 LSIRDY: LSI oscillator ready
Set and cleared by hardware to indicate when the LSI oscillator is stable. After the LSION bit is
cleared, LSIRDY goes low after 3 LSI oscillator clock cycles.
0: LSI oscillator not ready
1: LSI oscillator ready
Bit 0 LSION: LSI oscillator enable
Set and cleared by software.
0: LSI oscillator OFF
1: LSI oscillator ON

7.4.11 AHB peripheral reset register (RCC_AHBRSTR)

Address: 0x28
Reset value: 0x0000 0000
Access: no wait states, word, half-word and byte access

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

GPIO GPIO
GPIOF GPIOB GPIOA
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. D C Res.
RST RST RST
RST RST

rw rw rw rw rw

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

Bits 31:23 Reserved, must be kept at reset value.

Bit 22 GPIOFRST: I/O port F reset
Set and cleared by software.
0: No effect
1: Reset I/O port F
Bit 21
Reserved, must be kept at reset value.

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RM0360 Reset and clock control (RCC)

Bit 20 GPIODRST: I/O port D reset

Set and cleared by software.
0: No effect
1: Reset I/O port D
Bit 19 GPIOCRST: I/O port C reset
Set and cleared by software.
0: No effect
1: Reset I/O port C
Bit 18 GPIOBRST: I/O port B reset
Set and cleared by software.
0: No effect
1: Reset I/O port B
Bit 17 GPIOARST: I/O port A reset
Set and cleared by software.
0: No effect
1: Reset I/O port A
Bits 16:0 Reserved, must be kept at reset value.

7.4.12 Clock configuration register 2 (RCC_CFGR2)

Address: 0x2C
Reset value: 0x0000 0000
Access: no wait states, word, half-word and byte access

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. PREDIV[3:0]

rw rw rw rw

Bits 31:4 Reserved, must be kept at reset value.

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Reset and clock control (RCC) RM0360

Bits 3:0 PREDIV[3:0] PREDIV division factor

These bits are set and cleared by software to select PREDIV division factor. They can be
written only when the PLL is disabled.
Note: Bit 0 is the same bit as bit 17 in Clock configuration register (RCC_CFGR), so
modifying bit 17 in Clock configuration register (RCC_CFGR) also modifies bit 0 in
Clock configuration register 2 (RCC_CFGR2) (for compatibility with other STM32
products)
0000: PREDIV input clock not divided
0001: PREDIV input clock divided by 2
0010: PREDIV input clock divided by 3
0011: PREDIV input clock divided by 4
0100: PREDIV input clock divided by 5
0101: PREDIV input clock divided by 6
0110: PREDIV input clock divided by 7
0111: PREDIV input clock divided by 8
1000: PREDIV input clock divided by 9
1001: PREDIV input clock divided by 10
1010: PREDIV input clock divided by 11
1011: PREDIV input clock divided by 12
1100: PREDIV input clock divided by 13
1101: PREDIV input clock divided by 14
1110: PREDIV input clock divided by 15
1111: PREDIV input clock divided by 16

7.4.13 Clock configuration register 3 (RCC_CFGR3)

Address: 0x30
Reset value: 0x0000 0000
Access: no wait states, word, half-word and byte access

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

ADC USB I2C1

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. USART1SW[1:0]
SW SW SW

rw rw rw rw rw

Bits 31:9 Reserved, must be kept at reset value.

Bit 8 ADCSW: ADC clock source selection
Obsolete setting. To be kept at reset value, connecting the HSI14 clock to the ADC
asynchronous clock input. Proper ADC clock selection is done inside the ADC_CFGR2 (refer
to Section 12.10.5: ADC configuration register 2 (ADC_CFGR2) on page 220).
Bit 7 USBSW: USB clock source selection
This bit is set and cleared by software to select the USB clock source.
0: USB clock disabled (default)
1: PLL clock (PLLCLK) selected as USB clock

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RM0360 Reset and clock control (RCC)

Bits 6:5 Reserved, must be kept at reset value.

Bit 4 I2C1SW: I2C1 clock source selection
This bit is set and cleared by software to select the I2C1 clock source.
0: HSI clock selected as I2C1 clock source (default)
1: System clock (SYSCLK) selected as I2C1 clock
Bits 3:2 Reserved, must be kept at reset value.
Bits 1:0 USART1SW[1:0]: USART1 clock source selection
This bit is set and cleared by software to select the USART1 clock source.
00: PCLK selected as USART1 clock source (default)
01: System clock (SYSCLK) selected as USART1 clock
10: LSE clock selected as USART1 clock
11: HSI clock selected as USART1 clock

7.4.14 Clock control register 2 (RCC_CR2)

Address: 0x34
Reset value: 0xXX00 XX80, where X is undefined.
Access: no wait states, word, half-word and byte access

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

HSI14 HSI14 HSI14

HSI14CAL[7:0] HSI14TRIM[4:0]
DIS RDY ON

r r r r r r r r rw rw rw rw rw rw r rw

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:8 HSI14CAL[7:0]: HSI14 clock calibration
These bits are initialized automatically at startup.
Bits 7:3 HSI14TRIM[4:0]: HSI14 clock trimming
These bits provide an additional user-programmable trimming value that is added to the
HSI14CAL[7:0] bits. It can be programmed to adjust to variations in voltage and temperature
that influence the frequency of the HSI14.
The default value is 16, which, when added to the HSI14CAL value, should trim the HSI14 to
14 MHz ± 1%. The trimming step is around 50 kHz between two consecutive HSI14CAL steps.
Bit 2 HSI14DIS HSI14 clock request from ADC disable
Set and cleared by software.
When set this bit prevents the ADC interface from enabling the HSI14 oscillator.
0: ADC interface can turn on the HSI14 oscillator
1: ADC interface can not turn on the HSI14 oscillator

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124
Reset and clock control (RCC) RM0360

Bit 1 HSI14RDY: HSI14 clock ready flag

Set by hardware to indicate that HSI14 oscillator is stable. After the HSI14ON bit is cleared,
HSI14RDY goes low after 6 HSI14 oscillator clock cycles. When HSI14ON is not set but the
HSI14 oscillator is enabled by the peripheral through a clock request, this bit is not set.
0: HSI14 oscillator not ready
1: HSI14 oscillator ready
Bit 0 HSI14ON: HSI14 clock enable
Set and cleared by software. When the HSI14 oscillator is enabled by the peripheral through a
clock request, this bit is not set and resetting it does not stop the HSI14 oscillator.
0: HSI14 oscillator OFF
1: HSI14 oscillator ON

122/775 RM0360 Rev 5

 0x24
0x20
0x18
0x14
0x08
0x04
0x00

0x1C
0x0C

0x010
Offset
7.4.15
RM0360

RCC_CR

RCC_CIR

RCC_CSR
Register

Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value

RCC_CFGR

RCC_BDCR
RCC_AHBENR

RCC_APB1ENR
RCC_APB2ENR
RCC_APB1RSTR
RCC_APB2RSTR
Res.

X
LPWRSTF Res. Res. Res. Res. Res. Res. PLL NODIV Res. 31

0
WWDGRSTF Res. Res. Res. Res. Res. Res. Res. Res. 30

0
IWDGRSTF Res. Res. Res. Res. Res. Res. Res. Res. 29

[2:0]

0
0
0

X X X
SFTRSTF Res. PWREN Res. Res. PWRRST Res. Res. Res.

MCOPRE
28

0
0
0
PORRSTF Res. CRSEN Res. Res. CRSRST Res. Res. Res. 27

X X
PINRSTF Res. Res. Res. Res. Res. Res. Res. Res. 26
RCC register map

0
0

OBLRSTF Res. Res. Res. Res. Res. Res. Res. PLL RDY 25
MCO [3:0]

0
0

RMVF Res. Res. Res. Res. Res. Res. Res. PLL ON 24

0
0
0

X X X
V18PWR RSTF Res. USBEN Res. Res. USBRST Res. CSSC Res. Res. 23
DBGMCURS

0
0
0
0
Res. Res. I2C2EN DBGMCUEN Res. I2C2RST Res. Res. Res. 22

0
0
0
0
Res. Res. I2C1EN Res. GPIOEEN I2C1RST Res. HSI14 RDYC Res. 21

0
0

0
0
0
Res. Res. USART5EN Res. USART4RST USART5RST Res. PLLRDYC Res. 20

0
0

0
0
0
0

Res. Res. USART4EN Res. GPIOCEN USART4RST Res. HSERDYC CSSON 19

0
0
0
0
0
0

0
0

USART3EN TIM17 EN GPIOBEN USART3RST TIM17RST HSIRDYC HSEBYP

PLLMUL[3:0]

Res. Res. 18
HSERD

0
0
0
0
0
0
0
0

USART2EN TIM16 EN GPIOAEN USART2RST TIM16RST LSERDYC

RM0360 Rev 5
Res. Res. PLLXTPRE 17

0
0
0
0
0
0

Res. BDRST Res. TIM15 EN Res. Res. TIM15RST LSIRDYC HSEON 16

PLLSRC[1:0]
0

0
0

Res. RTCEN Res. Res. Res. Res. Res. Res. 15

0
0

0
0
0
0

Res. Res. SPI2EN USART1EN Res. SPI2RST USART1RST Res. ADC PRE 14
0
0

Res. Res. Res. Res. Res. Res. Res. HSI14 RDYIE Res. 13

0
0
0
0

Res. Res. Res. SPI1EN Res. Res. SPI1RST PLLRDYIE Res. 12

0
0
0
0
0
0

Res. Res. WWDGEN TIM1EN Res. WWDGRST TIM1RST HSERDYIE Res. 11

Table 21. RCC register map and reset values

0
0
0
HSICAL[7:0]

Res. Res. Res. Res. Res. Res. Res. HSIRDYIE 10

0
0

0
0
0

0
Res. Res. ADCEN Res. Res. ADCRST LSERDYIE 9
[2:0]
PPRE
The following table gives the RCC register map and the reset values.

SEL
[1:0]
RTC

0
0
0
0
0
0

Res. TIM14EN Res. Res. TIM14RST Res. LSIRDYIE 8

0
0
1

Res. Res. Res. Res. Res. Res. Res. CSSF 7

0
0

0
0

Res. Res. Res. Res. CRCEN Res. Res. Res. 6

0

0
0
0
0
0
0

Res. Res. TIM7EN USART6EN Res. TM7RST USART6RST HSI14 RDYF 5

HPRE[3:0]

0
0
0

0
0

0
1
Res. TIM6EN Res. FLITFEN TM6RST Res. PLLRDYF 4
HSITRIM[4:0]

LSE

[1:0]
DRV
0
0
0

0
Res. Res. Res. Res. Res. Res. HSERDYF 3
[1:0]

0
0

0
1
SWS

Res. LSEBYP Res. Res. SRAMEN Res. Res. HSIRDYF Res. 2

0
0
0
0
1

0
LSIRDY LSERDY TIM3EN Res. Res. TIM3RST Res. LSERDYF HSIRDY 1
SW
[1:0]

0
0
1

0
0
0
0

0
LSION LSEON Res. SYSCFGEN DMAEN Res. SYSCFGRST LSIRDYF HSION 0
Reset and clock control (RCC)

123/775
124
 0x34
0x30
0x28

0x2C
Offset

124/775
RCC_CR2
Register

Reset value
Reset value
Reset value
Reset value

RCC_CFGR3
RCC_CFGR2
RCC_AHBRSTR
Res. Res. Res. Res. 31
Res. Res. Res. Res. 30
Res. Res. Res. Res. 29
Res. Res. Res. Res. 28
Res. Res. Res.
Reset and clock control (RCC)

Res. 27
Res. Res. Res. Res. 26
Res. Res. Res. Res. 25
Res. Res. Res. Res. 24
Res. Res. Res. Res. 23
0

Res. Res. Res. GPIOF RST 22

Res. Res. Res. Res. 21
0

Res. Res. Res. GPIOD RST 20

0

Res. Res. Res. GPIOC RST 19

0

Res. Res. Res. GPIOB RST 18

0

Res. Res. GPIOA RST

RM0360 Rev 5
Res. 17
Res. Res. Res. Res. 16
Res. Res. Res. 15
Res. Res. Res. 14
Res.
X X X

Res. Res. 13
Res. Res. Res. 12
Res. Res. Res. 11
Res.
X X X

Res. Res. 10
HSI14CAL[7:0]

Res. Res. Res. 9

Refer to Section 2.2 on page 37 for the register boundary addresses.
0

X X
Table 21. RCC register map and reset values (continued)

ADCSW Res. Res. 8

1
0

USBSW Res. Res. 7

Res.
0

Res. Res. 6
Res.
0

Res. Res. 5
0
0

I2C1SW Res. Res. 4

Res.
0
0

Res.
HSI14TRIM[14:0]

3
Res.
0
0

HSI14DIS Res. 2
0
0
0

HSI14RDY Res. 1
USART1SW[1:0]
0
0
0
PREDIV[3:0]

HSI14ON Res. 0
RM0360
RM0360 General-purpose I/Os (GPIO)

8 General-purpose I/Os (GPIO)

8.1 Introduction
Each general-purpose I/O port has four 32-bit configuration registers (GPIOx_MODER,
GPIOx_OTYPER, GPIOx_OSPEEDR and GPIOx_PUPDR), two 32-bit data registers
(GPIOx_IDR and GPIOx_ODR) and a 32-bit set/reset register (GPIOx_BSRR). Ports A and
B also have a 32-bit locking register (GPIOx_LCKR) and two 32-bit alternate function
selection registers (GPIOx_AFRH and GPIOx_AFRL).
On STM32F030xB and STM32F030xC devices, also ports C and Dhave two 32-bit alternate
function selection registers (GPIOx_AFRH and GPIOx_AFRL).

8.2 GPIO main features

• Output states: push-pull or open drain + pull-up/down
• Output data from output data register (GPIOx_ODR) or peripheral (alternate function
output)
• Speed selection for each I/O
• Input states: floating, pull-up/down, analog
• Input data to input data register (GPIOx_IDR) or peripheral (alternate function input)
• Bit set and reset register (GPIOx_ BSRR) for bitwise write access to GPIOx_ODR
• Locking mechanism (GPIOx_LCKR) provided to freeze the port A or B I/O port
configuration.
• Analog function
• Alternate function selection registers (at most 16 AFs possible per I/O)
• Fast toggle capable of changing every two clock cycles
• Highly flexible pin multiplexing allows the use of I/O pins as GPIOs or as one of several
peripheral functions

8.3 GPIO functional description

Subject to the specific hardware characteristics of each I/O port listed in the datasheet, each
port bit of the general-purpose I/O (GPIO) ports can be individually configured by software in
several modes:
• Input floating
• Input pull-up
• Input-pull-down
• Analog
• Output open-drain with pull-up or pull-down capability
• Output push-pull with pull-up or pull-down capability
• Alternate function push-pull with pull-up or pull-down capability
• Alternate function open-drain with pull-up or pull-down capability
Each I/O port bit is freely programmable, however the I/O port registers have to be
accessed as 32-bit words, half-words or bytes. The purpose of the GPIOx_BSRR register is

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General-purpose I/Os (GPIO) RM0360

to allow atomic read/modify accesses to any of the GPIOx_ODR registers. In this way, there
is no risk of an IRQ occurring between the read and the modify access.
Figure 14 shows the basic structures of a standard I/O port bit. Table 22 gives the possible
port bit configurations.

Figure 14. Basic structure of an I/O port bit

To/from on-chip
peripherals, Analog input/output
power control
Digital input
and EXTI

Input data register

On/off
Read
Bit set/reset registers

VDDIOx
TTL Schmitt trigger
on/off Pull
Write
Output data register

Input driver up
I/O pin
Output driver VDDIOx
on/off Pull
P-MOS down
Output
Read/write control
N-MOS VSS

Alternate function VSS Push-pull,

From on-chip output open-drain
peripheral or disabled

MSv33182V2

Table 22. Port bit configuration table(1)

MODER(i) OSPEEDR(i) PUPDR(i)
OTYPER(i) I/O configuration
[1:0] [1:0] [1:0]

0 0 0 GP output PP
0 0 1 GP output PP + PU
0 1 0 GP output PP + PD
0 SPEED 1 1 Reserved
01
1 [1:0] 0 0 GP output OD
1 0 1 GP output OD + PU
1 1 0 GP output OD + PD
1 1 1 Reserved (GP output OD)
0 0 0 AF PP
0 0 1 AF PP + PU
0 1 0 AF PP + PD
0 SPEED 1 1 Reserved
10
1 [1:0] 0 0 AF OD
1 0 1 AF OD + PU
1 1 0 AF OD + PD
1 1 1 Reserved

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RM0360 General-purpose I/Os (GPIO)

Table 22. Port bit configuration table(1) (continued)

MODER(i) OSPEEDR(i) PUPDR(i)
OTYPER(i) I/O configuration
[1:0] [1:0] [1:0]

x x x 0 0 Input Floating
x x x 0 1 Input PU
00
x x x 1 0 Input PD
x x x 1 1 Reserved (input floating)
x x x 0 0 Input/output Analog
x x x 0 1
11
x x x 1 0 Reserved
x x x 1 1
1. GP = general-purpose, PP = push-pull, PU = pull-up, PD = pull-down, OD = open-drain, AF = alternate
function.

8.3.1 General-purpose I/O (GPIO)

During and just after reset, the alternate functions are not active and most of the I/O ports
are configured in input floating mode.
The debug pins are in AF pull-up/pull-down after reset:
• PA14: SWCLK in pull-down
• PA13: SWDIO in pull-up
When the pin is configured as output, the value written to the output data register
(GPIOx_ODR) is output on the I/O pin. It is possible to use the output driver in push-pull
mode or open-drain mode (only the low level is driven, high level is HI-Z).
The input data register (GPIOx_IDR) captures the data present on the I/O pin at every AHB
clock cycle.
All GPIO pins have weak internal pull-up and pull-down resistors, which can be activated or
not depending on the value in the GPIOx_PUPDR register.

8.3.2 I/O pin alternate function multiplexer and mapping

The device I/O pins are connected to on-board peripherals/modules through a multiplexer
that allows only one peripheral alternate function (AF) connected to an I/O pin at a time. In
this way, there can be no conflict between peripherals available on the same I/O pin.
Each I/O pin has a multiplexer with up to sixteen alternate function inputs (AF0 to AF15) that
can be configured through the GPIOx_AFRL (for pin 0 to 7) and GPIOx_AFRH (for pin 8 to
15) registers:
• After reset the multiplexer selection is alternate function 0 (AF0). The I/Os are
configured in alternate function mode through GPIOx_MODER register.
• The specific alternate function assignments for each pin are detailed in the device
datasheet.
In addition to this flexible I/O multiplexing architecture, each peripheral has alternate
functions mapped onto different I/O pins to optimize the number of peripherals available in
smaller packages.

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To use an I/O in a given configuration, the user has to proceed as follows:

• Debug function: after each device reset these pins are assigned as alternate function
pins immediately usable by the debugger host
• GPIO: configure the desired I/O as output, input or analog in the GPIOx_MODER
register.
• Peripheral alternate function:
– Connect the I/O to the desired AFx in one of the GPIOx_AFRL or GPIOx_AFRH
register.
– Select the type, pull-up/pull-down and output speed via the GPIOx_OTYPER,
GPIOx_PUPDR and GPIOx_OSPEEDER registers, respectively.
– Configure the desired I/O as an alternate function in the GPIOx_MODER register.
• Additional functions:
– ADC connection can be enabled in ADC registers regardless the configured GPIO
mode. When ADC uses a GPIO, it is recommended to configure the GPIO in
analog mode, through the GPIOx_MODER register.
– For the additional functions like RTC, WKUPx and oscillators, configure the
required function in the related RTC, PWR and RCC registers. These functions
have priority over the configuration in the standard GPIO registers.
Refer to the “Alternate function mapping” table in the device datasheet for the detailed
mapping of the alternate function I/O pins.

8.3.3 I/O port control registers

Each of the GPIO ports has four 32-bit memory-mapped control registers (GPIOx_MODER,
GPIOx_OTYPER, GPIOx_OSPEEDR, GPIOx_PUPDR) to configure up to 16 I/Os. The
GPIOx_MODER register is used to select the I/O mode (input, output, AF, analog). The
GPIOx_OTYPER and GPIOx_OSPEEDR registers are used to select the output type (push-
pull or open-drain) and speed. The GPIOx_PUPDR register is used to select the pull-
up/pull-down whatever the I/O direction.

8.3.4 I/O port data registers

Each GPIO has two 16-bit memory-mapped data registers: input and output data registers
(GPIOx_IDR and GPIOx_ODR). GPIOx_ODR stores the data to be output, it is read/write
accessible. The data input through the I/O are stored into the input data register
(GPIOx_IDR), a read-only register.
See Section 8.4.5: GPIO port input data register (GPIOx_IDR) (x = A to D, F) and
Section 8.4.6: GPIO port output data register (GPIOx_ODR) (x = A to D, F) for the register
descriptions.

8.3.5 I/O data bitwise handling

The bit set reset register (GPIOx_BSRR) is a 32-bit register which allows the application to
set and reset each individual bit in the output data register (GPIOx_ODR). The bit set reset
register has twice the size of GPIOx_ODR.
To each bit in GPIOx_ODR, correspond two control bits in GPIOx_BSRR: BS(i) and BR(i).
When written to 1, bit BS(i) sets the corresponding ODR(i) bit. When written to 1, bit BR(i)
resets the ODR(i) corresponding bit.

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RM0360 General-purpose I/Os (GPIO)

Writing any bit to 0 in GPIOx_BSRR does not have any effect on the corresponding bit in
GPIOx_ODR. If there is an attempt to both set and reset a bit in GPIOx_BSRR, the set
action takes priority.
Using the GPIOx_BSRR register to change the values of individual bits in GPIOx_ODR is a
“one-shot” effect that does not lock the GPIOx_ODR bits. The GPIOx_ODR bits can always
be accessed directly. The GPIOx_BSRR register provides a way of performing atomic
bitwise handling.
There is no need for the software to disable interrupts when programming the GPIOx_ODR
at bit level: it is possible to modify one or more bits in a single atomic AHB write access.

8.3.6 GPIO locking mechanism

It is possible to freeze the port A and B GPIO control registers by applying a specific write
sequence to the GPIOx_LCKR register. The frozen registers are GPIOx_MODER,
GPIOx_OTYPER, GPIOx_OSPEEDR, GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH.
To write the GPIOx_LCKR register, a specific write / read sequence has to be applied. When
the right LOCK sequence is applied to bit 16 in this register, the value of LCKR[15:0] is used
to lock the configuration of the I/Os (during the write sequence the LCKR[15:0] value must
be the same). When the LOCK sequence has been applied to a port bit, the value of the port
bit can no longer be modified until the next MCU reset or peripheral reset. Each
GPIOx_LCKR bit freezes the corresponding bit in the control registers (GPIOx_MODER,
GPIOx_OTYPER, GPIOx_OSPEEDR, GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH.
The LOCK sequence (refer to Section 8.4.8: GPIO port configuration lock register
(GPIOx_LCKR) (x = A to B)) can only be performed using a word (32-bit long) access to the
GPIOx_LCKR register due to the fact that GPIOx_LCKR bit 16 has to be set at the same
time as the [15:0] bits.
For more details refer to LCKR register description in Section 8.4.8: GPIO port configuration
lock register (GPIOx_LCKR) (x = A to B).

8.3.7 I/O alternate function input/output

Two registers are provided to select one of the alternate function inputs/outputs available for
each I/O. With these registers, the user can connect an alternate function to some other pin
as required by the application.
This means that a number of possible peripheral functions are multiplexed on each GPIO
using the GPIOx_AFRL and GPIOx_AFRH alternate function registers. The application can
thus select any one of the possible functions for each I/O. The AF selection signal being
common to the alternate function input and alternate function output, a single channel is
selected for the alternate function input/output of a given I/O.
For code example refer to Section A.4.2: Alternate function selection sequence on
page 728.
To know which functions are multiplexed on each GPIO pin refer to the device datasheet.

8.3.8 External interrupt/wake-up lines

All ports have external interrupt capability. To use external interrupt lines, the given pin must
not be configured in analog mode or being used as oscillator pin, so the input trigger is kept
enabled.

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Refer to Section 11.2: Extended interrupts and events controller (EXTI) and to
Section 11.2.3: Event management.

8.3.9 Input configuration

When the I/O port is programmed as input:
• The output buffer is disabled
• The Schmitt trigger input is activated
• The pull-up and pull-down resistors are activated depending on the value in the
GPIOx_PUPDR register
• The data present on the I/O pin are sampled into the input data register every AHB
clock cycle
• A read access to the input data register provides the I/O state
Figure 15 shows the input configuration of the I/O port bit.

Figure 15. Input floating / pull up / pull down configurations

To / from on-chip
peripherals, Analog input/output
power control
and EXTI
Input data register

On
Read
Bit set/reset registers

VDDIOx
TTL Schmitt trigger
on/off Pull
Write
Output data register

Input driver up
I/O pin
Output driver
on/off Pull
down
Read/write
VSS

MSv33183V2

8.3.10 Output configuration

When the I/O port is programmed as output:
• The output buffer is enabled:
– Open drain mode: a “0” in the output register activates the N-MOS whereas a “1”
in the output register leaves the port in Hi-Z (the P-MOS is never activated)
– Push-pull mode: a “0” in the output register activates the N-MOS whereas a “1” in
the output register activates the P-MOS
• The Schmitt trigger input is activated
• The pull-up and pull-down resistors are activated depending on the value in the
GPIOx_PUPDR register
• The data present on the I/O pin are sampled into the input data register every AHB
clock cycle
• A read access to the input data register gets the I/O state
• A read access to the output data register gets the last written value

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RM0360 General-purpose I/Os (GPIO)

Figure 16 shows the output configuration of the I/O port bit.

Figure 16. Output configuration

To / from on-chip
peripherals, Analog input/output
power control
and EXTI

Input data register

On
Read
Bit set/reset registers

VDDIOx
TTL Schmitt trigger
on/off Pull
Write
Output data register

Input driver up
I/O pin
Output driver VDDIOx
on/off Pull
P-MOS down
Output
Read/write control
N-MOS VSS

VSS Push-pull or
open-drain
MSv33184V3

8.3.11 Alternate function configuration

When the I/O port is programmed as alternate function:
• The output buffer can be configured in open-drain or push-pull mode
• The output buffer is driven by the signals coming from the peripheral (transmitter
enable and data)
• The Schmitt trigger input is activated
• The weak pull-up and pull-down resistors are activated or not depending on the value
in the GPIOx_PUPDR register
• The data present on the I/O pin are sampled into the input data register every AHB
clock cycle
• A read access to the input data register gets the I/O state

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General-purpose I/Os (GPIO) RM0360

Figure 17 shows the alternate function configuration of the I/O port bit.

Figure 17. Alternate function configuration

Analog input/output
To/from on-chip
peripheral Alternate function input

Input data register

On
Read
Bit set/reset registers

VDDIOx
TTL Schmitt trigger
on/off Pull
Write
Output data register

Input driver up
I/O pin
Output driver VDDIOx
on/off Pull
P-MOS down
Output
Read/write control
N-MOS VSS

VSS
From on-chip Alternate function output Push-pull
peripheral or open-drain

MSv31479V2

Analog input/output
To/from on-chip
peripheral Alternate function input
Input data register

On
Read
Bit set/reset registers

VDDIOx
TTL Schmitt trigger
on/off Pull
Write
Output data register

Input driver up
I/O pin
Output driver VDDIOx
on/off Pull
P-MOS down
Output
Read/write control
N-MOS VSS

VSS
From on-chip Alternate function output Push-pull
peripheral or open-drain

MSv31479V2

8.3.12 Analog configuration

When the I/O port is programmed as analog configuration:
• The output buffer is disabled
• The Schmitt trigger input is deactivated, providing zero consumption for every analog
value of the I/O pin. The output of the Schmitt trigger is forced to a constant value (0).
• The weak pull-up and pull-down resistors are disabled by hardware
• Read access to the input data register gets the value “0”
For code example refer to Section A.4.3: Analog GPIO configuration on page 729.

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RM0360 General-purpose I/Os (GPIO)

Figure 18 shows the high-impedance, analog-input configuration of the I/O port bits.

Figure 18. High impedance-analog configuration

To/from on-chip Analog input/output

peripheral

Input data register

Off
Read
0
Bit set/reset registers

Schmitt trigger

Write
Output data register
Input driver

I/O pin
Output driver

Read/write

MS55993V1

8.3.13 Using the HSE or LSE oscillator pins as GPIOs

When the HSE or LSE oscillator is switched OFF (default state after reset), the related
oscillator pins can be used as normal GPIOs.
When the HSE or LSE oscillator is switched ON (by setting the HSEON or LSEON bit in the
RCC_CSR register) the oscillator takes control of its associated pins and the GPIO
configuration of these pins has no effect.
When the oscillator is configured in a user external clock mode, only the pin is reserved for
clock input and the OSC_OUT or OSC32_OUT pin can still be used as normal GPIO.

8.3.14 Using the GPIO pins in the RTC supply domain

The PC13/PC14/PC15 GPIO functionality is lost when the core supply domain is powered
off (when the device enters Standby mode). In this case, if their GPIO configuration is not
bypassed by the RTC configuration, these pins are set in an analog input mode.
For details about I/O control by the RTC, refer to Section 21.4: RTC functional description.

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General-purpose I/Os (GPIO) RM0360

8.4 GPIO registers

For a summary of register bits, register address offsets and reset values, refer to Table 23.
The peripheral registers can be written in word, half word or byte mode.

8.4.1 GPIO port mode register (GPIOx_MODER)

(x =A to D, F)
Address offset:0x00
Reset value: 0x2800 0000 for port A
Reset value: 0x0000 0000 for other ports

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

MODER15[1:0] MODER14[1:0] MODER13[1:0] MODER12[1:0] MODER11[1:0] MODER10[1:0] MODER9[1:0] MODER8[1:0]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

MODER7[1:0] MODER6[1:0] MODER5[1:0] MODER4[1:0] MODER3[1:0] MODER2[1:0] MODER1[1:0] MODER0[1:0]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:0 MODER[15:0][1:0]: Port x configuration I/O pin y (y = 15 to 0)

These bits are written by software to configure the I/O mode.
00: Input mode (reset state)
01: General purpose output mode
10: Alternate function mode
11: Analog mode

8.4.2 GPIO port output type register (GPIOx_OTYPER)

(x = A to D, F)
Address offset: 0x04
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OT15 OT14 OT13 OT12 OT11 OT10 OT9 OT8 OT7 OT6 OT5 OT4 OT3 OT2 OT1 OT0
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 OT[15:0]: Port x configuration I/O pin y (y = 15 to 0)
These bits are written by software to configure the I/O output type.
0: Output push-pull (reset state)
1: Output open-drain

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RM0360 General-purpose I/Os (GPIO)

8.4.3 GPIO port output speed register (GPIOx_OSPEEDR)

(x = A to D, F)
Address offset: 0x08
Reset value: 0x0C00 0000 (for port A)
Reset value: 0x0000 0000 (for other ports)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OSPEEDR15 OSPEEDR14 OSPEEDR13 OSPEEDR12 OSPEEDR11 OSPEEDR10 OSPEEDR9 OSPEEDR8
[1:0] [1:0] [1:0] [1:0] [1:0] [1:0] [1:0] [1:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OSPEEDR7 OSPEEDR6 OSPEEDR5 OSPEEDR4 OSPEEDR3 OSPEEDR2 OSPEEDR1 OSPEEDR0
[1:0] [1:0] [1:0] [1:0] [1:0] [1:0] [1:0] [1:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:0 OSPEEDR[15:0][1:0]: Port x configuration I/O pin y (y = 15 to 0)

These bits are written by software to configure the I/O output speed.
x0: Low speed
01: Medium speed
11: High speed
Note: Refer to the device datasheet for the frequency specifications and the power supply
and load conditions for each speed..

8.4.4 GPIO port pull-up/pull-down register (GPIOx_PUPDR)

(x = A to ,D, F)
Address offset: 0x0C
Reset value: 0x2400 0000 (for port A)
Reset value: 0x0000 0000 (for other ports)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PUPDR15[1:0] PUPDR14[1:0] PUPDR13[1:0] PUPDR12[1:0] PUPDR11[1:0] PUPDR10[1:0] PUPDR9[1:0] PUPDR8[1:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PUPDR7[1:0] PUPDR6[1:0] PUPDR5[1:0] PUPDR4[1:0] PUPDR3[1:0] PUPDR2[1:0] PUPDR1[1:0] PUPDR0[1:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:0 PUPDR[15:0][1:0]: Port x configuration I/O pin y (y = 15 to 0)

These bits are written by software to configure the I/O pull-up or pull-down
00: No pull-up, pull-down
01: Pull-up
10: Pull-down
11: Reserved

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General-purpose I/Os (GPIO) RM0360

8.4.5 GPIO port input data register (GPIOx_IDR)

(x = A to D, F)
Address offset: 0x10
Reset value: 0x0000 XXXX

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDR15 IDR14 IDR13 IDR12 IDR11 IDR10 IDR9 IDR8 IDR7 IDR6 IDR5 IDR4 IDR3 IDR2 IDR1 IDR0
r r r r r r r r r r r r r r r r

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 IDR[15:0]: Port x input data I/O pin y (y = 15 to 0)
These bits are read-only. They contain the input value of the corresponding I/O port.

8.4.6 GPIO port output data register (GPIOx_ODR)

(x = A to D, F)
Address offset: 0x14
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ODR15 ODR14 ODR13 ODR12 ODR11 ODR10 ODR9 ODR8 ODR7 ODR6 ODR5 ODR4 ODR3 ODR2 ODR1 ODR0
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 ODR[15:0]: Port output data I/O pin y (y = 15 to 0)
These bits can be read and written by software.
Note: For atomic bit set/reset, the ODR bits can be individually set and/or reset by writing to
the GPIOx_BSRR register (x = A..D, F).

136/775 RM0360 Rev 5

RM0360 General-purpose I/Os (GPIO)

8.4.7 GPIO port bit set/reset register (GPIOx_BSRR)

(x = A to D, F)
Address offset: 0x18
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BR15 BR14 BR13 BR12 BR11 BR10 BR9 BR8 BR7 BR6 BR5 BR4 BR3 BR2 BR1 BR0
w w w w w w w w w w w w w w w w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BS15 BS14 BS13 BS12 BS11 BS10 BS9 BS8 BS7 BS6 BS5 BS4 BS3 BS2 BS1 BS0
w w w w w w w w w w w w w w w w

Bits 31:16 BR[15:0]: Port x reset I/O pin y (y = 15 to 0)

These bits are write-only. A read to these bits returns the value 0x0000.
0: No action on the corresponding ODRx bit
1: Resets the corresponding ODRx bit
Note: If both BSx and BRx are set, BSx has priority.
Bits 15:0 BS[15:0]: Port x set I/O pin y (y = 15 to 0)
These bits are write-only. A read to these bits returns the value 0x0000.
0: No action on the corresponding ODRx bit
1: Sets the corresponding ODRx bit

8.4.8 GPIO port configuration lock register (GPIOx_LCKR)

(x = A to B)
This register is used to lock the configuration of the port bits when a correct write sequence
is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the
GPIO. During the write sequence, the value of LCKR[15:0] must not change. When the
LOCK sequence has been applied on a port bit, the value of this port bit can no longer be
modified until the next MCU reset or peripheral reset.
Note: A specific write sequence is used to write to the GPIOx_LCKR register. Only word access
(32-bit long) is allowed during this locking sequence.
Each lock bit freezes a specific configuration register (control and alternate function
registers).
Address offset: 0x1C
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. LCKK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LCK15 LCK14 LCK13 LCK12 LCK11 LCK10 LCK9 LCK8 LCK7 LCK6 LCK5 LCK4 LCK3 LCK2 LCK1 LCK0
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

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General-purpose I/Os (GPIO) RM0360

Bits 31:17 Reserved, must be kept at reset value.

Bit 16 LCKK: Lock key
This bit can be read any time. It can only be modified using the lock key write sequence.
0: Port configuration lock key not active
1: Port configuration lock key active. The GPIOx_LCKR register is locked until the next MCU
reset or peripheral reset.
LOCK key write sequence:
WR LCKR[16] = 1 + LCKR[15:0]
WR LCKR[16] = 0 + LCKR[15:0]
WR LCKR[16] = 1 + LCKR[15:0]
RD LCKR
RD LCKR[16] = 1 (this read operation is optional but it confirms that the lock is active)
Note: During the LOCK key write sequence, the value of LCK[15:0] must not change.
Any error in the lock sequence aborts the lock.
After the first lock sequence on any bit of the port, any read access on the LCKK bit
returns 1 until the next MCU reset or peripheral reset.For code example refer to
Section A.4.1: Lock sequence on page 728.
Bits 15:0 LCK[15:0]: Port x lock I/O pin y (y = 15 to 0)
These bits are read/write but can only be written when the LCKK bit is 0.
0: Port configuration not locked
1: Port configuration locked

8.4.9 GPIO alternate function low register (GPIOx_AFRL)

(x = A to D, )
Address offset: 0x20
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFSEL7[3:0] AFSEL6[3:0] AFSEL5[3:0] AFSEL4[3:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFSEL3[3:0] AFSEL2[3:0] AFSEL1[3:0] AFSEL0[3:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:0 AFSELy[3:0]: Alternate function selection for port x pin y (y = 0..7)
These bits are written by software to configure alternate function I/Os
AFSELy selection:
1000: Reserved
0000: AF0
1001: Reserved
0001: AF1
1010: Reserved
0010: AF2
1011: Reserved
0011: AF3
1100: Reserved
0100: AF4
1101: Reserved
0101: AF5
1110: Reserved
0110: AF6
1111: Reserved
0111: AF7

138/775 RM0360 Rev 5

RM0360 General-purpose I/Os (GPIO)

8.4.10 GPIO alternate function high register (GPIOx_AFRH)

(x = A to D, F)
Address offset: 0x24
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFSEL15[3:0] AFSEL14[3:0] AFSEL13[3:0] AFSEL12[3:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFSEL11[3:0] AFSEL10[3:0] AFSEL9[3:0] AFSEL8[3:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:0 AFSELy[3:0]: Alternate function selection for port x pin y (y = 8..15)
These bits are written by software to configure alternate function I/Os
AFSELy selection:
0000: AF0 1000: Reserved
0001: AF1 1001: Reserved
0010: AF2 1010: Reserved
0011: AF3 1011: Reserved
0100: AF4 1100: Reserved
0101: AF5 1101: Reserved
0110: AF6 1110: Reserved
0111: AF7 1111: Reserved

8.4.11 GPIO port bit reset register (GPIOx_BRR) (x = A to D, F)

Address offset: 0x28
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BR15 BR14 BR13 BR12 BR11 BR10 BR9 BR8 BR7 BR6 BR5 BR4 BR3 BR2 BR1 BR0
w w w w w w w w w w w w w w w w

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 BR[15:0]: Port x reset IO pin y (y = 15 to 0)
These bits are write-only. A read to these bits returns the value 0x0000.
0: No action on the corresponding ODx bit
1: Reset the corresponding ODx bit

RM0360 Rev 5 139/775

141
 0x18
0x14
0x10
0x08
0x08
0x04
0x00
0x00

0x0C
0x0C

140/775
8.4.12

Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value

GPIOx_IDR

GPIOx_ODR

GPIOx_BSRR
GPIOx_PUPDR
GPIOA_PUPDR
GPIOx_MODER
GPIOA_MODER

GPIOx_OTYPER
(where x = B..D,F)

(where x = A..D, F)
(where x = A..D, F)
(where x = A..D, F)
(where x = B..D, F)
(where x = B..D, F)
(where x = A..D, F)

GPIOx_OSPEEDR
GPIOA_OSPEEDR
Offset Register name

0
0
0
0
0
0
0
BR15 Res. Res. Res. 31
PUPDR15[1:0] PUPDR15[1:0] OSPEEDR15[1:0] OSPEEDR15[1:0] MODER15[1:0] MODER15[1:0]

0
0
0
0
0
0
0
BR14 Res. Res. Res. 30

0
0
1
0
0
0
1
BR13 Res. Res. Res. 29
General-purpose I/Os (GPIO)

PUPDR14[1:0] PUPDR14[1:0] OSPEEDR14[1:0] OSPEEDR14[1:0] MODER14[1:0] MODER14[1:0]

0
0
0
0
0
0
0
BR12 Res. Res. Res. 28

0
0
0
0
1
0
1
BR11 Res. Res. Res. 27
PUPDR13[1:0] PUPDR13[1:0] OSPEEDR13[1:0] OSPEEDR13[1:0] MODER13[1:0] MODER13[1:0]
GPIO register map

0
0
1
0
1
0
BR10 Res. Res. Res. 0 26

0
0
0
0
0
0
0
BR9 Res. Res. Res. 25
PUPDR12[1:0] PUPDR12[1:0] OSPEEDR12[1:0] OSPEEDR12[1:0] MODER12[1:0] MODER12[1:0]

0
0
0
0
0
0
0

BR8 Res. Res. Res. 24

0
0
0
0
0
0
0

BR7 Res. Res. Res. 23

PUPDR11[1:0] PUPDR11[1:0] OSPEEDR11[1:0] OSPEEDR11[1:0] MODER11[1:0] MODER11[1:0]

0
0
0
0
0
0
0

BR6 Res. Res. Res. 22

0
0
0
0
0
0
0

BR5 Res. Res. Res. 21

PUPDR10[1:0] PUPDR10[1:0] OSPEEDR10[1:0] OSPEEDR10[1:0] MODER10[1:0] MODER10[1:0]

0
0
0
0
0
0
0

BR4 Res. Res. Res. 20

0
0
0
0
0
0
0

BR3 Res. Res. Res. 19

PUPDR9[1:0] PUPDR9[1:0] OSPEEDR9[1:0] OSPEEDR9[1:0] MODER9[1:0] MODER9[1:0]

0
0
0
0
0
0
0

BR2 Res. Res. Res. 18

RM0360 Rev 5
0
0
0
0
0
0
0

BR1 Res. Res. Res. 17

PUPDR8[1:0] PUPDR8[1:0] OSPEEDR8[1:0] OSPEEDR8[1:0] MODER8[1:0] MODER8[1:0]

0
0
0
0
0
0
0

BR0 Res. Res. Res. 16

0
0
0
0
0
0
0

0
0

BS15 ODR15 IDR15 OT15 15

PUPDR7[1:0] PUPDR7[1:0] OSPEEDR7[1:0] OSPEEDR7[1:0] MODER7[1:0] MODER7[1:0]

0
0
0
0
0
0
0

0
0

BS14 ODR14 IDR14 OT14 14

0
0
0
0
0
0
0

0
0

BS13 ODR13 IDR13 OT13 13

PUPDR6[1:0] PUPDR6[1:0] OSPEEDR6[1:0] OSPEEDR6[1:0] MODER6[1:0] MODER6[1:0]

0
0
0
0
0
0
0

0
0

BS12 ODR12 IDR12 OT12 12

0
0
0
0
0
0
0

0
0

BS11 ODR11 IDR11 OT11

Table 23. GPIO register map and reset values

PUPDR5[1:0] PUPDR5[1:0] OSPEEDR5[1:0] OSPEEDR5[1:0] MODER5[1:0] MODER5[1:0]

11

0
0
0
0
0
0
0

0
0

BS10 ODR10 IDR10 OT10 10

The following table gives the GPIO register map and reset values.

0
0
0
0
0
0
0

0
0

BS9 ODR9 IDR9 OT9 9

PUPDR4[1:0] PUPDR4[1:0] OSPEEDR4[1:0] OSPEEDR4[1:0] MODER4[1:0] MODER4[1:0]

0
0
0
0
0
0
0

0
0

BS8 ODR8 IDR8 OT8 8

0
0
0
0
0
0
0

0
0

BS7 ODR7 IDR7 OT7 7

PUPDR3[1:0] PUPDR3[1:0] OSPEEDR3[1:0] OSPEEDR3[1:0] MODER3[1:0] MODER3[1:0]

0
0
0
0
0
0
0

0
0

BS6 ODR6 IDR6 OT6 6

0
0

0
0
0
0
0
0
0

BS5 ODR5 IDR5 OT5 5

PUPDR2[1:0] PUPDR2[1:0] OSPEEDR2[1:0] OSPEEDR2[1:0] MODER2[1:0] MODER2[1:0]

0
0

0
0
0
0
0
0
0

BS4 ODR4 IDR4 OT4 4

0
0

0
0
0
0
0
0
0

BS3 ODR3 IDR3 OT3 3

PUPDR1[1:0] PUPDR1[1:0] OSPEEDR1[1:0] OSPEEDR1[1:0] MODER1[1:0] MODER1[1:0]

0
0

0
0
0
0
0
0
0

BS2 ODR2 IDR2 OT2 2

0
0

0
0
0
0
0
0
0

BS1 ODR1 IDR1 OT1 1

PUPDR0[1:0] PUPDR0[1:0] OSPEEDR0[1:0] OSPEEDR0[1:0] MODER0[1:0] MODER0[1:0]

0
0

0
0
0
0
0
0
0

BS0 ODR0 IDR0 OT0 0

RM0360
RM0360 General-purpose I/Os (GPIO)

Table 23. GPIO register map and reset values (continued)

Offset Register name

31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12

10
11

9
8
7
6
5
4
3
2
1
0
LCK15
LCK14
LCK13
LCK12

LCK10
LCK11
GPIOx_LCKR

LCKK

LCK9
LCK8
LCK7
LCK6
LCK5
LCK4
LCK3
LCK2
LCK1
LCK0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0x1C (where x = A..B)

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
GPIOx_AFRL AFSEL7 AFSEL6 AFSEL5 AFSEL4 AFSEL3 AFSEL2 AFSEL1 AFSEL0
0x20 (where x = A.., B) [3:0] [3:0] [3:0] [3:0] [3:0] [3:0] [3:0] [3:0]
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
GPIOx_AFRH AFSEL15 AFSEL14 AFSEL13 AFSEL12 AFSEL11 AFSEL10 AFSEL9 AFSEL8
0x24 (where x = A..B) [3:0] [3:0] [3:0] [3:0] [3:0] [3:0] [3:0] [3:0]
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
GPIOx_BRR

BR15
BR14
BR13
BR12

BR10
BR11
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

BR9
BR8
BR7
BR6
BR5
BR4
BR3
BR2
BR1
BR0
0x28 (where x = A..D, F)
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Refer to Section 2.2 on page 37 for the register boundary addresses.

RM0360 Rev 5 141/775

141
System configuration controller (SYSCFG) RM0360

9 System configuration controller (SYSCFG)

The devices feature a set of configuration registers. The main purposes of the system
configuration controller are the following:
• Enabling/disabling I2C Fast Mode Plus on some IO ports
• Remapping some DMA trigger sources to different DMA channels
• Remapping the memory located at the beginning of the code area
• Managing the external interrupt line connection to the GPIOs
• Managing robustness feature

9.1 SYSCFG registers

9.1.1 SYSCFG configuration register 1 (SYSCFG_CFGR1)

This register is used for specific configurations of memory and DMA requests remap and to
control special I/O features.
Two bits are used to configure the type of memory accessible at address 0x0000 0000.
These bits are used to select the physical remap by software and so, bypass the hardware
BOOT selection.
After reset these bits take the value selected by the actual boot mode configuration.
Address offset: 0x00
Reset value: 0x0000 000X (X is the memory mode selected by the actual boot mode
configuration
Note: For STM32F030xC devices, DMA remapping bits are replaced by more flexible mapping
configured through DMA_CSELR register. Refer to Section 10.6.7: DMA channel selection
register (DMA_CSELR) for more details.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
USART3 I2C_ I2C_ I2C_ I2C_ I2C_ I2C_
I2C2_ I2C1_
Res. Res. Res. Res. Res. _DMA_ Res. Res. PA10_ PA9_ PB9_ PB8_ PB7_ PB6_
FMP FMP
RMP FMP FMP FMP FMP FMP FMP
rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USART1 USART1
TIM17_ TIM16_ ADC_ PA11_
_RX_ _TX_ MEM_MODE
Res. Res Res DMA_ DMA_ DMA_ Res. Res. PA12_ Res. Res.
DMA_ DMA_ [1:0]
RMP RMP RMP RMP
RMP RMP
rw rw rw rw rw rw rw rw

Bits 31:27 Reserved, must be kept at reset value.

Bit 26 USART3_DMA_RMP: USART3 DMA request remapping bit. Available on STM32F070xB
devices only.
This bit is set and cleared by software. It controls the remapping of USART3 DMA requests.
0: Disabled, need to enable remap before use.
1: Remap (USART3_RX and USART3_TX DMA requests mapped on DMA channel 3 and 2
respectively)

142/775 RM0360 Rev 5

RM0360 System configuration controller (SYSCFG)

Bits 25:24 Reserved, must be kept at reset value.

Bits 23:22 I2C_PAx_FMP: Fast Mode Plus (FM+) driving capability activation bits. Available on
STM32F030x4, STM32F030x6, STM32F070x6 and STM32F030xC devices only.
These bits are set and cleared by software. Each bit enables I2C FM+ mode for PA10 and PA9
I/Os.
0: PAx pin operates in standard mode.
1: I2C FM+ mode enabled on PAx pin and the Speed control is bypassed.
Bit 21 I2C2_FMP: FM+ driving capability activation for I2C2. Available on STM32F070xB and
STM32F030xC devices only.
This bit is set and cleared by software. This bit is OR-ed with I2C_Pxx_FM+ bits.
0: FM+ mode is controlled by I2C_Pxx_FM+ bits only.
1: FM+ mode is enabled on all I2C2 pins selected through selection bits in GPIOx_AFR
registers. This is the only way to enable the FM+ mode for pads without a dedicated
I2C_Pxx_FM+ control bit.
Bit 20 I2C1_FMP: FM+ driving capability activation for I2C1. Not available on STM32F030x8 devices.
This bit is set and cleared by software. This bit is OR-ed with I2C_Pxx_FM+ bits.
0: FM+ mode is controlled by I2C_Pxx_FM+ bits only.
1: FM+ mode is enabled on all I2C1 pins selected through selection bits in GPIOx_AFR
registers. This is the only way to enable the FM+ mode for pads without a dedicated
I2C_Pxx_FM+ control bit.
Bits 19:16 I2C_PBx_FMP: Fast Mode Plus (FM+) driving capability activation bits.
These bits are set and cleared by software. Each bit enables I2C FM+ mode for PB6, PB7,
PB8, and PB9 I/Os.
0: PBx pin operates in standard mode.
1: I2C FM+ mode enabled on PBx pin and the Speed control is bypassed.
Bits 15:13 Reserved, must be kept at reset value.
Bit 12 TIM17_DMA_RMP: TIM17 DMA request remapping bit. Available on STM32F030x4,
STM32F030x6, STM32F070x6, STM32F030x8 and STM32F070xB devices only.
This bit is set and cleared by software. It controls the remapping of TIM17 DMA requests.
0: No remap (TIM17_CH1 and TIM17_UP DMA requests mapped on DMA channel 1)
1: Remap (TIM17_CH1 and TIM17_UP DMA requests mapped on DMA channel 2)
Bit 11 TIM16_DMA_RMP: TIM16 DMA request remapping bit. Available on STM32F030x4,
STM32F030x6, STM32F070x6, STM32F030x8 and STM32F070xB devices only.
This bit is set and cleared by software. It controls the remapping of TIM16 DMA requests.
0: No remap (TIM16_CH1 and TIM16_UP DMA requests mapped on DMA channel 3)
1: Remap (TIM16_CH1 and TIM16_UP DMA requests mapped on DMA channel 4)
Bit 10 USART1_RX_DMA_RMP: USART1_RX DMA request remapping bit. Available on
STM32F030x4, STM32F030x6, STM32F070x6, STM32F030x8 and STM32F070xB devices
only.
This bit is set and cleared by software. It controls the remapping of USART1_RX DMA
requests.
0: No remap (USART1_RX DMA request mapped on DMA channel 3)
1: Remap (USART1_RX DMA request mapped on DMA channel 5)

RM0360 Rev 5 143/775

148
System configuration controller (SYSCFG) RM0360

Bit 9 USART1_TX_DMA_RMP: USART1_TX DMA request remapping bit. . Available on

STM32F030x4,STM32F030x6, STM32F070x6, STM32F030x8 and STM32F070xB devices
only.
This bit is set and cleared by software. It bit controls the remapping of USART1_TX DMA
requests.
0: No remap (USART1_TX DMA request mapped on DMA channel 2)
1: Remap (USART1_TX DMA request mapped on DMA channel 4)
Bit 8 ADC_DMA_RMP: ADC DMA request remapping bit. Available on
STM32F030x4,STM32F030x6, STM32F070x6, STM32F030x8 and STM32F070xB devices
only.
This bit is set and cleared by software. It controls the remapping of ADC DMA requests.
0: No remap (ADC DMA request mapped on DMA channel 1)
1: Remap (ADC DMA request mapped on DMA channel 2)
Bits 7:5 Reserved, must be kept at reset value.
Bit 4 PA11_PA12_RMP: PA11 and PA12 remapping bit for small packages (28 and 20 pins).
Available on STM32F070x6 devices only.
This bit is set and cleared by software. It controls the mapping of either PA9/10 or PA11/12 pin
pair on small pin-count packages.
0: No remap (pin pair PA9/10 mapped on the pins)
1: Remap (pin pair PA11/12 mapped instead of PA9/10)
Bits 3:2 Reserved, must be kept at reset value.
Bits 1:0 MEM_MODE[1:0]: Memory mapping selection bits
These bits are set and cleared by software. They control the memory internal mapping at
address 0x0000 0000. After reset these bits take on the value selected by the actual boot
mode configuration. Refer to Section 2.5: Boot configuration for more details.
x0: Main Flash memory mapped at 0x0000 0000
01: System Flash memory mapped at 0x0000 0000
11: Embedded SRAM mapped at 0x0000 0000

9.1.2 SYSCFG external interrupt configuration register 1

(SYSCFG_EXTICR1)
Address offset: 0x08
Reset value: 0x0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXTI3[3:0] EXTI2[3:0] EXTI1[3:0] EXTI0[3:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

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Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 EXTIx[3:0]: EXTI x configuration bits (x = 0 to 3)
These bits are written by software to select the source input for the EXTIx external interrupt.
x000: PA[x] pin
x001: PB[x] pin
x010: PC[x] pin
x011: PD[x] pin
x100: Reserved
x101: PF[x] pin
other configurations: reserved

Note: Some of the I/O pins mentioned in the above register may not be available on small
packages.

9.1.3 SYSCFG external interrupt configuration register 2

(SYSCFG_EXTICR2)
Address offset: 0x0C
Reset value: 0x0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXTI7[3:0] EXTI6[3:0] EXTI5[3:0] EXTI4[3:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 EXTIx[3:0]: EXTI x configuration bits (x = 4 to 7)
These bits are written by software to select the source input for the EXTIx external interrupt.
x000: PA[x] pin
x001: PB[x] pin
x010: PC[x] pin
x011: PD[x] pin
x100: Reserved
x101: PF[x] pin
other configurations: reserved

Note: Some of the I/O pins mentioned in the above register may not be available on small
packages.

9.1.4 SYSCFG external interrupt configuration register 3

(SYSCFG_EXTICR3)
Address offset: 0x10
Reset value: 0x0000

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31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXTI11[3:0] EXTI10[3:0] EXTI9[3:0] EXTI8[3:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 EXTIx[3:0]: EXTI x configuration bits (x = 8 to 11)
These bits are written by software to select the source input for the EXTIx external interrupt.
x000: PA[x] pin
x001: PB[x] pin
x010: PC[x] pin
x011: PD[x] pin
x100: Reserved
x101: PF[x] pin
other configurations: reserved

Note: Some of the I/O pins mentioned in the above register may not be available on small
packages.

9.1.5 SYSCFG external interrupt configuration register 4

(SYSCFG_EXTICR4)
Address offset: 0x14
Reset value: 0x0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXTI15[3:0] EXTI14[3:0] EXTI13[3:0] EXTI12[3:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 EXTIx[3:0]: EXTI x configuration bits (x = 12 to 15)
These bits are written by software to select the source input for the EXTIx external interrupt.
x000: PA[x] pin
x001: PB[x] pin
x010: PC[x] pin
x011: PD[x] pin
x100: Reserved
x101: PF[x] pin
other configurations: reserved

Note: Some of the I/O pins mentioned in the above register may not be available on small
packages.

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9.1.6 SYSCFG configuration register 2 (SYSCFG_CFGR2)

Address offset: 0x18
System reset value: 0x0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SRAM_
SRAM_ LOCKUP
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. PARITY
PEF _LOCK
_LOCK
rc_w1 rw rw

Bits 31:9 Reserved, must be kept at reset value

Bit 8 SRAM_PEF: SRAM parity error flag
This bit is set by hardware when an SRAM parity error is detected. It is cleared by software by
writing ‘1’.
0: No SRAM parity error detected
1: SRAM parity error detected
Bits 7:2 Reserved, must be kept at reset value
Bit 1 SRAM_PARITY_LOCK: SRAM parity lock bit
This bit is set by software and cleared by a system reset. It can be used to enable and lock the
SRAM parity error signal connection to TIM1/15/16/17 Break input.
0: SRAM parity error disconnected from TIM1/15/16/17 Break input
1: SRAM parity error connected to TIM1/15/16/17 Break input
Bit 0 LOCKUP_LOCK: Cortex-M0 LOCKUP bit enable bit
This bit is set by software and cleared by a system reset. It can be use to enable and lock the
connection of Cortex-M0 LOCKUP (Hardfault) output to TIM1/15/16/17 Break input.
0: Cortex-M0 LOCKUP output disconnected from TIM1/15/16/17 Break input
1: Cortex-M0 LOCKUP output connected to TIM1/15/16/17 Break input

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9.1.7 SYSCFG register maps

The following table gives the SYSCFG register map and the reset values.

Table 24. SYSCFG register map and reset values

Offset Register
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12

10
11

9
8
7
6
5
4
3
2
1
0
USART1_RX_DMA_RMP
USART1_TX_DMA_RMP
USART3_DMA_RMP

TIM17_DMA_RMP
TIM16_DMA_RMP

PA11_PA12_RMP

MEM_MODE[1:0]
ADC_DMA_RMP
I2C_PA10_FMP

I2C_PB9_FMP
I2C_PB8_FMP
I2C_PB7_FMP
I2C_PB6_FMP
I2C_PA9_FMP
I2C2_FMP
I2C1_FMP
Res.
Res.
Res.
Res.
Res.

Res.
Res.

Res.
Res.
Res.

Res.

Res.

Res.
Res.
SYSCFG_CFGR1
0x00

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 X X
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
SYSCFG_EXTICR1 EXTI3[3:0] EXTI2[3:0] EXTI1[3:0] EXTI0[3:0]
0x08
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
SYSCFG_EXTICR2 EXTI7[3:0] EXTI6[3:0] EXTI5[3:0] EXTI4[3:0]
0x0C
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
SYSCFG_EXTICR3 EXTI11[3:0] EXTI10[3:0] EXTI9[3:0] EXTI8[3:0]
0x10
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

SYSCFG_EXTICR4 EXTI15[3:0] EXTI14[3:0] EXTI13[3:0] EXTI12[3:0]

0x14
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SRAM_PARITY_LOCK
LOCUP_LOCK
SRAM_PEF
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.
Res.
Res.
Res.
Res.
Res.
SYSCFG_CFGR2
0x18

Reset value 0 0 0

Refer to Section 2.2 on page 37 for the register boundary addresses.

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10 Direct memory access controller (DMA)

10.1 Introduction
The direct memory access (DMA) controller is a bus master and system peripheral.
The DMA is used to perform programmable data transfers between memory-mapped
peripherals and/or memories, upon the control of an off-loaded CPU.
The DMA controller features a single AHB master architecture.
There is one instance of DMA with 5 channels.
Each channel is dedicated to managing memory access requests from one or more
peripherals. The DMA includes an arbiter for handling the priority between DMA requests.

10.2 DMA main features

• Single AHB master
• Peripheral-to-memory, memory-to-peripheral, memory-to-memory and peripheral-to-
peripheral data transfers
• Access, as source and destination, to on-chip memory-mapped devices such as flash
memory, SRAM, and AHB and APB peripherals
• All DMA channels independently configurable:
– Each channel is associated either with a DMA request signal coming from a
peripheral, or with a software trigger in memory-to-memory transfers. This
configuration is done by software.
– Priority between the requests is programmable by software (4 levels per channel:
very high, high, medium, low) and by hardware in case of equality (such as
request to channel 1 has priority over request to channel 2).
– Transfer size of source and destination are independent (byte, half-word, word),
emulating packing and unpacking. Source and destination addresses must be
aligned on the data size.
– Support of transfers from/to peripherals to/from memory with circular buffer
management
– Programmable number of data to be transferred: 0 to 216 - 1
• Generation of an interrupt request per channel. Each interrupt request is caused from
any of the three DMA events: transfer complete, half transfer, or transfer error.

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10.3 DMA implementation

10.3.1 DMA
DMA is implemented with the hardware configuration parameters shown in the table below.

Table 25. DMA implementation

Feature DMA

Number of channels 5

10.3.2 DMA request mapping

DMA controller
The hardware requests from the peripherals are simply logically ORed before entering the
DMA. This means that on one channel, only one request must be enabled at a time (see
Figure 19).
The peripheral DMA requests can be independently activated/de-activated by programming
the DMA control bit in the registers of the corresponding peripheral.
Caution: A same peripheral request can be assigned to two different channels only if the application
ensures that these channels are not requested to be served at the same time. In other
words, if two different channels receive a same asserted peripheral request at the same
time, an unpredictable DMA hardware behavior occurs.
Table 26 and Table 27 list the DMA requests for each channel and alternate position.

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Figure 19. DMA request mapping

DMA Fixed hardware priority

Peripheral request signals

High priority

ADC(1),
TIM17_CH1, HW request 1 Channel1
TIM17_UP(1)
SW trigger 1
(MEM2MEM bit)

ADC(2), SPI1_RX,
USART1_TX,(1)
I2C1_TX , TIM1_CH1, HW request 2 Channel2
TIM3_CH3,
TIM17_CH1,(2) SW trigger 2
TIM17_UP (2) (MEM2MEM bit)

SPI1_TX,
USART1_RX(1),
I2C1_RX, TIM1_CH2,
Channel3 Internal
TIM3_CH4, TIM3_UP , HW request 3
DMA
TIM6_UP, TIM16_CH1,(1) request
TIM16_UP
(1) SW trigger 3
(MEM2MEM bit)

SPI2_RX,
(2)
USART1_TX,
I2C2_TX, USART2_TX,
TIM1_CH4,TIM1_TRIG, HW request 4 Channel4
TIM1_COM,
TIM3_CH1,TIM3_TRIG, SW trigger 4
TIM16_CH1,(2) (MEM2MEM bit)
TIM16_UP (2)

SPI2_TX,
(2)
USART1_RX,
HW request 5 Channel5
I2C2_RX, USART2_RX,
TIM1_CH3, TIM1_UP,
TIM15_CH1, SW trigger 5
TIM15_UP,TIM15_TRIG, (MEM2MEM bit) Low priority
TIM15_COM

MS32607V1

1. DMA request mapped on this DMA channel only if the corresponding remapping bit is cleared in SYSCFG configuration
register 1 (SYSCFG_CFGR1).
2. DMA request mapped on this DMA channel only if the corresponding remapping bit is set in SYSCFG configuration register
1 (SYSCFG_CFGR1).

Table 26. DMA requests for each channel

on STM32F030x4/x6/x8 and STM32F070x6/xB devices
Peripherals Channel 1 Channel 2 Channel 3 Channel 4 Channel 5
ADC ADC(1) ADC(2) - - -
SPI - SPI1_RX SPI1_TX SPI2_RX SPI2_TX
USART1_TX(1) USART1_RX(1) USART1_TX(2) USART1_RX(2)
USART -
USART3_TX(2) USART3_RX(2) USART2_TX USART2_RX
I2C - I2C1_TX I2C1_RX I2C2_TX I2C2_RX

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Table 26. DMA requests for each channel

on STM32F030x4/x6/x8 and STM32F070x6/xB devices (continued)
Peripherals Channel 1 Channel 2 Channel 3 Channel 4 Channel 5
TIM1_CH4
TIM1_CH3
TIM1 - TIM1_CH1 TIM1_CH2 TIM1_TRIG
TIM1_UP
TIM1_COM
TIM3_CH4 TIM3_CH1
TIM3 - TIM3_CH3 -
TIM3_UP TIM3_TRIG
TIM6 - - TIM6_UP - -
TIM7 - - - TIM7_UP -
TIM15_CH1
TIM15_UP
TIM15 - - - -
TIM15_TRIG
TIM15_COM
TIM16_CH1(1) TIM16_CH1(2)
TIM16 - - -
TIM16_UP(1) TIM16_UP(2)
TIM17_CH1(1) TIM17_CH1(2)
TIM17 - - -
TIM17_UP(1) TIM17_UP(2)
1. DMA request mapped on this DMA channel only if the corresponding remapping bit is cleared in SYSCFG configuration
register 1 (SYSCFG_CFGR1).
2. DMA request mapped on this DMA channel only if the corresponding remapping bit is set in SYSCFG configuration register
1 (SYSCFG_CFGR1).

Table 27. DMA requests for each channel on STM32F030xC devices

CxS[3:0] Channel 1 Channel 2 Channel 3 Channel 4 Channel 5

TIM1_CH4
TIM3_CH4
- TIM3_CH3 TIM1_TRIG TIM1_UP
TIM3_UP
TIM1_COM
TIM15_CH1
TIM15_UP
- - - -
TIM15_TRIG
TIM15_COM
ADC - TIM6_UP TIM7_UP -
0000
- USART1_TX USART1_RX USART2_TX USART2_ RX
- - - - -
- SPI1_RX SPI1_TX SPI2_RX SPI2_TX
- I2C1_TX I2C1_RX I2C2_TX I2C2_RX
- TIM1_CH1 TIM1_CH2 - TIM1_CH3
TIM17_CH1 TIM16_CH1 TIM3_CH1
- -
TIM17_UP TIM16_UP TIM3_TRIG
0001 ADC ADC TIM6_UP TIM7_UP -
0010 - I2C1_TX I2C1_RX I2C2_TX I2C2_RX
0011 - SPI1_RX SPI1_TX SPI2_RX SPI2_TX
0100 - TIM1_CH1 TIM1_CH2 - TIM1_CH3

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Table 27. DMA requests for each channel on STM32F030xC devices (continued)
CxS[3:0] Channel 1 Channel 2 Channel 3 Channel 4 Channel 5

0101 - - - - -
TIM3_CH1
0110 - - - -
TIM3_TRIG
TIM17_CH1 TIM17_CH1 TIM16_CH1 TIM16_CH1
0111 -
TIM17_UP TIM17_UP TIM16_UP TIM16_UP
1000 USART1_ RX USART1_TX USART1_RX USART1_TX USART1_ RX
1001 USART2_ RX USART2_TX USART2_ RX USART2_TX USART2_ RX
1010 USART3_ RX USART3_TX USART3_ RX USART3_TX USART3_ RX
1011 USART4_ RX USART4_TX USART4_ RX USART4_TX USART4_ RX
1100 USART5_ RX USART5_TX USART5_ RX USART5_TX USART5_ RX
1101 USART6_ RX USART6_TX USART6_ RX USART6_TX USART6_ RX

10.4 DMA functional description

10.4.1 DMA block diagram

The DMA block diagram is shown in the figure below.

Figure 20. DMA block diagram

FLITF Flash
System
Cortex-M0

SRAM
Bus matrix

DMA Ch.1
Reset & clock
Ch.2 DMA CRC GPIOA GPIOB
control (RCC)

up to
CH. 5 Bridge

Arbiter APB

GPIOC GPIOD GPIOF

AHB Slave
ADC SPI1
DMA request USART1 SPI2
USART2 TIM1
I2C2 TIM3
I2C1 TIM6
TIM7 TIM15
USART3 TIM16
USART4 TIM17

MS32606V1

The DMA controller performs direct memory transfer by sharing the AHB system bus with
other system masters. The bus matrix implements round-robin scheduling. DMA requests

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may stop the CPU access to the system bus for a number of bus cycles, when CPU and
DMA target the same destination (memory or peripheral).
According to its configuration through the AHB slave interface, the DMA controller arbitrates
between the DMA channels and their associated received requests. The DMA controller
also schedules the DMA data transfers over the single AHB port master.
The DMA controller generates an interrupt per channel to the interrupt controller.

10.4.2 DMA transfers

The software configures the DMA controller at channel level, in order to perform a block
transfer, composed of a sequence of AHB bus transfers.
A DMA block transfer may be requested from a peripheral, or triggered by the software in
case of memory-to-memory transfer.
After an event, the following steps of a single DMA transfer occur:
1. The peripheral sends a single DMA request signal to the DMA controller.
2. The DMA controller serves the request, depending on the priority of the channel
associated to this peripheral request.
3. As soon as the DMA controller grants the peripheral, an acknowledge is sent to the
peripheral by the DMA controller.
4. The peripheral releases its request as soon as it gets the acknowledge from the DMA
controller.
5. Once the request is de-asserted by the peripheral, the DMA controller releases the
acknowledge.
The peripheral may order a further single request and initiate another single DMA transfer.
The request/acknowledge protocol is used when a peripheral is either the source or the
destination of the transfer. For example, in case of memory-to-peripheral transfer, the
peripheral initiates the transfer by driving its single request signal to the DMA controller. The
DMA controller reads then a single data in the memory and writes this data to the peripheral.
For a given channel x, a DMA block transfer consists of a repeated sequence of:
• a single DMA transfer, encapsulating two AHB transfers of a single data, over the DMA
AHB bus master:
– a single data read (byte, half-word or word) from the peripheral data register or a
location in the memory, addressed through an internal current peripheral/memory
address register.
The start address used for the first single transfer is the base address of the
peripheral or memory, and is programmed in the DMA_CPARx or DMA_CMARx
register.
– a single data write (byte, half-word or word) to the peripheral data register or a
location in the memory, addressed through an internal current peripheral/memory
address register.
The start address used for the first transfer is the base address of the peripheral or
memory, and is programmed in the DMA_CPARx or DMA_CMARx register.
• post-decrementing of the programmed DMA_CNDTRx register
This register contains the remaining number of data items to transfer (number of AHB
‘read followed by write’ transfers).
This sequence is repeated until DMA_CNDTRx is null.

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Note: The AHB master bus source/destination address must be aligned with the programmed size
of the transferred single data to the source/destination.

10.4.3 DMA arbitration

The DMA arbiter manages the priority between the different channels.
When an active channel x is granted by the arbiter (hardware requested or software
triggered), a single DMA transfer is issued (such as a AHB ‘read followed by write’ transfer
of a single data). Then, the arbiter considers again the set of active channels and selects the
one with the highest priority.
The priorities are managed in two stages:
• software: priority of each channel is configured in the DMA_CCRx register, to one of
the four different levels:
– very high
– high
– medium
– low
• hardware: if two requests have the same software priority level, the channel with the
lowest index gets priority. For example, channel 2 gets priority over channel 4.
When a channel x is programmed for a block transfer in memory-to-memory mode,
re arbitration is considered between each single DMA transfer of this channel x. Whenever
there is another concurrent active requested channel, the DMA arbiter automatically
alternates and grants the other highest-priority requested channel, which may be of lower
priority than the memory-to-memory channel.

10.4.4 DMA channels

Each channel may handle a DMA transfer between a peripheral register located at a fixed
address, and a memory address. The amount of data items to transfer is programmable.
The register that contains the amount of data items to transfer is decremented after each
transfer.
A DMA channel is programmed at block transfer level.

Programmable data sizes

The transfer sizes of a single data (byte, half-word, or word) to the peripheral and memory
are programmable through, respectively, the PSIZE[1:0] and MSIZE[1:0] fields of the
DMA_CCRx register.

Pointer incrementation
The peripheral and memory pointers may be automatically incremented after each transfer,
depending on the PINC and MINC bits of the DMA_CCRx register.
If the incremented mode is enabled (PINC or MINC set to 1), the address of the next
transfer is the address of the previous one incremented by 1, 2 or 4, depending on the data
size defined in PSIZE[1:0] or MSIZE[1:0]. The first transfer address is the one programmed
in the DMA_CPARx or DMA_CMARx register. During transfers, these registers keep the
initially programmed value. The current transfer addresses (in the current internal
peripheral/memory address register) are not accessible by software.

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If the channel x is configured in non-circular mode, no DMA request is served after the last
data transfer (once the number of single data to transfer reaches zero). The DMA channel
must be disabled in order to reload a new number of data items into the DMA_CNDTRx
register.
Note: If the channel x is disabled, the DMA registers are not reset. The DMA channel registers
(DMA_CCRx, DMA_CPARx and DMA_CMARx) retain the initial values programmed during
the channel configuration phase.
In circular mode, after the last data transfer, the DMA_CNDTRx register is automatically
reloaded with the initially programmed value. The current internal address registers are
reloaded with the base address values from the DMA_CPARx and DMA_CMARx registers.

Channel configuration procedure

The following sequence is needed to configure a DMA channel x:
1. Set the peripheral register address in the DMA_CPARx register.
The data is moved from/to this address to/from the memory after the peripheral event,
or after the channel is enabled in memory-to-memory mode.
2. Set the memory address in the DMA_CMARx register.
The data is written to/read from the memory after the peripheral event or after the
channel is enabled in memory-to-memory mode.
3. Configure the total number of data to transfer in the DMA_CNDTRx register.
After each data transfer, this value is decremented.
4. Configure the parameters listed below in the DMA_CCRx register:
– the channel priority
– the data transfer direction
– the circular mode
– the peripheral and memory incremented mode
– the peripheral and memory data size
– the interrupt enable at half and/or full transfer and/or transfer error
5. Activate the channel by setting the EN bit in the DMA_CCRx register.
For code example refer to the Appendix Section A.5.1: DMA channel configuration
sequence.
A channel, as soon as enabled, may serve any DMA request from the peripheral connected
to this channel, or may start a memory-to-memory block transfer.
Note: The two last steps of the channel configuration procedure may be merged into a single
access to the DMA_CCRx register, to configure and enable the channel.

Channel state and disabling a channel

A channel x in active state is an enabled channel (read DMA_CCRx.EN = 1). An active
channel x is a channel that must have been enabled by the software (DMA_CCRx.EN set
to 1) and afterwards with no occurred transfer error (DMA_ISR.TEIFx = 0). In case there is a
transfer error, the channel is automatically disabled by hardware (DMA_CCRx.EN = 0).

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The three following use cases may happen:

• Suspend and resume a channel
This corresponds to the two following actions:
– An active channel is disabled by software (writing DMA_CCRx.EN = 0 whereas
DMA_CCRx.EN = 1).
– The software enables the channel again (DMA_CCRx.EN set to 1) without
reconfiguring the other channel registers (such as DMA_CNDTRx, DMA_CPARx
and DMA_CMARx).
This case is not supported by the DMA hardware, that does not guarantee that the
remaining data transfers are performed correctly.
• Stop and abort a channel
If the application does not need any more the channel, this active channel can be
disabled by software. The channel is stopped and aborted but the DMA_CNDTRx
register content may not correctly reflect the remaining data transfers versus the
aborted source and destination buffer/register.
• Abort and restart a channel
This corresponds to the software sequence: disable an active channel, then
reconfigure the channel and enable it again.
This is supported by the hardware if the following conditions are met:
– The application guarantees that, when the software is disabling the channel, a
DMA data transfer is not occurring at the same time over its master port. For
example, the application can first disable the peripheral in DMA mode, in order to
ensure that there is no pending hardware DMA request from this peripheral.
– The software must operate separated write accesses to the same DMA_CCRx
register: First disable the channel. Second reconfigure the channel for a next block
transfer including the DMA_CCRx if a configuration change is needed. There are
read-only DMA_CCRx register fields when DMA_CCRx.EN=1. Finally enable
again the channel.
When a channel transfer error occurs, the EN bit of the DMA_CCRx register is cleared by
hardware. This EN bit can not be set again by software to re-activate the channel x, until the
TEIFx bit of the DMA_ISR register is set.

Circular mode (in memory-to-peripheral/peripheral-to-memory transfers)

The circular mode is available to handle circular buffers and continuous data flows (such as
ADC scan mode). This feature is enabled using the CIRC bit in the DMA_CCRx register.
Note: The circular mode must not be used in memory-to-memory mode. Before enabling a
channel in circular mode (CIRC = 1), the software must clear the MEM2MEM bit of the
DMA_CCRx register. When the circular mode is activated, the amount of data to transfer is
automatically reloaded with the initial value programmed during the channel configuration
phase, and the DMA requests continue to be served.
In order to stop a circular transfer, the software needs to stop the peripheral from generating
DMA requests (such as quit the ADC scan mode), before disabling the DMA channel.
The software must explicitly program the DMA_CNDTRx value before starting/enabling a
transfer, and after having stopped a circular transfer.

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Memory-to-memory mode
The DMA channels may operate without being triggered by a request from a peripheral. This
mode is called memory-to-memory mode, and is initiated by software.
If the MEM2MEM bit in the DMA_CCRx register is set, the channel, if enabled, initiates
transfers. The transfer stops once the DMA_CNDTRx register reaches zero.
Note: The memory-to-memory mode must not be used in circular mode. Before enabling a
channel in memory-to-memory mode (MEM2MEM = 1), the software must clear the CIRC
bit of the DMA_CCRx register.

Peripheral-to-peripheral mode
Any DMA channel can operate in peripheral-to-peripheral mode:
• when the hardware request from a peripheral is selected to trigger the DMA channel
This peripheral is the DMA initiator and paces the data transfer from/to this peripheral
to/from a register belonging to another memory-mapped peripheral (this one being not
configured in DMA mode).
• when no peripheral request is selected and connected to the DMA channel
The software configures a register-to-register transfer by setting the MEM2MEM bit of
the DMA_CCRx register.

Programming transfer direction, assigning source/destination

The value of the DIR bit of the DMA_CCRx register sets the direction of the transfer, and
consequently, it identifies the source and the destination, regardless the source/destination
type (peripheral or memory):
• DIR = 1 defines typically a memory-to-peripheral transfer. More generally, if DIR = 1:
– The source attributes are defined by the DMA_MARx register, the MSIZE[1:0]
field and MINC bit of the DMA_CCRx register.
Regardless of their usual naming, these ‘memory’ register, field and bit are used to
define the source peripheral in peripheral-to-peripheral mode.
– The destination attributes are defined by the DMA_PARx register, the PSIZE[1:0]
field and PINC bit of the DMA_CCRx register.
Regardless of their usual naming, these ‘peripheral’ register, field and bit are used
to define the destination memory in memory-to-memory mode.
• DIR = 0 defines typically a peripheral-to-memory transfer. More generally, if DIR = 0:
– The source attributes are defined by the DMA_PARx register, the PSIZE[1:0] field
and PINC bit of the DMA_CCRx register.
Regardless of their usual naming, these ‘peripheral’ register, field and bit are used
to define the source memory in memory-to-memory mode
– The destination attributes are defined by the DMA_MARx register, the
MSIZE[1:0] field and MINC bit of the DMA_CCRx register.
Regardless of their usual naming, these ‘memory’ register, field and bit are used to
define the destination peripheral in peripheral-to-peripheral mode.

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10.4.5 DMA data width, alignment and endianness

When PSIZE[1:0] and MSIZE[1:0] are not equal, the DMA controller performs some data
alignments as described in the table below.

Table 28. Programmable data width and endian behavior (when PINC = MINC = 1)
Source Destinat
port ion port Destination
Number Source content:
width width content:
of data address / data
(MSIZE (PSIZE address / data
items to (DMA_CMARx if DMA transfers
if if (DMA_CPARx if
transfer DIR = 1, else
DIR = 1, DIR = 1, DIR = 1, else
(NDT) DMA_CPARx)
else else DMA_CMARx)
PSIZE) MSIZE)

@0x0 / B0 1: read B0[7:0] @0x0 then write B0[7:0] @0x0 @0x0 / B0

@0x1 / B1 2: read B1[7:0] @0x1 then write B1[7:0] @0x1 @0x1 / B1
8 8 4
@0x2 / B2 3: read B2[7:0] @0x2 then write B2[7:0] @0x2 @0x2 / B2
@0x3 / B3 4: read B3[7:0] @0x3 then write B3[7:0] @0x3 @0x3 / B3

@0x0 / B0 1: read B0[7:0] @0x0 then write 00B0[15:0] @0x0 @0x0 / 00B0
@0x1 / B1 2: read B1[7:0] @0x1 then write 00B1[15:0] @0x2 @0x2 / 00B1
8 16 4
@0x2 / B2 3: read B2[7:0] @0x2 then write 00B2[15:0] @0x4 @0x4 / 00B2
@0x3 / B3 4: read B3[7:0] @0x3 then write 00B3[15:0] @0x6 @0x6 / 00B3

@0x0 / B0 1: read B0[7:0] @0x0 then write 000000B0[31:0] @0x0 @0x0 / 000000B0
@0x1 / B1 2: read B1[7:0] @0x1 then write 000000B1[31:0] @0x4 @0x4 / 000000B1
8 32 4
@0x2 / B2 3: read B2[7:0] @0x2 then write 000000B2[31:0] @0x8 @0x8 / 000000B2
@0x3 / B3 4: read B3[7:0] @0x3 then write 000000B3[31:0] @0xC @0xC / 000000B3

@0x0 / B1B0 1: read B1B0[15:0] @0x0 then write B0[7:0] @0x0 @0x0 / B0
@0x2 / B3B2 2: read B3B2[15:0] @0x2 then write B2[7:0] @0x1 @0x1 / B2
16 8 4
@0x4 / B5B4 3: read B5B4[15:0] @0x4 then write B4[7:0] @0x2 @0x2 / B4
@0x6 / B7B6 4: read B7B6[15:0] @0x6 then write B6[7:0] @0x3 @0x3 / B6

@0x0 / B1B0 1: read B1B0[15:0] @0x0 then write B1B0[15:0] @0x0 @0x0 / B1B0
@0x2 / B3B2 2: read B3B2[15:0] @0x2 then write B3B2[15:0] @0x2 @0x2 / B3B2
16 16 4
@0x4 / B5B4 3: read B5B4[15:0] @0x4 then write B5B4[15:0] @0x4 @0x4 / B5B4
@0x6 / B7B6 4: read B7B6[15:0] @0x6 then write B7B6[15:0] @0x6 @0x6 / B7B6

@0x0 / B1B0 1: read B1B0[15:0] @0x0 then write 0000B1B0[31:0] @0x0 @0x0 / 0000B1B0
@0x2 / B3B2 2: read B3B2[15:0] @0x2 then write 0000B3B2[31:0] @0x4 @0x4 / 0000B3B2
16 32 4
@0x4 / B5B4 3: read B5B4[15:0] @0x4 then write 0000B5B4[31:0] @0x8 @0x8 / 0000B5B4
@0x6 / B7B6 4: read B7B6[15:0] @0x6 then write 0000B7B6[31:0] @0xC @0xC / 0000B7B6

@0x0 / B3B2B1B0 1: read B3B2B1B0[31:0] @0x0 then write B0[7:0] @0x0 @0x0 / B0
@0x4 / B7B6B5B4 2: read B7B6B5B4[31:0] @0x4 then write B4[7:0] @0x1 @0x1 / B4
32 8 4
@0x8 / BBBAB9B8 3: read BBBAB9B8[31:0] @0x8 then write B8[7:0] @0x2 @0x2 / B8
@0xC / BFBEBDBC 4: read BFBEBDBC[31:0] @0xC then write BC[7:0] @0x3 @0x3 / BC

@0x0 / B3B2B1B0 1: read B3B2B1B0[31:0] @0x0 then write B1B0[15:0] @0x0 @0x0 / B1B0
@0x4 / B7B6B5B4 2: read B7B6B5B4[31:0] @0x4 then write B5B4[15:0] @0x2 @0x2 / B5B4
32 16 4
@0x8 / BBBAB9B8 3: read BBBAB9B8[31:0] @0x8 then write B9B8[15:0] @0x4 @0x4 / B9B8
@0xC / BFBEBDBC 4: read BFBEBDBC[31:0] @0xC then write BDBC[15:0] @0x6 @0x6 / BDBC

@0x0 / B3B2B1B0 1: read B3B2B1B0[31:0] @0x0 then write B3B2B1B0[31:0] @0x0 @0x0 / B3B2B1B0
@0x4 / B7B6B5B4 2: read B7B6B5B4[31:0] @0x4 then write B7B6B5B4[31:0] @0x4 @0x4 / B7B6B5B4
32 32 4
@0x8 / BBBAB9B8 3: read BBBAB9B8[31:0] @0x8 then write BBBAB9B8[31:0] @0x8 @0x8 / BBBAB9B8
@0xC / BFBEBDBC 4: read BFBEBDBC[31:0] @0xC then write BFBEBDBC[31:0] @0xC @0xC / BFBEBDBC

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Addressing AHB peripherals not supporting byte/half-word write transfers

When the DMA controller initiates an AHB byte or half-word write transfer, the data are
duplicated on the unused lanes of the AHB master 32-bit data bus (HWDATA[31:0]).
When the AHB slave peripheral does not support byte or half-word write transfers and does
not generate any error, the DMA controller writes the 32 HWDATA bits as shown in the two
examples below:
• To write the half-word 0xABCD, the DMA controller sets the HWDATA bus to
0xABCDABCD with a half-word data size (HSIZE = HalfWord in AHB master bus).
• To write the byte 0xAB, the DMA controller sets the HWDATA bus to 0xABABABAB
with a byte data size (HSIZE = Byte in the AHB master bus).
Assuming the AHB/APB bridge is an AHB 32-bit slave peripheral that does not take into
account the HSIZE data, any AHB byte or half-word transfer is changed into a 32-bit APB
transfer as described below:
• An AHB byte write transfer of 0xB0 to one of the 0x0, 0x1, 0x2 or 0x3 addresses, is
converted to an APB word write transfer of 0xB0B0B0B0 to the 0x0 address.
• An AHB half-word write transfer of 0xB1B0 to the 0x0 or 0x2 addresses, is converted to
an APB word write transfer of 0xB1B0B1B0 to the 0x0 address.

10.4.6 DMA error management

A DMA transfer error is generated when reading from or writing to a reserved address
space. When a DMA transfer error occurs during a DMA read or write access, the faulty
channel x is automatically disabled through a hardware clear of its EN bit in the
corresponding DMA_CCRx register.
The TEIFx bit of the DMA_ISR register is set. An interrupt is then generated if the TEIE bit of
the DMA_CCRx register is set.
The EN bit of the DMA_CCRx register can not be set again by software (channel x re-
activated) until the TEIFx bit of the DMA_ISR register is cleared (by setting the CTEIFx bit of
the DMA_IFCR register).
When the software is notified with a transfer error over a channel which involves a
peripheral, the software has first to stop this peripheral in DMA mode, in order to disable any
pending or future DMA request. Then software may normally reconfigure both DMA and the
peripheral in DMA mode for a new transfer.

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10.5 DMA interrupts

An interrupt can be generated on a half transfer, transfer complete or transfer error for each
DMA channel x. Separate interrupt enable bits are available for flexibility.

Table 29. DMA interrupt requests

Interrupt
Interrupt request Interrupt event Event flag
enable bit

Half transfer on channel x HTIFx HTIEx

Transfer complete on channel x TCIFx TCIEx
Channel x interrupt
Transfer error on channel x TEIFx TEIEx
Half transfer or transfer complete or transfer error on channel x GIFx -

10.6 DMA registers

Refer to Section 1.2 for a list of abbreviations used in register descriptions.
The DMA registers have to be accessed by words (32-bit).

10.6.1 DMA interrupt status register (DMA_ISR)

Address offset: 0x00
Reset value: 0x0000 0000
Every status bit is cleared by hardware when the software sets the corresponding clear bit
or the corresponding global clear bit CGIFx, in the DMA_IFCR register.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. TEIF5 HTIF5 TCIF5 GIF5
r r r r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TEIF4 HTIF4 TCIF4 GIF4 TEIF3 HTIF3 TCIF3 GIF3 TEIF2 HTIF2 TCIF2 GIF2 TEIF1 HTIF1 TCIF1 GIF1
r r r r r r r r r r r r r r r r

Bits 31:20 Reserved, must be kept at reset value.

Bit 19 TEIF5: Transfer error (TE) flag for channel 5
0: No TE event
1: A TE event occurred.
Bit 18 HTIF5: Half transfer (HT) flag for channel 5
0: No HT event
1: An HT event occurred.
Bit 17 TCIF5: Transfer complete (TC) flag for channel 5
0: No TC event
1: A TC event occurred.
Bit 16 GIF5: global interrupt flag for channel 5
0: No TE, HT, or TC event
1: A TE, HT, or TC event occurred.

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Bit 15 TEIF4: Transfer error (TE) flag for channel 4

0: No TE event
1: A TE event occurred.
Bit 14 HTIF4: Half transfer (HT) flag for channel 4
0: No HT event
1: An HT event occurred.
Bit 13 TCIF4: Transfer complete (TC) flag for channel 4
0: No TC event
1: A TC event occurred.
Bit 12 GIF4: global interrupt flag for channel 4
0: No TE, HT, or TC event
1: A TE, HT, or TC event occurred.
Bit 11 TEIF3: Transfer error (TE) flag for channel 3
0: No TE event
1: A TE event occurred.
Bit 10 HTIF3: Half transfer (HT) flag for channel 3
0: No HT event
1: An HT event occurred.
Bit 9 TCIF3: Transfer complete (TC) flag for channel 3
0: No TC event
1: A TC event occurred.
Bit 8 GIF3: Global interrupt flag for channel 3
0: No TE, HT, or TC event
1: A TE, HT, or TC event occurred.
Bit 7 TEIF2: Transfer error (TE) flag for channel 2
0: No TE event
1: A TE event occurred.
Bit 6 HTIF2: Half transfer (HT) flag for channel 2
0: No HT event
1: An HT event occurred.
Bit 5 TCIF2: Transfer complete (TC) flag for channel 2
0: No TC event
1: A TC event occurred.
Bit 4 GIF2: Global interrupt flag for channel 2
0: No TE, HT, or TC event
1: A TE, HT, or TC event occurred.
Bit 3 TEIF1: Transfer error (TE) flag for channel 1
0: No TE event
1: A TE event occurred.
Bit 2 HTIF1: Half transfer (HT) flag for channel 1
0: No HT event
1: An HT event occurred.
Bit 1 TCIF1: Transfer complete (TC) flag for channel 1
0: No TC event
1: A TC event occurred.

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Bit 0 GIF1: Global interrupt flag for channel 1

0: No TE, HT, or TC event
1: A TE, HT, or TC event occurred.

10.6.2 DMA interrupt flag clear register (DMA_IFCR)

Address offset: 0x04
Reset value: 0x0000 0000
Setting the global clear bit CGIFx of the channel x in this DMA_IFCR register, causes the
DMA hardware to clear the corresponding GIFx bit and any individual flag among TEIFx,
HTIFx, TCIFx, in the DMA_ISR register.
Setting any individual clear bit among CTEIFx, CHTIFx, CTCIFx in this DMA_IFCR register,
causes the DMA hardware to clear the corresponding individual flag and the global flag
GIFx in the DMA_ISR register, provided that none of the two other individual flags is set.
Writing 0 into any flag clear bit has no effect.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CTEIF5 CHTIF5 CTCIF5 CGIF5
w w w w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTEIF4 CHTIF4 CTCIF4 CGIF4 CTEIF3 CHTIF3 CTCIF3 CGIF3 CTEIF2 CHTIF2 CTCIF2 CGIF2 CTEIF1 CHTIF1 CTCIF1 CGIF1
w w w w w w w w w w w w w w w w

Bits 31:20 Reserved, must be kept at reset value.

Bit 19 CTEIF5: Transfer error flag clear for channel 5
Bit 18 CHTIF5: Half transfer flag clear for channel 5
Bit 17 CTCIF5: Transfer complete flag clear for channel 5
Bit 16 CGIF5: Global interrupt flag clear for channel 5
Bit 15 CTEIF4: Transfer error flag clear for channel 4
Bit 14 CHTIF4: Half transfer flag clear for channel 4
Bit 13 CTCIF4: Transfer complete flag clear for channel 4
Bit 12 CGIF4: Global interrupt flag clear for channel 4
Bit 11 CTEIF3: Transfer error flag clear for channel 3
Bit 10 CHTIF3: Half transfer flag clear for channel 3
Bit 9 CTCIF3: Transfer complete flag clear for channel 3
Bit 8 CGIF3: Global interrupt flag clear for channel 3
Bit 7 CTEIF2: Transfer error flag clear for channel 2
Bit 6 CHTIF2: Half transfer flag clear for channel 2
Bit 5 CTCIF2: Transfer complete flag clear for channel 2
Bit 4 CGIF2: Global interrupt flag clear for channel 2
Bit 3 CTEIF1: Transfer error flag clear for channel 1

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Bit 2 CHTIF1: Half transfer flag clear for channel 1

Bit 1 CTCIF1: Transfer complete flag clear for channel 1
Bit 0 CGIF1: Global interrupt flag clear for channel 1

10.6.3 DMA channel x configuration register (DMA_CCRx)

Address offset: 0x08 + 0x14 * (x - 1), (x = 1 to 5)
Reset value: 0x0000 0000
The register fields/bits MEM2MEM, PL[1:0], MSIZE[1:0], PSIZE[1:0], MINC, PINC, and DIR
are read-only when EN = 1.
The states of MEM2MEM and CIRC bits must not be both high at the same time.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MEM2
Res. PL[1:0] MSIZE[1:0] PSIZE[1:0] MINC PINC CIRC DIR TEIE HTIE TCIE EN
MEM
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:15 Reserved, must be kept at reset value.

Bit 14 MEM2MEM: Memory-to-memory mode
0: Disabled
1: Enabled
Note: This bit is set and cleared by software. It must not be written when the channel is
enabled (EN = 1). It is read-only when the channel is enabled (EN = 1).
Bits 13:12 PL[1:0]: Priority level
00: Low
01: Medium
10: High
11: Very high
Note: This bitfield is set and cleared by software. It must not be written when the channel is
enabled (EN = 1). It is read-only when the channel is enabled (EN = 1).
Bits 11:10 MSIZE[1:0]: Memory size
Defines the data size of each DMA transfer to the identified memory.
In memory-to-memory mode, this bitfield identifies the memory source if DIR = 1 and the
memory destination if DIR = 0.
In peripheral-to-peripheral mode, this bitfield identifies the peripheral source if DIR = 1 and
the peripheral destination if DIR = 0.
00: 8 bits
01: 16 bits
10: 32 bits
11: Reserved
Note: This bitfield is set and cleared by software. It must not be written when the channel is
enabled (EN = 1). It is read-only when the channel is enabled (EN = 1).

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Bits 9:8 PSIZE[1:0]: Peripheral size

Defines the data size of each DMA transfer to the identified peripheral.
In memory-to-memory mode, this bitfield identifies the memory destination if DIR = 1 and the
memory source if DIR = 0.
In peripheral-to-peripheral mode, this bitfield identifies the peripheral destination if DIR = 1
and the peripheral source if DIR = 0.
00: 8 bits
01: 16 bits
10: 32 bits
11: Reserved
Note: This bitfield is set and cleared by software. It must not be written when the channel is
enabled (EN = 1). It is read-only when the channel is enabled (EN = 1).
Bit 7 MINC: Memory increment mode
Defines the increment mode for each DMA transfer to the identified memory.
In memory-to-memory mode, this bit identifies the memory source if DIR = 1 and the memory
destination if DIR = 0.
In peripheral-to-peripheral mode, this bit identifies the peripheral source if DIR = 1 and the
peripheral destination if DIR = 0.
0: Disabled
1: Enabled
Note: This bit is set and cleared by software. It must not be written when the channel is
enabled (EN = 1). It is read-only when the channel is enabled (EN = 1).
Bit 6 PINC: Peripheral increment mode
Defines the increment mode for each DMA transfer to the identified peripheral.
n memory-to-memory mode, this bit identifies the memory destination if DIR = 1 and the
memory source if DIR = 0.
In peripheral-to-peripheral mode, this bit identifies the peripheral destination if DIR = 1 and
the peripheral source if DIR = 0.
0: Disabled
1: Enabled
Note: This bit is set and cleared by software. It must not be written when the channel is
enabled (EN = 1). It is read-only when the channel is enabled (EN = 1).
Bit 5 CIRC: Circular mode
0: Disabled
1: Enabled
Note: This bit is set and cleared by software. It must not be written when the channel is
enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1).

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Bit 4 DIR: Data transfer direction

This bit must be set only in memory-to-peripheral and peripheral-to-memory modes.
0: Read from peripheral
– Source attributes are defined by PSIZE and PINC, plus the DMA_CPARx register.
This is still valid in a memory-to-memory mode.
– Destination attributes are defined by MSIZE and MINC, plus the DMA_CMARx
register. This is still valid in a peripheral-to-peripheral mode.
1: Read from memory
– Destination attributes are defined by PSIZE and PINC, plus the DMA_CPARx
register. This is still valid in a memory-to-memory mode.
– Source attributes are defined by MSIZE and MINC, plus the DMA_CMARx register.
This is still valid in a peripheral-to-peripheral mode.
Note: This bit is set and cleared by software. It must not be written when the channel is
enabled (EN = 1). It is read-only when the channel is enabled (EN = 1).
Bit 3 TEIE: Transfer error interrupt enable
0: Disabled
1: Enabled
Note: This bit is set and cleared by software. It must not be written when the channel is
enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1).
Bit 2 HTIE: Half transfer interrupt enable
0: Disabled
1: Enabled
Note: This bit is set and cleared by software. It must not be written when the channel is
enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1).
Bit 1 TCIE: Transfer complete interrupt enable
0: Disabled
1: Enabled
Note: This bit is set and cleared by software. It must not be written when the channel is
enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1).
Bit 0 EN: Channel enable
When a channel transfer error occurs, this bit is cleared by hardware. It can not be set again
by software (channel x re-activated) until the TEIFx bit of the DMA_ISR register is cleared
(by setting the CTEIFx bit of the DMA_IFCR register).
0: Disabled
1: Enabled
Note: This bit is set and cleared by software.

10.6.4 DMA channel x number of data to transfer register (DMA_CNDTRx)

Address offset: 0x0C + 0x14 * (x - 1), (x = 1 to 5)
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

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Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 NDT[15:0]: Number of data to transfer (0 to 216 - 1)
This bitfield is updated by hardware when the channel is enabled:
– It is decremented after each single DMA ‘read followed by write’ transfer, indicating
the remaining amount of data items to transfer.
– It is kept at zero when the programmed amount of data to transfer is reached, if the
channel is not in circular mode (CIRC = 0 in the DMA_CCRx register).
– It is reloaded automatically by the previously programmed value, when the transfer
is complete, if the channel is in circular mode (CIRC = 1).
If this bitfield is zero, no transfer can be served whatever the channel status (enabled or not).
Note: This bitfield is set and cleared by software. It must not be written when the channel is
enabled (EN = 1). It is read-only when the channel is enabled (EN = 1).

10.6.5 DMA channel x peripheral address register (DMA_CPARx)

Address offset: 0x10 + 0x14 * (x - 1), (x = 1 to 5)
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA[31:16]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:0 PA[31:0]: Peripheral address

It contains the base address of the peripheral data register from/to which the data is
read/written.
When PSIZE[1:0] = 01 (16 bits), bit 0 of PA[31:0] is ignored. Access is automatically aligned
to a half-word address.
When PSIZE[1:0] = 10 (32 bits), bits 1 and 0 of PA[31:0] are ignored. Access is automatically
aligned to a word address.
In memory-to-memory mode, this bitfield identifies the memory destination address if DIR = 1
and the memory source address if DIR = 0.
In peripheral-to-peripheral mode, this bitfield identifies the peripheral destination address if
DIR = 1 and the peripheral source address if DIR = 0.
Note: This bitfield is set and cleared by software. It must not be written when the channel is
enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1).

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10.6.6 DMA channel x memory address register (DMA_CMARx)

Address offset: 0x14 + 0x14 * (x - 1), (x = 1 to 5)
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA[31:16]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:0 MA[31:0]: Peripheral address

It contains the base address of the memory from/to which the data is read/written.
When MSIZE[1:0] = 01 (16 bits), bit 0 of MA[31:0] is ignored. Access is automatically aligned
to a half-word address.
When MSIZE[1:0] = 10 (32 bits), bits 1 and 0 of MA[31:0] are ignored. Access is automatically
aligned to a word address.
In memory-to-memory mode, this bitfield identifies the memory source address if DIR = 1 and
the memory destination address if DIR = 0.
In peripheral-to-peripheral mode, this bitfield identifies the peripheral source address if
DIR = 1 and the peripheral destination address if DIR = 0.
Note: This bitfield is set and cleared by software. It must not be written when the channel is
enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1).

10.6.7 DMA channel selection register (DMA_CSELR)

Address offset: 0xA8
Reset value: 0x0000 0000
This register is present only on STM32F030xC devices.
This register is used to manage the mapping of DMA channels as detailed in Section 10.3.2:
DMA request mapping.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. C5S[3:0]
rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
C4S[3:0] C3S[3:0] C2S[3:0] C1S[3:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:20 Reserved, must be kept at reset value.

Bits 19:16 C5S[3:0]: DMA channel 5 selection
Details available in Section 10.3.2: DMA request mapping
Bits 15:12 C4S[3:0]: DMA channel 4 selection
Details available in Section 10.3.2: DMA request mapping
Bits 11:8 C3S[3:0]: DMA channel 3 selection
Details available in Section 10.3.2: DMA request mapping

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RM0360 Direct memory access controller (DMA)

Bits 7:4 C2S[3:0]: DMA channel 2 selection

Details available in Section 10.3.2: DMA request mapping
Bits 3:0 C1S[3:0]: DMA channel 1 selection
Details available in Section 10.3.2: DMA request mapping

10.6.8 DMA register map

Table 30. DMA register map and reset values

Offset Register name

31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12

10
11

9
8
7
6
5
4
3
2
1
0
HTIF5
TCIF5

HTIF4
TCIF4

HTIF3
TCIF3

HTIF2
TCIF2

HTIF1
TCIF1
TEIF5

TEIF4

TEIF3

TEIF2

TEIF1
GIF5

GIF4

GIF3

GIF2

GIF1
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
DMA_ISR
0x000
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

CHTIF5
CTCIF5

CHTIF4
CTCIF4

CHTIF3
CTCIF3

CHTIF2
CTCIF2

CHTIF1
CTCIF1
CTEIF5

CTEIF4

CTEIF3

CTEIF2

CTEIF1
CGIF5

CGIF4

CGIF3

CGIF2

CGIF1
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
DMA_IFCR
0x004
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MEM2MEM

MSIZE[1:0]

PSIZE[1:0]
PL[1:0]

MINC

CIRC
PINC

HTIE
TCIE
TEIE
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

DIR

EN
DMA_CCR1
0x008

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

DMA_CNDTR1 NDTR[15:0]
0x00C
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DMA_CPAR1 PA[31:0]
0x010
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DMA_CMAR1 MA[31:0]
0x014
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x018 Reserved Reserved.
MEM2MEM

MSIZE[1:0]

PSIZE[1:0]
PL[1:0]

MINC

CIRC
PINC

HTIE
TCIE
TEIE
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

DIR

EN
DMA_CCR2
0x01C

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

DMA_CNDTR2 NDTR[15:0]
0x020
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DMA_CPAR2 PA[31:0]
0x024
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DMA_CMAR2 MA[31:0]
0x028
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x02C Reserved Reserved.
MEM2MEM

MSIZE[1:0]

PSIZE[1:0]
PL[1:0]

MINC

CIRC
PINC

HTIE
TCIE
TEIE
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

DIR

EN

DMA_CCR3
0x030

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

DMA_CNDTR3 NDTR[15:0]
0x034
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DMA_CPAR3 PA[31:0]
0x038
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DMA_CMAR3 MA[31:0]
0x03C
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x040 Reserved Reserved.

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Table 30. DMA register map and reset values (continued)

Offset Register name

31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12

10
11

9
8
7
6
5
4
3
2
1
0
MEM2MEM

MSIZE[1:0]

PSIZE[1:0]
PL[1:0]

MINC

CIRC
PINC

HTIE
TCIE
TEIE
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

DIR

EN
DMA_CCR4
0x044

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
DMA_CNDTR4 NDTR[15:0]
0x048
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DMA_CPAR4 PA[31:0]
0x04C
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DMA_CMAR4 MA[31:0]
0x050
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x054 Reserved Reserved.

MEM2MEM

MSIZE[1:0]

PSIZE[1:0]
PL[1:0]

MINC

CIRC
PINC

HTIE
TCIE
TEIE
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

DIR

EN
DMA_CCR5
0x058

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
DMA_CNDTR5 NDTR[15:0]
0x05C
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DMA_CPAR5 PA[31:0]
0x060
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DMA_CMAR5 MA[31:0]
0x064
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x068-
Reserved Reserved.
0x0A4
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

DMA_CSELR C5S[3:0] C4S[3:0] C3S[3:0] C2S[3:0] C1S[3:0]

0x0A8
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Refer to Section 2.2 for the register boundary addresses.

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RM0360 Interrupts and events

11 Interrupts and events

11.1 Nested vectored interrupt controller (NVIC)

11.1.1 NVIC main features

• 32 maskable interrupt channels (not including the sixteen Arm® Cortex®-M0 interrupt
lines)
• 4 programmable priority levels (2 bits of interrupt priority are used)
• Low-latency exception and interrupt handling
• Power management control
• Implementation of System control registers
The NVIC and the processor core interface are closely coupled, which enables low latency
interrupt processing and efficient processing of late arriving interrupts.
All interrupts including the core exceptions are managed by the NVIC. For more information
on exceptions and NVIC programming, refer to the PM0215 programming manual.
For code example refer to the Appendix section A.6.1: NVIC initialization.

11.1.2 SysTick calibration value register

The SysTick calibration value is set to 6000, which gives a reference time base of 1 ms with
the SysTick clock set to 6 MHz (max fHCLK / 8).

11.1.3 Interrupt and exception vectors

Table 31 is the vector table for STM32F0x0 devices. Consider peripheral availability on your
device.

Table 31. Vector table

Position

Priority

Type of
Acronym Description Address
priority

- - - - Reserved 0x0000 0000

- -3 Fixed Reset Reset 0x0000 0004
Non maskable interrupt. The RCC clock security
- -2 Fixed NMI 0x0000 0008
system (CSS) is linked to the NMI vector.
- -1 Fixed HardFault All classes of fault 0x0000 000C
- 3 Settable SVCall System service call via SWI instruction 0x0000 002C
- 5 Settable PendSV Pendable request for system service 0x0000 0038
- 6 Settable SysTick System tick timer 0x0000 003C
0 7 Settable WWDG Window watchdog interrupt 0x0000 0040
1 - - Reserved - 0x0000 0044
2 9 Settable RTC RTC interrupts (combined EXTI lines 17, 19 and 20) 0x0000 0048

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Table 31. Vector table (continued)

Position

Priority
Type of
Acronym Description Address
priority

3 10 Settable FLASH Flash global interrupt 0x0000 004C

4 11 Settable RCC RCC global interrupts 0x0000 0050
5 12 Settable EXTI0_1 EXTI Line[1:0] interrupts 0x0000 0054
6 13 Settable EXTI2_3 EXTI Line[3:2] interrupts 0x0000 0058
7 14 Settable EXTI4_15 EXTI Line[15:4] interrupts 0x0000 005C
8 - - Reserved - 0x0000 0060
9 16 Settable DMA_CH1 DMA channel 1 interrupt 0x0000 0064
10 17 Settable DMA_CH2_3 DMA channel 2 and 3 interrupts 0x0000 0068
11 18 Settable DMA_CH4_5 DMA channel 4 and 5 interrupts 0x0000 006C
12 19 Settable ADC ADC interrupts 0x0000 0070
TIM1_BRK_UP_
13 20 Settable TIM1 break, update, trigger and commutation interrupt 0x0000 0074
TRG_COM
14 21 Settable TIM1_CC TIM1 capture compare interrupt 0x0000 0078
15 - - Reserved - 0x0000 007C
16 23 Settable TIM3 TIM3 global interrupt 0x0000 0080
17 24 Settable TIM6 TIM6 global interrupt 0x0000 0084
18 - - Reserved - 0x0000 0088
19 26 Settable TIM14 TIM14 global interrupt 0x0000 008C
20 27 Settable TIM15 TIM15 global interrupt 0x0000 0090
21 28 Settable TIM16 TIM16 global interrupt 0x0000 0094
22 29 Settable TIM17 TIM17 global interrupt 0x0000 0098
23 30 Settable I2C1 I2C1 global interrupt 0x0000 009C
24 31 Settable I2C2 I2C2 global interrupt 0x0000 00A0
25 32 Settable SPI1 SPI1 global interrupt 0x0000 00A4
26 33 Settable SPI2 SPI2 global interrupt 0x0000 00A8
27 34 Settable USART1 USART1 global interrupt 0x0000 00AC
28 35 Settable USART2 USART2 global interrupt 0x0000 00B0
USART3, USART4, USART5, USART6 global
29 36 Settable USART3_4_5_6 0x0000 00B4
interrupts
30 - - Reserved - 0x0000 00B8
31 38 Settable USB USB global interrupt (combined with EXTI line 18) 0x0000 00BC

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11.2 Extended interrupts and events controller (EXTI)

The extended interrupts and events controller (EXTI) manages the external and internal
asynchronous events/interrupts and generates the event request to the CPU/Interrupt
controller and a wake-up request to the Power manager.
The EXTI allows the management of up to 28 external/internal event line (21 external event
lines and 7 internal event lines).
The active edge of each external interrupt line can be chosen independently, whilst for
internal interrupt the active edge is always the rising one. An interrupt could be left pending:
in case of an external one, a status register is instantiated and indicates the source of the
interrupt; an event is always a simple pulse and it’s used for triggering the core Wake-up
(e.g. Cortex-M0 RXEV pin). For internal interrupts, the pending status is assured by the
generating IP, so no need for a specific flag. Each input line can be masked independently
for interrupt or event generation, in addition the internal lines are sampled only in STOP
mode. This controller allows also to emulate the (only) external events by software,
multiplexed with the corresponding hardware event line, by writing to a dedicated register.

11.2.1 Main features

The EXTI main features are the following:
• Supports generation of up to 32 event/interrupt requests
• Independent mask on each event/interrupt line
• Automatic disable of internal lines when system is not in STOP mode
• Independent trigger for external event/interrupt line
• Dedicated status bit for external interrupt line
• Emulation for all the external event requests

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11.2.2 Block diagram

The extended interrupt/event block diagram is shown in Figure 21.

Figure 21. Extended interrupts and events controller (EXTI) block diagram

APB bus

PCLK Peripheral interface

Falling Rising Software

Event Interrupt Pending
trigger trigger interrupt
mask mask request
selection selection event
register register register
register register register

Interrupts
External Edge detect
events circuit
Events
Stop mode Rising
edge
Internal events detect

Wakeup

MS19952V3

11.2.3 Event management

The STM32F0x0 is able to handle external or internal events in order to wake up the core
(WFE). The wake-up event can be generated either by:
• enabling an interrupt in the peripheral control register but not in the NVIC, and enabling
the SEVONPEND bit in the Cortex-M0 System control register. When the MCU
resumes from WFE, the EXTI peripheral interrupt pending bit and the peripheral NVIC
IRQ channel pending bit (in the NVIC interrupt clear pending register) have to be
cleared.
• or by configuring an external or internal EXTI line in event mode. When the CPU
resumes from WFE, it is not necessary to clear the peripheral interrupt pending bit or
the NVIC IRQ channel pending bit as the pending bit corresponding to the event line is
not set.

11.2.4 Functional description

For the external interrupt lines, to generate the interrupt, the interrupt line should be
configured and enabled. This is done by programming the two trigger registers with the
desired edge detection and by enabling the interrupt request by writing a ‘1’ to the
corresponding bit in the interrupt mask register. When the selected edge occurs on the
external interrupt line, an interrupt request is generated. The pending bit corresponding to
the interrupt line is also set. This request is reset by writing a ‘1’ in the pending register.

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RM0360 Interrupts and events

For the internal interrupt lines, the active edge is always the rising edge, the interrupt is
enabled by default in the interrupt mask register and there is no corresponding pending bit
in the pending register.
To generate the event, the event line should be configured and enabled. This is done by
programming the two trigger registers with the desired edge detection and by enabling the
event request by writing a ‘1’ to the corresponding bit in the event mask register. When the
selected edge occurs on the event line, an event pulse is generated. The pending bit
corresponding to the event line is not set.
For the external lines, an interrupt/event request can also be generated by software by
writing a ‘1’ in the software interrupt/event register.
Note: The interrupts or events associated to the internal lines can be triggered only when the
system is in STOP mode. If the system is still running, no interrupt/event is generated.
For code example refer to the Appendix section A.6.2: External interrupt selection.

Hardware interrupt selection

To configure a line as interrupt source, use the following procedure:
• Configure the corresponding mask bit in the EXTI_IMR register.
• Configure the trigger selection bits of the interrupt line (EXTI_RTSR and EXTI_FTSR)
• Configure the enable and mask bits that control the NVIC IRQ channel mapped to the
EXTI so that an interrupt coming from one of the EXTI line can be correctly
acknowledged.

Hardware event selection

To configure a line as event source, use the following procedure:
• Configure the corresponding mask bit in the EXTI_EMR register.
• Configure the Trigger Selection bits of the Event line (EXTI_RTSR and EXTI_FTSR)

Software interrupt/event selection

Any of the external lines can be configured as software interrupt/event lines. The following is
the procedure to generate a software interrupt.
• Configure the corresponding mask bit (EXTI_IMR, EXTI_EMR)
• Set the required bit of the software interrupt register (EXTI_SWIER)

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11.2.5 External and internal interrupt/event line mapping

The GPIOs are connected to the 16 external interrupt/event lines in the following manner:

Figure 22. External interrupt/event GPIO mapping

EXTI0[3:0] bits in the SYSCFG_EXTICR1 register

PA0
PB0 EXTI0
PC0
PD0
PF0

EXTI1[3:0] bits in the SYSCFG_EXTICR1 register

PA1
PB1 EXTI1
PC1
PD1
PF1 ...

EXTI15[3:0] bits in the SYSCFG_EXTICR4 register

PA15
PB15 EXTI15
PC15
PD15
PF15

MSv36432V1

The remaining lines are connected as follow:

• EXTI line 16 is reserved (internally held low)
• EXTI line 17 is connected to the RTC Alarm event
• EXTI line 18 is connected to the internal USB wake-up event
• EXTI line 19 is connected to the RTC Tamper and TimeStamp events
• EXTI line 20 is connected to the RTC Wake-up event (available only on STM32F070xB
and STM32F030xC devices)
• EXTI line 21 is reserved (internally held low)
• EXTI line 22 is reserved (internally held low)
• EXTI line 23 is reserved (internally held low)
• EXTI line 24 is reserved (internally held low)
• EXTI line 25 is reserved (internally held low)
• EXTI line 26 is reserved (internally held low)
• EXTI line 27 is reserved (internally held low)
• EXTI line 28 is reserved (internally held low)
• EXTI line 29 is reserved (internally held low)
• EXTI line 30 is reserved (internally held low)
• EXTI line 31 is reserved (internally held low)
Note: EXTI lines which are reserved or not used on some devices are considered as internal.

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RM0360 Interrupts and events

11.3 EXTI registers

Refer to Section 1.2 on page 33 for a list of abbreviations used in register descriptions.
The peripheral registers have to be accessed by words (32-bit).

11.3.1 Interrupt mask register (EXTI_IMR)

Address offset: 0x00
Reset value: 0x0FF4 0000 (STM32F030x4, STM32F030x6 devices)
0x7FF4 0000 (STM32F070x6 devices)
0x0F94 0000 (STM32F030x8 devices)
0x7F84 0000 (STM32F070xB and STM32F030xC devices)
Note: The reset value for the internal lines is set to ‘1’ in order to enable the interrupt by default.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IM31 IM30 IM29 IM28 IM27 IM26 IM25 IM24 IM23 IM22 IM21 IM20 IM19 IM18 IM17 IM16
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IM15 IM14 IM13 IM12 IM11 IM10 IM9 IM8 IM7 IM6 IM5 IM4 IM3 IM2 IM1 IM0
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:0 IMx: Interrupt Mask on line x (x = 31 to 0)

0: Interrupt request from Line x is masked
1: Interrupt request from Line x is not masked

11.3.2 Event mask register (EXTI_EMR)

Address offset: 0x04
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EM31 EM30 EM29 EM28 EM27 EM26 EM25 EM24 EM23 EM22 EM21 EM20 EM19 EM18 EM17 EM16
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EM15 EM14 EM13 EM12 EM11 EM10 EM9 EM8 EM7 EM6 EM5 EM4 EM3 EM2 EM1 EM0
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:0 EMx: Event mask on line x (x = 31 to 0)

0: Event request from Line x is masked
1: Event request from Line x is not masked

11.3.3 Rising trigger selection register (EXTI_RTSR)

Address offset: 0x08
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RT31 Res. Res. Res. Res. Res. Res. Res. Res. RT22 RT21 RT20 RT19 Res. RT17 RT16
rw rw rw rw rw rw rw

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15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RT15 RT14 RT13 RT12 RT11 RT10 RT9 RT8 RT7 RT6 RT5 RT4 RT3 RT2 RT1 RT0
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bit 31 RT31: Rising trigger event configuration bit of line 31

0: Rising trigger disabled (for Event and Interrupt) for input line
1: Rising trigger enabled (for Event and Interrupt) for input line.
Bits 30:23 Reserved, must be kept at reset value.
Bits 22:19 RTx: Rising trigger event configuration bit of line x (x = 22 to 19)
0: Rising trigger disabled (for Event and Interrupt) for input line
1: Rising trigger enabled (for Event and Interrupt) for input line.
Bit 18 Reserved, must be kept at reset value.
Bits 17:0 RTx: Rising trigger event configuration bit of line x (x = 17 to 0)
0: Rising trigger disabled (for Event and Interrupt) for input line
1: Rising trigger enabled (for Event and Interrupt) for input line.

Note: The external wake-up lines are edge triggered. No glitches must be generated on these
lines. If a rising edge on an external interrupt line occurs during a write operation to the
EXTI_RTSR register, the pending bit is not set.
Rising and falling edge triggers can be set for the same interrupt line. In this case, both
generate a trigger condition.

11.3.4 Falling trigger selection register (EXTI_FTSR)

Address offset: 0x0C
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FT31 Res. Res. Res. Res. Res. Res. Res. Res. FT22 FT21 FT20 FT19 Res. FT17 FT16
rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FT15 FT14 FT13 FT12 FT11 FT10 FT9 FT8 FT7 FT6 FT5 FT4 FT3 FT2 FT1 FT1
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bit 31 FT31: Falling trigger event configuration bit of line 31

0: Falling trigger disabled (for Event and Interrupt) for input line
1: Falling trigger enabled (for Event and Interrupt) for input line.
Bits 30:23 Reserved, must be kept at reset value.
Bits 22:19 FTx: Falling trigger event configuration bit of line x (x = 22 to 19)
0: Falling trigger disabled (for Event and Interrupt) for input line.
1: Falling trigger enabled (for Event and Interrupt) for input line.
Bit 18 Reserved, must be kept at reset value.
Bits 17:0 FTx: Falling trigger event configuration bit of line x (x = 17 to 0)
0: Falling trigger disabled (for Event and Interrupt) for input line.
1: Falling trigger enabled (for Event and Interrupt) for input line.

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Note: The external wake-up lines are edge triggered. No glitches must be generated on these
lines. If a falling edge on an external interrupt line occurs during a write operation to the
EXTI_FTSR register, the pending bit is not set.
Rising and falling edge triggers can be set for the same interrupt line. In this case, both
generate a trigger condition.

11.3.5 Software interrupt event register (EXTI_SWIER)

Address offset: 0x10
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SWI31 Res. Res. Res. Res. Res. Res. Res. Res. SWI22 SWI21 SWI20 SWI19 Res. SWI17 SWI16
rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

SWI15 SWI14 SWI13 SWI12 SWI11 SWI10 SWI9 SWI8 SWI7 SWI6 SWI5 SWI4 SWI3 SWI2 SWI1 SWI0

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bit 31 SWI31: Software interrupt on line 31

If the interrupt is enabled on this line in the EXTI_IMR, writing a ‘1’ to this bit when it is at ‘0’
sets the corresponding pending bit in EXTI_PR resulting in an interrupt request generation.
This bit is cleared by clearing the corresponding bit of EXTI_PR (by writing a ‘1’ to the bit)
Bits 30:23 Reserved, must be kept at reset value.
Bits 22:19 SWIx: Software interrupt on line x (x = 22 to 19)
If the interrupt is enabled on this line in the EXTI_IMR, writing a ‘1’ to this bit when it is at ‘0’
sets the corresponding pending bit in EXTI_PR resulting in an interrupt request generation.
This bit is cleared by clearing the corresponding bit of EXTI_PR (by writing a ‘1’ to the bit)
Bit 18 Reserved, must be kept at reset value.
Bits 17:0 SWIx: Software interrupt on line x (x = 17 to 0)
If the interrupt is enabled on this line in the EXTI_IMR, writing a ‘1’ to this bit when it is at ‘0’
sets the corresponding pending bit in EXTI_PR resulting in an interrupt request generation.
This bit is cleared by clearing the corresponding bit of EXTI_PR (by writing a ‘1’ to the bit).

11.3.6 Pending register (EXTI_PR)

Address offset: 0x14
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PIF31 Res. Res. Res. Res. Res. Res. Res. Res. PIF22 PIF21 PIF20 PIF19 Res. PIF17 PIF16
rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PIF15 PIF14 PIF13 PIF12 PIF11 PIF10 PIF9 PIF8 PIF7 PIF6 PIF5 PIF4 PIF3 PIF2 PIF1 PIF0
rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1

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Bit 31 PIF31: Pending bit on line 31

0: no trigger request occurred
1: selected trigger request occurred
This bit is set when the selected edge event arrives on the external interrupt line. This bit is
cleared by writing a 1 to the bit.
Bits 30:23 Reserved, must be kept at reset value.
Bits 22:19 PIFx: Pending bit on line x (x = 22 to 19)
0: no trigger request occurred
1: selected trigger request occurred
This bit is set when the selected edge event arrives on the external interrupt line. This bit is
cleared by writing a 1 to the bit.
Bit 18 Reserved, must be kept at reset value.
Bits 17:0 PIFx: Pending bit on line x (x = 17 to 0)
0: no trigger request occurred
1: selected trigger request occurred
This bit is set when the selected edge event arrives on the external interrupt line. This bit is
cleared by writing a 1 to the bit.

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11.3.7 EXTI register map

The following table gives the EXTI register map and the reset values.

Table 32. External interrupt/event controller register map and reset values

Offset Register 31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12

10
11

9
8
7
6
5
4
3
2
1
0
EXTI_IMR IM[31:0]
0x00
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
EXTI_EMR EM[31:0]
0x04
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RT31

RT23
RT22
RT21
RT20
RT19
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.
EXTI_RTSR RT[17:0]
0x08
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
FT31

FT23
FT22
FT21
FT20
FT19
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.
EXTI_FTSR FT[17:0]
0x0C
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SWI31

SWI23
SWI22
SWI21
SWI20
SWI19
Res.
Res.
Res.
Res.
Res.
Res.
Res.

EXTI_SWIER Res. SWI[17:0]

0x10
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
PIF31

PIF23
PIF22
PIF21
PIF20
PIF19
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.

EXTI_PR PIF[17:0]
0x14
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Refer to Section 2.2 on page 37 for the register boundary addresses.

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12 Analog-to-digital converter (ADC)

12.1 Introduction
The 12-bit ADC is a successive approximation analog-to-digital converter. It has up to 18
multiplexed channels allowing it to measure signals from 16 external and 2 internal sources.
A/D conversion of the various channels can be performed in single, continuous, scan or
discontinuous mode. The result of the ADC is stored in a left-aligned or right-aligned 16-bit
data register.
The analog watchdog feature allows the application to detect if the input voltage goes
outside the user-defined higher or lower thresholds.
An efficient low-power mode is implemented to allow very low consumption at low
frequency.

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12.2 ADC main features

• High performance
– 12-bit, 10-bit, 8-bit or 6-bit configurable resolution
– ADC conversion time: 1.0 µs for 12-bit resolution (1 MHz), 0.93 µs conversion
time for 10-bit resolution, faster conversion times can be obtained by lowering
resolution.
– Self-calibration
– Programmable sampling time
– Data alignment with built-in data coherency
– DMA support
• Low-power
– The application can reduce PCLK frequency for low-power operation while still
keeping optimum ADC performance. For example, 1.0 µs conversion time is kept,
whatever the PCLK frequency
– Wait mode: prevents ADC overrun in applications with low PCLK frequency
– Auto off mode: ADC is automatically powered off except during the active
conversion phase. This dramatically reduces the power consumption of the ADC.
• Analog input channels
– 16 external analog inputs
– 1 channel for internal temperature sensor (VSENSE)
– 1 channel for internal reference voltage (VREFINT)
• Start-of-conversion can be initiated:
– By software
– By hardware triggers with configurable polarity (timer events)
• Conversion modes
– Can convert a single channel or can scan a sequence of channels.
– Single mode converts selected inputs once per trigger
– Continuous mode converts selected inputs continuously
– Discontinuous mode
• Interrupt generation at the end of sampling, end of conversion, end of sequence
conversion, and in case of analog watchdog or overrun events
• Analog watchdog
• ADC input range: VSSA ≤ VIN ≤ VDDA

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12.3 ADC functional description

Figure 23 shows the ADC block diagram and Table 33 gives the ADC pin description.

Figure 23. ADC block diagram

VDDA >
_ VDD

Analog supply
SCANDIR up/ 2.4 V to 3.6 V AREADY
down EOSMP ADC interrupt
AUTOFF auto-off EOSEQ IRQ
CH_SEL[18:0] EOC CPU
mode
CONT single/ ADEN/ADDIS OVR master
DATA[11:0] AWD
cont.

AHB
AHB
to slave
Supply and APB
ADCAL self- reference master
VREF APB
calibration DMA
Input interface
VTS
selection SAR ADC
VIN DMA request
& scan SMP[2:0]
ADC_IN[15:0] control DMAEN
VIN[x] sampling time
Converted data DMACFG
start
Start & Stop
control
OVRMOD AWDx
AUTDLY overrun mode
auto-delayed conv. ADSTART Analog
S/W trigger ALIGN left/right AWDxEN watchdog
ADSTP
RSE[1:0] AWDxSGL
12, 10, 8, 6 bits AWDCHx[4:0]
LTx[11:0]
HTx[11:0]

TIM1_TRGO
TIM1_CC4 H/W
TIM2_TRGO trigger DISCEN
TIM3_TRGO discontinuous
EXTEN[1:0]
mode
TIM15_TRGO trigger enable
and edge selection

EXTSEL[2:0]
trigger selection

MSv32608V3

12.3.1 ADC pins and internal signals

Table 33. ADC input/output pins

Name Signal type Remarks

Input, analog power Analog power supply and positive reference voltage
VDDA
supply for the ADC
Input, analog supply
VSSA Ground for analog power supply
ground
ADC_INx Analog input signals 16 external analog input channels

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Table 34. ADC internal input/output signals

Internal signal
Signal type Description
name

Analog Input Connected either to internal channels or to ADC_INi

VIN[x]
channels external channels
TRGx Input ADC conversion triggers
VSENSE Input Internal temperature sensor output voltage
VREFINT Input Internal voltage reference output voltage
Internal analog watchdog output signal connected to on-
ADC_AWDx_OUT Output
chip timers (x = Analog watchdog number = 1)

Table 35. External triggers

Name Source EXTSEL[2:0]

TRG0 TIM1_TRGO 000

TRG1 TIM1_CC4 001
TRG2 TIM2_TRGO 010
TRG3 TIM3_TRGO 011
TRG4 TIM15_TRGO 100
TRG5 Reserved 101
TRG6 Reserved 110
TRG7 Reserved 111

12.3.2 Calibration (ADCAL)

The ADC has a calibration feature. During the calibration phase, the ADC calculates a
calibration factor which is internally applied to the ADC until the next ADC power-off. The
application must not use the ADC during calibration and must wait until it is complete.
Calibration should be performed before starting A/D conversion. It removes the offset error
which may vary from chip to chip due to process variation.
The calibration is initiated by software by setting ADCAL bit to 1. It can only be initiated
when the ADC is disabled (when ADEN = 0). ADCAL bit stays at 1 during the whole
calibration sequence. It is then cleared by hardware as soon the calibration completes. After
this, the calibration factor can be read from the ADC_DR register (from bits 6 to 0).
The internal analog calibration is kept if the ADC is disabled (ADEN = 0). When the ADC
operating conditions change (VDDA changes are the main contributor to ADC offset
variations and temperature change to a lesser extend), it is recommended to re-run a
calibration cycle.
The calibration factor is lost each time power is removed from the ADC (for example when
the product enters Standby mode).

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Calibration software procedure

1. Ensure that ADEN = 0 and DMAEN = 0.
2. Set ADCAL = 1.
3. Wait until ADCAL = 0.
4. The calibration factor can be read from bits 6:0 of ADC_DR.
For code example refer to the Appendix section A.7.1: ADC calibration.

Figure 24. ADC calibration

t CAB

ADCAL
ADC State OFF Startup CALIBRATE OFF

ADC_DR[6:0] 0x00 CALIBRATION FACTOR

by S/W by H/W
MS30335V1

12.3.3 ADC on-off control (ADEN, ADDIS, ADRDY)

At power-up, the ADC is disabled and put in power-down mode (ADEN = 0).
As shown in Figure 25, the ADC needs a stabilization time of tSTAB before it starts
converting accurately.
Two control bits are used to enable or disable the ADC:
• Set ADEN = 1 to enable the ADC. The ADRDY flag is set as soon as the ADC is ready
for operation.
• Set ADDIS = 1 to disable the ADC and put the ADC in power down mode. The ADEN
and ADDIS bits are then automatically cleared by hardware as soon as the ADC is fully
disabled.
Conversion can then start either by setting ADSTART to 1 (refer to Section 12.4: Conversion
on external trigger and trigger polarity (EXTSEL, EXTEN) on page 193) or when an external
trigger event occurs if triggers are enabled.
Follow this procedure to enable the ADC:
1. Clear the ADRDY bit in ADC_ISR register by programming this bit to 1.
2. Set ADEN = 1 in the ADC_CR register.
3. Wait until ADRDY = 1 in the ADC_ISR register and continue to write ADEN = 1
(ADRDY is set after the ADC startup time). This can be handled by interrupt if the
interrupt is enabled by setting the ADRDYIE bit in the ADC_IER register.
For code example refer to the Appendix section A.7.2: ADC enable sequence.

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Follow this procedure to disable the ADC:

1. Check that ADSTART = 0 in the ADC_CR register to ensure that no conversion is
ongoing. If required, stop any ongoing conversion by writing 1 to the ADSTP bit in the
ADC_CR register and waiting until this bit is read at 0.
2. Set ADDIS = 1 in the ADC_CR register.
3. If required by the application, wait until ADEN = 0 in the ADC_CR register, indicating
that the ADC is fully disabled (ADDIS is automatically reset once ADEN = 0).
4. Clear the ADRDY bit in ADC_ISR register by programming this bit to 1 (optional).
For code example refer to the Appendix section A.7.3: ADC disable sequence.
Caution: ADEN bit cannot be set when ADCAL = 1 and during four ADC clock cycles after the
ADCAL bit is cleared by hardware (end of calibration).

Figure 25. Enabling/disabling the ADC

ADEN
t STAB

ADR DY

ADDIS

ADC
OFF Startup RDY CONVERTING CH RDY REQ
stat -OF OFF

by S/W by H/W
MS30264V2

Note: In Auto-off mode (AUTOFF = 1) the power-on/off phases are performed automatically, by
hardware and the ADRDY flag is not set.
When the bus clock is much faster than the analog ADC_CK clock, a minimum delay of ten
analog ADC_CK cycles must be respected between ADEN and ADDIS bit settings.

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12.3.4 ADC clock (CKMODE)

The ADC has a dual clock-domain architecture, so that the ADC can be fed with a clock
(ADC asynchronous clock) independent from the APB clock (PCLK).

Figure 26. ADC clock scheme

RCC
(Reset & Clock Controller) APB interface
PCLK
Bits CKMODE[1:0]
of ADC_CFGR2
Analog
/2 or /4 Others ADC_CK Analog
ADC
00
ADC
asynchronous
clock Bits CKMODE[1:0] of
ADC_CFGR2

MSv31473V2

1. Refer to Section Reset and clock control (RCC) for how the PCLK clock and ADC asynchronous clock are
enabled.
The input clock of the analog ADC can be selected between two different clock sources (see
Figure 26: ADC clock scheme to see how the PCLK clock and the ADC asynchronous clock
are enabled):
a) The ADC clock can be a specific clock source, named “ADC asynchronous clock“
which is independent and asynchronous with the APB clock.
Refer to RCC Section for more information on generating this clock source.
To select this scheme, bits CKMODE[1:0] of the ADC_CFGR2 register must be
reset.
For code example refer to the Appendix section A.7.4: ADC clock selection.
b) The ADC clock can be derived from the APB clock of the ADC bus interface,
divided by a programmable factor (1, 2 or 4) according to bits CKMODE[1:0].
To select this scheme, bits CKMODE[1:0] of the ADC_CFGR2 register must be
different from “00”.
Option a) has the advantage of reaching the maximum ADC clock frequency whatever the
APB clock scheme selected.
Option b) has the advantage of bypassing the clock domain resynchronizations. This can be
useful when the ADC is triggered by a timer and if the application requires that the ADC is
precisely triggered without any uncertainty (otherwise, an uncertainty of the trigger instant is
added by the resynchronizations between the two clock domains).

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Table 36. Latency between trigger and start of conversion(1)

Latency between the trigger event
ADC clock source CKMODE[1:0]
and the start of conversion

Dedicated 14MHz clock 00 Latency is not deterministic (jitter)

Latency is deterministic (no jitter) and equal to
PCLK divided by 2 01
2.75 ADC clock cycles
Latency is deterministic (no jitter) and equal to
PCLK divided by 4 10
2.625 ADC clock cycles
1. Refer to the device datasheet for the maximum ADC_CLK frequency.

12.3.5 Configuring the ADC

The software must write the ADCAL and ADEN bits in the ADC_CR register only when the
ADC is disabled (ADEN cleared).
The software must only write to the ADSTART and ADDIS bits in the ADC_CR register only
if the ADC is enabled and there is no pending request to disable the ADC (ADEN = 1 and
ADDIS = 0).
For all the other control bits in the ADC_IER, ADC_CFGRi, ADC_SMPR, ADC_TR,
ADC_CHSELR and ADC_CCR registers, refer to the description of the corresponding
control bit in Section 12.10: ADC registers.
The software must only write to the ADSTP bit in the ADC_CR register if the ADC is enabled
(and possibly converting) and there is no pending request to disable the ADC (ADSTART =
1 and ADDIS = 0).
Note: There is no hardware protection preventing software from making write operations forbidden
by the above rules. If such a forbidden write access occurs, the ADC may enter an
undefined state. To recover correct operation in this case, the ADC must be disabled (clear
ADEN = 0 and all the bits in the ADC_CR register).

12.3.6 Channel selection (CHSEL, SCANDIR)

There are up to 18 multiplexed channels:
• 16 analog inputs from GPIO pins (ADC_INx)
• 2 internal analog inputs (temperature sensor, internal reference voltage)
It is possible to convert a single channel or a sequence of channels.
The sequence of the channels to be converted can be programmed in the ADC_CHSELR
channel selection register: each analog input channel has a dedicated selection bit
(CHSELx).
The order in which the channels is scanned can be configured by programming the bit
SCANDIR bit in the ADC_CFGR1 register:
• SCANDIR = 0: forward scan Channel 0 to Channel 17
• SCANDIR = 1: backward scan Channel 17 to Channel 0

Temperature sensor, VREFINT internal channels

The temperature sensor is connected to channel ADC VIN[16].

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The internal voltage reference VREFINT is connected to channel ADC VIN[17].

12.3.7 Programmable sampling time (SMP)

Before starting a conversion, the ADC needs to establish a direct connection between the
voltage source to be measured and the embedded sampling capacitor of the ADC. This
sampling time must be enough for the input voltage source to charge the sample and hold
capacitor to the input voltage level.
Having a programmable sampling time allows the conversion speed to be trimmed
according to the input resistance of the input voltage source.
The ADC samples the input voltage for a number of ADC clock cycles that can be modified
using the SMP[2:0] bits in the ADC_SMPR register.
This programmable sampling time is common to all channels. If required by the application,
the software can change and adapt this sampling time between each conversions.
The total conversion time is calculated as follows:
tCONV = Sampling time + 12.5 x ADC clock cycles
Example:
With ADC_CLK = 14 MHz and a sampling time of 1.5 ADC clock cycles:
tCONV = 1.5 + 12.5 = 14 ADC clock cycles = 1 µs
The ADC indicates the end of the sampling phase by setting the EOSMP flag.

12.3.8 Single conversion mode (CONT = 0)

In Single conversion mode, the ADC performs a single sequence of conversions, converting
all the channels once. This mode is selected when CONT = 0 in the ADC_CFGR1 register.
Conversion is started by either:
• Setting the ADSTART bit in the ADC_CR register
• Hardware trigger event
Inside the sequence, after each conversion is complete:
• The converted data are stored in the 16-bit ADC_DR register
• The EOC (end of conversion) flag is set
• An interrupt is generated if the EOCIE bit is set
After the sequence of conversions is complete:
• The EOS (end of sequence) flag is set
• An interrupt is generated if the EOSIE bit is set
Then the ADC stops until a new external trigger event occurs or the ADSTART bit is set
again.
Note: To convert a single channel, program a sequence with a length of 1.

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12.3.9 Continuous conversion mode (CONT = 1)

In continuous conversion mode, when a software or hardware trigger event occurs, the ADC
performs a sequence of conversions, converting all the channels once and then
automatically re-starts and continuously performs the same sequence of conversions. This
mode is selected when CONT = 1 in the ADC_CFGR1 register. Conversion is started by
either:
• Setting the ADSTART bit in the ADC_CR register
• Hardware trigger event
Inside the sequence, after each conversion is complete:
• The converted data are stored in the 16-bit ADC_DR register
• The EOC (end of conversion) flag is set
• An interrupt is generated if the EOCIE bit is set
After the sequence of conversions is complete:
• The EOS (end of sequence) flag is set
• An interrupt is generated if the EOSIE bit is set
Then, a new sequence restarts immediately and the ADC continuously repeats the
conversion sequence.
Note: To convert a single channel, program a sequence with a length of 1.
It is not possible to have both discontinuous mode and continuous mode enabled: it is
forbidden to set both bits DISCEN = 1 and CONT = 1.

12.3.10 Starting conversions (ADSTART)

Software starts ADC conversions by setting ADSTART = 1.
When ADSTART is set, the conversion:
• Starts immediately if EXTEN = 00 (software trigger)
• At the next active edge of the selected hardware trigger if EXTEN ≠ 00
The ADSTART bit is also used to indicate whether an ADC operation is currently ongoing. It
is possible to re-configure the ADC while ADSTART = 0, indicating that the ADC is idle.
The ADSTART bit is cleared by hardware:
• In single mode with software trigger (CONT = 0, EXTEN = 00)
– At any end of conversion sequence (EOS = 1)
• In discontinuous mode with software trigger (CONT = 0, DISCEN = 1, EXTEN = 00)
– At end of conversion (EOC = 1)
• In all cases (CONT = x, EXTEN = XX)
– After execution of the ADSTP procedure invoked by software (see
Section 12.3.12: Stopping an ongoing conversion (ADSTP) on page 193)
Note: In continuous mode (CONT = 1), the ADSTART bit is not cleared by hardware when the
EOS flag is set because the sequence is automatically relaunched.
When hardware trigger is selected in single mode (CONT = 0 and EXTEN = 01), ADSTART
is not cleared by hardware when the EOS flag is set (except if DMAEN = 1 and
DMACFG = 0 in which case ADSTART is cleared at end of the DMA transfer). This avoids

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the need for software having to set the ADSTART bit again and ensures the next trigger
event is not missed.

12.3.11 Timings
The elapsed time between the start of a conversion and the end of conversion is the sum of
the configured sampling time plus the successive approximation time depending on data
resolution:

tCONV = tSMPL + tSAR = [1.5 |min + 12.5 |12bit] x tADC_CLK

tCONV = tSMPL + tSAR = 107.1 ns |min + 892.8 ns |12bit = 1 µs |min (for fADC_CLK = 14 MHz)

Figure 27. Analog to digital conversion time

ADC state RDY SAMPLING CH(N) CONVERTING CH(N) SAMPLING CH(N+1)

Analog
CH(N) CH(N+1)
channel
Internal S/H Sample AIN(N+1) Hold AIN(N) Sample AIN(N+1)
t SMPL (1) t SAR(2)
set
by SW
ADSTART
set by HW cleared by SW
EOSMP set cleared
EOC by HW by SW

ADC_DR DATA N-1 DATA N

(1) t SMPL depends on SMP[2:0]

(2) t SAR depends on RES[2:0] MS30336V1

Figure 28. ADC conversion timings

ADSTART(1) tLATENCY (2)

ADC state Ready S0 Conversion 0 S1 Conversion 1 S2 Conversion 2 S3 Conversion 3

(3) (3)
WLATENCY WLATENCY WLATENCY (3)
ADC_DR

Data 0 Data 1 Data 2

MSv33174V1

1. EXTEN = 00 or EXTEN ≠ 00
2. Trigger latency (refer to datasheet for more details)
3. ADC_DR register write latency (refer to datasheet for more details)

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12.3.12 Stopping an ongoing conversion (ADSTP)

The software can decide to stop any ongoing conversions by setting ADSTP = 1 in the
ADC_CR register.
This resets the ADC operation and the ADC is idle, ready for a new operation.
When the ADSTP bit is set by software, any ongoing conversion is aborted and the result is
discarded (ADC_DR register is not updated with the current conversion).
The scan sequence is also aborted and reset (meaning that restarting the ADC would re-
start a new sequence).
Once this procedure is complete, the ADSTP and ADSTART bits are both cleared by
hardware and the software must wait until ADSTART=0 before starting new conversions.

Figure 29. Stopping an ongoing conversion

ADC state RDY SAMPLING CH(N) CONVERTING CH(N) RDY

ADSTART set by SW cleared by HW

set by SW cleared by HW
ADSTOP
ADC_DR DATA N-1

MS30337V1

12.4 Conversion on external trigger and trigger polarity (EXTSEL,

EXTEN)
A conversion or a sequence of conversion can be triggered either by software or by an
external event (for example timer capture). If the EXTEN[1:0] control bits are not equal to
“0b00”, then external events are able to trigger a conversion with the selected polarity. The
trigger selection is effective once software has set bit ADSTART = 1.
Any hardware triggers which occur while a conversion is ongoing are ignored.
If bit ADSTART = 0, any hardware triggers which occur are ignored.
Table 37 provides the correspondence between the EXTEN[1:0] values and the trigger
polarity.

Table 37. Configuring the trigger polarity

Source EXTEN[1:0]

Trigger detection disabled 00

Detection on rising edge 01
Detection on falling edge 10
Detection on both rising and falling edges 11

Note: The polarity of the external trigger can be changed only when the ADC is not converting
(ADSTART = 0).
The EXTSEL[2:0] control bits are used to select which of 8 possible events can trigger
conversions.

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Refer to Table 35: External triggers in Section 12.3.1: ADC pins and internal signals for the
list of all the external triggers that can be used for regular conversion.
The software source trigger events can be generated by setting the ADSTART bit in the
ADC_CR register.
Note: The trigger selection can be changed only when the ADC is not converting (ADSTART = 0).

12.4.1 Discontinuous mode (DISCEN)

This mode is enabled by setting the DISCEN bit in the ADC_CFGR1 register.
In this mode (DISCEN = 1), a hardware or software trigger event is required to start each
conversion defined in the sequence. On the contrary, if DISCEN = 0, a single hardware or
software trigger event successively starts all the conversions defined in the sequence.
Example:
• DISCEN = 1, channels to be converted = 0, 3, 7, 10
– 1st trigger: channel 0 is converted and an EOC event is generated
– 2nd trigger: channel 3 is converted and an EOC event is generated
– 3rd trigger: channel 7 is converted and an EOC event is generated
– 4th trigger: channel 10 is converted and both EOC and EOS events are
generated.
– 5th trigger: channel 0 is converted an EOC event is generated
– 6th trigger: channel 3 is converted and an EOC event is generated
– ...
• DISCEN = 0, channels to be converted = 0, 3, 7, 10
– 1st trigger: the complete sequence is converted: channel 0, then 3, 7 and 10. Each
conversion generates an EOC event and the last one also generates an EOS
event.
– Any subsequent trigger events restarts the complete sequence.
Note: It is not possible to have both discontinuous mode and continuous mode enabled: it is
forbidden to set both bits DISCEN = 1 and CONT = 1.

12.4.2 Programmable resolution (RES) - Fast conversion mode

It is possible to obtain faster conversion times (tSAR) by reducing the ADC resolution.
The resolution can be configured to be either 12, 10, 8, or 6 bits by programming the
RES[1:0] bits in the ADC_CFGR1 register. Lower resolution allows faster conversion times
for applications where high data precision is not required.
Note: The RES[1:0] bit must only be changed when the ADEN bit is reset.
The result of the conversion is always 12 bits wide and any unused LSB bits are read as
zeros.
Lower resolution reduces the conversion time needed for the successive approximation
steps as shown in Table 38.

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Table 38. tSAR timings depending on resolution

tSAR tSMPL (min) tCONV
RES[1:0] tSAR (ns) at tCONV (ns) at
(ADC clock (ADC clock (ADC clock cycles)
bits fADC = 14 MHz fADC = 14 MHz
cycles) cycles) (with min. tSMPL)

12 12.5 893 1.5 14 1000

10 11.5 821 1.5 13 928
8 9.5 678 1.5 11 785
6 7.5 535 1.5 9 643

12.4.3 End of conversion, end of sampling phase (EOC, EOSMP flags)

The ADC indicates each end of conversion (EOC) event.
The ADC sets the EOC flag in the ADC_ISR register as soon as a new conversion data
result is available in the ADC_DR register. An interrupt can be generated if the EOCIE bit is
set in the ADC_IER register. The EOC flag is cleared by software either by writing 1 to it, or
by reading the ADC_DR register.
The ADC also indicates the end of sampling phase by setting the EOSMP flag in the
ADC_ISR register. The EOSMP flag is cleared by software by writing1 to it. An interrupt can
be generated if the EOSMPIE bit is set in the ADC_IER register.
The aim of this interrupt is to allow the processing to be synchronized with the conversions.
Typically, an analog multiplexer can be accessed in hidden time during the conversion
phase, so that the multiplexer is positioned when the next sampling starts.
Note: As there is only a very short time left between the end of the sampling and the end of the
conversion, it is recommenced to use polling or a WFE instruction rather than an interrupt
and a WFI instruction.

12.4.4 End of conversion sequence (EOS flag)

The ADC notifies the application of each end of sequence (EOS) event.
The ADC sets the EOS flag in the ADC_ISR register as soon as the last data result of a
conversion sequence is available in the ADC_DR register. An interrupt can be generated if
the EOSIE bit is set in the ADC_IER register. The EOS flag is cleared by software by writing
1 to it.

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12.4.5 Example timing diagrams (single/continuous modes

hardware/software triggers)

Figure 30. Single conversions of a sequence, software trigger

ADSTART(1)

EOC

EOS

SCANDIR

ADC state(2) RDY CH0 CH9 CH10 CH17 RDY CH17 CH10 CH9 CH0 RDY

ADC_DR D0 D9 D10 D17 D17 D10 D9 D0

by S/W by H/W

MSv30338V3

1. EXTEN = 00, CONT = 0

2. CHSEL = 0x20601, WAIT = 0, AUTOFF = 0
For code example refer to the Appendix section A.7.5: Single conversion sequence -
software trigger.

Figure 31. Continuous conversion of a sequence, software trigger

ADSTART(1)

EOC

EOS

ADSTP

SCANDIR

ADC state(2) RDY CH0 CH9 CH10 CH17 CH0 CH9 CH10 STP RDY CH17 CH10

ADC_DR D0 D9 D10 D17 D0 D9 D17

by S/W by H/W

MSv30339V2

1. EXTEN = 00, CONT = 1,

2. CHSEL = 0x20601, WAIT = 0, AUTOFF = 0
For code example refer to the Appendix section A.7.6: Continuous conversion sequence -
software trigger.

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Figure 32. Single conversions of a sequence, hardware trigger

ADSTART(1)

EOC

EOS

TRGx(1)

ADC state(2) RDY CH0 CH1 CH2 CH3 RDY CH0 CH1 CH2 CH3 RDY

ADC_DR D0 D1 D2 D3 D0 D1 D2 D3

by S/W by H/W
triggered ignored

MSv30340V2

1. EXTSEL = TRGx (over-frequency), EXTEN = 01 (rising edge), CONT = 0

2. CHSEL = 0xF, SCANDIR = 0, WAIT = 0, AUTOFF = 0
For code example refer to the Appendix section A.7.7: Single conversion sequence -
hardware trigger.

Figure 33. Continuous conversions of a sequence, hardware trigger

ADSTART(1)

EOC

EOS

ADSTP

TRGx(1)

ADC state(2) RDY CH0 CH1 CH2 CH3 CH0 CH1 CH2 CH3 CH0 STOP RDY

ADC_DR D0 D1 D2 D3 D0 D1 D2 D3

by S/W by H/W
triggered ignored

MSv30341V2

1. EXTSEL = TRGx, EXTEN = 10 (falling edge), CONT = 1

2. CHSEL = 0xF, SCANDIR = 0, WAIT = 0, AUTOFF = 0
For code example refer to the Appendix section A.7.8: Continuous conversion sequence -
hardware trigger.

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12.5 Data management

12.5.1 Data register and data alignment (ADC_DR, ALIGN)

At the end of each conversion (when an EOC event occurs), the result of the converted data
is stored in the ADC_DR data register which is 16-bit wide.
The format of the ADC_DR depends on the configured data alignment and resolution.
The ALIGN bit in the ADC_CFGR1 register selects the alignment of the data stored after
conversion. Data can be right-aligned (ALIGN = 0) or left-aligned (ALIGN = 1) as shown in
Figure 34.

Figure 34. Data alignment and resolution

ALIGN RES 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 0x0 0x0 DR[11:0]

0x1 0x00 DR[9:0]
0x2 0x00 DR[7:0]
0x3 0x00 DR[5:0]
1 0x0 DR[11:0] 0x0
0x1 DR[9:0] 0x00
0x2 DR[7:0] 0x00
0x3 0x00 DR[5:0] 0x0

MS30342V1

12.5.2 ADC overrun (OVR, OVRMOD)

The overrun flag (OVR) indicates a data overrun event, when the converted data was not
read in time by the CPU or the DMA, before the data from a new conversion is available.
The OVR flag is set in the ADC_ISR register if the EOC flag is still at ‘1’ at the time when a
new conversion completes. An interrupt can be generated if the OVRIE bit is set in the
ADC_IER register.
When an overrun condition occurs, the ADC keeps operating and can continue to convert
unless the software decides to stop and reset the sequence by setting the ADSTP bit in the
ADC_CR register.
The OVR flag is cleared by software by writing 1 to it.
It is possible to configure if the data is preserved or overwritten when an overrun event
occurs by programming the OVRMOD bit in the ADC_CFGR1 register:
• OVRMOD = 0
– An overrun event preserves the data register from being overwritten: the old data
is maintained and the new conversion is discarded. If OVR remains at 1, further
conversions can be performed but the resulting data is discarded.
• OVRMOD = 1
– The data register is overwritten with the last conversion result and the previous
unread data is lost. If OVR remains at 1, further conversions can be performed
and the ADC_DR register always contains the data from the latest conversion.

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Figure 35. Example of overrun (OVR)

ADSTART(1)

EOC

EOS

OVR

ADSTP

TRGx(1)

ADC state(2)
RDY CH0 CH1 CH2 CH0 CH1 CH2 CH0 STOP RDY

ADC_DR read OVERRUN

access

ADC_DR
(OVRMOD=0) D0 D1 D2 D0

ADC_DR
(OVRMOD=1) D0 D1 D2 D0 D1 D2

by S/W by H/W
triggered

MSv30343V3

12.5.3 Managing a sequence of data converted without using the DMA

If the conversions are slow enough, the conversion sequence can be handled by software.
In this case the software must use the EOC flag and its associated interrupt to handle each
data result. Each time a conversion is complete, the EOC bit is set in the ADC_ISR register
and the ADC_DR register can be read. The OVRMOD bit in the ADC_CFGR1 register
should be configured to 0 to manage overrun events as an error.

12.5.4 Managing converted data without using the DMA without overrun
It may be useful to let the ADC convert one or more channels without reading the data after
each conversion. In this case, the OVRMOD bit must be configured at 1 and the OVR flag
should be ignored by the software. When OVRMOD = 1, an overrun event does not prevent
the ADC from continuing to convert and the ADC_DR register always contains the latest
conversion data.

12.5.5 Managing converted data using the DMA

Since all converted channel values are stored in a single data register, it is efficient to use
DMA when converting more than one channel. This avoids losing the conversion data
results stored in the ADC_DR register.

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When DMA mode is enabled (DMAEN bit set in the ADC_CFGR1 register), a DMA request
is generated after the conversion of each channel. This allows the transfer of the converted
data from the ADC_DR register to the destination location selected by the software.
Note: The DMAEN bit in the ADC_CFGR1 register must be set after the ADC calibration phase.
Despite this, if an overrun occurs (OVR = 1) because the DMA could not serve the DMA
transfer request in time, the ADC stops generating DMA requests and the data
corresponding to the new conversion is not transferred by the DMA. Which means that all
the data transferred to the RAM can be considered as valid.
Depending on the configuration of OVRMOD bit, the data is either preserved or overwritten
(refer to Section 12.5.2: ADC overrun (OVR, OVRMOD) on page 198).
The DMA transfer requests are blocked until the software clears the OVR bit.
Two different DMA modes are proposed depending on the application use and are
configured with bit DMACFG in the ADC_CFGR1 register:
• DMA one shot mode (DMACFG = 0).
This mode should be selected when the DMA is programmed to transfer a fixed
number of data words.
• DMA circular mode (DMACFG = 1)
This mode should be selected when programming the DMA in circular mode or double
buffer mode.

DMA one shot mode (DMACFG = 0)

In this mode, the ADC generates a DMA transfer request each time a new conversion data
word is available and stops generating DMA requests once the DMA has reached the last
DMA transfer (when a transfer complete interrupt occurs, see Section 10: Direct memory
access controller (DMA)) even if a conversion has been started again.
For code example refer to the Appendix section A.7.9: DMA one shot mode sequence.
When the DMA transfer is complete (all the transfers configured in the DMA controller have
been done):
• The content of the ADC data register is frozen.
• Any ongoing conversion is aborted and its partial result discarded
• No new DMA request is issued to the DMA controller. This avoids generating an
overrun error if there are still conversions which are started.
• The scan sequence is stopped and reset
• The DMA is stopped

DMA circular mode (DMACFG = 1)

In this mode, the ADC generates a DMA transfer request each time a new conversion data
word is available in the data register, even if the DMA has reached the last DMA transfer.
This allows the DMA to be configured in circular mode to handle a continuous analog input
data stream.
For code example refer to the Appendix section A.7.10: DMA circular mode sequence.

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12.6 Low-power features

12.6.1 Wait mode conversion

Wait mode conversion can be used to simplify the software as well as optimizing the
performance of applications clocked at low frequency where there might be a risk of ADC
overrun occurring.
When the WAIT bit is set in the ADC_CFGR1 register, a new conversion can start only if the
previous data has been treated, once the ADC_DR register has been read or if the EOC bit
has been cleared.
This is a way to automatically adapt the speed of the ADC to the speed of the system that
reads the data.
Note: Any hardware triggers which occur while a conversion is ongoing or during the wait time
preceding the read access are ignored.

Figure 36. Wait mode conversion (continuous mode, software trigger)

ADSTART

EOC

EOS

ADSTP

ADC_DR Read access

ADC state RDY CH1 DLY CH2 DLY CH3 DLY CH1 DLY STOP RDY

ADC_DR D1 D2 D3 D1

by S/W by H/W

MSv30344V2

1. EXTEN = 00, CONT = 1

2. CHSEL = 0x3, SCANDIR = 0, WAIT = 1, AUTOFF = 0
For code example refer to the Appendix section A.7.11: Wait mode sequence.

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12.6.2 Auto-off mode (AUTOFF)

The ADC has an automatic power management feature which is called auto-off mode, and
is enabled by setting AUTOFF = 1 in the ADC_CFGR1 register.
When AUTOFF = 1, the ADC is always powered off when not converting and automatically
wakes-up when a conversion is started (by software or hardware trigger). A startup-time is
automatically inserted between the trigger event which starts the conversion and the
sampling time of the ADC. The ADC is then automatically disabled once the sequence of
conversions is complete.
Auto-off mode can cause a dramatic reduction in the power consumption of applications
which need relatively few conversions or when conversion requests are timed far enough
apart (for example with a low frequency hardware trigger) to justify the extra power and
extra time used for switching the ADC on and off.
Auto-off mode can be combined with the wait mode conversion (WAIT = 1) for applications
clocked at low frequency. This combination can provide significant power savings if the ADC
is automatically powered-off during the wait phase and restarted as soon as the ADC_DR
register is read by the application (see Figure 38: Behavior with WAIT = 1, AUTOFF = 1).
Note: Refer to the Section Reset and clock control (RCC) for the description of how to manage
the dedicated 14 MHz internal oscillator. The ADC interface can automatically switch
ON/OFF the 14 MHz internal oscillator to save power.

Figure 37. Behavior with WAIT = 0, AUTOFF = 1

TRGx

EOC

EOS

ADC_DR Read
access

ADC state RDY Startup CH1 CH2 CH3 CH4 OFF Startup

ADC_DR D1 D2 D3 D4

by S/W by H/W
triggered

MSv30345V2

1. EXTSEL = TRGx, EXTEN = 01 (rising edge), CONT = x, ADSTART = 1, CHSEL = 0xF, SCANDIR = 0, WAIT = 1,
AUTOFF = 1
For code example refer to the Appendix section A.7.12: Auto Off and no wait mode
sequence.

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Figure 38. Behavior with WAIT = 1, AUTOFF = 1

TRGx

EOC

EOS

ADC_DR Read
access DLY DLY DLY DLY

OFF

OFF
ADC state RDY Startup CH1 OFF Startup CH2 Startup CH3 OFF Startup CH1 CH2

D1 D2 D3 D4
ADC_DR

by S/W by H/W
triggered

MSv30346V2

1. EXTSEL = TRGx, EXTEN = 01 (rising edge), CONT = x, ADSTART = 1, CHSEL = 0xF, SCANDIR = 0, WAIT = 1,
AUTOFF = 1
For code example refer to the Appendix section A.7.13: Auto Off and wait mode sequence.

12.7 Analog window watchdog

12.7.1 Description of the analog watchdog

The AWD analog watchdog is enabled by setting the AWDEN bit in the ADC_CFGR1
register. It is used to monitor that either one selected channel or all enabled channels (see
Table 40: Analog watchdog channel selection) remain within a configured voltage range
(window) as shown in Figure 39.
The AWD analog watchdog status bit is set if the analog voltage converted by the ADC is
below a lower threshold or above a higher threshold. These thresholds are programmed in
HT[11:0] and LT[11:0] bit of ADC_TR register. An interrupt can be enabled by setting the
AWDIE bit in the ADC_IER register.
The AWD flag is cleared by software by programming it to it.
When converting data with a resolution of less than 12-bit (according to bits RES[1:0]), the
LSB of the programmed thresholds must be kept cleared because the internal comparison
is always performed on the full 12-bit raw converted data (left aligned).
For code example refer to the Appendix section A.7.14: Analog watchdog.
Table 39 describes how the comparison is performed for all the possible resolutions.

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Table 39. Analog watchdog comparison

Analog watchdog comparison between:
Resolution
bits Comments
Raw converted
RES[1:0] Thresholds
data, left aligned(1)

00: 12-bit DATA[11:0] LT[11:0] and HT[11:0] -

01: 10-bit DATA[11:2],00 LT[11:0] and HT[11:0] The user must configure LT1[1:0] and HT1[1:0] to “00”
The user must configure LT1[3:0] and HT1[3:0] to
10: 8-bit DATA[11:4],0000 LT[11:0] and HT[11:0]
“0000”
The user must configure LT1[5:0] and HT1[5:0] to
11: 6-bit DATA[11:6],000000 LT[11:0] and HT[11:0]
“000000”
1. The watchdog comparison is performed on the raw converted data before any alignment calculation.

Table 40 shows how to configure the AWDSGL and AWDEN bits in the ADC_CFGR1
register to enable the analog watchdog on one or more channels.

Figure 39. Analog watchdog guarded area

Analog voltage

Higher threshold HTx

Guarded area
Lower threshold LTx

MS45396V1

Table 40. Analog watchdog channel selection

Channels guarded by the analog watchdog AWDSGL bit AWDEN bit

None x 0
All channels 0 1
Single(1) channel 1 1
1. Selected by the AWDCH[4:0] bits

12.7.2 ADC_AWD1_OUT output signal generation

The analog watchdog is associated to an internal hardware signal, ADC_AWD1_OUT that is
directly connected to the ETR input (external trigger) of some on-chip timers (refer to the
timers section for details on how to select the ADC_AWD1_OUT signal as ETR).

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ADC_AWD1_OUT is activated when the analog watchdog is enabled:

• ADC_AWD1_OUT is set when a guarded conversion is outside the programmed
thresholds.
• ADC_AWD1_OUT is reset after the end of the next guarded conversion which is inside
the programmed thresholds. It remains at 1 if the next guarded conversions are still
outside the programmed thresholds.
• ADC_AWD1_OUT is also reset when disabling the ADC (when setting ADDIS to 1).
Note that stopping conversions (ADSTP set), might clear the ADC_AWD1_OUT state.
• ADC_AWD1_OUT state does not change when the ADC converts the none-guarded
channel (see Figure 40)
AWD flag is set by hardware and reset by software: AWD flag has no influence on the
generation of ADC_AWD1_OUT (as an example, ADC_AWD1_OUT can toggle while AWD
flag remains at 1 if the software has not cleared the flag).
The ADC_AWD1_OUT signal is generated by the ADC_CLK domain. This signal can be
generated even the APB clock is stopped.
The AWD comparison is performed at the end of each ADC conversion. The
ADC_AWD1_OUT rising edge and falling edge occurs two ADC_CLK clock cycles after the
comparison.
As ADC_AWD1_OUT is generated by the ADC_CLK domain and AWD flag is generated by
the APB clock domain, the rising edges of these signals are not synchronized.

Figure 40. ADC_AWD1_OUT signal generation

ADC STATE RDY Conversion1 Conversion2 Conversion3 Conversion4 Conversion5 Conversion6 Conversion7
inside outside inside outside outside outside inside
EOC FLAG

Cleared Cleared Cleared Cleared

AWD FLAG by SW by SW by SW by SW

ADC_AWD1_OUT

- Converted channels: 1,2,3,4,5,6,7

- Guarded converted channels: 1,2,3,4,5,6,7

MSv65326V1

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Figure 41. ADC_AWD1_OUT signal generation (AWD flag not cleared by software)

ADC STATE RDY Conversion1 Conversion2 Conversion3 Conversion4 Conversion5 Conversion6 Conversion7

inside outside inside outside outside outside inside

EOC FLAG

not cleared by SW
AWD FLAG

ADC_AWD1_OUT

- Converted channels: 1,2,3,4,5,6,7

- Guarded converted channels: 1,2,3,4,5,6,7
MSv65327V1

Figure 42. ADC1_AWD_OUT signal generation (on a single channel)

ADC STATE Conversion1 Conversion2 Conversion1 Conversion2 Conversion1 Conversion2 Conversion1 Conversion2

outside inside outside outside

EOC FLAG

EOS FLAG
Cleared Cleared
by SW by SW
AWD FLAG

ADCy_AWD1_OUT

- Converted channels: 1 and 2

- Only channel 1 is guarded

MSv65328V1

12.7.3 Analog watchdog threshold control

LT[11:0] and HT[11:0] can be changed during an analog-to-digital conversion (that is
between the start of the conversion and the end of conversion of the ADC internal state). If
LT and HT bits are programmed during the ADC guarded channel conversion, the watchdog
function is masked for this conversion. This mask is cleared when starting a new
conversion, and the resulting new AWD threshold is applied starting the next ADC
conversion result. AWD comparison is performed at each end of conversion. If the current
ADC data are out of the new threshold interval, this does not generated any interrupt or an
ADC_AWD1_OUT signal. The Interrupt and the ADC_AWD1_OUT generation only occurs
at the end of the ADC conversion that started after the threshold update. If
ADC_AWD1_OUT is already asserted, programming the new threshold does not deassert
the ADC_AWD1_OUT signal.

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Figure 43. Analog watchdog threshold update

ADC state Conversion Conversion Conversion Conversion

Threshould updated

LT, HT XXXX XXXY XXXZ

Comparison Active Masked Active

MSv65329V1

12.8 Temperature sensor and internal reference voltage

The temperature sensor can be used to measure the junction temperature (TJ) of the
device. The temperature sensor is internally connected to the ADC VIN[16] input channel
which is used to convert the sensor’s output voltage to a digital value. The sampling time for
the temperature sensor analog pin must be greater than the minimum TS_temp value
specified in the datasheet. When not in use, the sensor can be put in power down mode.
The temperature sensor output voltage changes linearly with temperature, however its
characteristics may vary significantly from chip to chip due to the process variations. To
improve the accuracy of the temperature sensor (especially for absolute temperature
measurement), calibration values are individually measured for each part by ST during
production test and stored in the system memory area. Refer to the specific device
datasheet for additional information.
The internal voltage reference (VREFINT) provides a stable (bandgap) voltage output for the
ADC and comparators. VREFINT is internally connected to the ADC VIN[17] input channel.
The precise voltage of VREFINT is individually measured for each part by ST during
production test and stored in the system memory area. It is accessible in read-only mode.
Figure 44 shows the block diagram of connections between the temperature sensor, the
internal voltage reference and the ADC.
The TSEN bit must be set to enable the conversion of ADC VIN[16] (temperature sensor)
and the VREFEN bit must be set to enable the conversion of ADC VIN[17] (VREFINT).

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Main features
• Linearity: ±2 °C max., precision depending on calibration

Figure 44. Temperature sensor and VREFINT channel block diagram

TSEN control bit

V SENSE
Temperature ADC VIN[16]
sensor

Address/data bus
converted data
ADC

Internal VREFINT
power ADC VIN[17]
block

VREFEN control bit

ai16065c

Reading the temperature

1. Select the ADC VIN[16] input channel.
2. Select an appropriate sampling time specified in the device datasheet (TS_temp).
3. Set the TSEN bit in the ADC_CCR register to wake up the temperature sensor from
power down mode and wait for its stabilization time (tSTART).
For code example refer to the Appendix section A.7.15: Temperature configuration.
4. Start the ADC conversion by setting the ADSTART bit in the ADC_CR register (or by
external trigger).
5. Read the resulting VSENSE data in the ADC_DR register.
6. Calculate the temperature using the following formula

Temperature ( in °C ) = Sense_DATA – TS_CAL1- + TS_CAL1_TEMP

-------------------------------------------------------------------
Avg_Slope_Code

Avg_Slope_Code = Avg_Slope × 4096 ⁄ 3300

Sense_DATA = TS_DATA × V DDA ⁄ 3.3

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Where:
• TS_CAL1 is the temperature sensor calibration value acquired at TS_CAL1_TEMP
(refer to the datasheet for TS_CAL1 value)
• TS_DATA is the actual temperature sensor output value converted by ADC
Refer to the specific device datasheet for more information about TS_CAL1 calibration
point.
• Avg_Slope is the coefficient of the temperature sensor output voltage expressed in
mV/°C (refer to the datasheet for Avg_Slope value).
For code example refer to the A.7.16: Temperature computation.
Note: The sensor has a startup time after waking from power down mode before it can output
VSENSE at the correct level. The ADC also has a startup time after power-on, so to minimize
the delay, the ADEN and TSEN bits should be set at the same time.

Calculating the actual VDDA voltage using the internal reference voltage
The VDDA power supply voltage applied to the device may be subject to variation or not
precisely known. The embedded internal voltage reference (VREFINT) and its calibration
data, acquired by the ADC during the manufacturing process at VDDA_Charac, can be used to
evaluate the actual VDDA voltage level.
The following formula gives the actual VDDA voltage supplying the device:
VDDA = VDDA_Charac x VREFINT_CAL / VREFINT_DATA
Where:
• VDDA_Charac is the value of VDDA voltage characterized at VREFINT during the
manufacturing process. It is specified in the device datasheet.
• VREFINT_CAL is the VREFINT calibration value
• VREFINT_DATA is the actual VREFINT output value converted by ADC

Converting a supply-relative ADC measurement to an absolute voltage value

The ADC is designed to deliver a digital value corresponding to the ratio between the analog
power supply and the voltage applied on the converted channel. For most application use
cases, it is necessary to convert this ratio into a voltage independent of VDDA. For
applications where VDDA is known and ADC converted values are right-aligned you can use
the following formula to get this absolute value:
V DDA
V CHANNELx = -------------------------------------- × ADC_DATA x
NUM_CODES

For applications where VDDA value is not known, you must use the internal voltage
reference and VDDA can be replaced by the expression provided in Section : Calculating the
actual VDDA voltage using the internal reference voltage, resulting in the following formula:
V DDA_Charac × VREFINT_CAL × ADC_DATA x
V CHANNELx = ---------------------------------------------------------------------------------------------------------------------------------
-
VREFINT_DATA × NUM_CODES

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Where:
• VDDA_Charac is the value of VDDA voltage characterized at VREFINT during the
manufacturing process. It is specified in the device datasheet.
• VREFINT_CAL is the VREFINT calibration value
• ADC_DATAx is the value measured by the ADC on channelx (right-aligned)
• VREFINT_DATA is the actual VREFINT output value converted by the ADC
• NUM_CODES is the number of ADC output codes. For example with 12-bit resolution,
it is 212 = 4096 or with 8-bit resolution, 28 = 256.
Note: If ADC measurements are done using an output format other than 12 bit right-aligned, all the
parameters must first be converted to a compatible format before the calculation is done.

12.9 ADC interrupts

An interrupt can be generated by any of the following events:
• ADC power-up, when the ADC is ready (ADRDY flag)
• End of any conversion (EOC flag)
• End of a sequence of conversions (EOS flag)
• When an analog watchdog detection occurs (AWD flag)
• When the end of sampling phase occurs (EOSMP flag)
• when a data overrun occurs (OVR flag)
Separate interrupt enable bits are available for flexibility.

Table 41. ADC interrupts

Interrupt event Event flag Enable control bit

ADC ready ADRDY ADRDYIE

End of conversion EOC EOCIE
End of sequence of conversions EOS EOSIE
Analog watchdog status bit is set AWD AWDIE
End of sampling phase EOSMP EOSMPIE
Overrun OVR OVRIE

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12.10 ADC registers

Refer to Section 1.2 for a list of abbreviations used in register descriptions.

12.10.1 ADC interrupt and status register (ADC_ISR)

Address offset: 0x00
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res. Res. Res. Res. Res. Res. Res. Res. AWD Res. Res. OVR EOS EOC EOSMP ADRDY

rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1

Bits 31:13 Reserved, must be kept at reset value.

Bits 12:10 Reserved, must be kept at reset value.
Bits 9:8 Reserved, must be kept at reset value.
Bit 7 AWD: Analog watchdog flag
This bit is set by hardware when the converted voltage crosses the values programmed in ADC_TR
register. It is cleared by software by programming it to 1.
0: No analog watchdog event occurred (or the flag event was already acknowledged and cleared by
software)
1: Analog watchdog event occurred
Bits 6:5 Reserved, must be kept at reset value.
Bit 4 OVR: ADC overrun
This bit is set by hardware when an overrun occurs, meaning that a new conversion has complete
while the EOC flag was already set. It is cleared by software writing 1 to it.
0: No overrun occurred (or the flag event was already acknowledged and cleared by software)
1: Overrun has occurred
Bit 3 EOS: End of sequence flag
This bit is set by hardware at the end of the conversion of a sequence of channels selected by the
CHSEL bits. It is cleared by software writing 1 to it.
0: Conversion sequence not complete (or the flag event was already acknowledged and cleared by
software)
1: Conversion sequence complete

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Bit 2 EOC: End of conversion flag

This bit is set by hardware at the end of each conversion of a channel when a new data result is
available in the ADC_DR register. It is cleared by software writing 1 to it or by reading the ADC_DR
register.
0: Channel conversion not complete (or the flag event was already acknowledged and cleared by
software)
1: Channel conversion complete
Bit 1 EOSMP: End of sampling flag
This bit is set by hardware during the conversion, at the end of the sampling phase.It is cleared by
software by programming it to ‘1’.
0: Not at the end of the sampling phase (or the flag event was already acknowledged and cleared by
software)
1: End of sampling phase reached
Bit 0 ADRDY: ADC ready
This bit is set by hardware after the ADC has been enabled (ADEN = 1) and when the ADC reaches
a state where it is ready to accept conversion requests.
It is cleared by software writing 1 to it.
0: ADC not yet ready to start conversion (or the flag event was already acknowledged and cleared
by software)
1: ADC is ready to start conversion

Note: In auto-off mode (AUTOFF = 1) the power-on/off phases are performed automatically, by
hardware and the ADRDY flag is not set.

12.10.2 ADC interrupt enable register (ADC_IER)

Address offset: 0x04
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EOSMP ADRDY
Res. Res. Res. Res. Res. Res. Res. Res. AWDIE Res. Res. OVRIE EOSIE EOCIE
IE IE
rw rw rw rw rw rw

Bits 31:13 Reserved, must be kept at reset value.

Bits 12:10 Reserved, must be kept at reset value.
Bits 9:8 Reserved, must be kept at reset value.
Bit 7 AWDIE: Analog watchdog interrupt enable
This bit is set and cleared by software to enable/disable the analog watchdog interrupt.
0: Analog watchdog interrupt disabled
1: Analog watchdog interrupt enabled
Note: The Software is allowed to write this bit only when ADSTART bit is cleared (this ensures that no
conversion is ongoing).
Bits 6:5 Reserved, must be kept at reset value.

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Bit 4 OVRIE: Overrun interrupt enable

This bit is set and cleared by software to enable/disable the overrun interrupt.
0: Overrun interrupt disabled
1: Overrun interrupt enabled. An interrupt is generated when the OVR bit is set.
Note: The software is allowed to write this bit only when ADSTART bit is cleared (this ensures that no
conversion is ongoing).
Bit 3 EOSIE: End of conversion sequence interrupt enable
This bit is set and cleared by software to enable/disable the end of sequence of conversions
interrupt.
0: EOS interrupt disabled
1: EOS interrupt enabled. An interrupt is generated when the EOS bit is set.
Note: The software is allowed to write this bit only when ADSTART bit is cleared (this ensures that no
conversion is ongoing).
Bit 2 EOCIE: End of conversion interrupt enable
This bit is set and cleared by software to enable/disable the end of conversion interrupt.
0: EOC interrupt disabled
1: EOC interrupt enabled. An interrupt is generated when the EOC bit is set.
Note: The software is allowed to write this bit only when ADSTART bit is cleared (this ensures that no
conversion is ongoing).
Bit 1 EOSMPIE: End of sampling flag interrupt enable
This bit is set and cleared by software to enable/disable the end of the sampling phase interrupt.
0: EOSMP interrupt disabled.
1: EOSMP interrupt enabled. An interrupt is generated when the EOSMP bit is set.
Note: The software is allowed to write this bit only when ADSTART bit is cleared (this ensures that no
conversion is ongoing).
Bit 0 ADRDYIE: ADC ready interrupt enable
This bit is set and cleared by software to enable/disable the ADC Ready interrupt.
0: ADRDY interrupt disabled.
1: ADRDY interrupt enabled. An interrupt is generated when the ADRDY bit is set.
Note: The software is allowed to write this bit only when ADSTART bit is cleared (this ensures that no
conversion is ongoing).

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12.10.3 ADC control register (ADC_CR)

Address offset: 0x08
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

ADCAL Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

rs
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADSTA
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. ADSTP Res. ADDIS ADEN
RT
rs rs rs rs

Bit 31 ADCAL: ADC calibration

This bit is set by software to start the calibration of the ADC.
It is cleared by hardware after calibration is complete.
0: Calibration complete
1: Write 1 to calibrate the ADC. Read at 1 means that a calibration is in progress.
Note: The software is allowed to set ADCAL only when the ADC is disabled (ADCAL = 0,
ADSTART = 0, ADSTP = 0, ADDIS = 0, AUTOFF = 0, and ADEN = 0).

Bits 30:28 Reserved, must be kept at reset value.

Bits 27:5 Reserved, must be kept at reset value.
Bit 4 ADSTP: ADC stop conversion command
This bit is set by software to stop and discard an ongoing conversion (ADSTP Command).
It is cleared by hardware when the conversion is effectively discarded and the ADC is ready to
accept a new start conversion command.
0: No ADC stop conversion command ongoing
1: Write 1 to stop the ADC. Read 1 means that an ADSTP command is in progress.
Note: Setting ADSTP to ‘1’ is only effective when ADSTART = 1 and ADDIS = 0 (ADC is enabled and
may be converting and there is no pending request to disable the ADC)
Bit 3 Reserved, must be kept at reset value.

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Bit 2 ADSTART: ADC start conversion command

This bit is set by software to start ADC conversion. Depending on the EXTEN [1:0] configuration bits,
a conversion either starts immediately (software trigger configuration) or once a hardware trigger
event occurs (hardware trigger configuration).
It is cleared by hardware:
– In single conversion mode (CONT = 0, DISCEN = 0), when software trigger is selected
(EXTEN = 00): at the assertion of the end of Conversion Sequence (EOS) flag.
– In discontinuous conversion mode(CONT = 0, DISCEN = 1), when the software trigger is selected
(EXTEN = 00): at the assertion of the end of Conversion (EOC) flag.
– In all other cases: after the execution of the ADSTP command, at the same time as the ADSTP bit is
cleared by hardware.
0: No ADC conversion is ongoing.
1: Write 1 to start the ADC. Read 1 means that the ADC is operating and may be converting.
Note: The software is allowed to set ADSTART only when ADEN = 1 and ADDIS = 0 (ADC is enabled
and there is no pending request to disable the ADC).

Bit 1 ADDIS: ADC disable command

This bit is set by software to disable the ADC (ADDIS command) and put it into power-down state
(OFF state).
It is cleared by hardware once the ADC is effectively disabled (ADEN is also cleared by hardware at
this time).
0: No ADDIS command ongoing
1: Write 1 to disable the ADC. Read 1 means that an ADDIS command is in progress.
Note: Setting ADDIS to ‘1’ is only effective when ADEN = 1 and ADSTART = 0 (which ensures that no
conversion is ongoing)
Bit 0 ADEN: ADC enable command
This bit is set by software to enable the ADC. The ADC is effectively ready to operate once the
ADRDY flag has been set.
It is cleared by hardware when the ADC is disabled, after the execution of the ADDIS command.
0: ADC is disabled (OFF state)
1: Write 1 to enable the ADC.
Note: The software is allowed to set ADEN only when all bits of ADC_CR registers are 0 (ADCAL = 0,
ADSTP = 0, ADSTART = 0, ADDIS = 0 and ADEN = 0)

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12.10.4 ADC configuration register 1 (ADC_CFGR1)

Address offset: 0x0C
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWDE AWDS DISCE
Res. AWDCH[4:0] Res. Res. Res. Res. Res. Res. Res.
N GL N
rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AUTOF OVRM SCAND DMAC DMAE
WAIT CONT EXTEN[1:0] Res. EXTSEL[2:0] ALIGN RES[1:0]
F OD IR FG N
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bit 31 Reserved, must be kept at reset value.

Bits 30:26 AWDCH[4:0]: Analog watchdog channel selection
These bits are set and cleared by software. They select the input channel to be guarded by
the analog watchdog.
00000: ADC analog input Channel 0 monitored by AWD
00001: ADC analog input Channel 1 monitored by AWD
.....
10001: ADC analog input Channel 17 monitored by AWD
Others: Reserved
Note: The channel selected by the AWDCH[4:0] bits must be also set into the CHSELR
register.
The software is allowed to write this bit only when ADSTART bit is cleared (this ensures
that no conversion is ongoing).
Bits 25:24 Reserved, must be kept at reset value.
Bit 23 AWDEN: Analog watchdog enable
This bit is set and cleared by software.
0: Analog watchdog disabled
1: Analog watchdog enabled
Note: The software is allowed to write this bit only when ADSTART bit is cleared (this ensures
that no conversion is ongoing).

Bit 22 AWDSGL: Enable the watchdog on a single channel or on all channels

This bit is set and cleared by software to enable the analog watchdog on the channel
identified by the AWDCH[4:0] bits or on all the channels
0: Analog watchdog enabled on all channels
1: Analog watchdog enabled on a single channel
Note: The software is allowed to write this bit only when ADSTART bit is cleared (this ensures
that no conversion is ongoing).

Bits 21:17 Reserved, must be kept at reset value.

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Bit 16 DISCEN: Discontinuous mode

This bit is set and cleared by software to enable/disable discontinuous mode.
0: Discontinuous mode disabled
1: Discontinuous mode enabled
Note: It is not possible to have both discontinuous mode and continuous mode enabled: it is
forbidden to set both bits DISCEN = 1 and CONT = 1.
The software is allowed to write this bit only when ADSTART bit is cleared (this ensures
that no conversion is ongoing).
Bit 15 AUTOFF: Auto-off mode
This bit is set and cleared by software to enable/disable auto-off mode..
0: Auto-off mode disabled
1: Auto-off mode enabled
Note: The software is allowed to write this bit only when ADSTART bit is cleared (this ensures
that no conversion is ongoing).

Bit 14 WAIT: Wait conversion mode

This bit is set and cleared by software to enable/disable wait conversion mode..
0: Wait conversion mode off
1: Wait conversion mode on
Note: The software is allowed to write this bit only when ADSTART bit is cleared (this ensures
that no conversion is ongoing).

Bit 13 CONT: Single / continuous conversion mode

This bit is set and cleared by software. If it is set, conversion takes place continuously until it
is cleared.
0: Single conversion mode
1: Continuous conversion mode
Note: It is not possible to have both discontinuous mode and continuous mode enabled: it is
forbidden to set both bits DISCEN = 1 and CONT = 1.
The software is allowed to write this bit only when ADSTART bit is cleared (this ensures
that no conversion is ongoing).
Bit 12 OVRMOD: Overrun management mode
This bit is set and cleared by software and configure the way data overruns are managed.
0: ADC_DR register is preserved with the old data when an overrun is detected.
1: ADC_DR register is overwritten with the last conversion result when an overrun is
detected.
Note: The software is allowed to write this bit only when ADSTART bit is cleared (this ensures
that no conversion is ongoing).

Bits 11:10 EXTEN[1:0]: External trigger enable and polarity selection

These bits are set and cleared by software to select the external trigger polarity and enable
the trigger.
00: Hardware trigger detection disabled (conversions can be started by software)
01: Hardware trigger detection on the rising edge
10: Hardware trigger detection on the falling edge
11: Hardware trigger detection on both the rising and falling edges
Note: The software is allowed to write this bit only when ADSTART bit is cleared (this ensures
that no conversion is ongoing).

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Bit 9 Reserved, must be kept at reset value.

Bits 8:6 EXTSEL[2:0]: External trigger selection
These bits select the external event used to trigger the start of conversion (refer to Table 35:
External triggers for details):
000: TRG0
001: TRG1
010: TRG2
011: TRG3
100: TRG4
101: TRG5
110: TRG6
111: TRG7
Note: The software is allowed to write this bit only when ADSTART bit is cleared (this ensures
that no conversion is ongoing).

Bit 5 ALIGN: Data alignment

This bit is set and cleared by software to select right or left alignment. Refer to Figure 34:
Data alignment and resolution on page 198
0: Right alignment
1: Left alignment
Note: The software is allowed to write this bit only when ADSTART bit is cleared (this ensures
that no conversion is ongoing).

Bits 4:3 RES[1:0]: Data resolution

These bits are written by software to select the resolution of the conversion.
00: 12 bits
01: 10 bits
10: 8 bits
11: 6 bits

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Bit 2 SCANDIR: Scan sequence direction

This bit is set and cleared by software to select the direction in which the channels is scanned
in the sequence.
0: Upward scan (from CHSEL0 to CHSEL17)
1: Backward scan (from CHSEL17 to CHSEL0)
Note: The software is allowed to write this bit only when ADSTART bit is cleared (this ensures
that no conversion is ongoing).

Bit 1 DMACFG: Direct memory access configuration

This bit is set and cleared by software to select between two DMA modes of operation and is
effective only when DMAEN = 1.
0: DMA one shot mode selected
1: DMA circular mode selected
For more details, refer to Section 12.5.5: Managing converted data using the DMA on
page 199.
Note: The software is allowed to write this bit only when ADSTART bit is cleared (this ensures
that no conversion is ongoing).

Bit 0 DMAEN: Direct memory access enable

This bit is set and cleared by software to enable the generation of DMA requests. This allows
the DMA controller to be used to manage automatically the converted data. For more details,
refer to Section 12.5.5: Managing converted data using the DMA on page 199.
0: DMA disabled
1: DMA enabled
Note: The software is allowed to write this bit only when ADSTART bit is cleared (this ensures
that no conversion is ongoing).

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12.10.5 ADC configuration register 2 (ADC_CFGR2)

Address offset: 0x10
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CKMODE[1:0] Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

Bits 31:30 CKMODE[1:0]: ADC clock mode

These bits are set and cleared by software to define how the analog ADC is clocked:
00: ADCCLK (Asynchronous clock mode), generated at product level (refer to RCC section)
01: PCLK/2 (Synchronous clock mode)
10: PCLK/4 (Synchronous clock mode)
11: Reserved
In all synchronous clock modes, there is no jitter in the delay from a timer trigger to the start of a
conversion.
Note: The software is allowed to write these bits only when the ADC is disabled (ADCAL = 0,
ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0).
Bits 29:10 Reserved, must be kept at reset value.
Bits 9:0 Reserved, must be kept at reset value.

12.10.6 ADC sampling time register (ADC_SMPR)

Address offset: 0x14
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. SMP[2:0]

rw rw rw

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Bits 31:3 Reserved, must be kept at reset value.

Bits 2:0 SMP[2:0]: Sampling time selection
These bits are written by software to select the sampling time that applies to all channels.
000: 1.5 ADC clock cycles
001: 7.5 ADC clock cycles
010: 13.5 ADC clock cycles
011: 28.5 ADC clock cycles
100: 41.5 ADC clock cycles
101: 55.5 ADC clock cycles
110: 71.5 ADC clock cycles
111: 239.5 ADC clock cycles
Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no
conversion is ongoing).

12.10.7 ADC watchdog threshold register (ADC_TR)

Address offset: 0x20
Reset value: 0x0FFF 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. HT[11:0]

rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res. Res. Res. Res. LT[11:0]

rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:28 Reserved, must be kept at reset value.

Bits 27:16 HT[11:0]: Analog watchdog higher threshold
These bits are written by software to define the higher threshold for the analog watchdog. Refer to
Section 12.7: Analog window watchdog on page 203
Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no
conversion is ongoing).
Bits 15:12 Reserved, must be kept at reset value.
Bits 11:0 LT[11:0]: Analog watchdog lower threshold
These bits are written by software to define the lower threshold for the analog watchdog.
Refer to Section 12.7: Analog window watchdog on page 203.
Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no
conversion is ongoing).

12.10.8 ADC channel selection register (ADC_CHSELR)

Address offset: 0x28
Reset value: 0x0000 0000

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31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CHSEL CHSEL
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
17 16
rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CHSEL CHSEL CHSEL CHSEL CHSEL CHSEL CHSEL CHSEL CHSEL CHSEL CHSEL CHSEL CHSEL CHSEL CHSEL CHSEL
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:18 Reserved, must be kept at reset value.

Bits 17:0 CHSELx: Channel-x selection
These bits are written by software and define which channels are part of the sequence of channels
to be converted.
0: Input Channel-x is not selected for conversion
1: Input Channel-x is selected for conversion
Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no
conversion is ongoing).

12.10.9 ADC data register (ADC_DR)

Address offset: 0x40
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

DATA[15:0]

r r r r r r r r r r r r r r r r

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 DATA[15:0]: Converted data
These bits are read-only. They contain the conversion result from the last converted channel. The
data are left- or right-aligned as shown in Figure 34: Data alignment and resolution on page 198.
Just after a calibration is complete, DATA[6:0] contains the calibration factor.

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12.10.10 ADC common configuration register (ADC_CCR)

Address offset: 0x308
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
VREF
Res. Res. Res. Res. Res. Res. Res. Res. TSEN Res. Res. Res.
EN
rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

Bits 31:25 Reserved, must be kept at reset value.

Bit 24 Reserved, must be kept at reset value.
Bit 23 TSEN: Temperature sensor enable
This bit is set and cleared by software to enable/disable the temperature sensor.
0: Temperature sensor disabled
1: Temperature sensor enabled
Note: Software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion
is ongoing).
Bit 22 VREFEN: VREFINT enable
This bit is set and cleared by software to enable/disable the VREFINT.
0: VREFINT disabled
1: VREFINT enabled
Note: Software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion
is ongoing).
Bits 21:0 Reserved, must be kept at reset value.

12.11 ADC register map

The following table summarizes the ADC registers.

Table 42. ADC register map and reset values

Register
Offset
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12

10
11

9
8
7
6
5
4
3
2
1
0

name
EOSMP
ADRDY
AWD

OVR

EOC
EOS
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.
Res.
Res.

Res.
Res.
Res

ADC_ISR
0x00

Reset value 0 0 0 0 0 0
EOSMPIE
ADRDYIE
AWDIE

OVRIE

EOCIE
EOSIE
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.
Res.
Res.

Res.
Res.
Res

ADC_IER
0x04

Reset value 0 0 0 0 0 0
ADSTART
ADCAL

ADSTP

ADDIS
ADEN
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.

ADC_CR
0x08

Reset value 0 0 0 0 0

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 ...
...
...
0x40
0x38
0x34
0x30
0x28
0x24
0x20
0x18
0x14
0x10

0x3C
0x2C
0x1C
0x0C

0x308
Offset

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name

ADC_TR

ADC_DR

Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved

ADC_CCR
Register

Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value

ADC_SMPR
ADC_CFGR2
ADC_CFGR1

ADC_CHSELR
0
Res. Res. Res. Res. Res. Res. 31
CKMODE[1:0]

0
0
Res. Res. Res. Res. Res. 30
0
Res. Res. Res. Res. Res. Res 29
0

Res. Res. Res. Res. Res. Res. 28

1
0

Res. Res. Res. Res. Res. 27

AWDCH[4:0]

1
0

Res. Res. Res. Res. Res. 26

Analog-to-digital converter (ADC)

1
Res. Res. Res. Res. Res. Res. 25

1
Res. Res. Res. Res. Res. Res. 24

0
1
0

TSEN Res. Res. Res. Res. AWDEN 23

0
1
0

VREFEN Res. Res. Res. Res. AWDSGL 22

1
Res. Res. Res. Res. Res. Res. 21
HT[11:0]

1
Res. Res. Res. Res. Res. Res. 20
1
Res. Res. Res. Res. Res. Res. 19
1
Res. Res. Res Res. Res. Res. 18

RM0360 Rev 5
Res. Res. CHSEL17 Res. Res. Res. 17
1 1

0
0

Res. Res. CHSEL16 Res. Res. DISCEN 16

0
0

Res. CHSEL15 Res. Res. Res. AUTOFF 15

Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved

0 0
0
0

Res. CHSEL14 Res. Res. Res. WAIT 14

0
0
0

Res. CHSEL13 Res. Res. Res. CONT

Refer to Section 2.2 for the register boundary addresses.

13

0
0
0

Res. CHSEL12 Res. Res. Res. OVRMOD 12

0
0
0
0

Res. CHSEL11 Res. Res. 11

EXTEN[1:0]

0
0
0
0

Res. CHSEL10 Res. Res. 10

0
0
0

Res. CHSEL9 Res. Res. Res. 9

0
0
0
0

Res. CHSEL8 Res.

Table 42. ADC register map and reset values (continued)

0 8
0
0
0

Res. CHSEL7 Res. 7

[2:0]

Res.
DATA[15:0]
EXTSEL

0
0
0
0

Res. CHSEL6 Res. 6

0
0
0
0

Res. CHSEL5 Res. ALIGN 5

LT[11:0]

0
0
0
0

Res. CHSEL4 Res. 4

[1:0]
RES

0
0
0

Res. CHSEL3 Res. Res. 3

0
0
0

Res. CHSEL2 SCANDIR 2

0
0
0

Res. CHSEL1 Res. DMACFG 1

[2:0]
SMP

Res.
0
0
0

0
0 0 0

Res. CHSEL0 DMAEN 0

RM0360
RM0360 Advanced-control timers (TIM1)

13 Advanced-control timers (TIM1)

13.1 TIM1 introduction

The advanced-control timers (TIM1) consist of a 16-bit auto-reload counter driven by a
programmable prescaler.
It may be used for a variety of purposes, including measuring the pulse lengths of input
signals (input capture) or generating output waveforms (output compare, PWM,
complementary PWM with dead-time insertion).
Pulse lengths and waveform periods can be modulated from a few microseconds to several
milliseconds using the timer prescaler and the RCC clock controller prescalers.
The advanced-control (TIM1) and general-purpose (TIMx) timers are completely
independent, and do not share any resources. They can be synchronized together as
described in Section 13.3.20.

13.2 TIM1 main features

TIM1 timer features include:
• 16-bit up, down, up/down auto-reload counter.
• 16-bit programmable prescaler allowing dividing (also “on the fly”) the counter clock
frequency either by any factor between 1 and 65535.
• Up to 4 independent channels for:
– Input Capture
– Output Compare
– PWM generation (Edge- and Center-aligned modes)
– One-pulse mode output
• Complementary outputs with programmable dead-time
• Synchronization circuit to control the timer with external signals and to interconnect
several timers together.
• Repetition counter to update the timer registers only after a given number of cycles of
the counter.
• Break input to put the timer’s output signals in reset state or in a known state.
• Interrupt/DMA generation on the following events:
– Update: counter overflow/underflow, counter initialization (by software or
internal/external trigger)
– Trigger event (counter start, stop, initialization or count by internal/external trigger)
– Input capture
– Output compare
– Break input
• Supports incremental (quadrature) encoder and hall-sensor circuitry for positioning
purposes
• Trigger input for external clock or cycle-by-cycle current management

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Figure 45. Advanced-control timer block diagram

Internal Clock (CK_INT)

CK_TIM1 from RCC ETRF
Trigger
ETRP Controller
ETR Polarity Selection & Edge
TIMx_ETR Input Filter TRGO
Detector & Prescaler
to other timers
ITR0 to ADC
TGI
ITR1 ITR
Slave
ITR2 TRC Mode Reset, Enable, Up/Down, Count
TRGI
ITR3 Controller

TI1F_ED

TI1FP1 Encoder
TI2FP2 Interface

REP Register
UI
U AutoReload Register
Repetition
counter U
Stop, Clear or Up/Down

CK_PSC PSC CK_CNT CNT

+/-
Prescaler COUNTER
DTG registers
CC1I CC1I TIMx_CH1
TI1 TI1FP1
XOR
Input Filter &
IC1 IC1PS U OC1REF
TI1FP2 Prescaler Capture/Compare 1 Register DTG output OC1
Edge detector
control TIMx_CH1N
TIMx_CH1 TRC OC1N
CC2I
CC2I TIMx_CH2
TI2 TI2FP1 IC2 IC2PS U
TIMx_CH2 Input Filter & Prescaler OC2REF output OC2
Edge detector TI2FP2 Capture/Compare 2 Register DTG
control TIMx_CH2N
TRC OC2N
CC3I
CC3I TIMx_CH3
TI3 TI3FP3 IC3 U
TIMx_CH3 Input Filter & IC3PS OC3REF output OC3
Edge detector
TI3FP4 Prescaler Capture/Compare 3 Register DTG
control TIMx_CH3N
TRC OC3N
CC4I
CC4I
U TIMx_CH4
TI4FP3 IC4 IC4PS
TI4 Input Filter & OC4REF output
TIMx_CH4 TI4FP4 Prescaler Capture/Compare 4 Register
Edge detector control OC4
TRC

ETRF

BRK BI
TIMx_BKIN Polarity Selection

Clock failure event from clock controller

CSS (Clock Security system

Notes:
Reg Preload registers transferred
to active registers on U event
according to control bit

event

interrupt & DMA output

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RM0360 Advanced-control timers (TIM1)

13.3 TIM1 functional description

13.3.1 Time-base unit

The main block of the programmable advanced-control timer is a 16-bit counter with its
related auto-reload register. The counter can count up, down or both up and down. The
counter clock can be divided by a prescaler.
The counter, the auto-reload register and the prescaler register can be written or read by
software. This is true even when the counter is running.
The time-base unit includes:
• Counter register (TIMx_CNT)
• Prescaler register (TIMx_PSC)
• Auto-reload register (TIMx_ARR)
• Repetition counter register (TIMx_RCR)
The auto-reload register is preloaded. Writing to or reading from the auto-reload register
accesses the preload register. The content of the preload register are transferred into the
shadow register permanently or at each update event (UEV), depending on the auto-reload
preload enable bit (ARPE) in TIMx_CR1 register. The update event is sent when the counter
reaches the overflow (or underflow when downcounting) and if the UDIS bit equals 0 in the
TIMx_CR1 register. It can also be generated by software. The generation of the update
event is described in detailed for each configuration.
The counter is clocked by the prescaler output CK_CNT, which is enabled only when the
counter enable bit (CEN) in TIMx_CR1 register is set (refer also to the slave mode controller
description to get more details on counter enabling).
Note that the counter starts counting 1 clock cycle after setting the CEN bit in the TIMx_CR1
register.

Prescaler description
The prescaler can divide the counter clock frequency by any factor between 1 and 65536. It
is based on a 16-bit counter controlled through a 16-bit register (in the TIMx_PSC register).
It can be changed on the fly as this control register is buffered. The new prescaler ratio is
taken into account at the next update event.
Figure 47 and Figure 48 give some examples of the counter behavior when the prescaler
ratio is changed on the fly:

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Figure 46. Counter timing diagram with prescaler division change from 1 to 2

CK_PSC

CEN

Timerclock = CK_CNT

Counter register F7 F8 F9 FA FB FC 00 01 02 03

Update event (UEV)

Prescaler control register 0 1

Write a new value in TIMx_PSC

Prescaler buffer 0 1

Prescaler counter 0 0 1 0 1 0 1 0 1
MS31076V2

Figure 47. Counter timing diagram with prescaler division change from 1 to 4

CK_PSC

CEN

Timerclock = CK_CNT

F7 F8 F9 FA FB FC 00 01
Counter register

Update event (UEV)

0 3
Prescaler control register

Write a new value in TIMx_PSC

0 3
Prescaler buffer

0 0 1 2 3 0 1 2 3
Prescaler counter

MS31077V2

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RM0360 Advanced-control timers (TIM1)

13.3.2 Counter modes

Upcounting mode
In upcounting mode, the counter counts from 0 to the auto-reload value (content of the
TIMx_ARR register), then restarts from 0 and generates a counter overflow event.
If the repetition counter is used, the update event (UEV) is generated after upcounting is
repeated for the number of times programmed in the repetition counter register
(TIMx_RCR). Else the update event is generated at each counter overflow.
Setting the UG bit in the TIMx_EGR register (by software or by using the slave mode
controller) also generates an update event.
The UEV event can be disabled by software by setting the UDIS bit in the TIMx_CR1
register. This is to avoid updating the shadow registers while writing new values in the
preload registers. Then no update event occurs until the UDIS bit has been written to 0.
However, the counter restarts from 0, as well as the counter of the prescaler (but the
prescale rate does not change). In addition, if the URS bit (update request selection) in
TIMx_CR1 register is set, setting the UG bit generates an update event UEV but without
setting the UIF flag (thus no interrupt or DMA request is sent). This is to avoid generating
both update and capture interrupts when clearing the counter on the capture event.
When an update event occurs, all the registers are updated and the update flag (UIF bit in
TIMx_SR register) is set (depending on the URS bit):
• The repetition counter is reloaded with the content of TIMx_RCR register,
• The auto-reload shadow register is updated with the preload value (TIMx_ARR),
• The buffer of the prescaler is reloaded with the preload value (content of the TIMx_PSC
register).
The following figures show some examples of the counter behavior for different clock
frequencies when TIMx_ARR=0x36.

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Figure 48. Counter timing diagram, internal clock divided by 1

CK_PSC

CNT_EN

Timerclock = CK_CNT

Counter register 31 32 33 34 35 36 00 01 02 03 04 05 06 07

Counter overflow

Update event (UEV)

Update interrupt flag

(UIF)

MS31078V2

Figure 49. Counter timing diagram, internal clock divided by 2

CK_PSC

CNT_EN

Timerclock = CK_CNT

Counter register 0034 0035 0036 0000 0001 0002 0003

Counter overflow

Update event (UEV)

Update interrupt flag

(UIF)

MS31079V2

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RM0360 Advanced-control timers (TIM1)

Figure 50. Counter timing diagram, internal clock divided by 4

CK_PSC

CNT_EN

Timerclock = CK_CNT

Counter register 0035 0036 0000 0001

Counter overflow

Update event (UEV)

Update interrupt flag

(UIF)

MS31080V2

Figure 51. Counter timing diagram, internal clock divided by N

CK_PSC

Timerclock = CK_CNT

Counter register 1F 20 00

Counter overflow

Update event (UEV)

Update interrupt flag

(UIF)

MS31081V2

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Figure 52. Counter timing diagram, update event when ARPE=0

(TIMx_ARR not preloaded)

CK_PSC

CEN

Timerclock = CK_CNT

Counter register 31 32 33 34 35 36 00 01 02 03 04 05 06 07

Counter overflow

Update event (UEV)

Update interrupt flag

(UIF)

Auto-reload preload
register FF 36

Write a new value in TIMx_ARR

MS31082V2

Figure 53. Counter timing diagram, update event when ARPE=1

(TIMx_ARR preloaded)

CK_PSC

CEN

Timerclock = CK_CNT

Counter register F0 F1 F2 F3 F4 F5 00 01 02 03 04 05 06 07

Counter overflow

Update event (UEV)

Update interrupt flag

(UIF)
Auto-reload preload
F5 36
register

Auto-reload shadow
register F5 36

Write a new value in TIMx_ARR MS31083V2

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RM0360 Advanced-control timers (TIM1)

Downcounting mode
In downcounting mode, the counter counts from the auto-reload value (content of the
TIMx_ARR register) down to 0, then restarts from the auto-reload value and generates a
counter underflow event.
If the repetition counter is used, the update event (UEV) is generated after downcounting is
repeated for the number of times programmed in the repetition counter register
(TIMx_RCR). Else the update event is generated at each counter underflow.
Setting the UG bit in the TIMx_EGR register (by software or by using the slave mode
controller) also generates an update event.
The UEV update event can be disabled by software by setting the UDIS bit in TIMx_CR1
register. This is to avoid updating the shadow registers while writing new values in the
preload registers. Then no update event occurs until UDIS bit has been written to 0.
However, the counter restarts from the current auto-reload value, whereas the counter of the
prescaler restarts from 0 (but the prescale rate doesn’t change).
In addition, if the URS bit (update request selection) in TIMx_CR1 register is set, setting the
UG bit generates an update event UEV but without setting the UIF flag (thus no interrupt or
DMA request is sent). This is to avoid generating both update and capture interrupts when
clearing the counter on the capture event.
When an update event occurs, all the registers are updated and the update flag (UIF bit in
TIMx_SR register) is set (depending on the URS bit):
• The repetition counter is reloaded with the content of TIMx_RCR register
• The buffer of the prescaler is reloaded with the preload value (content of the TIMx_PSC
register)
• The auto-reload active register is updated with the preload value (content of the
TIMx_ARR register). Note that the auto-reload is updated before the counter is
reloaded, so that the next period is the expected one
The following figures show some examples of the counter behavior for different clock
frequencies when TIMx_ARR=0x36.

Figure 54. Counter timing diagram, internal clock divided by 1

CK_PSC

CNT_EN

Timer clock = CK_CNT

Counter register 05 04 03 02 01 00 36 35 34 33 32 31 30 2F

Counter underflow (cnt_udf)

Update event (UEV)

Update interrupt flag (UIF)

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Figure 55. Counter timing diagram, internal clock divided by 2

CK_PSC

CNT_EN

Timer clock = CK_CNT

Counter register 0002 0001 0000 0036 0035 0034 0033

Counter underflow

Update event (UEV)

Update interrupt flag (UIF)

Figure 56. Counter timing diagram, internal clock divided by 4

CK_PSC

CNT_EN

Timer clock = CK_CNT

Counter register 0001 0000 0036 0035

Counter underflow

Update event (UEV)

Update interrupt flag (UIF)

Figure 57. Counter timing diagram, internal clock divided by N

CK_PSC

Timer clock = CK_CNT

Counter register 20 1F 00 36

Counter underflow

Update event (UEV)

Update interrupt flag (UIF)

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RM0360 Advanced-control timers (TIM1)

Figure 58. Counter timing diagram, update event when repetition counter is not used

CK_PSC

CEN

Timer clock = CK_CNT

Counter register 05 04 03 02 01 00 36 35 34 33 32 31 30 2F

Counter underflow

Update event (UEV)

Update interrupt flag (UIF)

Auto-reload register FF 36

Write a new value in TIMx_ARR

Center-aligned mode (up/down counting)

In center-aligned mode, the counter counts from 0 to the auto-reload value (content of the
TIMx_ARR register) – 1, generates a counter overflow event, then counts from the auto-
reload value down to 1 and generates a counter underflow event. Then it restarts counting
from 0.
Center-aligned mode is active when the CMS bits in TIMx_CR1 register are not equal to
'00'. The Output compare interrupt flag of channels configured in output is set when: the
counter counts down (Center aligned mode 1, CMS = “01”), the counter counts up (Center
aligned mode 2, CMS = “10”) the counter counts up and down (Center aligned mode 3,
CMS = “11”).
In this mode, the DIR direction bit in the TIMx_CR1 register cannot be written. It is updated
by hardware and gives the current direction of the counter.
The update event can be generated at each counter overflow and at each counter underflow
or by setting the UG bit in the TIMx_EGR register (by software or by using the slave mode
controller) also generates an update event. In this case, the counter restarts counting from
0, as well as the counter of the prescaler.
The UEV update event can be disabled by software by setting the UDIS bit in the TIMx_CR1
register. This is to avoid updating the shadow registers while writing new values in the
preload registers. Then no update event occurs until UDIS bit has been written to 0.
However, the counter continues counting up and down, based on the current auto-reload
value.
In addition, if the URS bit (update request selection) in TIMx_CR1 register is set, setting the
UG bit generates an UEV update event but without setting the UIF flag (thus no interrupt or
DMA request is sent). This is to avoid generating both update and capture interrupts when
clearing the counter on the capture event.

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When an update event occurs, all the registers are updated and the update flag (UIF bit in
TIMx_SR register) is set (depending on the URS bit):
• The repetition counter is reloaded with the content of TIMx_RCR register
• The buffer of the prescaler is reloaded with the preload value (content of the TIMx_PSC
register)
• The auto-reload active register is updated with the preload value (content of the
TIMx_ARR register). Note that if the update source is a counter overflow, the auto-
reload is updated before the counter is reloaded, so that the next period is the expected
one (the counter is loaded with the new value).
The following figures show some examples of the counter behavior for different clock
frequencies.

Figure 59. Counter timing diagram, internal clock divided by 1, TIMx_ARR = 0x6

CK_PSC

CNT_EN

Timer clock = CK_CNT

Counter register 04 03 02 01 00 01 02 03 04 05 06 05 04 03

Counter underflow

Counter overflow

Update event (UEV)

Update interrupt flag (UIF)

1. Here, center-aligned mode 1 is used (for more details refer to Section 13.4: TIM1 registers on page 272).

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RM0360 Advanced-control timers (TIM1)

Figure 60. Counter timing diagram, internal clock divided by 2

CK_PSC

CNT_EN

Timerclock = CK_CNT

Counter register 0002 0001 0000 0036 0035 0034 0033

Counter underflow

Update event (UEV)

Update interrupt flag

(UIF)

MS31185V1

Figure 61. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36

CK_PSC

CNT_EN

Timerclock = CK_CNT

Counter register 0034 0035 0036 0035

Counter overflow

Update event (UEV)

Update interrupt flag

(UIF)

Note: Here, center_aligned mode 2 or 3 is updated with an UIF on overflow

MS31191V1

1. Center-aligned mode 2 or 3 is used with an UIF on overflow.

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Figure 62. Counter timing diagram, internal clock divided by N

CK_PSC

Timerclock = CK_CNT

Counter register 20 1F 01 00

Counter underflow

Update event (UEV)

Update interrupt flag

(UIF)

MS31192V1

Figure 63. Counter timing diagram, update event with ARPE=1 (counter underflow)

CK_PSC

CEN

Timerclock = CK_CNT

Counter register 06 05 04 03 02 01 00 01 02 03 04 05 06 07

Counter underflow

Update event (UEV)

Update interrupt flag

(UIF)

Auto-reload preload
register FD 36

Write a new value in TIMx_ARR

Auto-reload active
register FD 36

MS31193V1

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RM0360 Advanced-control timers (TIM1)

Figure 64. Counter timing diagram, Update event with ARPE=1 (counter overflow)

CK_PSC

CEN

Timer clock = CK_CNT

Counter register F7 F8 F9 FA FB FC 36 35 34 33 32 31 30 2F

Counter overflow

Update event (UEV)

Update interrupt flag

(UIF)
Auto-reload preload
FD 36
register

Write a new value in TIMx_ARR

Auto-reload active
register FD 36

MS31194V1

13.3.3 Repetition counter

Section 13.3.1: Time-base unit describes how the update event (UEV) is generated with
respect to the counter overflows/underflows. It is actually generated only when the repetition
counter has reached zero. This can be useful when generating PWM signals.
This means that data are transferred from the preload registers to the shadow registers
(TIMx_ARR auto-reload register, TIMx_PSC prescaler register, but also TIMx_CCRx
capture/compare registers in compare mode) every N counter overflows or underflows,
where N is the value in the TIMx_RCR repetition counter register.
The repetition counter is decremented:
• At each counter overflow in upcounting mode,
• At each counter underflow in downcounting mode,
• At each counter overflow and at each counter underflow in center-aligned mode.
Although this limits the maximum number of repetition to 128 PWM cycles, it makes it
possible to update the duty cycle twice per PWM period. When refreshing compare
registers only once per PWM period in center-aligned mode, maximum resolution is
2xTck, due to the symmetry of the pattern.
The repetition counter is an auto-reload type; the repetition rate is maintained as defined by
the TIMx_RCR register value (refer to Figure 65). When the update event is generated by
software (by setting the UG bit in TIMx_EGR register) or by hardware through the slave
mode controller, it occurs immediately whatever the value of the repetition counter is and the
repetition counter is reloaded with the content of the TIMx_RCR register.

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In center-aligned mode, for odd values of RCR, the update event occurs either on the
overflow or on the underflow depending on when the RCR register was written and when
the counter was started. If the RCR was written before starting the counter, the UEV occurs
on the overflow. If the RCR was written after starting the counter, the UEV occurs on the
underflow. For example for RCR = 3, the UEV is generated on each 4th overflow or
underflow event depending on when RCR was written.

Figure 65. Update rate examples depending on mode and TIMx_RCR register settings

Counter-aligned mode Edge-aligned mode

Counter Upcounting Downcounting
TIMx_CNT

TIMx_RCR = 0
UEV

TIMx_RCR = 1
UEV

UEV
TIMx_RCR = 2

TIMx_RCR = 3 UEV

TIMx_RCR = 3
and
UEV
re-synchronization
(by SW) (by SW) (by SW)

UEV Update event: Preload registers transferred to active registers and update interrupt generated

MSv33112V1

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RM0360 Advanced-control timers (TIM1)

13.3.4 Clock sources

The counter clock can be provided by the following clock sources:
• Internal clock (CK_INT)
• External clock mode1: external input pin
• External clock mode2: external trigger input ETR
• Internal trigger inputs (ITRx): using one timer as prescaler for another timer, for
example, Timer 1 can be configured to act as a prescaler for Timer 2. Refer to Using
one timer as prescaler for another on page 337 for more details.

Internal clock source (CK_INT)

If the slave mode controller is disabled (SMS=000), then the CEN, DIR (in the TIMx_CR1
register) and UG bits (in the TIMx_EGR register) are actual control bits and can be changed
only by software (except UG which remains cleared automatically). As soon as the CEN bit
is written to 1, the prescaler is clocked by the internal clock CK_INT.
Figure 66 shows the behavior of the control circuit and the upcounter in normal mode,
without prescaler.

Figure 66. Control circuit in normal mode, internal clock divided by 1

Internal clock

CEN=CNT_EN

UG

CNT_INIT

Counter clock = CK_CNT = CK_PSC

Counter register 31 32 33 34 35 36 00 01 02 03 04 05 06 07

MS31085V2

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External clock source mode 1

This mode is selected when SMS=111 in the TIMx_SMCR register. The counter can count at
each rising or falling edge on a selected input.

Figure 67. TI2 external clock connection example

TIMx_SMCR
TS[2:0]

or TI2F or
TI1F or Encoder
ITRx mode
0xx
TI1_ED
100 TRGI External clock
TI1FP1 mode 1 CK_PSC
TI2F_Rising 101
TI2 Edge 0 TI2FP2 ETRF External clock
Filter 110
detector 1 ETRF mode 2
TI2F_Falling 111
CK_INT Internal clock
mode
ICF[3:0] CC2P (internal clock)

TIMx_CCMR1 TIMx_CCER
ECE SMS[2:0]
TIMx_SMCR

MS31196V1

For example, to configure the upcounter to count in response to a rising edge on the TI2
input, use the following procedure:
1. Configure channel 2 to detect rising edges on the TI2 input by writing CC2S = ‘01’ in
the TIMx_CCMR1 register.
2. Configure the input filter duration by writing the IC2F[3:0] bits in the TIMx_CCMR1
register (if no filter is needed, keep IC2F=0000).
3. Select rising edge polarity by writing CC2P=0 in the TIMx_CCER register.
4. Configure the timer in external clock mode 1 by writing SMS=111 in the TIMx_SMCR
register.
5. Select TI2 as the trigger input source by writing TS=110 in the TIMx_SMCR register.
6. Enable the counter by writing CEN=1 in the TIMx_CR1 register.
Note: The capture prescaler is not used for triggering, so it does not need to be configured.
For code examples refer to the Appendix section A.8.1: Upcounter on TI2 rising edge.
When a rising edge occurs on TI2, the counter counts once and the TIF flag is set.
The delay between the rising edge on TI2 and the actual clock of the counter is due to the
resynchronization circuit on TI2 input.

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RM0360 Advanced-control timers (TIM1)

Figure 68. Control circuit in external clock mode 1

TI2

CNT_EN

Counter clock = CK_CNT = CK_PSC

Counter register 34 35 36

TIF

Write TIF=0

MS31087V2

External clock source mode 2

This mode is selected by writing ECE=1 in the TIMx_SMCR register.
The counter can count at each rising or falling edge on the external trigger input ETR.
The Figure 69 gives an overview of the external trigger input block.

Figure 69. External trigger input block

or TI2F or
TI1F or Encoder
mode

TRGI External clock

ETR mode 1 CK_PSC
0
Divider ETRP
ETR pin Filter ETRF External clock
/1, /2, /4, /8
1 fDTS downcounter mode 2
CK_INT Internal clock
ETP ETPS[1:0] ETF[3:0] mode
(internal clock)
TIMx_SMCR TIMx_SMCR TIMx_SMCR

ECE SMS[2:0]
TIMx_SMCR

MS33116V1

For example, to configure the upcounter to count each 2 rising edges on ETR, use the
following procedure:

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1. As no filter is needed in this example, write ETF[3:0]=0000 in the TIMx_SMCR register.

2. Set the prescaler by writing ETPS[1:0]=01 in the TIMx_SMCR register
3. Select rising edge detection on the ETR pin by writing ETP=0 in the TIMx_SMCR
register
4. Enable external clock mode 2 by writing ECE=1 in the TIMx_SMCR register.
5. Enable the counter by writing CEN=1 in the TIMx_CR1 register.
The counter counts once each 2 ETR rising edges.
For code example refer to the Appendix section A.8.2: Up counter on each 2 ETR rising
edges.
The delay between the rising edge on ETR and the actual clock of the counter is due to the
resynchronization circuit on the ETRP signal.

Figure 70. Control circuit in external clock mode 2

f CK_INT

CNT_EN

ETR

ETRP

ETRF

Counter clock =
CK_INT =CK_PSC

Counter register 34 35 36

MS33111V2

13.3.5 Capture/compare channels

Each Capture/Compare channel is built around a capture/compare register (including a
shadow register), a input stage for capture (with digital filter, multiplexing and prescaler) and
an output stage (with comparator and output control).
Figure 71 to Figure 74 give an overview of one Capture/Compare channel.
The input stage samples the corresponding TIx input to generate a filtered signal TIxF.
Then, an edge detector with polarity selection generates a signal (TIxFPx) which can be
used as trigger input by the slave mode controller or as the capture command. It is
prescaled before the capture register (ICxPS).

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Figure 71. Capture/compare channel (example: channel 1 input stage)

TI1F_ED
To the slave mode controller

TI1 TI1F_Rising
Filter TI1F Edge 0 TI1FP1
fDTS downcounter TI1F_Falling 01
detector 1
TI2FP1 IC1 Divider IC1PS
10
/1, /2, /4, /8
ICF[3:0] CC1P/CC1NP TRC
11
TIMx_CCMR1 TIMx_CCER (from slave mode
TI2F_Rising controller)
0
(from channel 2)
CC1S[1:0] ICPS[1:0] CC1E
TI2F_Falling
1
(from channel 2) TIMx_CCMR1 TIMx_CCER

MS33115V1

The output stage generates an intermediate waveform which is then used for reference:
OCxRef (active high). The polarity acts at the end of the chain.

Figure 72. Capture/compare channel 1 main circuit

APB Bus

MCU-peripheral interface
(if 16-bit)

8 8
high

S write CCR1H
low

Read CCR1H S write_in_progress

read_in_progress write CCR1L
Read CCR1L Capture/compare preload register R
R Output CC1S[1]
capture_transfer compare_transfer mode
CC1S[0]
CC1S[1] Input
mode OC1PE
CC1S[0] Capture/compare shadow register OC1PE
UEV
TIM1_CCMR1
Comparator (from time
IC1PS Capture
base unit)
CC1E CNT>CCR1
Counter CNT=CCR1
CC1G
TIM1_EGR

MS31089V2

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Figure 73. Output stage of capture/compare channel (channel 1 to 3)

TIMx_SMCR
OCCS

OCREF_CLR
0
0
ETRF Output OC1
1 enable
‘0’
x0 1 circuit
ocref_clr_int
10
OC1_DT CC1P
CNT>CCR1 11
Output mode OC1REF Dead-time TIM1_CCER
CNT=CCR1 controller generator
OC1N_DT
11
10 0 OC1N
Output
‘0’ 0x enable
1 circuit

CC1NE CC1E TIM1_CCER

OC1CE OC1M[2:0] DTG[7:0] CC1NE CC1E CC1NP MOE OSSI OSSR TIM1_BDTR
TIM1_CCMR1 TIM1_BDTR TIM1_CCER TIM1_CCER

MS31047V1

Figure 74. Output stage of capture/compare channel (channel 4)

TIMx_SMCR
OCCS

OCREF_CLR 0 To the master

mode controller
ETRF 1

ocref_clr_int
‘0’ 0 0
CNT > CCR4 Output OC4
Output enable
OC4REF 1
mode 1 circuit
CNT = CCR4
controller
CC5E CC4P
TIM1_CCER TIM1_CCER CC4E TIM1_CCER
OC2M[2:0]
MOE OSSI TIM1_BDTR
TIM1_CCMR2
OIS4 TIM1_CR2

MS31048V1

The capture/compare block is made of one preload register and one shadow register. Write
and read always access the preload register.
In capture mode, captures are actually done in the shadow register, which is copied into the
preload register.
In compare mode, the content of the preload register is copied into the shadow register
which is compared to the counter.

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13.3.6 Input capture mode

In Input capture mode, the Capture/Compare Registers (TIMx_CCRx) are used to latch the
value of the counter after a transition detected by the corresponding ICx signal. When a
capture occurs, the corresponding CCXIF flag (TIMx_SR register) is set and an interrupt or
a DMA request can be sent if they are enabled. If a capture occurs while the CCxIF flag was
already high, then the over-capture flag CCxOF (TIMx_SR register) is set. CCxIF can be
cleared by software by writing it to ‘0’ or by reading the captured data stored in the
TIMx_CCRx register. CCxOF is cleared when it is written with 0.
The following example shows how to capture the counter value in TIMx_CCR1 when TI1
input rises. To do this, use the following procedure:
• Select the active input: TIMx_CCR1 must be linked to the TI1 input, so write the CC1S
bits to 01 in the TIMx_CCMR1 register. As soon as CC1S becomes different from 00,
the channel is configured in input and the TIMx_CCR1 register becomes read-only.
• Program the appropriate input filter duration in relation with the signal connected to the
timer (when the input is one of the TIx (ICxF bits in the TIMx_CCMRx register). Let’s
imagine that, when toggling, the input signal is not stable during at must 5 internal clock
cycles. We must program a filter duration longer than these 5 clock cycles. We can
validate a transition on TI1 when 8 consecutive samples with the new level have been
detected (sampled at fDTS frequency). Then write IC1F bits to 0011 in the
TIMx_CCMR1 register.
• Select the edge of the active transition on the TI1 channel by writing CC1P and CC1NP
bits to 0 in the TIMx_CCER register (rising edge in this case).
• Program the input prescaler. In our example, we wish the capture to be performed at
each valid transition, so the prescaler is disabled (write IC1PS bits to ‘00’ in the
TIMx_CCMR1 register).
• Enable capture from the counter into the capture register by setting the CC1E bit in the
TIMx_CCER register.
• If needed, enable the related interrupt request by setting the CC1IE bit in the
TIMx_DIER register, and/or the DMA request by setting the CC1DE bit in the
TIMx_DIER register.
For code example refer to the Appendix section A.8.3: Input capture configuration.
When an input capture occurs:
• The TIMx_CCR1 register gets the value of the counter on the active transition.
• CC1IF flag is set (interrupt flag). CC1OF is also set if at least two consecutive captures
occurred whereas the flag was not cleared.
• An interrupt is generated depending on the CC1IE bit.
• A DMA request is generated depending on the CC1DE bit.
For code example refer to the Appendix section A.8.4: Input capture data management.
In order to handle the overcapture, it is recommended to read the data before the
overcapture flag. This is to avoid missing an overcapture which could happen after reading
the flag and before reading the data.
Note: IC interrupt and/or DMA requests can be generated by software by setting the
corresponding CCxG bit in the TIMx_EGR register.

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13.3.7 PWM input mode

This mode is a particular case of input capture mode. The procedure is the same except:
• Two ICx signals are mapped on the same TIx input.
• These 2 ICx signals are active on edges with opposite polarity.
• One of the two TIxFP signals is selected as trigger input and the slave mode controller
is configured in reset mode.
For example, one can measure the period (in TIMx_CCR1 register) and the duty cycle (in
TIMx_CCR2 register) of the PWM applied on TI1 using the following procedure (depending
on CK_INT frequency and prescaler value):
• Select the active input for TIMx_CCR1: write the CC1S bits to 01 in the TIMx_CCMR1
register (TI1 selected).
• Select the active polarity for TI1FP1 (used both for capture in TIMx_CCR1 and counter
clear): write the CC1P and CC1NP bits to ‘0’ (active on rising edge).
• Select the active input for TIMx_CCR2: write the CC2S bits to 10 in the TIMx_CCMR1
register (TI1 selected).
• Select the active polarity for TI1FP2 (used for capture in TIMx_CCR2): write the CC2P
bit to '1' and the CC2NP bit to '0' (active on falling edge).
• Select the valid trigger input: write the TS bits to 101 in the TIMx_SMCR register
(TI1FP1 selected).
• Configure the slave mode controller in reset mode: write the SMS bits to 100 in the
TIMx_SMCR register.
• Enable the captures: write the CC1E and CC2E bits to ‘1’ in the TIMx_CCER register.
For code example refer to the Appendix section A.8.5: PWM input configuration.

Figure 75. PWM input mode timing

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13.3.8 Forced output mode

In output mode (CCxS bits = 00 in the TIMx_CCMRx register), each output compare signal
(OCxREF and then OCx/OCxN) can be forced to active or inactive level directly by software,
independently of any comparison between the output compare register and the counter.
To force an output compare signal (OCXREF/OCx) to its active level, one just needs to write
101 in the OCxM bits in the corresponding TIMx_CCMRx register. Thus OCXREF is forced
high (OCxREF is always active high) and OCx get opposite value to CCxP polarity bit.
For example: CCxP=0 (OCx active high) => OCx is forced to high level.
The OCxREF signal can be forced low by writing the OCxM bits to 100 in the TIMx_CCMRx
register.
Anyway, the comparison between the TIMx_CCRx shadow register and the counter is still
performed and allows the flag to be set. Interrupt and DMA requests can be sent
accordingly. This is described in the output compare mode section below.

13.3.9 Output compare mode

This function is used to control an output waveform or indicating when a period of time has
elapsed.
When a match is found between the capture/compare register and the counter, the output
compare function:
• Assigns the corresponding output pin to a programmable value defined by the output
compare mode (OCxM bits in the TIMx_CCMRx register) and the output polarity (CCxP
bit in the TIMx_CCER register). The output pin can keep its level (OCXM=000), be set
active (OCxM=001), be set inactive (OCxM=010) or can toggle (OCxM=011) on match.
• Sets a flag in the interrupt status register (CCxIF bit in the TIMx_SR register).
• Generates an interrupt if the corresponding interrupt mask is set (CCXIE bit in the
TIMx_DIER register).
• Sends a DMA request if the corresponding enable bit is set (CCxDE bit in the
TIMx_DIER register, CCDS bit in the TIMx_CR2 register for the DMA request
selection).
The TIMx_CCRx registers can be programmed with or without preload registers using the
OCxPE bit in the TIMx_CCMRx register.
In output compare mode, the update event UEV has no effect on OCxREF and OCx output.
The timing resolution is one count of the counter. Output compare mode can also be used to
output a single pulse (in One Pulse mode).

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Procedure:
1. Select the counter clock (internal, external, prescaler).
2. Write the desired data in the TIMx_ARR and TIMx_CCRx registers.
3. Set the CCxIE bit if an interrupt request is to be generated.
4. Select the output mode. For example:
– Write OCxM = 011 to toggle OCx output pin when CNT matches CCRx
– Write OCxPE = 0 to disable preload register
– Write CCxP = 0 to select active high polarity
– Write CCxE = 1 to enable the output
5. Enable the counter by setting the CEN bit in the TIMx_CR1 register.
For code example refer to the Appendix section A.8.7: Output compare configuration.
The TIMx_CCRx register can be updated at any time by software to control the output
waveform, provided that the preload register is not enabled (OCxPE=’0’, else TIMx_CCRx
shadow register is updated only at the next update event UEV). An example is given in
Figure 76.

Figure 76. Output compare mode, toggle on OC1

Write B201h in the CC1R register

TIM1_CNT 0039 003A 003B B200 B201

TIM1_CCR1 003A B201

OC1REF= OC1

Match detected on CCR1

Interrupt generated if enabled

MS31092V1

13.3.10 PWM mode

Pulse Width Modulation mode allows to generate a signal with a frequency determined by
the value of the TIMx_ARR register and a duty cycle determined by the value of the
TIMx_CCRx register.
The PWM mode can be selected independently on each channel (one PWM per OCx
output) by writing ‘110’ (PWM mode 1) or ‘111’ (PWM mode 2) in the OCxM bits in the
TIMx_CCMRx register. The corresponding preload register must be enabled by setting the

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OCxPE bit in the TIMx_CCMRx register, and eventually the auto-reload preload register (in
upcounting or center-aligned modes) by setting the ARPE bit in the TIMx_CR1 register.
As the preload registers are transferred to the shadow registers only when an update event
occurs, before starting the counter, all registers must be initialized by setting the UG bit in
the TIMx_EGR register.
OCx polarity is software programmable using the CCxP bit in the TIMx_CCER register. It
can be programmed as active high or active low. OCx output is enabled by a combination of
the CCxE, CCxNE, MOE, OSSI and OSSR bits (TIMx_CCER and TIMx_BDTR registers).
Refer to the TIMx_CCER register description for more details.
In PWM mode (1 or 2), TIMx_CNT and TIMx_CCRx are always compared to determine
whether TIMx_CCRx ≤ TIMx_CNT or TIMx_CNT ≤ TIMx_CCRx (depending on the direction
of the counter).
The timer is able to generate PWM in edge-aligned mode or center-aligned mode
depending on the CMS bits in the TIMx_CR1 register.

PWM edge-aligned mode

• Upcounting configuration
Upcounting is active when the DIR bit in the TIMx_CR1 register is low. Refer to the
Upcounting mode on page 229.
In the following example, we consider PWM mode 1. The reference PWM signal
OCxREF is high as long as TIMx_CNT < TIMx_CCRx else it becomes low. If the
compare value in TIMx_CCRx is greater than the auto-reload value (in TIMx_ARR)
then OCxREF is held at ‘1’. If the compare value is 0 then OCxRef is held at ‘0’.
Figure 77 shows some edge-aligned PWM waveforms in an example where
TIMx_ARR=8.

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Figure 77. Edge-aligned PWM waveforms (ARR=8)

Counter register 0 1 2 3 4 5 6 7 8 0 1

OCXREF
CCRx=4
CCxIF

OCXREF
CCRx=8
CCxIF

OCXREF ‘1’
CCRx>8
CCxIF

OCXREF ‘0’
CCRx=0
CCxIF

MS31093V1

For code example refer to the Appendix section A.8.8: Edge-aligned PWM configuration
example.
• Downcounting configuration
Downcounting is active when DIR bit in TIMx_CR1 register is high. Refer to the
Downcounting mode on page 233
In PWM mode 1, the reference signal OCxRef is low as long as
TIMx_CNT > TIMx_CCRx else it becomes high. If the compare value in TIMx_CCRx is
greater than the auto-reload value in TIMx_ARR, then OCxREF is held at ‘1’. 0% PWM
is not possible in this mode.

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PWM center-aligned mode

Center-aligned mode is active when the CMS bits in TIMx_CR1 register are different from
‘00’ (all the remaining configurations having the same effect on the OCxRef/OCx signals).
The compare flag is set when the counter counts up, when it counts down or both when it
counts up and down depending on the CMS bits configuration. The direction bit (DIR) in the
TIMx_CR1 register is updated by hardware and must not be changed by software. Refer to
the Center-aligned mode (up/down counting) on page 235.
Figure 78 shows some center-aligned PWM waveforms in an example where:
• TIMx_ARR=8,
• PWM mode is the PWM mode 1,
• The flag is set when the counter counts down corresponding to the center-aligned
mode 1 selected for CMS=01 in TIMx_CR1 register.
For code example refer to the Appendix section A.8.9: Center-aligned PWM configuration
example.

Figure 78. Center-aligned PWM waveforms (ARR=8)

Counter register 0 1 2 3 4 5 6 7 8 7 6 5 4 3 2 1 0 1

OCxREF
CCRx = 4

CCxIF CMS=01
CMS=10
CMS=11

OCxREF
CCRx=7

CMS=10 or 11
CCxIF
‘1’
OCxREF
CCRx=8

CCxIF CMS=01
CMS=10
CMS=11
‘1’
OCxREF
CCRx>8

CCxIF CMS=01
CMS=10
CMS=11
‘0’
OCxREF
CCRx=0

CCxIF CMS=01
CMS=10
CMS=11

AI14681b

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Hints on using center-aligned mode:

• When starting in center-aligned mode, the current up-down configuration is used. It
means that the counter counts up or down depending on the value written in the DIR bit
in the TIMx_CR1 register. Moreover, the DIR and CMS bits must not be changed at the
same time by the software.
• Writing to the counter while running in center-aligned mode is not recommended as it
can lead to unexpected results. In particular:
– The direction is not updated if a value greater than the auto-reload value is written
in the counter (TIMx_CNT>TIMx_ARR). For example, if the counter was counting
up, it continues to count up.
– The direction is updated if 0 or the TIMx_ARR value is written in the counter but no
Update Event UEV is generated.
• The safest way to use center-aligned mode is to generate an update by software
(setting the UG bit in the TIMx_EGR register) just before starting the counter and not to
write the counter while it is running.

13.3.11 Complementary outputs and dead-time insertion

The advanced-control timers (TIM1) can output two complementary signals and manage the
switching-off and the switching-on instants of the outputs.
This time is generally known as dead-time and it has to be adjusted depending on the
devices that are connected to the outputs and their characteristics (intrinsic delays of level-
shifters, delays due to power switches...)
The polarity of the outputs (main output OCx or complementary OCxN) can be selected
independently for each output. This is done by writing to the CCxP and CCxNP bits in the
TIMx_CCER register.
The complementary signals OCx and OCxN are activated by a combination of several
control bits: the CCxE and CCxNE bits in the TIMx_CCER register and the MOE, OISx,
OISxN, OSSI and OSSR bits in the TIMx_BDTR and TIMx_CR2 registers. Refer to
Table 45: Output control bits for complementary OCx and OCxN channels with break
feature on page 290 for more details. In particular, the dead-time is activated when
switching to the IDLE state (MOE falling down to 0).
Dead-time insertion is enabled by setting both CCxE and CCxNE bits, and the MOE bit if the
break circuit is present. There is one 10-bit dead-time generator for each channel. From a
reference waveform OCxREF, it generates 2 outputs OCx and OCxN. If OCx and OCxN are
active high:
• The OCx output signal is the same as the reference signal except for the rising edge,
which is delayed relative to the reference rising edge.
• The OCxN output signal is the opposite of the reference signal except for the rising
edge, which is delayed relative to the reference falling edge.
If the delay is greater than the width of the active output (OCx or OCxN) then the
corresponding pulse is not generated.
The following figures show the relationships between the output signals of the dead-time
generator and the reference signal OCxREF. (we suppose CCxP=0, CCxNP=0, MOE=1,
CCxE=1 and CCxNE=1 in these examples)

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Figure 79. Complementary output with dead-time insertion.

OCxREF

OCx
delay
OCxN
delay

MS31095V1

Figure 80. Dead-time waveforms with delay greater than the negative pulse.

OCxREF

OCx

delay
OCxN

MS31096V1

Figure 81. Dead-time waveforms with delay greater than the positive pulse.

OCxREF

OCx

OCxN

delay

MS31097V1

The dead-time delay is the same for each of the channels and is programmable with the
DTG bits in the TIMx_BDTR register. Refer to Section 13.4.18: TIM1 break and dead-time
register (TIM1_BDTR) on page 295 for delay calculation.

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Re-directing OCxREF to OCx or OCxN

In output mode (forced, output compare or PWM), OCxREF can be re-directed to the OCx
output or to OCxN output by configuring the CCxE and CCxNE bits in the TIMx_CCER
register.
This allows to send a specific waveform (such as PWM or static active level) on one output
while the complementary remains at its inactive level. Other alternative possibilities are to
have both outputs at inactive level or both outputs active and complementary with dead-
time.
Note: When only OCxN is enabled (CCxE=0, CCxNE=1), it is not complemented and becomes
active as soon as OCxREF is high. For example, if CCxNP=0 then OCxN=OCxRef. On the
other hand, when both OCx and OCxN are enabled (CCxE=CCxNE=1) OCx becomes
active when OCxREF is high whereas OCxN is complemented and becomes active when
OCxREF is low.

13.3.12 Using the break function

When using the break function, the output enable signals and inactive levels are modified
according to additional control bits (MOE, OSSI and OSSR bits in the TIMx_BDTR register,
OISx and OISxN bits in the TIMx_CR2 register). In any case, the OCx and OCxN outputs
cannot be set both to active level at a given time. Refer to Table 45: Output control bits for
complementary OCx and OCxN channels with break feature on page 290 for more details.
The source for break (BRK) channel can be an external source connected to the BKIN pin or
one of the following internal sources:
• the core LOCKUP output
• the PVD output
• the SRAM parity error signal
• a clock failure event generated by the CSS detector
• the output from a comparator
When exiting from reset, the break circuit is disabled and the MOE bit is low. The break
function can be enabled by setting the BKE bit in the TIMx_BDTR register. The break input
polarity can be selected by configuring the BKP bit in the same register. BKE and BKP can
be modified at the same time. When the BKE and BKP bits are written, a delay of 1 APB
clock cycle is applied before the writing is effective. Consequently, it is necessary to wait 1
APB clock period to correctly read back the bit after the write operation.
Because MOE falling edge can be asynchronous, a resynchronization circuit has been
inserted between the actual signal (acting on the outputs) and the synchronous control bit
(accessed in the TIMx_BDTR register). It results in some delays between the asynchronous
and the synchronous signals. In particular, if MOE is set to 1 whereas it was low, a delay
must be inserted (dummy instruction) before reading it correctly. This is because the write
acts on the asynchronous signal whereas the read reflects the synchronous signal.

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When a break occurs (selected level on the break input):

• The MOE bit is cleared asynchronously, putting the outputs in inactive state, idle state
or in reset state (selected by the OSSI bit). This feature functions even if the MCU
oscillator is off.
• Each output channel is driven with the level programmed in the OISx bit in the
TIMx_CR2 register as soon as MOE=0. If OSSI=0 then the timer releases the enable
output else the enable output remains high.
• When complementary outputs are used:
– The outputs are first put in reset state inactive state (depending on the polarity).
This is done asynchronously so that it works even if no clock is provided to the
timer.
– If the timer clock is still present, then the dead-time generator is reactivated in
order to drive the outputs with the level programmed in the OISx and OISxN bits
after a dead-time. Even in this case, OCx and OCxN cannot be driven to their
active level together. Note that because of the resynchronization on MOE, the
dead-time duration is a bit longer than usual (around 2 ck_tim clock cycles).
– If OSSI=0 then the timer releases the enable outputs else the enable outputs
remain or become high as soon as one of the CCxE or CCxNE bits is high.
• The break status flag (BIF bit in the TIMx_SR register) is set. An interrupt can be
generated if the BIE bit in the TIMx_DIER register is set.
• If the AOE bit in the TIMx_BDTR register is set, the MOE bit is automatically set again
at the next update event UEV. This can be used to perform a regulation, for instance.
Else, MOE remains low until it is written with 1 again. In this case, it can be used for
security and the break input can be connected to an alarm from power drivers, thermal
sensors or any security components.
Note: The break inputs is acting on level. Thus, the MOE cannot be set while the break input is
active (neither automatically nor by software). In the meantime, the status flag BIF cannot
be cleared.
The break can be generated by the BRK input which has a programmable polarity and an
enable bit BKE in the TIMx_BDTR Register.
In addition to the break input and the output management, a write protection has been
implemented inside the break circuit to safeguard the application. It allows to freeze the
configuration of several parameters (dead-time duration, OCx/OCxN polarities and state
when disabled, OCxM configurations, break enable and polarity). The protection can be
selected among 3 levels with the LOCK bits in the TIMx_BDTR register. Refer to
Section 13.4.18: TIM1 break and dead-time register (TIM1_BDTR) on page 295. The LOCK
bits can be written only once after an MCU reset.
The Figure 82 shows an example of behavior of the outputs in response to a break.

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Figure 82. Output behavior in response to a break

BREAK (MOE )

OCxREF

OCx
(OCxN not implemented, CCxP=0, OISx=1)

OCx
(OCxN not implemented, CCxP=0, OISx=0)

OCx
(OCxN not implemented, CCxP=1, OISx=1)

OCx
(OCxN not implemented, CCxP=1, OISx=0)

OCx

OCxN delay delay delay

(CCxE=1, CCxP=0, OISx=0, CCxNE=1, CCxNP=0, OISxN=1)

OCx

OCxN delay delay delay

(CCxE=1, CCxP=0, OISx=1, CCxNE=1, CCxNP=1, OISxN=1)

OCx

OCxN delay
(CCxE=1, CCxP=0, OISx=0, CCxNE=0, CCxNP=0, OISxN=1)

OCx

OCxN delay
(CCxE=1, CCxP=0, OISx=1, CCxNE=0, CCxNP=0, OISxN=0)

OCx

OCxN
(CCxE=1, CCxP=0, CCxNE=0, CCxNP=0, OISx=OISxN=0 or OISx=OISxN=1)

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13.3.13 Clearing the OCxREF signal on an external event

The OCxREF signal of a given channel can be cleared when a high level is applied on the
OCREF_CLR_INPUT (OCxCE enable bit in the corresponding TIMx_CCMRx register set to
1). OCxREF remains low until the next update event (UEV) occurs. This function can only
be used in Output compare and PWM modes. It does not work in Forced mode.
OCREF_CLR_INPUT can be selected between the OCREF_CLR input and ETRF (ETR
after the filter) by configuring the OCCS bit in the TIMx_SMCR register.
When ETRF is chosen, ETR must be configured as follows:
The OCxREF signal for a given channel can be driven Low by applying a High level to the
ETRF input (OCxCE enable bit of the corresponding TIMx_CCMRx register set to ‘1’). The
OCxREF signal remains Low until the next update event, UEV, occurs.
This function can only be used in output compare and PWM modes, and does not work in
forced mode.
For example, the OCxREF signal can be connected to the output of a comparator to be
used for current handling. In this case, the ETR must be configured as follow:
1. The External Trigger Prescaler should be kept off: bits ETPS[1:0] of the TIMx_SMCR
register set to ‘00’.
2. The external clock mode 2 must be disabled: bit ECE of the TIMx_SMCR register set to
‘0’.
3. The External Trigger Polarity (ETP) and the External Trigger Filter (ETF) can be
configured according to the user needs.
For code example refer to the Appendix section A.8.10: ETR configuration to clear
OCxREF.
Figure 83 shows the behavior of the OCxREF signal when the ETRF Input becomes High,
for both values of the enable bit OCxCE. In this example, the timer TIMx is programmed in
PWM mode.

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Figure 83. Clearing TIMx OCxREF

(CCRx)

Counter (CNT)

ETRF

OCxREF
(OCxCE = ‘0’)

OCxREF
(OCxCE = ‘1’)

OCxREF_CLR OCxREF_CLR
becomes high still high
MS33105V1

Note: In case of a PWM with a 100% duty cycle (if CCRx>ARR), then OCxREF is enabled again at
the next counter overflow.

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13.3.14 6-step PWM generation

When complementary outputs are used on a channel, preload bits are available on the
OCxM, CCxE and CCxNE bits. The preload bits are transferred to the shadow bits at the
COM commutation event. Thus one can program in advance the configuration for the next
step and change the configuration of all the channels at the same time. COM can be
generated by software by setting the COM bit in the TIMx_EGR register or by hardware (on
TRGI rising edge).
A flag is set when the COM event occurs (COMIF bit in the TIMx_SR register), which can
generate an interrupt (if the COMIE bit is set in the TIMx_DIER register) or a DMA request
(if the COMDE bit is set in the TIMx_DIER register).
The Figure 84 describes the behavior of the OCx and OCxN outputs when a COM event
occurs, in 3 different examples of programmed configurations.

Figure 84. 6-step generation, COM example (OSSR=1)

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13.3.15 One-pulse mode

One-pulse mode (OPM) is a particular case of the previous modes. It allows the counter to
be started in response to a stimulus and to generate a pulse with a programmable length
after a programmable delay.
Starting the counter can be controlled through the slave mode controller. Generating the
waveform can be done in output compare mode or PWM mode. One-pulse mode is selected
by setting the OPM bit in the TIMx_CR1 register. This makes the counter stop automatically
at the next update event UEV.
A pulse can be correctly generated only if the compare value is different from the counter
initial value. Before starting (when the timer is waiting for the trigger), the configuration must
be:
• In upcounting: CNT < CCRx ≤ ARR (in particular, 0 < CCRx)
• In downcounting: CNT > CCRx

Figure 85. Example of one pulse mode

TI2

OC1REF

OC1

TIM1_ARR
Counter

TIM1_CCR1

0
tDELAY t
tPULSE

For example one may want to generate a positive pulse on OC1 with a length of tPULSE and
after a delay of tDELAY as soon as a positive edge is detected on the TI2 input pin.
Let’s use TI2FP2 as trigger 1:
• Map TI2FP2 to TI2 by writing CC2S=’01’ in the TIMx_CCMR1 register.
• TI2FP2 must detect a rising edge, write CC2P=’0’ and CC2NP=’0’ in the TIMx_CCER
register.
• Configure TI2FP2 as trigger for the slave mode controller (TRGI) by writing TS=’110’ in
the TIMx_SMCR register.
• TI2FP2 is used to start the counter by writing SMS to ‘110’ in the TIMx_SMCR register
(trigger mode).

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The OPM waveform is defined by writing the compare registers (taking into account the
clock frequency and the counter prescaler).
• The tDELAY is defined by the value written in the TIMx_CCR1 register.
• The tPULSE is defined by the difference between the auto-reload value and the compare
value (TIMx_ARR - TIMx_CCR1+1).
• Let’s say one want to build a waveform with a transition from ‘0’ to ‘1’ when a compare
match occurs and a transition from ‘1’ to ‘0’ when the counter reaches the auto-reload
value. To do this PWM mode 2 must be enabled by writing OC1M=111 in the
TIMx_CCMR1 register. Optionally the preload registers can be enabled by writing
OC1PE=’1’ in the TIMx_CCMR1 register and ARPE in the TIMx_CR1 register. In this
case one has to write the compare value in the TIMx_CCR1 register, the auto-reload
value in the TIMx_ARR register, generate an update by setting the UG bit and wait for
external trigger event on TI2. CC1P is written to ‘0’ in this example.
In our example, the DIR and CMS bits in the TIMx_CR1 register should be low.
For code example refer to the Appendix section A.8.16: One-Pulse mode.
Since only 1 pulse (Single mode) is needed, a 1 must be written in the OPM bit in the
TIMx_CR1 register to stop the counter at the next update event (when the counter rolls over
from the auto-reload value back to 0). When OPM bit in the TIMx_CR1 register is set to '0',
so the Repetitive Mode is selected.

Particular case: OCx fast enable

In One-pulse mode, the edge detection on TIx input set the CEN bit which enables the
counter. Then the comparison between the counter and the compare value makes the
output toggle. But several clock cycles are needed for these operations and it limits the
minimum delay tDELAY min we can get.
If one wants to output a waveform with the minimum delay, the OCxFE bit can be set in the
TIMx_CCMRx register. Then OCxRef (and OCx) are forced in response to the stimulus,
without taking in account the comparison. Its new level is the same as if a compare match
had occurred. OCxFE acts only if the channel is configured in PWM1 or PWM2 mode.
For code example refer to the part of code, conditioned by PULSE_WITHOUT_DELAY > 0
in the Appendix section A.8.16: One-Pulse mode.

13.3.16 Encoder interface mode

To select Encoder Interface mode write SMS=‘001’ in the TIMx_SMCR register if the
counter is counting on TI2 edges only, SMS=’010’ if it is counting on TI1 edges only and
SMS=’011’ if it is counting on both TI1 and TI2 edges.
Select the TI1 and TI2 polarity by programming the CC1P and CC2P bits in the TIMx_CCER
register. When needed, the input filter can be programmed as well. CC1NP and CC2NP
must be kept low.
The two inputs TI1 and TI2 are used to interface to an incremental encoder. Refer to
Table 43. The counter is clocked by each valid transition on TI1FP1 or TI2FP2 (TI1 and TI2
after input filter and polarity selection, TI1FP1=TI1 if not filtered and not inverted,
TI2FP2=TI2 if not filtered and not inverted) assuming that it is enabled (CEN bit in
TIMx_CR1 register written to ‘1’). The sequence of transitions of the two inputs is evaluated
and generates count pulses as well as the direction signal. Depending on the sequence the
counter counts up or down, the DIR bit in the TIMx_CR1 register is modified by hardware

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accordingly. The DIR bit is calculated at each transition on any input (TI1 or TI2), whatever
the counter is counting on TI1 only, TI2 only or both TI1 and TI2.
Encoder interface mode acts simply as an external clock with direction selection. This
means that the counter just counts continuously between 0 and the auto-reload value in the
TIMx_ARR register (0 to ARR or ARR down to 0 depending on the direction). So the
TIMx_ARR must be configured before starting. In the same way, the capture, compare,
prescaler, repetition counter, trigger output features continue to work as normal. Encoder
mode and External clock mode 2 are not compatible and must not be selected together.
In this mode, the counter is modified automatically following the speed and the direction of
the incremental encoder and its content, therefore, always represents the encoder’s
position. The count direction correspond to the rotation direction of the connected sensor.
The table summarizes the possible combinations, assuming TI1 and TI2 do not switch at the
same time.

Table 43. Counting direction versus encoder signals

Level on TI1FP1 signal TI2FP2 signal
opposite
signal (TI1FP1
Active edge
for TI2,
Rising Falling Rising Falling
TI2FP2 for
TI1)

Counting on High Down Up No Count No Count

TI1 only Low Up Down No Count No Count

Counting on High No Count No Count Up Down

TI2 only Low No Count No Count Down Up

Counting on High Down Up Up Down

TI1 and TI2 Low Up Down Down Up

An external incremental encoder can be connected directly to the MCU without external
interface logic. However, comparators are normally be used to convert the encoder’s
differential outputs to digital signals. This greatly increases noise immunity. The third
encoder output which indicate the mechanical zero position, may be connected to an
external interrupt input and trigger a counter reset.
Figure 86 gives an example of counter operation, showing count signal generation and
direction control. It also shows how input jitter is compensated where both edges are
selected. This might occur if the sensor is positioned near to one of the switching points. For
this example we assume that the configuration is the following:
• CC1S=’01’ (TIMx_CCMR1 register, TI1FP1 mapped on TI1).
• CC2S=’01’ (TIMx_CCMR2 register, TI1FP2 mapped on TI2).
• CC1P=’0’ (TIMx_CCER register, TI1FP1 non-inverted, TI1FP1=TI1).
• CC2P=’0’ (TIMx_CCER register, TI1FP2 non-inverted, TI1FP2= TI2).
• SMS=’011’ (TIMx_SMCR register, both inputs are active on both rising and falling
edges).
• CEN=’1’ (TIMx_CR1 register, Counter enabled).
For code example refer to the Appendix section A.8.11: Encoder interface.

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Figure 86. Example of counter operation in encoder interface mode.

forward jitter backward jitter forward

TI1

TI2

Counter

up down up

MS33107V1

Figure 87 gives an example of counter behavior when TI1FP1 polarity is inverted (same
configuration as above except CC1P=’1’).

Figure 87. Example of encoder interface mode with TI1FP1 polarity inverted.

forward jitter backward jitter forward

TI1

TI2

Counter

down up down

MS33108V1

The timer, when configured in Encoder Interface mode provides information on the sensor’s
current position. Dynamic information can be obtained (speed, acceleration, deceleration)
by measuring the period between two encoder events using a second timer configured in
capture mode. The output of the encoder which indicates the mechanical zero can be used
for this purpose. Depending on the time between two events, the counter can also be read
at regular times. This can be done by latching the counter value into a third input capture
register if available (then the capture signal must be periodic and can be generated by
another timer). when available, it is also possible to read its value through a DMA request
generated by a real-time clock.

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13.3.17 Timer input XOR function

The TI1S bit in the TIMx_CR2 register, allows the input filter of channel 1 to be connected to
the output of a XOR gate, combining the three input pins TIMx_CH1, TIMx_CH2 and
TIMx_CH3.
The XOR output can be used with all the timer input functions such as trigger or input
capture. An example of this feature used to interface Hall sensors is given in
Section 13.3.18 below.

13.3.18 Interfacing with Hall sensors

This is done using the advanced-control timers (TIM1) to generate PWM signals to drive the
motor and another timer (TIM3) referred to as “interfacing timer” in Figure 88. The
“interfacing timer” captures the 3 timer input pins (CC1, CC2, CC3) connected through a
XOR to the TI1 input channel (selected by setting the TI1S bit in the TIMx_CR2 register).
The slave mode controller is configured in reset mode; the slave input is TI1F_ED. Thus,
each time one of the 3 inputs toggles, the counter restarts counting from 0. This creates a
time base triggered by any change on the Hall inputs.
On the “interfacing timer”, capture/compare channel 1 is configured in capture mode,
capture signal is TRC (See Figure 71: Capture/compare channel (example: channel 1 input
stage) on page 245). The captured value, which corresponds to the time elapsed between 2
changes on the inputs, gives information about motor speed.
The “interfacing timer” can be used in output mode to generate a pulse which changes the
configuration of the channels of the advanced-control timer (TIM1) (by triggering a COM
event). The TIM1 timer is used to generate PWM signals to drive the motor. To do this, the
interfacing timer channel must be programmed so that a positive pulse is generated after a
programmed delay (in output compare or PWM mode). This pulse is sent to the advanced-
control timer (TIM1) through the TRGO output.
Example: one wants to change the PWM configuration of the advanced-control timer TIM1
after a programmed delay each time a change occurs on the Hall inputs connected to one of
the TIMx timers.
• Configure 3 timer inputs XORed to the TI1 input channel by writing the TI1S bit in the
TIMx_CR2 register to ‘1’,
• Program the time base: write the TIMx_ARR to the max value (the counter must be
cleared by the TI1 change. Set the prescaler to get a maximum counter period longer
than the time between 2 changes on the sensors,
• Program channel 1 in capture mode (TRC selected): write the CC1S bits in the
TIMx_CCMR1 register to ‘01’. The digital filter can also be programmed if needed,
• Program channel 2 in PWM 2 mode with the desired delay: write the OC2M bits to ‘111’
and the CC2S bits to ‘00’ in the TIMx_CCMR1 register,
• Select OC2REF as trigger output on TRGO: write the MMS bits in the TIMx_CR2
register to ‘101’,
In the advanced-control timer TIM1, the right ITR input must be selected as trigger input, the
timer is programmed to generate PWM signals, the capture/compare control signals are
preloaded (CCPC=1 in the TIMx_CR2 register) and the COM event is controlled by the
trigger input (CCUS=1 in the TIMx_CR2 register). The PWM control bits (CCxE, OCxM) are
written after a COM event for the next step (this can be done in an interrupt subroutine
generated by the rising edge of OC2REF).

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Figure 88 describes this example.

Figure 88. Example of hall sensor interface

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13.3.19 TIMx and external trigger synchronization

The TIMx timer can be synchronized with an external trigger in several modes: Reset mode,
Gated mode and Trigger mode.

Slave mode: Reset mode

The counter and its prescaler can be reinitialized in response to an event on a trigger input.
Moreover, if the URS bit from the TIMx_CR1 register is low, an update event UEV is
generated. Then all the preloaded registers (TIMx_ARR, TIMx_CCRx) are updated.
In the following example, the upcounter is cleared in response to a rising edge on TI1 input:
• Configure the channel 1 to detect rising edges on TI1. Configure the input filter duration
(in this example, we do not need any filter, so we keep IC1F=0000). The capture
prescaler is not used for triggering, so it does not need to be configured. The CC1S bits
select the input capture source only, CC1S = 01 in the TIMx_CCMR1 register. Write
CC1P=0 and CC1NP=’0’ in TIMx_CCER register to validate the polarity (and detect
rising edges only).
• Configure the timer in reset mode by writing SMS=100 in TIMx_SMCR register. Select
TI1 as the input source by writing TS=101 in TIMx_SMCR register.
• Start the counter by writing CEN=1 in the TIMx_CR1 register.
For code example refer to the Appendix section A.8.12: Reset mode.
The counter starts counting on the internal clock, then behaves normally until TI1 rising
edge. When TI1 rises, the counter is cleared and restarts from 0. In the meantime, the
trigger flag is set (TIF bit in the TIMx_SR register) and an interrupt request, or a DMA
request can be sent if enabled (depending on the TIE and TDE bits in TIMx_DIER register).
The following figure shows this behavior when the auto-reload register TIMx_ARR=0x36.
The delay between the rising edge on TI1 and the actual reset of the counter is due to the
resynchronization circuit on TI1 input.

Figure 89. Control circuit in reset mode

TI1

UG

Counter clock = ck_cnt = ck_psc

Counter register 30 31 32 33 34 35 36 00 01 02 03 00 01 02 03

TIF

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Slave mode: Gated mode

The counter can be enabled depending on the level of a selected input.
In the following example, the upcounter counts only when TI1 input is low:
• Configure the channel 1 to detect low levels on TI1. Configure the input filter duration
(in this example, we do not need any filter, so we keep IC1F=0000). The capture
prescaler is not used for triggering, so it does not need to be configured. The CC1S bits
select the input capture source only, CC1S=01 in TIMx_CCMR1 register. Write
CC1P=1 and CC1NP=’0’ in TIMx_CCER register to validate the polarity (and detect
low level only).
• Configure the timer in gated mode by writing SMS=101 in TIMx_SMCR register. Select
TI1 as the input source by writing TS=101 in TIMx_SMCR register.
• Enable the counter by writing CEN=1 in the TIMx_CR1 register (in gated mode, the
counter doesn’t start if CEN=0, whatever is the trigger input level).
For code example refer to the Appendix section A.8.13: Gated mode.
The counter starts counting on the internal clock as long as TI1 is low and stops as soon as
TI1 becomes high. The TIF flag in the TIMx_SR register is set both when the counter starts
or stops.
The delay between the rising edge on TI1 and the actual stop of the counter is due to the
resynchronization circuit on TI1 input.

Figure 90. Control circuit in gated mode

TI1

cnt_en

Counter clock = ck_cnt = ck_psc

Counter register 30 31 32 33 34 35 36 37 38

TIF

Write TIF=0

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Slave mode: Trigger mode

The counter can start in response to an event on a selected input.
In the following example, the upcounter starts in response to a rising edge on TI2 input:
• Configure the channel 2 to detect rising edges on TI2. Configure the input filter duration
(in this example, we do not need any filter, so we keep IC2F=0000). The capture
prescaler is not used for triggering, so it does not need to be configured. The CC2S bits
are configured to select the input capture source only, CC2S=01 in TIMx_CCMR1
register. Write CC2P=1 and CC2NP=0 in TIMx_CCER register to validate the polarity
(and detect low level only).
• Configure the timer in trigger mode by writing SMS=110 in TIMx_SMCR register. Select
TI2 as the input source by writing TS=110 in TIMx_SMCR register.
For code example refer to the Appendix section A.8.14: Trigger mode.
When a rising edge occurs on TI2, the counter starts counting on the internal clock and the
TIF flag is set.
The delay between the rising edge on TI2 and the actual start of the counter is due to the
resynchronization circuit on TI2 input.

Figure 91. Control circuit in trigger mode

TI2

cnt_en

Counter clock = ck_cnt = ck_psc

Counter register 34 35 36 37 38

TIF

Slave mode: external clock mode 2 + trigger mode

The external clock mode 2 can be used in addition to another slave mode (except external
clock mode 1 and encoder mode). In this case, the ETR signal is used as external clock
input, and another input can be selected as trigger input (in reset mode, gated mode or
trigger mode). It is recommended not to select ETR as TRGI through the TS bits of
TIMx_SMCR register.
In the following example, the upcounter is incremented at each rising edge of the ETR
signal as soon as a rising edge of TI1 occurs:
1. Configure the external trigger input circuit by programming the TIMx_SMCR register as
follows:
– ETF = 0000: no filter
– ETPS=00: prescaler disabled
– ETP=0: detection of rising edges on ETR and ECE=1 to enable the external clock
mode 2.

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2. Configure the channel 1 as follows, to detect rising edges on TI:

– IC1F=0000: no filter.
– The capture prescaler is not used for triggering and does not need to be
configured.
– CC1S=01in TIMx_CCMR1 register to select only the input capture source
– CC1P=0 and CC1NP=’0’ in TIMx_CCER register to validate the polarity (and
detect rising edge only).
3. Configure the timer in trigger mode by writing SMS=110 in TIMx_SMCR register. Select
TI1 as the input source by writing TS=101 in TIMx_SMCR register.
For code example refer to the Appendix section A.8.15: External clock mode 2 + trigger
mode.
A rising edge on TI1 enables the counter and sets the TIF flag. The counter then counts on
ETR rising edges.
The delay between the rising edge of the ETR signal and the actual reset of the counter is
due to the resynchronization circuit on ETRP input.

Figure 92. Control circuit in external clock mode 2 + trigger mode

TI1

CEN/CNT_EN

ETR

Counter clock = CK_CNT = CK_PSC

Counter register 34 35 36

TIF

MS33110V1

13.3.20 Timer synchronization

The TIM timers are linked together internally for timer synchronization or chaining. Refer to
Section 14.3.15: Timer synchronization on page 336 for details.

13.3.21 Debug mode

When the microcontroller enters debug mode (Cortex™-M0 core halted), the TIMx counter
either continues to work normally or stops, depending on DBG_TIMx_STOP configuration
bit in DBG module.

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13.4 TIM1 registers

Refer to Section 1.2 on page 33 for a list of abbreviations used in register descriptions.

13.4.1 TIM1 control register 1 (TIM1_CR1)

Address offset: 0x00
Reset value: 0x0000

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. CKD[1:0] ARPE CMS[1:0] DIR OPM URS UDIS CEN
rw rw rw rw rw rw rw rw rw rw

Bits 15:10 Reserved, must be kept at reset value.

Bits 9:8 CKD[1:0]: Clock division
This bit-field indicates the division ratio between the timer clock (CK_INT) frequency and the
dead-time and sampling clock (tDTS)used by the dead-time generators and the digital filters
(ETR, TIx),
00: tDTS=tCK_INT
01: tDTS=2*tCK_INT
10: tDTS=4*tCK_INT
11: Reserved, do not program this value
Bit 7 ARPE: Auto-reload preload enable
0: TIMx_ARR register is not buffered
1: TIMx_ARR register is buffered
Bits 6:5 CMS[1:0]: Center-aligned mode selection
00: Edge-aligned mode. The counter counts up or down depending on the direction bit
(DIR).
01: Center-aligned mode 1. The counter counts up and down alternatively. Output compare
interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set
only when the counter is counting down.
10: Center-aligned mode 2. The counter counts up and down alternatively. Output compare
interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set
only when the counter is counting up.
11: Center-aligned mode 3. The counter counts up and down alternatively. Output compare
interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set
both when the counter is counting up or down.
Note: It is not allowed to switch from edge-aligned mode to center-aligned mode as long as
the counter is enabled (CEN=1).
Bit 4 DIR: Direction
0: Counter used as upcounter
1: Counter used as downcounter
Note: This bit is read only when the timer is configured in Center-aligned mode or Encoder
mode.
Bit 3 OPM: One pulse mode
0: Counter is not stopped at update event
1: Counter stops counting at the next update event (clearing the bit CEN)

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Bit 2 URS: Update request source

This bit is set and cleared by software to select the UEV event sources.
0: Any of the following events generate an update interrupt or DMA request if enabled.
These events can be:
– Counter overflow/underflow
– Setting the UG bit
– Update generation through the slave mode controller
1: Only counter overflow/underflow generates an update interrupt or DMA request if
enabled.
Bit 1 UDIS: Update disable
This bit is set and cleared by software to enable/disable UEV event generation.
0: UEV enabled. The Update (UEV) event is generated by one of the following events:
– Counter overflow/underflow
– Setting the UG bit
– Update generation through the slave mode controller
Buffered registers are then loaded with their preload values.
1: UEV disabled. The Update event is not generated, shadow registers keep their value
(ARR, PSC, CCRx). However the counter and the prescaler are reinitialized if the UG bit is
set or if a hardware reset is received from the slave mode controller.
Bit 0 CEN: Counter enable
0: Counter disabled
1: Counter enabled
Note: External clock, gated mode and encoder mode can work only if the CEN bit has been
previously set by software. However trigger mode can set the CEN bit automatically by
hardware.

13.4.2 TIM1 control register 2 (TIM1_CR2)

Address offset: 0x04
Reset value: 0x0000

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. OIS4 OIS3N OIS3 OIS2N OIS2 OIS1N OIS1 TI1S MMS[2:0] CCDS CCUS Res. CCPC
rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bit 15 Reserved, must be kept at reset value.

Bit 14 OIS4: Output Idle state 4 (OC4 output)
refer to OIS1 bit
Bit 13 OIS3N: Output Idle state 3 (OC3N output)
refer to OIS1N bit
Bit 12 OIS3: Output Idle state 3 (OC3 output)
refer to OIS1 bit
Bit 11 OIS2N: Output Idle state 2 (OC2N output)
refer to OIS1N bit
Bit 10 OIS2: Output Idle state 2 (OC2 output)
refer to OIS1 bit

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Bit 9 OIS1N: Output Idle state 1 (OC1N output)

0: OC1N=0 after a dead-time when MOE=0
1: OC1N=1 after a dead-time when MOE=0
Note: This bit cannot be modified as long as LOCK level 1, 2 or 3 has been programmed
(LOCK bits in TIMx_BDTR register).
Bit 8 OIS1: Output Idle state 1 (OC1 output)
0: OC1=0 (after a dead-time if OC1N is implemented) when MOE=0
1: OC1=1 (after a dead-time if OC1N is implemented) when MOE=0
Note: This bit cannot be modified as long as LOCK level 1, 2 or 3 has been programmed
(LOCK bits in TIMx_BDTR register).
Bit 7 TI1S: TI1 selection
0: The TIMx_CH1 pin is connected to TI1 input
1: The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination)
Bits 6:4 MMS[2:0]: Master mode selection
These bits allow to select the information to be sent in master mode to slave timers for
synchronization (TRGO). The combination is as follows:
000: Reset - the UG bit from the TIMx_EGR register is used as trigger output (TRGO). If the
reset is generated by the trigger input (slave mode controller configured in reset mode) then
the signal on TRGO is delayed compared to the actual reset.
001: Enable - the Counter Enable signal CNT_EN is used as trigger output (TRGO). It is
useful to start several timers at the same time or to control a window in which a slave timer is
enable. The Counter Enable signal is generated by a logic OR between CEN control bit and
the trigger input when configured in gated mode. When the Counter Enable signal is
controlled by the trigger input, there is a delay on TRGO, except if the master/slave mode is
selected (see the MSM bit description in TIMx_SMCR register).
010: Update - The update event is selected as trigger output (TRGO). For instance a master
timer can then be used as a prescaler for a slave timer.
011: Compare Pulse - The trigger output send a positive pulse when the CC1IF flag is to be
set (even if it was already high), as soon as a capture or a compare match occurred.
(TRGO).
100: Compare - OC1REF signal is used as trigger output (TRGO)
101: Compare - OC2REF signal is used as trigger output (TRGO)
110: Compare - OC3REF signal is used as trigger output (TRGO)
111: Compare - OC4REF signal is used as trigger output (TRGO)
Bit 3 CCDS: Capture/compare DMA selection
0: CCx DMA request sent when CCx event occurs
1: CCx DMA requests sent when update event occurs
Bit 2 CCUS: Capture/compare control update selection
0: When capture/compare control bits are preloaded (CCPC=1), they are updated by setting
the COMG bit only
1: When capture/compare control bits are preloaded (CCPC=1), they are updated by setting
the COMG bit or when an rising edge occurs on TRGI
Note: This bit acts only on channels that have a complementary output.
Bit 1 Reserved, must be kept at reset value.
Bit 0 CCPC: Capture/compare preloaded control
0: CCxE, CCxNE and OCxM bits are not preloaded
1: CCxE, CCxNE and OCxM bits are preloaded, after having been written, they are updated
only when a communication event (COM) occurs (COMG bit set or rising edge detected on
TRGI, depending on the CCUS bit).
Note: This bit acts only on channels that have a complementary output.

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13.4.3 TIM1 slave mode control register (TIM1_SMCR)

Address offset: 0x08
Reset value: 0x0000

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETP ECE ETPS[1:0] ETF[3:0] MSM TS[2:0] OCCS SMS[2:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bit 15 ETP: External trigger polarity

This bit selects whether ETR or ETR is used for trigger operations
0: ETR is non-inverted, active at high level or rising edge.
1: ETR is inverted, active at low level or falling edge.
Bit 14 ECE: External clock enable
This bit enables External clock mode 2.
0: External clock mode 2 disabled
1: External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF
signal.
Note: 1: Setting the ECE bit has the same effect as selecting external clock mode 1 with
TRGI connected to ETRF (SMS=111 and TS=111).
2: It is possible to simultaneously use external clock mode 2 with the following slave
modes: reset mode, gated mode and trigger mode. Nevertheless, TRGI must not be
connected to ETRF in this case (TS bits must not be 111).
3: If external clock mode 1 and external clock mode 2 are enabled at the same time,
the external clock input is ETRF.
Bits 13:12 ETPS[1:0]: External trigger prescaler
External trigger signal ETRP frequency must be at most 1/4 of TIMxCLK frequency. A
prescaler can be enabled to reduce ETRP frequency. It is useful when inputting fast external
clocks.
00: Prescaler OFF
01: ETRP frequency divided by 2
10: ETRP frequency divided by 4
11: ETRP frequency divided by 8

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Bits 11:8 ETF[3:0]: External trigger filter

This bit-field then defines the frequency used to sample ETRP signal and the length of the
digital filter applied to ETRP. The digital filter is made of an event counter in which N
consecutive events are needed to validate a transition on the output:
0000: No filter, sampling is done at fDTS
0001: fSAMPLING = fCK_INT, N = 2
0010: fSAMPLING = fCK_INT, N = 4
0011: fSAMPLING = fCK_INT, N = 8
0100: fSAMPLING = fDTS / 2, N = 6
0101: fSAMPLING = fDTS / 2, N = 8
0110: fSAMPLING = fDTS / 4, N = 6
0111: fSAMPLING = fDTS / 4, N = 8
1000: fSAMPLING = fDTS / 8, N = 6
1001: fSAMPLING = fDTS / 8, N = 8
1010: fSAMPLING = fDTS / 16, N = 5
1011: fSAMPLING = fDTS / 16, N = 6
1100: fSAMPLING = fDTS / 16, N = 8
1101: fSAMPLING = fDTS / 32, N = 5
1110: fSAMPLING = fDTS / 32, N = 6
1111: fSAMPLING = fDTS / 32, N = 8
Note: Care must be taken that fDTS is replaced in the formula by CK_INT when ETF[3:0] = 1,
2 or 3.
Bit 7 MSM: Master/slave mode
0: No action
1: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect
synchronization between the current timer and its slaves (through TRGO). It is useful if we
want to synchronize several timers on a single external event.

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Bits 6:4 TS[2:0]: Trigger selection

This bit-field selects the trigger input to be used to synchronize the counter.
000: Internal Trigger 0 (ITR0)
001: Reserved
010: Internal Trigger 2 (ITR2)
011: Internal Trigger 3 (ITR3)
100: TI1 Edge Detector (TI1F_ED)
101: Filtered Timer Input 1 (TI1FP1)
110: Filtered Timer Input 2 (TI2FP2)
111: External Trigger input (ETRF)
See Table 44: TIMx Internal trigger connection for more details on ITRx meaning for each
Timer.
Note: These bits must be changed only when they are not used (e.g. when SMS=000) to
avoid wrong edge detections at the transition.
Bit 3 OCCS: OCREF clear selection.
This bit is used to select the OCREF clear source.
0:OCREF_CLR_INT is connected to the OCREF_CLR input
1: OCREF_CLR_INT is connected to ETRF
Bits 2:0 SMS[2:0]: Slave mode selection
When external signals are selected the active edge of the trigger signal (TRGI) is linked to the
polarity selected on the external input (see Input Control register and Control Register
description.
000: Slave mode disabled - if CEN = ‘1’ then the prescaler is clocked directly by the internal
clock.
001: Encoder mode 1 - Counter counts up/down on TI1FP1 edge depending on TI2FP2
level.
010: Encoder mode 2 - Counter counts up/down on TI2FP2 edge depending on TI1FP1
level.
011: Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges
depending on the level of the other input.
100: Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter
and generates an update of the registers.
101: Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The
counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of
the counter are controlled.
110: Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not
reset). Only the start of the counter is controlled.
111: External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter.
Note: The gated mode must not be used if TI1F_ED is selected as the trigger input
(TS=’100’). Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the
gated mode checks the level of the trigger signal.
Note: The clock of the slave timer must be enabled prior to receive events from the master
timer, and must not be changed on-the-fly while triggers are received from the master
timer.

Table 44. TIMx Internal trigger connection

Slave TIM ITR0 (TS = 000) ITR2 (TS = 010) ITR3 (TS = 011)

TIM1 TIM15 TIM3 TIM17

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13.4.4 TIM1 DMA/interrupt enable register (TIM1_DIER)

Address offset: 0x0C
Reset value: 0x0000

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COM
Res. TDE CC4DE CC3DE CC2DE CC1DE UDE BIE TIE COMIE CC4IE CC3IE CC2IE CC1IE UIE
DE
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bit 15 Reserved, must be kept at reset value.

Bit 14 TDE: Trigger DMA request enable
0: Trigger DMA request disabled
1: Trigger DMA request enabled
Bit 13 COMDE: COM DMA request enable
0: COM DMA request disabled
1: COM DMA request enabled
Bit 12 CC4DE: Capture/Compare 4 DMA request enable
0: CC4 DMA request disabled
1: CC4 DMA request enabled
Bit 11 CC3DE: Capture/Compare 3 DMA request enable
0: CC3 DMA request disabled
1: CC3 DMA request enabled
Bit 10 CC2DE: Capture/Compare 2 DMA request enable
0: CC2 DMA request disabled
1: CC2 DMA request enabled
Bit 9 CC1DE: Capture/Compare 1 DMA request enable
0: CC1 DMA request disabled
1: CC1 DMA request enabled
Bit 8 UDE: Update DMA request enable
0: Update DMA request disabled
1: Update DMA request enabled
Bit 7 BIE: Break interrupt enable
0: Break interrupt disabled
1: Break interrupt enabled
Bit 6 TIE: Trigger interrupt enable
0: Trigger interrupt disabled
1: Trigger interrupt enabled
Bit 5 COMIE: COM interrupt enable
0: COM interrupt disabled
1: COM interrupt enabled
Bit 4 CC4IE: Capture/Compare 4 interrupt enable
0: CC4 interrupt disabled
1: CC4 interrupt enabled

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Bit 3 CC3IE: Capture/Compare 3 interrupt enable

0: CC3 interrupt disabled
1: CC3 interrupt enabled
Bit 2 CC2IE: Capture/Compare 2 interrupt enable
0: CC2 interrupt disabled
1: CC2 interrupt enabled
Bit 1 CC1IE: Capture/Compare 1 interrupt enable
0: CC1 interrupt disabled
1: CC1 interrupt enabled
Bit 0 UIE: Update interrupt enable
0: Update interrupt disabled
1: Update interrupt enabled

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13.4.5 TIM1 status register (TIM1_SR)

Address offset: 0x10
Reset value: 0x0000

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. CC4OF CC3OF CC2OF CC1OF Res. BIF TIF COMIF CC4IF CC3IF CC2IF CC1IF UIF
rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0

Bits 15:13 Reserved, must be kept at reset value.

Bit 12 CC4OF: Capture/Compare 4 overcapture flag
refer to CC1OF description
Bit 11 CC3OF: Capture/Compare 3 overcapture flag
refer to CC1OF description
Bit 10 CC2OF: Capture/Compare 2 overcapture flag
refer to CC1OF description
Bit 9 CC1OF: Capture/Compare 1 overcapture flag
This flag is set by hardware only when the corresponding channel is configured in input
capture mode. It is cleared by software by writing it to ‘0’.
0: No overcapture has been detected.
1: The counter value has been captured in TIMx_CCR1 register while CC1IF flag was
already set
Bit 8 Reserved, must be kept at reset value.
Bit 7 BIF: Break interrupt flag
This flag is set by hardware as soon as the break input goes active. It can be cleared by
software if the break input is not active.
0: No break event occurred.
1: An active level has been detected on the break input.
Bit 6 TIF: Trigger interrupt flag
This flag is set by hardware on trigger event (active edge detected on TRGI input when the
slave mode controller is enabled in all modes but gated mode.It is cleared by software.
0: No trigger event occurred.
1: Trigger interrupt pending.
Bit 5 COMIF: COM interrupt flag
This flag is set by hardware on COM event (when Capture/compare Control bits - CCxE,
CCxNE, OCxM - have been updated). It is cleared by software by writing it to ‘0’.
0: No COM event occurred.
1: COM interrupt pending.
Bit 4 CC4IF: Capture/Compare 4 interrupt flag
refer to CC1IF description
Bit 3 CC3IF: Capture/Compare 3 interrupt flag
refer to CC1IF description

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Bit 2 CC2IF: Capture/Compare 2 interrupt flag

refer to CC1IF description
Bit 1 CC1IF: Capture/Compare 1 interrupt flag
If channel CC1 is configured as output:
This flag is set by hardware when the counter matches the compare value, with some
exception in center-aligned mode (refer to the CMS bits in the TIMx_CR1 register description).
It is cleared by software.
0: No match.
1: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register.
When the contents of TIMx_CCR1 are greater than the contents of TIMx_ARR, the CC1IF
bit goes high on the counter overflow (in upcounting and up/down-counting modes) or
underflow (in downcounting mode)
If channel CC1 is configured as input:
This bit is set by hardware on a capture. It is cleared by software or by reading the
TIMx_CCR1 register.
0: No input capture occurred
1: The counter value has been captured in TIMx_CCR1 register (An edge has been
detected on IC1 which matches the selected polarity)
Bit 0 UIF: Update interrupt flag
This bit is set by hardware on an update event. It is cleared by software.
0: No update occurred.
1: Update interrupt pending. This bit is set by hardware when the registers are updated:
– At overflow or underflow regarding the repetition counter value (update if repetition
counter = 0) and if the UDIS=0 in the TIMx_CR1 register.
– When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=0
and UDIS=0 in the TIMx_CR1 register.
– When CNT is reinitialized by a trigger event (refer to Section 13.4.3: TIM1 slave mode
control register (TIM1_SMCR)), if URS=0 and UDIS=0 in the TIMx_CR1 register.

13.4.6 TIM1 event generation register (TIM1_EGR)

Address offset: 0x14
Reset value: 0x0000

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. BG TG COMG CC4G CC3G CC2G CC1G UG
w w w w w w w w

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Bits 15:8 Reserved, must be kept at reset value.

Bit 7 BG: Break generation
This bit is set by software in order to generate an event, it is automatically cleared by
hardware.
0: No action
1: A break event is generated. MOE bit is cleared and BIF flag is set. Related interrupt or
DMA transfer can occur if enabled.
Bit 6 TG: Trigger generation
This bit is set by software in order to generate an event, it is automatically cleared by
hardware.
0: No action
1: The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if
enabled.
Bit 5 COMG: Capture/Compare control update generation
This bit can be set by software, it is automatically cleared by hardware
0: No action
1: When CCPC bit is set, it allows to update CCxE, CCxNE and OCxM bits
Note: This bit acts only on channels having a complementary output.
Bit 4 CC4G: Capture/Compare 4 generation
Refer to CC1G description
Bit 3 CC3G: Capture/Compare 3 generation
Refer to CC1G description
Bit 2 CC2G: Capture/Compare 2 generation
Refer to CC1G description
Bit 1 CC1G: Capture/Compare 1 generation
This bit is set by software in order to generate an event, it is automatically cleared by
hardware.
0: No action
1: A capture/compare event is generated on channel 1:
If channel CC1 is configured as output:
CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled.
If channel CC1 is configured as input:
The current value of the counter is captured in TIMx_CCR1 register. The CC1IF flag is set, the
corresponding interrupt or DMA request is sent if enabled. The CC1OF flag is set if the CC1IF
flag was already high.
Bit 0 UG: Update generation
This bit can be set by software, it is automatically cleared by hardware.
0: No action
1: Reinitialize the counter and generates an update of the registers. Note that the prescaler
counter is cleared too (anyway the prescaler ratio is not affected). The counter is cleared if
the center-aligned mode is selected or if DIR=0 (upcounting), else it takes the auto-reload
value (TIMx_ARR) if DIR=1 (downcounting).

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13.4.7 TIM1 capture/compare mode register 1 (TIM1_CCMR1)

Address offset: 0x18
Reset value: 0x0000
The channels can be used in input (capture mode) or in output (compare mode). The
direction of a channel is defined by configuring the corresponding CCxS bits. All the other
bits of this register have a different function in input and in output mode. For a given bit,
OCxx describes its function when the channel is configured in output, ICxx describes its
function when the channel is configured in input. So one must take care that the same bit
can have a different meaning for the input stage and for the output stage.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OC2 OC2 OC2 OC1 OC1 OC1
OC2M[2:0] OC1M[2:0]
CE PE FE CC2S[1:0] CE PE FE CC1S[1:0]
IC2F[3:0] IC2PSC[1:0] IC1F[3:0] IC1PSC[1:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Output compare mode

Bit 15 OC2CE: Output Compare 2 clear enable

Bits 14:12 OC2M[2:0]: Output Compare 2 mode
Bit 11 OC2PE: Output Compare 2 preload enable
Bit 10 OC2FE: Output Compare 2 fast enable
Bits 9:8 CC2S[1:0]: Capture/Compare 2 selection
This bit-field defines the direction of the channel (input/output) as well as the used input.
00: CC2 channel is configured as output
01: CC2 channel is configured as input, IC2 is mapped on TI2
10: CC2 channel is configured as input, IC2 is mapped on TI1
11: CC2 channel is configured as input, IC2 is mapped on TRC. This mode is working only if
an internal trigger input is selected through the TS bit (TIMx_SMCR register)
Note: CC2S bits are writable only when the channel is OFF (CC2E = ‘0’ in TIMx_CCER).
Bit 7 OC1CE: Output Compare 1 clear enable
OC1CE: Output Compare 1 Clear Enable
0: OC1Ref is not affected by the ETRF Input
1: OC1Ref is cleared as soon as a High level is detected on ETRF input

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Bits 6:4 OC1M: Output Compare 1 mode

These bits define the behavior of the output reference signal OC1REF from which OC1 and
OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends on
CC1P and CC1NP bits.
000: Frozen - The comparison between the output compare register TIMx_CCR1 and the
counter TIMx_CNT has no effect on the outputs (this mode is used to generate a timing
base).
001: Set channel 1 to active level on match. OC1REF signal is forced high when the counter
TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1).
010: Set channel 1 to inactive level on match. OC1REF signal is forced low when the
counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1).
011: Toggle - OC1REF toggles when TIMx_CNT=TIMx_CCR1.
100: Force inactive level - OC1REF is forced low.
101: Force active level - OC1REF is forced high.
110: PWM mode 1 - In upcounting, channel 1 is active as long as TIMx_CNT<TIMx_CCR1
else inactive. In downcounting, channel 1 is inactive (OC1REF=‘0’) as long as
TIMx_CNT>TIMx_CCR1 else active (OC1REF=’1’).
111: PWM mode 2 - In upcounting, channel 1 is inactive as long as TIMx_CNT<TIMx_CCR1
else active. In downcounting, channel 1 is active as long as TIMx_CNT>TIMx_CCR1 else
inactive.
Note: 1: These bits can not be modified as long as LOCK level 3 has been programmed
(LOCK bits in TIMx_BDTR register) and CC1S=’00’ (the channel is configured in
output).
2: In PWM mode 1 or 2, the OCREF level changes only when the result of the
comparison changes or when the output compare mode switches from “frozen” mode
to “PWM” mode.
3: On channels having a complementary output, this bit field is preloaded. If the CCPC
bit is set in the TIMx_CR2 register then the OC1M active bits take the new value from
the preloaded bits only when a COM event is generated.

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Bit 3 OC1PE: Output Compare 1 preload enable

0: Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the
new value is taken in account immediately.
1: Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload
register. TIMx_CCR1 preload value is loaded in the active register at each update event.
Note: These bits can not be modified as long as LOCK level 3 has been programmed (LOCK
bits in TIMx_BDTR register) and CC1S=’00’ (the channel is configured in output).
Bit 2 OC1FE: Output Compare 1 fast enable
This bit is used to accelerate the effect of an event on the trigger in input on the CC output.
0: CC1 behaves normally depending on counter and CCR1 values even when the trigger is
ON. The minimum delay to activate CC1 output when an edge occurs on the trigger input is
5 clock cycles.
1: An active edge on the trigger input acts like a compare match on CC1 output. Then, OC is
set to the compare level independently from the result of the comparison. Delay to sample
the trigger input and to activate CC1 output is reduced to 3 clock cycles. OCFE acts only if
the channel is configured in PWM1 or PWM2 mode.
Bits 1:0 CC1S: Capture/Compare 1 selection
This bit-field defines the direction of the channel (input/output) as well as the used input.
00: CC1 channel is configured as output
01: CC1 channel is configured as input, IC1 is mapped on TI1
10: CC1 channel is configured as input, IC1 is mapped on TI2
11: CC1 channel is configured as input, IC1 is mapped on TRC. This mode is working only if
an internal trigger input is selected through TS bit (TIMx_SMCR register)
Note: CC1S bits are writable only when the channel is OFF (CC1E = ‘0’ in TIMx_CCER).

Input capture mode

Bits 15:12 IC2F: Input capture 2 filter

Bits 11:10 IC2PSC[1:0]: Input capture 2 prescaler
Bits 9:8 CC2S: Capture/Compare 2 selection
This bit-field defines the direction of the channel (input/output) as well as the used input.
00: CC2 channel is configured as output
01: CC2 channel is configured as input, IC2 is mapped on TI2
10: CC2 channel is configured as input, IC2 is mapped on TI1
11: CC2 channel is configured as input, IC2 is mapped on TRC. This mode is working only if an
internal trigger input is selected through TS bit (TIMx_SMCR register)
Note: CC2S bits are writable only when the channel is OFF (CC2E = ‘0’ in TIMx_CCER).

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Bits 7:4 IC1F[3:0]: Input capture 1 filter

This bit-field defines the frequency used to sample TI1 input and the length of the digital filter applied to
TI1. The digital filter is made of an event counter in which N consecutive events are needed to validate
a transition on the output:
0000: No filter, sampling is done at fDTS
0001: fSAMPLING = fCK_INT, N = 2
0010: fSAMPLING = fCK_INT, N = 4
0011: fSAMPLING = fCK_INT, N = 8
0100: fSAMPLING = fDTS / 2, N = 6
0101: fSAMPLING = fDTS / 2, N = 8
0110: fSAMPLING = fDTS / 4, N = 6
0111: fSAMPLING = fDTS / 4, N = 8
1000: fSAMPLING = fDTS / 8, N = 6
1001: fSAMPLING = fDTS / 8, N = 8
1010: fSAMPLING = fDTS / 16, N = 5
1011: fSAMPLING = fDTS / 16, N = 6
1100: fSAMPLING = fDTS / 16, N = 8
1101: fSAMPLING = fDTS / 32, N = 5
1110: fSAMPLING = fDTS / 32, N = 6
1111: fSAMPLING = fDTS / 32, N = 8
Note: Care must be taken that fDTS is replaced in the formula by CK_INT when ICxF[3:0] = 1, 2 or 3.
Bits 3:2 IC1PSC: Input capture 1 prescaler
This bit-field defines the ratio of the prescaler acting on CC1 input (IC1).
The prescaler is reset as soon as CC1E=’0’ (TIMx_CCER register).
00: no prescaler, capture is done each time an edge is detected on the capture input
01: capture is done once every 2 events
10: capture is done once every 4 events
11: capture is done once every 8 events
Bits 1:0 CC1S: Capture/Compare 1 Selection
This bit-field defines the direction of the channel (input/output) as well as the used input.
00: CC1 channel is configured as output
01: CC1 channel is configured as input, IC1 is mapped on TI1
10: CC1 channel is configured as input, IC1 is mapped on TI2
11: CC1 channel is configured as input, IC1 is mapped on TRC. This mode is working only if an
internal trigger input is selected through TS bit (TIMx_SMCR register)
Note: CC1S bits are writable only when the channel is OFF (CC1E = ‘0’ in TIMx_CCER).

13.4.8 TIM1 capture/compare mode register 2 (TIM1_CCMR2)

Address offset: 0x1C
Reset value: 0x0000
Refer to the above CCMR1 register description.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OC4 OC4 OC4 OC3 OC3 OC3
OC4M[2:0] OC3M[2:0]
CE PE FE CC4S[1:0] CE. PE FE CC3S[1:0]
IC4F[3:0] IC4PSC[1:0] IC3F[3:0] IC3PSC[1:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

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Output compare mode

Bit 15 OC4CE: Output compare 4 clear enable

Bits 14:12 OC4M: Output compare 4 mode
Bit 11 OC4PE: Output compare 4 preload enable
Bit 10 OC4FE: Output compare 4 fast enable
Bits 9:8 CC4S: Capture/Compare 4 selection
This bit-field defines the direction of the channel (input/output) as well as the used input.
00: CC4 channel is configured as output
01: CC4 channel is configured as input, IC4 is mapped on TI4
10: CC4 channel is configured as input, IC4 is mapped on TI3
11: CC4 channel is configured as input, IC4 is mapped on TRC. This mode is working only if
an internal trigger input is selected through TS bit (TIMx_SMCR register)
Note: CC4S bits are writable only when the channel is OFF (CC4E = ‘0’ in TIMx_CCER).
Bit 7 OC3CE: Output compare 3 clear enable
Bits 6:4 OC3M: Output compare 3 mode
Bit 3 OC3PE: Output compare 3 preload enable
Bit 2 OC3FE: Output compare 3 fast enable
Bits 1:0 CC3S: Capture/Compare 3 selection
This bit-field defines the direction of the channel (input/output) as well as the used input.
00: CC3 channel is configured as output
01: CC3 channel is configured as input, IC3 is mapped on TI3
10: CC3 channel is configured as input, IC3 is mapped on TI4
11: CC3 channel is configured as input, IC3 is mapped on TRC. This mode is working only if
an internal trigger input is selected through TS bit (TIMx_SMCR register)
Note: CC3S bits are writable only when the channel is OFF (CC3E = ‘0’ in TIMx_CCER).

Input capture mode

Bits 15:12 IC4F: Input capture 4 filter

Bits 11:10 IC4PSC: Input capture 4 prescaler
Bits 9:8 CC4S: Capture/Compare 4 selection
This bit-field defines the direction of the channel (input/output) as well as the used input.
00: CC4 channel is configured as output
01: CC4 channel is configured as input, IC4 is mapped on TI4
10: CC4 channel is configured as input, IC4 is mapped on TI3
11: CC4 channel is configured as input, IC4 is mapped on TRC. This mode is working only if
an internal trigger input is selected through TS bit (TIMx_SMCR register)
Note: CC4S bits are writable only when the channel is OFF (CC4E = ‘0’ in TIMx_CCER).

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Bits 7:4 IC3F: Input capture 3 filter

Bits 3:2 IC3PSC: Input capture 3 prescaler
Bits 1:0 CC3S: Capture/compare 3 selection
This bit-field defines the direction of the channel (input/output) as well as the used input.
00: CC3 channel is configured as output
01: CC3 channel is configured as input, IC3 is mapped on TI3
10: CC3 channel is configured as input, IC3 is mapped on TI4
11: CC3 channel is configured as input, IC3 is mapped on TRC. This mode is working only if
an internal trigger input is selected through TS bit (TIMx_SMCR register)
Note: CC3S bits are writable only when the channel is OFF (CC3E = ‘0’ in TIMx_CCER).

13.4.9 TIM1 capture/compare enable register (TIM1_CCER)

Address offset: 0x20
Reset value: 0x0000

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. CC4P CC4E CC3NP CC3NE CC3P CC3E CC2NP CC2NE CC2P CC2E CC1NP CC1NE CC1P CC1E
rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 15:14 Reserved, must be kept at reset value.

Bit 13 CC4P: Capture/Compare 4 output polarity
refer to CC1P description
Bit 12 CC4E: Capture/Compare 4 output enable
refer to CC1E description
Bit 11 CC3NP: Capture/Compare 3 complementary output polarity
refer to CC1NP description
Bit 10 CC3NE: Capture/Compare 3 complementary output enable
refer to CC1NE description
Bit 9 CC3P: Capture/Compare 3 output polarity
refer to CC1P description
Bit 8 CC3E: Capture/Compare 3 output enable
refer to CC1E description
Bit 7 CC2NP: Capture/Compare 2 complementary output polarity
refer to CC1NP description
Bit 6 CC2NE: Capture/Compare 2 complementary output enable
refer to CC1NE description
Bit 5 CC2P: Capture/Compare 2 output polarity
refer to CC1P description
Bit 4 CC2E: Capture/Compare 2 output enable
refer to CC1E description

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RM0360 Advanced-control timers (TIM1)

Bit 3 CC1NP: Capture/Compare 1 complementary output polarity

CC1 channel configuration as output:
0: OC1N active high.
1: OC1N active low.
CC1 channel configuration as input:
This bit is used in conjunction with CC1P to define the polarity of TI1FP1 and TI2FP1. Refer to
CC1P description.
Note: On channels having a complementary output, this bit is preloaded. If the CCPC bit is
set in the TIMx_CR2 register then the CC1NP active bit takes the new value from the
preloaded bits only when a Commutation event is generated.
Note: This bit is not writable as soon as LOCK level 2 or 3 has been programmed (LOCK bits
in TIMx_BDTR register) and CC1S=”00” (the channel is configured in output).
Bit 2 CC1NE: Capture/Compare 1 complementary output enable
0: Off - OC1N is not active. OC1N level is then function of MOE, OSSI, OSSR, OIS1, OIS1N
and CC1E bits.
1: On - OC1N signal is output on the corresponding output pin depending on MOE, OSSI,
OSSR, OIS1, OIS1N and CC1E bits.
Note: On channels having a complementary output, this bit is preloaded. If the CCPC bit is
set in the TIMx_CR2 register then the CC1NE active bit takes the new value from the
preloaded bits only when a Commutation event is generated.
Bit 1 CC1P: Capture/Compare 1 output polarity
CC1 channel configured as output:
0: OC1 active high
1: OC1 active low
CC1 channel configured as input:
CC1NP/CC1P bits select the active polarity of TI1FP1 and TI2FP1 for trigger or capture
operations.
00: non-inverted/rising edge
The circuit is sensitive to TIxFP1 rising edge (capture or trigger operations in reset, external
clock or trigger mode), TIxFP1 is not inverted (trigger operation in gated mode or encoder
mode).
01: inverted/falling edge
The circuit is sensitive to TIxFP1 falling edge (capture or trigger operations in reset, external
clock or trigger mode), TIxFP1 is inverted (trigger operation in gated mode or encoder
mode).
10: reserved, do not use this configuration.
11: non-inverted/both edges
The circuit is sensitive to both TIxFP1 rising and falling edges (capture or trigger operations
in reset, external clock or trigger mode), TIxFP1 is not inverted (trigger operation in gated
mode). This configuration must not be used in encoder mode.
Note: On channels having a complementary output, this bit is preloaded. If the CCPC bit is
set in the TIMx_CR2 register then the CC1P active bit takes the new value from the
preloaded bits only when a Commutation event is generated.
Note: This bit is not writable as soon as LOCK level 2 or 3 has been programmed (LOCK bits
in TIMx_BDTR register).

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Advanced-control timers (TIM1) RM0360

Bit 0 CC1E: Capture/Compare 1 output enable

CC1 channel configured as output:
0: Off - OC1 is not active. OC1 level is then function of MOE, OSSI, OSSR, OIS1, OIS1N
and CC1NE bits.
1: On - OC1 signal is output on the corresponding output pin depending on MOE, OSSI,
OSSR, OIS1, OIS1N and CC1NE bits.
CC1 channel configured as input:
This bit determines if a capture of the counter value can actually be done into the input
capture/compare register 1 (TIMx_CCR1) or not.
0: Capture disabled.
1: Capture enabled.
Note: On channels having a complementary output, this bit is preloaded. If the CCPC bit is
set in the TIMx_CR2 register then the CC1E active bit takes the new value from the
preloaded bits only when a Commutation event is generated.

Table 45. Output control bits for complementary OCx and OCxN channels with
break feature
Control bits Output states(1)
MOE OSSI OSSR CCxE CCxNE
OCx output state OCxN output state
bit bit bit bit bit
Output Disabled (not driven by Output Disabled (not driven by the
0 0 0 the timer) timer)
OCx=0, OCx_EN=0 OCxN=0, OCxN_EN=0
Output Disabled (not driven by
OCxREF + Polarity OCxN=OCxREF
0 0 1 the timer)
xor CCxNP, OCxN_EN=1
OCx=0, OCx_EN=0
OCxREF + Polarity Output Disabled (not driven by the
0 1 0 OCx=OCxREF xor CCxP, timer)
OCx_EN=1 OCxN=0, OCxN_EN=0
Complementary to OCREF (not
OCREF + Polarity + dead-time
0 1 1 OCREF) + Polarity + dead-time
OCx_EN=1
OCxN_EN=1
1 X
Output Disabled (not driven by Output Disabled (not driven by the
1 0 0 the timer) timer)
OCx=CCxP, OCx_EN=0 OCxN=CCxNP, OCxN_EN=0
Off-State (output enabled with OCxREF + Polarity
1 0 1 inactive state) OCxN=OCxREF xor CCxNP,
OCx=CCxP, OCx_EN=1 OCxN_EN=1
OCxREF + Polarity Off-State (output enabled with
1 1 0 OCx=OCxREF xor CCxP, inactive state)
OCx_EN=1 OCxN=CCxNP, OCxN_EN=1
Complementary to OCREF (not
OCREF + Polarity + dead-time
1 1 1 OCREF) + Polarity + dead-time
OCx_EN=1
OCxN_EN=1

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RM0360 Advanced-control timers (TIM1)

Table 45. Output control bits for complementary OCx and OCxN channels with
break feature (continued)
Control bits Output states(1)
MOE OSSI OSSR CCxE CCxNE
OCx output state OCxN output state
bit bit bit bit bit

Output Disabled (not driven by Output Disabled (not driven by the

0 0 0 the timer) timer)
OCx=CCxP, OCx_EN=0 OCxN=CCxNP, OCxN_EN=0
0 0 1 Output Disabled (not driven by the timer)
0 1 0 Asynchronously: OCx=CCxP, OCx_EN=0, OCxN=CCxNP,
OCxN_EN=0
Then if the clock is present: OCx=OISx and OCxN=OISxN after a
0 1 1 dead-time, assuming that OISx and OISxN do not correspond to OCX
and OCxN both in active state.
0 X
Output Disabled (not driven by Output Disabled (not driven by the
1 0 0 the timer) timer)
OCx=CCxP, OCx_EN=0 OCxN=CCxNP, OCxN_EN=0
1 0 1 Off-State (output enabled with inactive state)
1 1 0 Asynchronously: OCx=CCxP, OCx_EN=1, OCxN=CCxNP,
OCxN_EN=1
Then if the clock is present: OCx=OISx and OCxN=OISxN after a
1 1 1 dead-time, assuming that OISx and OISxN do not correspond to OCX
and OCxN both in active state.
1. When both outputs of a channel are not used (CCxE = CCxNE = 0), the OISx, OISxN, CCxP and CCxNP bits must be kept
cleared.

Note: The state of the external I/O pins connected to the complementary OCx and OCxN channels
depends on the OCx and OCxN channel state and the GPIO registers.

13.4.10 TIM1 counter (TIM1_CNT)

Address offset: 0x24
Reset value: 0x0000

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 15:0 CNT[15:0]: Counter value

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Advanced-control timers (TIM1) RM0360

13.4.11 TIM1 prescaler (TIM1_PSC)

Address offset: 0x28
Reset value: 0x0000

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 15:0 PSC[15:0]: Prescaler value

The counter clock frequency (CK_CNT) is equal to fCK_PSC / (PSC[15:0] + 1).
PSC contains the value to be loaded in the active prescaler register at each update event
(including when the counter is cleared through UG bit of TIMx_EGR register or through trigger
controller when configured in “reset mode”).

13.4.12 TIM1 auto-reload register (TIM1_ARR)

Address offset: 0x2C
Reset value: 0xFFFF

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 15:0 ARR[15:0]: Auto-reload value

ARR is the value to be loaded in the actual auto-reload register.
Refer to the Section 13.3.1: Time-base unit on page 227 for more details about ARR update
and behavior.
The counter is blocked while the auto-reload value is null.

13.4.13 TIM1 repetition counter register (TIM1_RCR)

Address offset: 0x30
Reset value: 0x0000

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. REP[7:0]
rw rw rw rw rw rw rw rw

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RM0360 Advanced-control timers (TIM1)

Bits 15:8 Reserved, must be kept at reset value.

Bits 7:0 REP[7:0]: Repetition counter value
These bits allow the user to set-up the update rate of the compare registers (i.e. periodic
transfers from preload to active registers) when preload registers are enable, as well as the
update interrupt generation rate, if this interrupt is enable.
Each time the REP_CNT related downcounter reaches zero, an update event is generated
and it restarts counting from REP value. As REP_CNT is reloaded with REP value only at the
repetition update event U_RC, any write to the TIMx_RCR register is not taken in account until
the next repetition update event.
It means in PWM mode (REP+1) corresponds to:
– the number of PWM periods in edge-aligned mode
– the number of half PWM period in center-aligned mode.

13.4.14 TIM1 capture/compare register 1 (TIM1_CCR1)

Address offset: 0x34
Reset value: 0x0000

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR1[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 15:0 CCR1[15:0]: Capture/Compare 1 value

If channel CC1 is configured as output:
CCR1 is the value to be loaded in the actual capture/compare 1 register (preload value).
It is loaded permanently if the preload feature is not selected in the TIMx_CCMR1 register (bit
OC1PE). Else the preload value is copied in the active capture/compare 1 register when an
update event occurs.
The active capture/compare register contains the value to be compared to the counter
TIMx_CNT and signaled on OC1 output.

If channel CC1 is configured as input:

CCR1 is the counter value transferred by the last input capture 1 event (IC1).

13.4.15 TIM1 capture/compare register 2 (TIM1_CCR2)

Address offset: 0x38
Reset value: 0x0000

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR2[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

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Advanced-control timers (TIM1) RM0360

Bits 15:0 CCR2[15:0]: Capture/Compare 2 value

If channel CC2 is configured as output:
CCR2 is the value to be loaded in the actual capture/compare 2 register (preload value).
It is loaded permanently if the preload feature is not selected in the TIMx_CCMR2 register (bit
OC2PE). Else the preload value is copied in the active capture/compare 2 register when an
update event occurs.
The active capture/compare register contains the value to be compared to the counter
TIMx_CNT and signalled on OC2 output.
If channel CC2 is configured as input:
CCR2 is the counter value transferred by the last input capture 2 event (IC2).

13.4.16 TIM1 capture/compare register 3 (TIM1_CCR3)

Address offset: 0x3C
Reset value: 0x0000

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR3[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 15:0 CCR3[15:0]: Capture/Compare value

If channel CC3 is configured as output:
CCR3 is the value to be loaded in the actual capture/compare 3 register (preload value).
It is loaded permanently if the preload feature is not selected in the TIMx_CCMR3 register (bit
OC3PE). Else the preload value is copied in the active capture/compare 3 register when an
update event occurs.
The active capture/compare register contains the value to be compared to the counter
TIMx_CNT and signalled on OC3 output.

If channel CC3 is configured as input:

CCR3 is the counter value transferred by the last input capture 3 event (IC3).

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RM0360 Advanced-control timers (TIM1)

13.4.17 TIM1 capture/compare register 4 (TIM1_CCR4)

Address offset: 0x40
Reset value: 0x0000

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR4[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 15:0 CCR4[15:0]: Capture/Compare value

If channel CC4 is configured as output:
CCR4 is the value to be loaded in the actual capture/compare 4 register (preload value).
It is loaded permanently if the preload feature is not selected in the TIMx_CCMR4 register (bit
OC4PE). Else the preload value is copied in the active capture/compare 4 register when an
update event occurs.
The active capture/compare register contains the value to be compared to the counter
TIMx_CNT and signalled on OC4 output.
If channel CC4 is configured as input:
CCR4 is the counter value transferred by the last input capture 4 event (IC4).

13.4.18 TIM1 break and dead-time register (TIM1_BDTR)

Address offset: 0x44
Reset value: 0x0000

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MOE AOE BKP BKE OSSR OSSI LOCK[1:0] DTG[7:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Note: As the bits AOE, BKP, BKE, OSSI, OSSR and DTG[7:0] can be write-locked depending on
the LOCK configuration, it can be necessary to configure all of them during the first write
access to the TIMx_BDTR register.

Bit 15 MOE: Main output enable

This bit is cleared asynchronously by hardware as soon as the break input is active. It is set by
software or automatically depending on the AOE bit. It is acting only on the channels which are
configured in output.
0: OC and OCN outputs are disabled or forced to idle state.
1: OC and OCN outputs are enabled if their respective enable bits are set (CCxE, CCxNE in
TIMx_CCER register).
See OC/OCN enable description for more details (Section 13.4.9: TIM1 capture/compare
enable register (TIM1_CCER) on page 288).
Bit 14 AOE: Automatic output enable
0: MOE can be set only by software
1: MOE can be set by software or automatically at the next update event (if the break input is
not be active)
Note: This bit cannot be modified as long as LOCK level 1 has been programmed (LOCK bits
in TIMx_BDTR register).

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Advanced-control timers (TIM1) RM0360

Bit 13 BKP: Break polarity

0: Break input BRK is active low
1: Break input BRK is active high
Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits
in TIMx_BDTR register).
Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.
Bit 12 BKE: Break enable
0: Break inputs (BRK and CCS clock failure event) disabled
1; Break inputs (BRK and CCS clock failure event) enabled
Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in
TIMx_BDTR register).
Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.
Bit 11 OSSR: Off-state selection for Run mode
This bit is used when MOE=1 on channels having a complementary output which are
configured as outputs. OSSR is not implemented if no complementary output is implemented in
the timer.
See OC/OCN enable description for more details (Section 13.4.9: TIM1 capture/compare
enable register (TIM1_CCER) on page 288).
0: When inactive, OC/OCN outputs are disabled (OC/OCN enable output signal=0).
1: When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1
or CCxNE=1. Then, OC/OCN enable output signal=1
Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK
bits in TIMx_BDTR register).
Bit 10 OSSI: Off-state selection for Idle mode
This bit is used when MOE=0 on channels configured as outputs.
See OC/OCN enable description for more details (Section 13.4.9: TIM1 capture/compare
enable register (TIM1_CCER) on page 288).
0: When inactive, OC/OCN outputs are disabled (OC/OCN enable output signal=0).
1: When inactive, OC/OCN outputs are forced first with their idle level as soon as CCxE=1 or
CCxNE=1. OC/OCN enable output signal=1)
Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK
bits in TIMx_BDTR register).
Bits 9:8 LOCK[1:0]: Lock configuration
These bits offer a write protection against software errors.
00: LOCK OFF - No bit is write protected.
01: LOCK Level 1 = DTG bits in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2
register and BKE/BKP/AOE bits in TIMx_BDTR register can no longer be written.
10: LOCK Level 2 = LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER
register, as long as the related channel is configured in output through the CCxS bits) as well
as OSSR and OSSI bits can no longer be written.
11: LOCK Level 3 = LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in
TIMx_CCMRx registers, as long as the related channel is configured in output through the
CCxS bits) can no longer be written.
Note: The LOCK bits can be written only once after the reset. Once the TIMx_BDTR register
has been written, their content is frozen until the next reset.

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RM0360 Advanced-control timers (TIM1)

Bits 7:0 DTG[7:0]: Dead-time generator setup

This bit-field defines the duration of the dead-time inserted between the complementary
outputs. DT correspond to this duration.
DTG[7:5]=0xx => DT=DTG[7:0]x tdtg with tdtg=tDTS.
DTG[7:5]=10x => DT=(64+DTG[5:0])xtdtg with Tdtg=2xtDTS.
DTG[7:5]=110 => DT=(32+DTG[4:0])xtdtg with Tdtg=8xtDTS.
DTG[7:5]=111 => DT=(32+DTG[4:0])xtdtg with Tdtg=16xtDTS.
Example if TDTS=125 ns (8 MHz), dead-time possible values are:
0 to 15875 ns by 125 ns steps,
16 us to 31750 ns by 250 ns steps,
32 us to 63 us by 1 us steps,
64 us to 126 us by 2 us steps
Note: This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed
(LOCK bits in TIMx_BDTR register).

13.4.19 TIM1 DMA control register (TIM1_DCR)

Address offset: 0x48
Reset value: 0x0000

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. DBL[4:0] Res. Res. Res. DBA[4:0]
rw rw rw rw rw rw rw rw rw rw

Bits 15:13 Reserved, must be kept at reset value.

Bits 12:8 DBL[4:0]: DMA burst length
This 5-bit vector defines the number of DMA transfers (the timer recognizes a burst transfer
when a read or a write access is done to the TIMx_DMAR address)
00000: 1 transfer
00001: 2 transfers
00010: 3 transfers
...
10001: 18 transfers
Bits 7:5 Reserved, must be kept at reset value.
Bits 4:0 DBA[4:0]: DMA base address
This 5-bit vector defines the base-address for DMA transfers (when read/write access are
done through the TIMx_DMAR address). DBA is defined as an offset starting from the address
of the TIMx_CR1 register.
Example:
00000: TIMx_CR1,
00001: TIMx_CR2,
00010: TIMx_SMCR,
...
Example: Let us consider the following transfer: DBL = 7 transfers and DBA = TIMx_CR1. In
this case the transfer is done to/from 7 registers starting from the TIMx_CR1 address.

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Advanced-control timers (TIM1) RM0360

13.4.20 TIM1 DMA address for full transfer (TIM1_DMAR)

Address offset: 0x4C
Reset value: 0x0000

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAB[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 15:0 DMAB[15:0]: DMA register for burst accesses

A read or write operation to the DMAR register accesses the register located at the address
(TIMx_CR1 address) + (DBA + DMA index) x 4
where TIMx_CR1 address is the address of the control register 1, DBA is the DMA base
address configured in TIMx_DCR register, DMA index is automatically controlled by the DMA
transfer, and ranges from 0 to DBL (DBL configured in TIMx_DCR).

Example of how to use the DMA burst feature

In this example the timer DMA burst feature is used to update the contents of the CCRx
registers (x = 2, 3, 4) with the DMA transferring half words into the CCRx registers.
This is done in the following steps:
1. Configure the corresponding DMA channel as follows:
– DMA channel peripheral address is the DMAR register address
– DMA channel memory address is the address of the buffer in the RAM containing
the data to be transferred by DMA into CCRx registers.
– Number of data to transfer = 3 (See note below).
– Circular mode disabled.
2. Configure the DCR register by configuring the DBA and DBL bit fields as follows:
DBL = 3 transfers, DBA = 0xE.
3. Enable the TIMx update DMA request (set the UDE bit in the DIER register).
4. Enable TIMx
5. Enable the DMA channel
Note: This example is for the case where every CCRx register to be updated once. If every CCRx
register is to be updated twice for example, the number of data to transfer should be 6. Let's
take the example of a buffer in the RAM containing data1, data2, data3, data4, data5 and
data6. The data is transferred to the CCRx registers as follows: on the first update DMA
request, data1 is transferred to CCR2, data2 is transferred to CCR3, data3 is transferred to
CCR4 and on the second update DMA request, data4 is transferred to CCR2, data5 is
transferred to CCR3 and data6 is transferred to CCR4.

298/775 RM0360 Rev 5

 0x30
0x28
0x24
0x20
0x18
0x14
0x10
0x08
0x04
0x00

0x2C
0x1C
0x0C
Offset
RM0360

13.4.21

mode
mode
mode
mode
TIM1_SR
TIM1_CR2
TIM1_CR1

TIM1_PSC
TIM1_CNT

TIM1_RCR
TIM1_ARR
TIM1_EGR
Register

TIM1_DIER

Reset value
Reset value
Reset value
Reset value
Reset value

Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value

TIM1_CCER
TIM1_SMCR

Input capture
Input capture

TIM1_CCMR2
TIM1_CCMR2
TIM1_CCMR1
TIM1_CCMR1

Output compare
Output compare
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 31
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 30
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 29
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 28
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 27
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 26
TIM1 register map

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 25
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 24
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 23
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 22
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 21
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 20
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 19
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 18
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

RM0360 Rev 5
17
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 16

1
0
0
0
0
0
0
0

Res. Res. O24CE OC2CE Res. Res. Res. ETP Res. Res. 15

1
0
0
0
0
0
0
0
0
0

Res. Res. Res. Res. TDE ECE OIS4 Res. 14

1
0
0
0
0
0
0
0
0
0
0

Res. CC4P Res. Res. COMDE OIS3N Res. 13

[2:0]
[2:0]

IC4F[3:0]
IC2F[3:0]

OC4M
OC2M
[1:0]

1
0
0
0
0
0
0
0
0
0
0
0

Res. CC4E Res. CC4OF CC4DE OIS3 Res.

ETPS

12

1
0
0
0
0
0
0
0

Res. CC3NP OC4PE OC2PE Res. CC3OF CC3DE OIS2N Res. 11

Table 46. TIM1 register map and reset values

IC4
IC2

[1:0]
[1:0]

PSC
PSC

1
0
0
0
0
0
0
0

Res. CC3NE OC4FE OC2FE Res. CC2OF CC2DE OIS2 Res. 10

1
0
0
0
0
0
0
0
0

Res. CC3P Res. CC1OF CC1DE OIS1N 9

ETF[3:0]

[1:0]
[1:0]
[1:0]
[1:0]
[1:0]
CKD

1
0
0
0
0
0
0
0

Res. CC3E Res. Res. UDE OIS1

CC4S
CC4S
CC2S
CC2S

1
0
0
0
0
0
0
0

0
0
0

CC2NP OC3CE OC1CE BG BIF BIE MSM TI1S ARPE 7

PSC[15:0]
CNT[15:0]

ARR[15:0]

1
0
0
0
0
0
0
0

0
0
0

CC2NE TG TIF TIE 6

[1:0]
CMS

1
0
0
0
0
0
0
0

0
0
0

CC2P COM COMIF COMIE 5

[2:0]
[2:0]

IC3F[3:0]
IC1F[3:0]

OC3M
OC1M
TS[2:0]

1
0
0
0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0
0
0
0

0
0
0

CC2E CC4G CC4IF CC4IE DIR

MMS[2:0]

1
0
0
0
0
0
0
0

0
0
0

CC1NP OC3PE OC1PE CC3G CC3IF CC3IE OCCS CCDS OPM 3

REP[7:0]
IC3
IC1

[1:0]
[1:0]

PSC
PSC

1
0
0
0
0
0
0
0

0
0
0

CC1NE OC3FE OC1FE CC2G CC2IF CC2IE CCUS URS 2

1
0
0
0
0
0
0

0
0
0

CC1P CC1G CC1IF CC1IE Res. UDIS 1

[1:0]
[1:0]
[1:0]
[1:0]

1
0
0
0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0
0
0
0

0
0
0

CC1E UG UIF UIE CCPC CEN

SMS[2:0]

CC3S
CC3S
CC1S
CC1S
TIM1 registers are mapped as 16-bit addressable registers as described in the table below:

299/775
Advanced-control timers (TIM1)

300
Advanced-control timers (TIM1) RM0360

Table 46. TIM1 register map and reset values (continued)

Offset Register

31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12

10
11

9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
TIM1_CCR1 CCR1[15:0]
0x34
Reset value Res. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
TIM1_CCR2 CCR2[15:0]
0x38
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
TIM1_CCR3 CCR3[15:0]
0x3C
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
TIM1_CCR4 CCR4[15:0]
0x40
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

OSSR
LOCK

OSSI
MOE
AOE
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

BKP
BKE
TIM1_BDTR DT[7:0]
0x44 [1:0]

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.
Res.
Res.
TIM1_DCR DBL[4:0] DBA[4:0]
0x48
Reset value 0 0 0 0 0 0 0 0 0 0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

TIM1_DMAR DMAB[15:0]
0x4C
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Refer to Section 2.2 on page 37 for the register boundary addresses.

300/775 RM0360 Rev 5

RM0360 General-purpose timers (TIM3)

14 General-purpose timers (TIM3)

14.1 TIM3 introduction

The general-purpose timers consist of a 16-bit auto-reload counter driven by a
programmable prescaler.
They may be used for a variety of purposes, including measuring the pulse lengths of input
signals (input capture) or generating output waveforms (output compare and PWM).
Pulse lengths and waveform periods can be modulated from a few microseconds to several
milliseconds using the timer prescaler and the RCC clock controller prescalers.
The timers are completely independent, and do not share any resources. They can be
synchronized together as described in Section 14.3.15.

14.2 TIM3 main features

General-purpose TIMx timer features include:
• 16-bit (TIM3) up, down, up/down auto-reload counter.
• 16-bit programmable prescaler used to divide (also “on the fly”) the counter clock
frequency by any factor between 1 and 65535.
• Up to 4 independent channels for:
– Input capture
– Output compare
– PWM generation (Edge- and Center-aligned modes)
– One-pulse mode output
• Synchronization circuit to control the timer with external signals and to interconnect
several timers.
• Interrupt/DMA generation on the following events:
– Update: counter overflow/underflow, counter initialization (by software or
internal/external trigger)
– Trigger event (counter start, stop, initialization or count by internal/external trigger)
– Input capture
– Output compare
• Supports incremental (quadrature) encoder and hall-sensor circuitry for positioning
purposes
• Trigger input for external clock or cycle-by-cycle current management

RM0360 Rev 5 301/775

366
General-purpose timers (TIM3) RM0360

Figure 93. General-purpose timer block diagram (TIM3)

Internal clock (CK_INT)

TIMxCLK from RCC Trigger
ETRF controller
ETR Polarity selection & edge ETRP TRGO
TIMx_ETR Input filter
detector & prescaler to other timers
to DAC/ADC
ITR0 TGI
ITR1 ITR
Slave
ITR2 TRC TRGI controller Reset, enable, up, count
ITR3
mode
TI1F_ED

TI1FP1 Encoder
TI2FP2 interface

U
Auto-reload register UI
Stop, clear or up/down
U
CK_PSC PSC CK_CNT +/- CNT counter
prescaler
CC1I U CC1I
XOR TI1FP1 OC1REF
TI1 Input filter & IC1 IC1PS Output OC1 TIMx_CH1
TI1FP2 Prescaler Capture/Compare 1 register
edge detector control
TIMx_CH1 TRC
CC2I
U CC2I
TI2FP1
TI2 Input filter & IC2 Output OC2
TIMx_CH2 TI2FP2 Prescaler
IC2PS Capture/Compare 2 register OC2REF TIMx_CH2
edge detector control
TRC
CC3I CC3I
U
TI3FP3 OC3REF
TI3 Input filter & IC3 IC3PS Output OC3 TIMx_CH3
TI3FP4 Prescaler Capture/Compare 3 register
TIMx_CH3 edge detector control
TRC CC4I
U CC4I
TI4FP3
TI4 Input filter & IC4 Output OC4
TIMx_CH4 TI4FP4 Prescaler
IC4PS Capture/Compare 4 register OC4REF TIMx_CH4
edge detector control
TRC

ETRF

Notes:
Preload registers transferred
Reg
to active registers on U event
according to control bit

Event

Interrupt & DMA output

MS19673V1

14.3 TIM3 functional description

14.3.1 Time-base unit

The main block of the programmable timer is a 16-bit/32-bit counter with its related auto-
reload register. The counter can count up but also down or both up and down. The counter
clock can be divided by a prescaler.
The counter, the auto-reload register and the prescaler register can be written or read by
software. This is true even when the counter is running.

302/775 RM0360 Rev 5

RM0360 General-purpose timers (TIM3)

The time-base unit includes:

• Counter Register (TIMx_CNT)
• Prescaler Register (TIMx_PSC)
• Auto-Reload Register (TIMx_ARR)
The auto-reload register is preloaded. Writing to or reading from the auto-reload register
accesses the preload register. The content of the preload register are transferred into the
shadow register permanently or at each update event (UEV), depending on the auto-reload
preload enable bit (ARPE) in TIMx_CR1 register. The update event is sent when the counter
reaches the overflow (or underflow when downcounting) and if the UDIS bit equals 0 in the
TIMx_CR1 register. It can also be generated by software. The generation of the update
event is described in detail for each configuration.
The counter is clocked by the prescaler output CK_CNT, which is enabled only when the
counter enable bit (CEN) in TIMx_CR1 register is set (refer also to the slave mode controller
description to get more details on counter enabling).
Note that the actual counter enable signal CNT_EN is set 1 clock cycle after CEN.

Prescaler description
The prescaler can divide the counter clock frequency by any factor between 1 and 65536. It
is based on a 16-bit counter controlled through a 16-bit/32-bit register (in the TIMx_PSC
register). It can be changed on the fly as this control register is buffered. The new prescaler
ratio is taken into account at the next update event.
Figure 94 and Figure 95 give some examples of the counter behavior when the prescaler
ratio is changed on the fly:

Figure 94. Counter timing diagram with prescaler division change from 1 to 2

CK_PSC

CEN

Timerclock = CK_CNT

Counter register F7 F8 F9 FA FB FC 00 01 02 03

Update event (UEV)

Prescaler control register 0 1

Write a new value in TIMx_PSC

Prescaler buffer 0 1

Prescaler counter 0 0 1 0 1 0 1 0 1
MS31076V2

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366
General-purpose timers (TIM3) RM0360

Figure 95. Counter timing diagram with prescaler division change from 1 to 4

CK_PSC

CEN

Timerclock = CK_CNT

F7 F8 F9 FA FB FC 00 01
Counter register

Update event (UEV)

0 3
Prescaler control register

Write a new value in TIMx_PSC

0 3
Prescaler buffer

0 0 1 2 3 0 1 2 3
Prescaler counter

MS31077V2

14.3.2 Counter modes

Upcounting mode
In upcounting mode, the counter counts from 0 to the auto-reload value (content of the
TIMx_ARR register), then restarts from 0 and generates a counter overflow event.
An Update event can be generated at each counter overflow or by setting the UG bit in the
TIMx_EGR register (by software or by using the slave mode controller).
The UEV event can be disabled by software by setting the UDIS bit in TIMx_CR1 register.
This is to avoid updating the shadow registers while writing new values in the preload
registers. Then no update event occurs until the UDIS bit has been written to 0. However,
the counter restarts from 0, as well as the counter of the prescaler (but the prescale rate
does not change). In addition, if the URS bit (update request selection) in TIMx_CR1
register is set, setting the UG bit generates an update event UEV but without setting the UIF
flag (thus no interrupt or DMA request is sent). This is to avoid generating both update and
capture interrupts when clearing the counter on the capture event.
When an update event occurs, all the registers are updated and the update flag (UIF bit in
TIMx_SR register) is set (depending on the URS bit):
• The buffer of the prescaler is reloaded with the preload value (content of the TIMx_PSC
register)
• The auto-reload shadow register is updated with the preload value (TIMx_ARR)
The following figures show some examples of the counter behavior for different clock
frequencies when TIMx_ARR=0x36.

304/775 RM0360 Rev 5

RM0360 General-purpose timers (TIM3)

Figure 96. Counter timing diagram, internal clock divided by 1

CK_PSC

CNT_EN

Timerclock = CK_CNT

Counter register 31 32 33 34 35 36 00 01 02 03 04 05 06 07

Counter overflow

Update event (UEV)

Update interrupt flag

(UIF)

MS31078V2

Figure 97. Counter timing diagram, internal clock divided by 2

CK_PSC

CNT_EN

Timerclock = CK_CNT

Counter register 0034 0035 0036 0000 0001 0002 0003

Counter overflow

Update event (UEV)

Update interrupt flag

(UIF)

MS31079V2

RM0360 Rev 5 305/775

366
General-purpose timers (TIM3) RM0360

Figure 98. Counter timing diagram, internal clock divided by 4

CK_PSC

CNT_EN

Timerclock = CK_CNT

Counter register 0035 0036 0000 0001

Counter overflow

Update event (UEV)

Update interrupt flag

(UIF)

MS31080V2

Figure 99. Counter timing diagram, internal clock divided by N

CK_PSC

Timerclock = CK_CNT

Counter register 1F 20 00

Counter overflow

Update event (UEV)

Update interrupt flag

(UIF)

MS31081V2

306/775 RM0360 Rev 5

RM0360 General-purpose timers (TIM3)

Figure 100. Counter timing diagram, Update event when ARPE=0

(TIMx_ARR not preloaded)

CK_PSC

CEN

Timerclock = CK_CNT

Counter register 31 32 33 34 35 36 00 01 02 03 04 05 06 07

Counter overflow

Update event (UEV)

Update interrupt flag

(UIF)

Auto-reload preload
register FF 36

Write a new value in TIMx_ARR

MS31082V2

Figure 101. Counter timing diagram, Update event when ARPE=1

(TIMx_ARR preloaded)

CK_PSC

CEN

Timerclock = CK_CNT

Counter register F0 F1 F2 F3 F4 F5 00 01 02 03 04 05 06 07

Counter overflow

Update event (UEV)

Update interrupt flag

(UIF)
Auto-reload preload
F5 36
register

Auto-reload shadow
register F5 36

Write a new value in TIMx_ARR MS31083V2

RM0360 Rev 5 307/775

366
General-purpose timers (TIM3) RM0360

Downcounting mode
In downcounting mode, the counter counts from the auto-reload value (content of the
TIMx_ARR register) down to 0, then restarts from the auto-reload value and generates a
counter underflow event.
An Update event can be generate at each counter underflow or by setting the UG bit in the
TIMx_EGR register (by software or by using the slave mode controller)
The UEV update event can be disabled by software by setting the UDIS bit in TIMx_CR1
register. This is to avoid updating the shadow registers while writing new values in the
preload registers. Then no update event occurs until UDIS bit has been written to 0.
However, the counter restarts from the current auto-reload value, whereas the counter of the
prescaler restarts from 0 (but the prescale rate doesn’t change).
In addition, if the URS bit (update request selection) in TIMx_CR1 register is set, setting the
UG bit generates an update event UEV but without setting the UIF flag (thus no interrupt or
DMA request is sent). This is to avoid generating both update and capture interrupts when
clearing the counter on the capture event.
When an update event occurs, all the registers are updated and the update flag (UIF bit in
TIMx_SR register) is set (depending on the URS bit):
• The buffer of the prescaler is reloaded with the preload value (content of the TIMx_PSC
register).
• The auto-reload active register is updated with the preload value (content of the
TIMx_ARR register). Note that the auto-reload is updated before the counter is
reloaded, so that the next period is the expected one.
The following figures show some examples of the counter behavior for different clock
frequencies when TIMx_ARR=0x36.

Figure 102. Counter timing diagram, internal clock divided by 1

CK_PSC

CNT_EN

Timerclock = CK_CNT

Counter register 05 04 03 02 01 00 36 35 34 33 32 31 30 2F

Counter underflow
(cnt_udf)

Update event (UEV)

Update interrupt flag

(UIF)

MS31184V1

308/775 RM0360 Rev 5

RM0360 General-purpose timers (TIM3)

Figure 103. Counter timing diagram, internal clock divided by 2

CK_PSC

CNT_EN

Timerclock = CK_CNT

Counter register 0002 0001 0000 0036 0035 0034 0033

Counter underflow

Update event (UEV)

Update interrupt flag

(UIF)

MS31185V1

Figure 104. Counter timing diagram, internal clock divided by 4

CK_PSC

CNT_EN

Timerclock = CK_CNT

Counter register 0001 0000 0000 0001

Counter underflow

Update event (UEV)

Update interrupt flag

(UIF)

MS31186V1

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366
General-purpose timers (TIM3) RM0360

Figure 105. Counter timing diagram, internal clock divided by N

CK_PSC

Timerclock = CK_CNT

Counter register 20 1F 00 36

Counter underflow

Update event (UEV)

Update interrupt flag

(UIF)

MS31187V1

Figure 106. Counter timing diagram, Update event when repetition counter is not
used

CK_PSC

CEN

Timerclock = CK_CNT

Counter register 05 04 03 02 01 00 36 35 34 33 32 31 30 2F

Counter underflow

Update event (UEV)

Update interrupt flag

(UIF)

Auto-reload preload
register FF 36

Write a new value in TIMx_ARR

MS31188V1

310/775 RM0360 Rev 5

RM0360 General-purpose timers (TIM3)

Center-aligned mode (up/down counting)

In center-aligned mode, the counter counts from 0 to the auto-reload value (content of the
TIMx_ARR register) – 1, generates a counter overflow event, then counts from the auto-
reload value down to 1 and generates a counter underflow event. Then it restarts counting
from 0.
Center-aligned mode is active when the CMS bits in TIMx_CR1 register are not equal to
'00'. The Output compare interrupt flag of channels configured in output is set when: the
counter counts down (Center aligned mode 1, CMS = “01”), the counter counts up (Center
aligned mode 2, CMS = “10”) the counter counts up and down (Center aligned mode 3,
CMS = “11”).
In this mode, the direction bit (DIR from TIMx_CR1 register) cannot be written. It is updated
by hardware and gives the current direction of the counter.
The update event can be generated at each counter overflow and at each counter underflow
or by setting the UG bit in the TIMx_EGR register (by software or by using the slave mode
controller) also generates an update event. In this case, the counter restarts counting from
0, as well as the counter of the prescaler.
The UEV update event can be disabled by software by setting the UDIS bit in TIMx_CR1
register. This is to avoid updating the shadow registers while writing new values in the
preload registers. Then no update event occurs until the UDIS bit has been written to 0.
However, the counter continues counting up and down, based on the current auto-reload
value.
In addition, if the URS bit (update request selection) in TIMx_CR1 register is set, setting the
UG bit generates an update event UEV but without setting the UIF flag (thus no interrupt or
DMA request is sent). This is to avoid generating both update and capture interrupt when
clearing the counter on the capture event.
When an update event occurs, all the registers are updated and the update flag (UIF bit in
TIMx_SR register) is set (depending on the URS bit):
• The buffer of the prescaler is reloaded with the preload value (content of the TIMx_PSC
register).
• The auto-reload active register is updated with the preload value (content of the
TIMx_ARR register). Note that if the update source is a counter overflow, the auto-
reload is updated before the counter is reloaded, so that the next period is the expected
one (the counter is loaded with the new value).
The following figures show some examples of the counter behavior for different clock
frequencies.

RM0360 Rev 5 311/775

366
General-purpose timers (TIM3) RM0360

Figure 107. Counter timing diagram, internal clock divided by 1, TIMx_ARR=0x6

CK_PSC

CEN

Timerclock = CK_CNT

Counter register 04 03 02 01 00 01 02 03 04 05 06 05 04 03

Counter underflow

Counter overflow

Update event (UEV)

Update interrupt flag

(UIF)

MS31189V1

1. Here, center-aligned mode 1 is used (for more details refer to Section 14.4.1: TIM3 control register 1
(TIM3_CR1) on page 343).

Figure 108. Counter timing diagram, internal clock divided by 2

CK_PSC

CNT_EN

Timerclock = CK_CNT

Counter register 0003 0002 0001 0000 0001 0002 0003

Counter underflow

Update event (UEV)

Update interrupt flag

(UIF)

MS31190V1

312/775 RM0360 Rev 5

RM0360 General-purpose timers (TIM3)

Figure 109. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36

CK_PSC

CNT_EN

Timerclock = CK_CNT

Counter register 0034 0035 0036 0035

Counter overflow

Update event (UEV)

Update interrupt flag

(UIF)

Note: Here, center_aligned mode 2 or 3 is updated with an UIF on overflow

MS31191V1

1. Center-aligned mode 2 or 3 is used with an UIF on overflow.

Figure 110. Counter timing diagram, internal clock divided by N

CK_PSC

Timerclock = CK_CNT

Counter register 20 1F 01 00

Counter underflow

Update event (UEV)

Update interrupt flag

(UIF)

MS31192V1

RM0360 Rev 5 313/775

366
General-purpose timers (TIM3) RM0360

Figure 111. Counter timing diagram, Update event with ARPE=1 (counter underflow)

CK_PSC

CEN

Timerclock = CK_CNT

Counter register 06 05 04 03 02 01 00 01 02 03 04 05 06 07

Counter underflow

Update event (UEV)

Update interrupt flag

(UIF)

Auto-reload preload
register FD 36

Write a new value in TIMx_ARR

Auto-reload active
register FD 36

MS31193V1

Figure 112. Counter timing diagram, Update event with ARPE=1 (counter overflow)

CK_PSC

CEN

Timer clock = CK_CNT

Counter register F7 F8 F9 FA FB FC 36 35 34 33 32 31 30 2F

Counter overflow

Update event (UEV)

Update interrupt flag

(UIF)
Auto-reload preload
FD 36
register

Write a new value in TIMx_ARR

Auto-reload active
register FD 36

MS31194V1

314/775 RM0360 Rev 5

RM0360 General-purpose timers (TIM3)

14.3.3 Clock sources

The counter clock can be provided by the following clock sources:
• Internal clock (CK_INT)
• External clock mode1: external input pin (TIx)
• External clock mode2: external trigger input (ETR)
• Internal trigger inputs (ITRx): using one timer as prescaler for another timer, for
example, Timer 1 can be configured to act as a prescaler for Timer 2. Refer to : Using
one timer as prescaler for another on page 337 for more details.

Internal clock source (CK_INT)

If the slave mode controller is disabled (SMS=000 in the TIMx_SMCR register), then the
CEN, DIR (in the TIMx_CR1 register) and UG bits (in the TIMx_EGR register) are actual
control bits and can be changed only by software (except UG which remains cleared
automatically). As soon as the CEN bit is written to 1, the prescaler is clocked by the internal
clock CK_INT.
Figure 113 shows the behavior of the control circuit and the upcounter in normal mode,
without prescaler.

Figure 113. Control circuit in normal mode, internal clock divided by 1

Internal clock

CEN=CNT_EN

UG

CNT_INIT

Counter clock = CK_CNT = CK_PSC

Counter register 31 32 33 34 35 36 00 01 02 03 04 05 06 07

MS31085V2

External clock source mode 1

This mode is selected when SMS=111 in the TIMx_SMCR register. The counter can count at
each rising or falling edge on a selected input.

RM0360 Rev 5 315/775

366
General-purpose timers (TIM3) RM0360

Figure 114. TI2 external clock connection example

TIMx_SMCR
TS[2:0]

or TI2F or
TI1F or Encoder
ITRx mode
0xx
TI1_ED
100 TRGI External clock
TI1FP1 mode 1 CK_PSC
TI2F_Rising 101
TI2 Edge 0 TI2FP2 ETRF External clock
Filter 110
detector 1 ETRF mode 2
TI2F_Falling 111
CK_INT Internal clock
mode
ICF[3:0] CC2P (internal clock)

TIMx_CCMR1 TIMx_CCER
ECE SMS[2:0]
TIMx_SMCR

MS31196V1

For example, to configure the upcounter to count in response to a rising edge on the TI2
input, use the following procedure:
1. Configure channel 2 to detect rising edges on the TI2 input by writing CC2S= ‘01 in the
TIMx_CCMR1 register.
2. Configure the input filter duration by writing the IC2F[3:0] bits in the TIMx_CCMR1
register (if no filter is needed, keep IC2F=0000).
Note: The capture prescaler is not used for triggering, so it does not need to be configured.
3. Select rising edge polarity by writing CC2P=0 and CC2NP=0 in the TIMx_CCER
register.
4. Configure the timer in external clock mode 1 by writing SMS=111 in the TIMx_SMCR
register.
5. Select TI2 as the input source by writing TS=110 in the TIMx_SMCR register.
6. Enable the counter by writing CEN=1 in the TIMx_CR1 register.
For code example refer to the Appendix section A.8.2: Up counter on each 2 ETR rising
edges.
When a rising edge occurs on TI2, the counter counts once and the TIF flag is set.
The delay between the rising edge on TI2 and the actual clock of the counter is due to the
resynchronization circuit on TI2 input.

316/775 RM0360 Rev 5

RM0360 General-purpose timers (TIM3)

Figure 115. Control circuit in external clock mode 1

TI2

CNT_EN

Counter clock = CK_CNT = CK_PSC

Counter register 34 35 36

TIF

Write TIF=0

MS31087V2

External clock source mode 2

This mode is selected by writing ECE=1 in the TIMx_SMCR register.
The counter can count at each rising or falling edge on the external trigger input ETR.
The Figure 116 gives an overview of the external trigger input block.

Figure 116. External trigger input block

or TI2F or
TI1F or Encoder
mode

TRGI External clock

ETR mode 1 CK_PSC
0
Divider ETRP
ETR pin Filter ETRF External clock
/1, /2, /4, /8
1 fDTS downcounter mode 2
CK_INT Internal clock
ETP ETPS[1:0] ETF[3:0] mode
(internal clock)
TIMx_SMCR TIMx_SMCR TIMx_SMCR

ECE SMS[2:0]
TIMx_SMCR

MS33116V1

For example, to configure the upcounter to count each 2 rising edges on ETR, use the
following procedure:

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1. As no filter is needed in this example, write ETF[3:0]=0000 in the TIMx_SMCR register.

2. Set the prescaler by writing ETPS[1:0]=01 in the TIMx_SMCR register
3. Select rising edge detection on the ETR pin by writing ETP=0 in the TIMx_SMCR
register
4. Enable external clock mode 2 by writing ECE=1 in the TIMx_SMCR register.
5. Enable the counter by writing CEN=1 in the TIMx_CR1 register.
The counter counts once each 2 ETR rising edges.
The delay between the rising edge on ETR and the actual clock of the counter is due to the
resynchronization circuit on the ETRP signal.

Figure 117. Control circuit in external clock mode 2

f CK_INT

CNT_EN

ETR

ETRP

ETRF

Counter clock =
CK_INT =CK_PSC

Counter register 34 35 36

MS33111V2

14.3.4 Capture/compare channels

Each Capture/Compare channel is built around a capture/compare register (including a
shadow register), a input stage for capture (with digital filter, multiplexing and prescaler) and
an output stage (with comparator and output control).
The following figure gives an overview of one Capture/Compare channel.
The input stage samples the corresponding TIx input to generate a filtered signal TIxF.
Then, an edge detector with polarity selection generates a signal (TIxFPx) which can be
used as trigger input by the slave mode controller or as the capture command. It is
prescaled before the capture register (ICxPS).

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Figure 118. Capture/compare channel (example: channel 1 input stage)

TI1F_ED
To the slave mode controller

TI1 TI1F_Rising
Filter TI1F Edge 0 TI1FP1
fDTS downcounter TI1F_Falling 01
detector 1
TI2FP1 IC1 Divider IC1PS
10
/1, /2, /4, /8
ICF[3:0] CC1P/CC1NP TRC
11
TIMx_CCMR1 TIMx_CCER (from slave mode
TI2F_Rising controller)
0
(from channel 2)
CC1S[1:0] ICPS[1:0] CC1E
TI2F_Falling
1
(from channel 2) TIMx_CCMR1 TIMx_CCER

MS33115V1

The output stage generates an intermediate waveform which is then used for reference:
OCxRef (active high). The polarity acts at the end of the chain.

Figure 119. Capture/compare channel 1 main circuit

APB Bus

MCU-peripheral interface
(if 16-bit)

8 8
high

S write CCR1H
low

Read CCR1H S write_in_progress

read_in_progress write CCR1L
Read CCR1L Capture/compare preload register R
R Output CC1S[1]
capture_transfer compare_transfer mode
CC1S[0]
CC1S[1] Input
mode OC1PE
CC1S[0] Capture/compare shadow register OC1PE
UEV
TIMx_CCMR1
Comparator (from time
IC1PS Capture
base unit)
CC1E CNT>CCR1
Counter CNT=CCR1
CC1G
TIMx_EGR

MS33144V1

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Figure 120. Output stage of capture/compare channel (channel 1)

TIMx_SMCR
OCCS
To the master
OCREF_CLR 0
mode controller
ETRF 1

ocref_clr_int
CNT > CCR1 0
Output OC1REF Output OC1
mode enable
CNT = CCR1 1 circuit
controller

CC1P
TIMx_CCER CC1E TIM1_CCER
OC1M[2:0]
TIMx_CCMR1

MS33146V1

The capture/compare block is made of one preload register and one shadow register. Write
and read always access the preload register.
In capture mode, captures are actually done in the shadow register, which is copied into the
preload register.
In compare mode, the content of the preload register is copied into the shadow register
which is compared to the counter.

14.3.5 Input capture mode

In Input capture mode, the Capture/Compare Registers (TIMx_CCRx) are used to latch the
value of the counter after a transition detected by the corresponding ICx signal. When a
capture occurs, the corresponding CCXIF flag (TIMx_SR register) is set and an interrupt or
a DMA request can be sent if they are enabled. If a capture occurs while the CCxIF flag was
already high, then the over-capture flag CCxOF (TIMx_SR register) is set. CCxIF can be
cleared by software by writing it to 0 or by reading the captured data stored in the
TIMx_CCRx register. CCxOF is cleared when it is written with 0.
The following example shows how to capture the counter value in TIMx_CCR1 when TI1
input rises. To do this, use the following procedure:
• Select the active input: TIMx_CCR1 must be linked to the TI1 input, so write the CC1S
bits to 01 in the TIMx_CCMR1 register. As soon as CC1S becomes different from 00,
the channel is configured in input and the TIMx_CCR1 register becomes read-only.
• Program the appropriate input filter duration in relation with the signal connected to the
timer (when the input is one of the TIx (ICxF bits in the TIMx_CCMRx register). Let’s
imagine that, when toggling, the input signal is not stable during at must 5 internal clock
cycles. We must program a filter duration longer than these 5 clock cycles. We can
validate a transition on TI1 when 8 consecutive samples with the new level have been

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detected (sampled at fDTS frequency). Then write IC1F bits to 0011 in the
TIMx_CCMR1 register.
• Select the edge of the active transition on the TI1 channel by writing the CC1P and
CC1NP bits to 0 in the TIMx_CCER register (rising edge in this case).
• Program the input prescaler. In our example, we wish the capture to be performed at
each valid transition, so the prescaler is disabled (write IC1PS bits to 00 in the
TIMx_CCMR1 register).
• Enable capture from the counter into the capture register by setting the CC1E bit in the
TIMx_CCER register.
• If needed, enable the related interrupt request by setting the CC1IE bit in the
TIMx_DIER register, and/or the DMA request by setting the CC1DE bit in the
TIMx_DIER register.
For code example refer to the Appendix section A.8.3: Input capture configuration.
When an input capture occurs:
• The TIMx_CCR1 register gets the value of the counter on the active transition.
• CC1IF flag is set (interrupt flag). CC1OF is also set if at least two consecutive captures
occurred whereas the flag was not cleared.
• An interrupt is generated depending on the CC1IE bit.
• A DMA request is generated depending on the CC1DE bit.
For code example refer to the Appendix section A.8.4: Input capture data management.
In order to handle the overcapture, it is recommended to read the data before the
overcapture flag. This is to avoid missing an overcapture which could happen after reading
the flag and before reading the data.
Note: IC interrupt and/or DMA requests can be generated by software by setting the
corresponding CCxG bit in the TIMx_EGR register.

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14.3.6 PWM input mode

This mode is a particular case of input capture mode. The procedure is the same except:
• Two ICx signals are mapped on the same TIx input.
• These 2 ICx signals are active on edges with opposite polarity.
• One of the two TIxFP signals is selected as trigger input and the slave mode controller
is configured in reset mode.
For example, one can measure the period (in TIMx_CCR1 register) and the duty cycle (in
TIMx_CCR2 register) of the PWM applied on TI1 using the following procedure (depending
on CK_INT frequency and prescaler value):
• Select the active input for TIMx_CCR1: write the CC1S bits to 01 in the TIMx_CCMR1
register (TI1 selected).
• Select the active polarity for TI1FP1 (used both for capture in TIMx_CCR1 and counter
clear): write the CC1P to ‘0’ and the CC1NP bit to ‘0’ (active on rising edge).
• Select the active input for TIMx_CCR2: write the CC2S bits to 10 in the TIMx_CCMR1
register (TI1 selected).
• Select the active polarity for TI1FP2 (used for capture in TIMx_CCR2): write the CC2P
bit to ‘1’ and the CC2NP bit to ’0’(active on falling edge).
• Select the valid trigger input: write the TS bits to 101 in the TIMx_SMCR register
(TI1FP1 selected).
• Configure the slave mode controller in reset mode: write the SMS bits to 100 in the
TIMx_SMCR register.
• Enable the captures: write the CC1E and CC2E bits to ‘1 in the TIMx_CCER register.
For code example refer to the Appendix section A.8.5: PWM input configuration.

Figure 121. PWM input mode timing

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14.3.7 Forced output mode

In output mode (CCxS bits = 00 in the TIMx_CCMRx register), each output compare signal
(OCxREF and then OCx) can be forced to active or inactive level directly by software,
independently of any comparison between the output compare register and the counter.
To force an output compare signal (ocxref/OCx) to its active level, one just needs to write
101 in the OCxM bits in the corresponding TIMx_CCMRx register. Thus ocxref is forced high
(OCxREF is always active high) and OCx get opposite value to CCxP polarity bit.
e.g.: CCxP=0 (OCx active high) => OCx is forced to high level.
ocxref signal can be forced low by writing the OCxM bits to 100 in the TIMx_CCMRx
register.
Anyway, the comparison between the TIMx_CCRx shadow register and the counter is still
performed and allows the flag to be set. Interrupt and DMA requests can be sent
accordingly. This is described in the Output Compare Mode section.

14.3.8 Output compare mode

This function is used to control an output waveform or indicating when a period of time has
elapsed.
When a match is found between the capture/compare register and the counter, the output
compare function:
• Assigns the corresponding output pin to a programmable value defined by the output
compare mode (OCxM bits in the TIMx_CCMRx register) and the output polarity (CCxP
bit in the TIMx_CCER register). The output pin can keep its level (OCXM=000), be set
active (OCxM=001), be set inactive (OCxM=010) or can toggle (OCxM=011) on match.
• Sets a flag in the interrupt status register (CCxIF bit in the TIMx_SR register).
• Generates an interrupt if the corresponding interrupt mask is set (CCXIE bit in the
TIMx_DIER register).
• Sends a DMA request if the corresponding enable bit is set (CCxDE bit in the
TIMx_DIER register, CCDS bit in the TIMx_CR2 register for the DMA request
selection).
The TIMx_CCRx registers can be programmed with or without preload registers using the
OCxPE bit in the TIMx_CCMRx register.
In output compare mode, the update event UEV has no effect on ocxref and OCx output.
The timing resolution is one count of the counter. Output compare mode can also be used to
output a single pulse (in One-pulse mode).
Procedure:
1. Select the counter clock (internal, external, prescaler).
2. Write the desired data in the TIMx_ARR and TIMx_CCRx registers.
3. Set the CCxIE and/or CCxDE bits if an interrupt and/or a DMA request is to be
generated.
4. Select the output mode. For example, one must write OCxM=011, OCxPE=0, CCxP=0
and CCxE=1 to toggle OCx output pin when CNT matches CCRx, CCRx preload is not
used, OCx is enabled and active high.
5. Enable the counter by setting the CEN bit in the TIMx_CR1 register.
For code example refer to the Appendix section A.8.7: Output compare configuration.

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The TIMx_CCRx register can be updated at any time by software to control the output
waveform, provided that the preload register is not enabled (OCxPE=0, else TIMx_CCRx
shadow register is updated only at the next update event UEV). An example is given in
Figure 122.

Figure 122. Output compare mode, toggle on OC1

Write 0xB201 in the CC1R register

TIMx_CNT 0039 003A 003B B200 B201

TIMx_CCR1 003A B201

OC1REF= OC1

Match detected on CCR1

Interrupt generated if enabled
MSv67583V1

14.3.9 PWM mode

Pulse width modulation mode allows to generate a signal with a frequency determined by
the value of the TIMx_ARR register and a duty cycle determined by the value of the
TIMx_CCRx register.
The PWM mode can be selected independently on each channel (one PWM per OCx
output) by writing 110 (PWM mode 1) or ‘111 (PWM mode 2) in the OCxM bits in the
TIMx_CCMRx register. The corresponding preload register must be enabled by setting the
OCxPE bit in the TIMx_CCMRx register, and eventually the auto-reload preload register (in
upcounting or center-aligned modes) by setting the ARPE bit in the TIMx_CR1 register.
As the preload registers are transferred to the shadow registers only when an update event
occurs, before starting the counter, all registers must be initialized by setting the UG bit in
the TIMx_EGR register.
OCx polarity is software programmable using the CCxP bit in the TIMx_CCER register. It
can be programmed as active high or active low. OCx output is enabled by the CCxE bit in
the TIMx_CCER register. Refer to the TIMx_CCERx register description for more details.
In PWM mode (1 or 2), TIMx_CNT and TIMx_CCRx are always compared to determine
whether TIMx_CCRx ≤ TIMx_CNT or TIMx_CNT ≤ TIMx_CCRx (depending on the direction
of the counter). However, to comply with the OCREF_CLR functionality (OCREF can be

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cleared by an external event through the ETR signal until the next PWM period), the
OCREF signal is asserted only:
• When the result of the comparison changes, or
• When the output compare mode (OCxM bits in TIMx_CCMRx register) switches from
the “frozen” configuration (no comparison, OCxM=‘000) to one of the PWM modes
(OCxM=‘110 or ‘111).
This forces the PWM by software while the timer is running.
The timer is able to generate PWM in edge-aligned mode or center-aligned mode
depending on the CMS bits in the TIMx_CR1 register.

PWM edge-aligned mode

Upcounting configuration
Upcounting is active when the DIR bit in the TIMx_CR1 register is low. Refer to the Section :
Upcounting mode on page 304.
In the following example, we consider PWM mode 1. The reference PWM signal OCxREF is
high as long as TIMx_CNT <TIMx_CCRx else it becomes low. If the compare value in
TIMx_CCRx is greater than the auto-reload value (in TIMx_ARR) then OCxREF is held at ‘1.
If the compare value is 0 then OCxREF is held at ‘0. Figure 123 shows some edge-aligned
PWM waveforms in an example where TIMx_ARR=8.
For code example refer to the Appendix section A.8.9: Center-aligned PWM configuration
example.

Figure 123. Edge-aligned PWM waveforms (ARR=8)

Counter register 0 1 2 3 4 5 6 7 8 0 1

OCXREF
CCRx=4
CCxIF

OCXREF
CCRx=8
CCxIF

OCXREF ‘1’
CCRx>8
CCxIF

OCXREF ‘0’
CCRx=0
CCxIF

MS31093V1

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Downcounting configuration
Downcounting is active when DIR bit in TIMx_CR1 register is high. Refer to Downcounting
mode on page 308
In PWM mode 1, the reference signal ocxref is low as long as TIMx_CNT>TIMx_CCRx else
it becomes high. If the compare value in TIMx_CCRx is greater than the auto-reload value in
TIMx_ARR, then ocxref is held at ‘1. 0% PWM is not possible in this mode.

PWM center-aligned mode

Center-aligned mode is active when the CMS bits in TIMx_CR1 register are different from
‘00 (all the remaining configurations having the same effect on the ocxref/OCx signals). The
compare flag is set when the counter counts up, when it counts down or both when it counts
up and down depending on the CMS bits configuration. The direction bit (DIR) in the
TIMx_CR1 register is updated by hardware and must not be changed by software. Refer to
the Center-aligned mode (up/down counting) on page 311.
Figure 124 shows some center-aligned PWM waveforms in an example where:
• TIMx_ARR=8,
• PWM mode is the PWM mode 1,
• The flag is set when the counter counts down corresponding to the center-aligned
mode 1 selected for CMS=01 in TIMx_CR1 register.

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Figure 124. Center-aligned PWM waveforms (ARR=8)

Counter register 0 1 2 3 4 5 6 7 8 7 6 5 4 3 2 1 0 1

OCxREF
CCRx = 4

CCxIF CMS=01
CMS=10
CMS=11

OCxREF
CCRx=7

CMS=10 or 11
CCxIF
‘1’
OCxREF
CCRx=8

CCxIF CMS=01
CMS=10
CMS=11
‘1’
OCxREF
CCRx>8

CCxIF CMS=01
CMS=10
CMS=11
‘0’
OCxREF
CCRx=0

CCxIF CMS=01
CMS=10
CMS=11

AI14681b

Hints on using center-aligned mode:

• When starting in center-aligned mode, the current up-down configuration is used. It
means that the counter counts up or down depending on the value written in the DIR bit
in the TIMx_CR1 register. Moreover, the DIR and CMS bits must not be changed at the
same time by the software.
• Writing to the counter while running in center-aligned mode is not recommended as it
can lead to unexpected results. In particular:
– The direction is not updated if a value greater than the auto-reload value is written
in the counter (TIMx_CNT>TIMx_ARR). For example, if the counter was counting
up, it continues to count up.
– The direction is updated if 0 or the TIMx_ARR value is written in the counter but no
Update Event UEV is generated.
• The safest way to use center-aligned mode is to generate an update by software
(setting the UG bit in the TIMx_EGR register) just before starting the counter and not to
write the counter while it is running.

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14.3.10 One-pulse mode

One-pulse mode (OPM) is a particular case of the previous modes. It allows the counter to
be started in response to a stimulus and to generate a pulse with a programmable length
after a programmable delay.
Starting the counter can be controlled through the slave mode controller. Generating the
waveform can be done in output compare mode or PWM mode. One-pulse mode is selected
by setting the OPM bit in the TIMx_CR1 register. This makes the counter stop automatically
at the next update event UEV.
A pulse can be correctly generated only if the compare value is different from the counter
initial value. Before starting (when the timer is waiting for the trigger), the configuration must
be:
• In upcounting: CNT<CCRx ≤ ARR (in particular, 0<CCRx),
• In downcounting: CNT>CCRx.

Figure 125. Example of one-pulse mode

TI2

OC1REF
OC1

TIMx_ARR
Counter

TIMx_CCR1

0
t
tDELAY tPULSE
MSv67584V1

For example one may want to generate a positive pulse on OC1 with a length of tPULSE and
after a delay of tDELAY as soon as a positive edge is detected on the TI2 input pin.
Use TI2FP2 as trigger 1:
• Map TI2FP2 on TI2 by writing CC2S=01 in the TIMx_CCMR1 register.
• TI2FP2 must detect a rising edge, write CC2P=0 and CC2NP=’0’ in the TIMx_CCER
register.
• Configure TI2FP2 as trigger for the slave mode controller (TRGI) by writing TS=110 in
the TIMx_SMCR register.
• TI2FP2 is used to start the counter by writing SMS to ‘110 in the TIMx_SMCR register
(trigger mode).

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The OPM waveform is defined by writing the compare registers (taking into account the
clock frequency and the counter prescaler).
• The tDELAY is defined by the value written in the TIMx_CCR1 register.
• The tPULSE is defined by the difference between the auto-reload value and the compare
value (TIMx_ARR - TIMx_CCR1 + 1).
• Let’s say one want to build a waveform with a transition from ‘0 to ‘1 when a compare
match occurs and a transition from ‘1 to ‘0 when the counter reaches the auto-reload
value. To do this PWM mode 2 must be enabled by writing OC1M=111 in the
TIMx_CCMR1 register. Optionally the preload registers can be enabled by writing
OC1PE=1 in the TIMx_CCMR1 register and ARPE in the TIMx_CR1 register. In this
case one has to write the compare value in the TIMx_CCR1 register, the auto-reload
value in the TIMx_ARR register, generate an update by setting the UG bit and wait for
external trigger event on TI2. CC1P is written to ‘0 in this example.
In our example, the DIR and CMS bits in the TIMx_CR1 register should be low.
For code example refer to the Appendix section A.8.16: One-Pulse mode.
Since only 1 pulse (Single mode) is needed, a 1 must be written in the OPM bit in the
TIMx_CR1 register to stop the counter at the next update event (when the counter rolls over
from the auto-reload value back to 0). When OPM bit in the TIMx_CR1 register is set to '0',
so the Repetitive Mode is selected.

Particular case: OCx fast enable

In One-pulse mode, the edge detection on TIx input set the CEN bit which enables the
counter. Then the comparison between the counter and the compare value makes the
output toggle. But several clock cycles are needed for these operations and it limits the
minimum delay tDELAY min we can get.
If one wants to output a waveform with the minimum delay, the OCxFE bit can be set in the
TIMx_CCMRx register. Then OCxRef (and OCx) are forced in response to the stimulus,
without taking in account the comparison. Its new level is the same as if a compare match
had occurred. OCxFE acts only if the channel is configured in PWM1 or PWM2 mode.
For code example refer to the part of code, conditioned by PULSE_WITHOUT_DELAY > 0
in the Appendix section A.8.16: One-Pulse mode.

14.3.11 Clearing the OCxREF signal on an external event

1. The external trigger prescaler should be kept off: bits ETPS[1:0] in the TIMx_SMCR
register are cleared to 00.
2. The external clock mode 2 must be disabled: bit ECE in the TIM1_SMCR register is
cleared to 0.
3. The external trigger polarity (ETP) and the external trigger filter (ETF) can be
configured according to the application’s needs.
For code example refer to the Appendix section A.8.10: ETR configuration to clear
OCxREF.
Figure 126 shows the behavior of the OCxREF signal when the ETRF input becomes high,
for both values of the OCxCE enable bit. In this example, the timer TIMx is programmed in
PWM mode.

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Figure 126. Clearing TIMx OCxREF

(CCRx)

Counter (CNT)

ETRF

OCxREF
(OCxCE = ‘0’)

OCxREF
(OCxCE = ‘1’)

OCxREF_CLR OCxREF_CLR
becomes high still high
MS33105V1

1. In case of a PWM with a 100% duty cycle (if CCRx>ARR), OCxREF is enabled again at the next counter
overflow.

14.3.12 Encoder interface mode

To select Encoder Interface mode write SMS=‘001 in the TIMx_SMCR register if the counter
is counting on TI2 edges only, SMS=010 if it is counting on TI1 edges only and SMS=011 if
it is counting on both TI1 and TI2 edges.
Select the TI1 and TI2 polarity by programming the CC1P and CC2P bits in the TIMx_CCER
register. CC1NP and CC2NP must be kept cleared. When needed, the input filter can be
programmed as well.
The two inputs TI1 and TI2 are used to interface to an incremental encoder. Refer to
Table 47. The counter is clocked by each valid transition on TI1FP1 or TI2FP2 (TI1 and TI2
after input filter and polarity selection, TI1FP1=TI1 if not filtered and not inverted,
TI2FP2=TI2 if not filtered and not inverted) assuming that it is enabled (CEN bit in
TIMx_CR1 register written to ‘1). The sequence of transitions of the two inputs is evaluated
and generates count pulses as well as the direction signal. Depending on the sequence the
counter counts up or down, the DIR bit in the TIMx_CR1 register is modified by hardware
accordingly. The DIR bit is calculated at each transition on any input (TI1 or TI2), whatever
the counter is counting on TI1 only, TI2 only or both TI1 and TI2.
Encoder interface mode acts simply as an external clock with direction selection. This
means that the counter just counts continuously between 0 and the auto-reload value in the
TIMx_ARR register (0 to ARR or ARR down to 0 depending on the direction). So the
TIMx_ARR must be configured before starting. In the same way, the capture, compare,
prescaler, trigger output features continue to work as normal.
In this mode, the counter is modified automatically following the speed and the direction of
the incremental encoder and its content, therefore, always represents the encoder’s

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position. The count direction correspond to the rotation direction of the connected sensor.
The table summarizes the possible combinations, assuming TI1 and TI2 do not switch at the
same time.

Table 47. Counting direction versus encoder signals

Level on opposite TI1FP1 signal TI2FP2 signal
Active edge signal (TI1FP1 for
TI2, TI2FP2 for TI1) Rising Falling Rising Falling

Counting on High Down Up No Count No Count

TI1 only Low Up Down No Count No Count

Counting on High No Count No Count Up Down

TI2 only Low No Count No Count Down Up

Counting on High Down Up Up Down

TI1 and TI2 Low Up Down Down Up

An external incremental encoder can be connected directly to the MCU without external
interface logic. However, comparators are normally be used to convert the encoder’s
differential outputs to digital signals. This greatly increases noise immunity. The third
encoder output which indicate the mechanical zero position, may be connected to an
external interrupt input and trigger a counter reset.
Figure 127 gives an example of counter operation, showing count signal generation and
direction control. It also shows how input jitter is compensated where both edges are
selected. This might occur if the sensor is positioned near to one of the switching points. For
this example we assume that the configuration is the following:
• CC1S= 01 (TIMx_CCMR1 register, TI1FP1 mapped on TI1)
• CC2S= 01 (TIMx_CCMR2 register, TI2FP2 mapped on TI2)
• CC1P=0, CC1NP = ‘0’ (TIMx_CCER register, TI1FP1 noninverted, TI1FP1=TI1)
• CC2P=0, CC2NP = ‘0’ (TIMx_CCER register, TI2FP2 noninverted, TI2FP2=TI2)
• SMS= 011 (TIMx_SMCR register, both inputs are active on both rising and falling
edges)
• CEN= 1 (TIMx_CR1 register, Counter is enabled)
For code example refer to the Appendix section A.8.10: ETR configuration to clear
OCxREF.

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Figure 127. Example of counter operation in encoder interface mode

forward jitter backward jitter forward

TI1

TI2

Counter

up down up

MS33107V1

Figure 128 gives an example of counter behavior when TI1FP1 polarity is inverted (same
configuration as above except CC1P=1).

Figure 128. Example of encoder interface mode with TI1FP1 polarity inverted

forward jitter backward jitter forward

TI1

TI2

Counter

down up down

MS33108V1

The timer, when configured in Encoder Interface mode provides information on the sensor’s
current position. Dynamic information can be obtained (speed, acceleration, deceleration)
by measuring the period between two encoder events using a second timer configured in
capture mode. The output of the encoder which indicates the mechanical zero can be used
for this purpose. Depending on the time between two events, the counter can also be read
at regular times. This can be done by latching the counter value into a third input capture
register if available (then the capture signal must be periodic and can be generated by
another timer). when available, it is also possible to read its value through a DMA request
generated by a Real-Time clock.

14.3.13 Timer input XOR function

The TI1S bit in the TIM1_CR2 register, allows the input filter of channel 1 to be connected to
the output of a XOR gate, combining the three input pins TIMx_CH1 to TIMx_CH3.
The XOR output can be used with all the timer input functions such as trigger or input
capture.

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An example of this feature used to interface Hall sensors is given in Section 13.3.18 on
page 266.

14.3.14 Timers and external trigger synchronization

The TIMx Timers can be synchronized with an external trigger in several modes: Reset
mode, Gated mode and Trigger mode.

Slave mode: Reset mode

The counter and its prescaler can be reinitialized in response to an event on a trigger input.
Moreover, if the URS bit from the TIMx_CR1 register is low, an update event UEV is
generated. Then all the preloaded registers (TIMx_ARR, TIMx_CCRx) are updated.
In the following example, the upcounter is cleared in response to a rising edge on TI1 input:
• Configure the channel 1 to detect rising edges on TI1. Configure the input filter duration
(in this example, we do not need any filter, so we keep IC1F=0000). The capture
prescaler is not used for triggering, so it does not need to be configured. The CC1S bits
select the input capture source only, CC1S = 01 in the TIMx_CCMR1 register. Write
CC1P=0 and CC1NP=0 in TIMx_CCER register to validate the polarity (and detect
rising edges only).
• Configure the timer in reset mode by writing SMS=100 in TIMx_SMCR register. Select
TI1 as the input source by writing TS=101 in TIMx_SMCR register.
• Start the counter by writing CEN=1 in the TIMx_CR1 register.
For code example refer to the Appendix section A.8.12: Reset mode.
The counter starts counting on the internal clock, then behaves normally until TI1 rising
edge. When TI1 rises, the counter is cleared and restarts from 0. In the meantime, the
trigger flag is set (TIF bit in the TIMx_SR register) and an interrupt request, or a DMA
request can be sent if enabled (depending on the TIE and TDE bits in TIMx_DIER register).
The following figure shows this behavior when the auto-reload register TIMx_ARR=0x36.
The delay between the rising edge on TI1 and the actual reset of the counter is due to the
resynchronization circuit on TI1 input.

Figure 129. Control circuit in reset mode

TI1

UG

Counter clock = ck_cnt = ck_psc

Counter register 30 31 32 33 34 35 36 00 01 02 03 00 01 02 03

TIF

MS31401V2

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Slave mode: Gated mode

The counter can be enabled depending on the level of a selected input.
In the following example, the upcounter counts only when TI1 input is low:
• Configure the channel 1 to detect low levels on TI1. Configure the input filter duration
(in this example, we do not need any filter, so we keep IC1F=0000). The capture
prescaler is not used for triggering, so it does not need to be configured. The CC1S bits
select the input capture source only, CC1S=01 in TIMx_CCMR1 register. Write
CC1P=1 and CC1NP=0 in TIMx_CCER register to validate the polarity (and detect low
level only).
• Configure the timer in gated mode by writing SMS=101 in TIMx_SMCR register. Select
TI1 as the input source by writing TS=101 in TIMx_SMCR register.
• Enable the counter by writing CEN=1 in the TIMx_CR1 register (in gated mode, the
counter doesn’t start if CEN=0, whatever is the trigger input level).
For code example refer to the Appendix section A.8.13: Gated mode.
The counter starts counting on the internal clock as long as TI1 is low and stops as soon as
TI1 becomes high. The TIF flag in the TIMx_SR register is set both when the counter starts
or stops.
The delay between the rising edge on TI1 and the actual stop of the counter is due to the
resynchronization circuit on TI1 input.

Figure 130. Control circuit in gated mode

TI1

cnt_en

Counter clock = ck_cnt = ck_psc

Counter register 30 31 32 33 34 35 36 37 38

TIF

Write TIF=0

MS31402V1

1. The configuration “CCxP=CCxNP=1” (detection of both rising and falling edges) does not have any effect
in gated mode because gated mode acts on a level and not on an edge.

Slave mode: Trigger mode

The counter can start in response to an event on a selected input.
In the following example, the upcounter starts in response to a rising edge on TI2 input:
• Configure the channel 2 to detect rising edges on TI2. Configure the input filter duration
(in this example, we do not need any filter, so we keep IC2F=0000). The capture
prescaler is not used for triggering, so it does not need to be configured. CC2S bits are
selecting the input capture source only, CC2S=01 in TIMx_CCMR1 register. Write

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CC2P=1 and CC2NP=0 in TIMx_CCER register to validate the polarity (and detect low
level only).
• Configure the timer in trigger mode by writing SMS=110 in TIMx_SMCR register. Select
TI2 as the input source by writing TS=110 in TIMx_SMCR register.
For code example refer to the Appendix section A.8.14: Trigger mode.
When a rising edge occurs on TI2, the counter starts counting on the internal clock and the
TIF flag is set.
The delay between the rising edge on TI2 and the actual start of the counter is due to the
resynchronization circuit on TI2 input.

Figure 131. Control circuit in trigger mode

TI2

cnt_en

Counter clock = ck_cnt = ck_psc

Counter register 34 35 36 37 38

TIF

MS31403V1

Slave mode: External Clock mode 2 + trigger mode

The external clock mode 2 can be used in addition to another slave mode (except external
clock mode 1 and encoder mode). In this case, the ETR signal is used as external clock
input, and another input can be selected as trigger input when operating in reset mode,
gated mode or trigger mode. It is recommended not to select ETR as TRGI through the TS
bits of TIMx_SMCR register.
In the following example, the upcounter is incremented at each rising edge of the ETR
signal as soon as a rising edge of TI1 occurs:

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1. Configure the external trigger input circuit by programming the TIMx_SMCR register as
follows:
– ETF = 0000: no filter
– ETPS=00: prescaler disabled
– ETP=0: detection of rising edges on ETR and ECE=1 to enable the external clock
mode 2.
2. Configure the channel 1 as follows, to detect rising edges on TI:
– IC1F=0000: no filter.
– The capture prescaler is not used for triggering and does not need to be
configured.
– CC1S=01in TIMx_CCMR1 register to select only the input capture source
– CC1P=0 and CC1NP=0 in TIMx_CCER register to validate the polarity (and detect
rising edge only).
3. Configure the timer in trigger mode by writing SMS=110 in TIMx_SMCR register. Select
TI1 as the input source by writing TS=101 in TIMx_SMCR register.
For code example refer to the Appendix section A.8.15: External clock mode 2 + trigger
mode.
A rising edge on TI1 enables the counter and sets the TIF flag. The counter then counts on
ETR rising edges.
The delay between the rising edge of the ETR signal and the actual reset of the counter is
due to the resynchronization circuit on ETRP input.

Figure 132. Control circuit in external clock mode 2 + trigger mode

TI1

CEN/CNT_EN

ETR

Counter clock = CK_CNT = CK_PSC

Counter register 34 35 36

TIF

MS33110V1

14.3.15 Timer synchronization

The TIMx timers are linked together internally for timer synchronization or chaining. When
one Timer is configured in Master Mode, it can reset, start, stop or clock the counter of
another Timer configured in Slave Mode.

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Figure 133: Master/Slave timer example presents an overview of the trigger selection and
the master mode selection blocks.

Using one timer as prescaler for another

Figure 133. Master/Slave timer example

TIM1 TIM3
Clock
TS
MMS SMS

UEV
Master Slave CK_PSC
TRGO1 ITR1
mode mode
Prescaler Counter control control
Prescaler Counter

Input
trigger
selection

MS33125V1

For example, Timer 1 can be configured to act as a prescaler for Timer 3. Refer to
Figure 133. To do this:
• Configure Timer 1 in master mode so that it outputs a periodic trigger signal on each
update event UEV. If MMS=010 is written in the TIM1_CR2 register, a rising edge is
output on TRGO1 each time an update event is generated.
• To connect the TRGO1 output of Timer 1 to Timer 3, Timer 3 must be configured in
slave mode using ITR1 as internal trigger. This is selected through the TS bits in the
TIM3_SMCR register (writing TS=000).
• Then the Timer2's slave mode controller should be configured in external clock mode 1
(write SMS=111 in the TIM3_SMCR register). This causes Timer 3 to be clocked by the
rising edge of the periodic Timer 1 trigger signal (which correspond to the timer 1
counter overflow).
• Finally both timers must be enabled by setting their respective CEN bits within their
respective TIMx_CR1 registers. Make sure to enable Timer2 before enabling Timer1.
For code example refer to the Appendix section A.8.17: Timer prescaling another timer.
Note: If OCx is selected on Timer 1 as trigger output (MMS=1xx), its rising edge is used to clock
the counter of timer 3.

Using one timer to enable another timer

In this example, we control the enable of Timer 3 with the output compare 1 of Timer 1.
Refer to Figure 133 for connections. Timer 3 counts on the divided internal clock only when

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OC1REF of Timer 1 is high. Both counter clock frequencies are divided by 3 by the
prescaler compared to CK_INT (fCK_CNT = fCK_INT/3).
• Configure Timer 1 master mode to send its Output Compare 1 Reference (OC1REF)
signal as trigger output (MMS=100 in the TIM1_CR2 register).
• Configure the Timer 1 OC1REF waveform (TIM1_CCMR1 register).
• Configure Timer 3 to get the input trigger from Timer 1 (TS=000 in the TIM3_SMCR
register).
• Configure Timer 3 in gated mode (SMS=101 in TIM3_SMCR register).
• Enable Timer 3 by writing ‘1 in the CEN bit (TIM3_CR1 register).
• Start Timer 1 by writing ‘1 in the CEN bit (TIM1_CR1 register).
For code example refer to the Appendix section A.8.18: Timer enabling another timer.
Note: The counter 3 clock is not synchronized with counter 1, this mode only affects the Timer 3
counter enable signal.

Figure 134. Gating timer 3 with OC1REF of timer 1

CK_INT

TIMER1-OC1REF

TIMER1-CNT FC FD FE FF 00 01

TIMER3-CNT 3045 3046 3047 3048

TIMER3-TIF

Write TIF = 0
MS33127V1

In the example in Figure 134, the Timer 3 counter and prescaler are not initialized before
being started. So they start counting from their current value. It is possible to start from a
given value by resetting both timers before starting Timer 1. Then any value can be written
in the timer counters. The timers can easily be reset by software using the UG bit in the
TIMx_EGR registers.
In the next example, we synchronize Timer 1 and Timer 3. Timer 1 is the master and starts
from 0. Timer 3 is the slave and starts from 0xE7. The prescaler ratio is the same for both

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timers. Timer 3 stops when Timer 1 is disabled by writing ‘0 to the CEN bit in the TIM1_CR1
register:
• Configure Timer 1 master mode to send its Counter Enable signal (CNT_EN) as a
trigger output (MMS=001 in the TIM1_CR2 register).
• Configure the Timer 1 OC1REF waveform (TIM1_CCMR1 register).
• Configure Timer 3 to get the input trigger from Timer 1 (TS=000 in the TIM3_SMCR
register).
• Configure Timer 3 in gated mode (SMS=101 in TIM3_SMCR register).
• Reset Timer 1 by writing ‘1 in UG bit (TIM1_EGR register).
• Reset Timer 3 by writing ‘1 in UG bit (TIM3_EGR register).
• Initialize Timer 3 to 0xE7 by writing ‘0xE7’ in the timer 3 counter (TIM3_CNTL).
• Enable Timer 3 by writing ‘1 in the CEN bit (TIM3_CR1 register).
• Start Timer 1 by writing ‘1 in the CEN bit (TIM1_CR1 register).
• Stop Timer 1 by writing ‘0 in the CEN bit (TIM1_CR1 register).
For code example refer to the Appendix section A.8.19: Master and slave synchronization.

Figure 135. Gating timer 3 with Enable of timer 1

CK_INT

TIMER1-CEN=CNT_EN

TIMER1-CNT_INIT

TIMER1-CNT 75 00 01 02

TIMER3-CNT AB 00 E7 E8 E9

TIMER3-CNT_INIT

TIMER3-write CNT

TIMER3-TIF

Write TIF = 0
MS33129V1

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Using one timer to start another timer

In this example, we set the enable of Timer 3 with the update event of Timer 1. Refer to
Figure 133 for connections. Timer 3 starts counting from its current value (which can be
nonzero) on the divided internal clock as soon as the update event is generated by Timer 1.
When Timer 3 receives the trigger signal its CEN bit is automatically set and the counter
counts until we write ‘0 to the CEN bit in the TIM3_CR1 register. Both counter clock
frequencies are divided by 3 by the prescaler compared to CK_INT (fCK_CNT = fCK_INT/3).
• Configure Timer 1 master mode to send its Update Event (UEV) as trigger output
(MMS=010 in the TIM1_CR2 register).
• Configure the Timer 1 period (TIM1_ARR registers).
• Configure Timer 3 to get the input trigger from Timer 1 (TS=000 in the TIM3_SMCR
register).
• Configure Timer 3 in trigger mode (SMS=110 in TIM3_SMCR register).
• Start Timer 1 by writing ‘1 in the CEN bit (TIM1_CR1 register).

Figure 136. Triggering timer 3 with update of timer 1

CK_INT

TIMER1-UEV

TIMER1-CNT FD FE FF 00 01 02

TIMER3-CNT 45 46 47 48

TIMER3-CEN=CNT_EN

TIMER3-TIF

Write TIF = 0
MS33131V1

As in the previous example, both counters can be initialized before starting counting.
Figure 137 shows the behavior with the same configuration as in Figure 136 but in trigger
mode instead of gated mode (SMS=110 in the TIM3_SMCR register).

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Figure 137. Triggering timer 3 with Enable of timer 1

CK_INT

TIMER1-CEN=CNT_EN

TIMER1-CNT_INIT

TIMER1-CNT 75 00 01 02

TIMER3-CNT CD 00 E7 E8 E9 EA

TIMER3-CNT_INIT

TIMER3
write CNT

TIMER3-TIF

Write TIF = 0

MS33133V1

Starting 2 timers synchronously in response to an external trigger

In this example, we set the enable of timer 1 when its TI1 input rises, and the enable of
Timer 3 with the enable of Timer 1. Refer to Figure 133 for connections. To ensure the
counters are aligned, Timer 1 must be configured in Master/Slave mode (slave with respect
to TI1, master with respect to Timer 3):
• Configure Timer 1 master mode to send its Enable as trigger output (MMS=001 in the
TIM1_CR2 register).
• Configure Timer 1 slave mode to get the input trigger from TI1 (TS=100 in the
TIM1_SMCR register).
• Configure Timer 1 in trigger mode (SMS=110 in the TIM1_SMCR register).
• Configure the Timer 1 in Master/Slave mode by writing MSM=1 (TIM1_SMCR register).
• Configure Timer 3 to get the input trigger from Timer 1 (TS=000 in the TIM3_SMCR
register).
• Configure Timer 3 in trigger mode (SMS=110 in the TIM3_SMCR register).
For code example refer to the Appendix section A.8.20: Two timers synchronized by an
external trigger.
When a rising edge occurs on TI1 (Timer 1), both counters starts counting synchronously on
the internal clock and both TIF flags are set.
Note: In this example both timers are initialized before starting (by setting their respective UG
bits). Both counters starts from 0, but an offset can easily be inserted between them by
writing any of the counter registers (TIMx_CNT). One can see that the master/slave mode
insert a delay between CNT_EN and CK_PSC on timer 1.

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Figure 138. Triggering timer 1 and 3 with timer 1 TI1 input

CK_INT

TIMER1-TI1

TIMER1-CEN=CNT_EN

TIMER1-CK_PSC

TIMER1-CNT 00 01 02 03 04 05 06 07 08 09

TIMER1-TIF
TIMER3-CEN=CNT_EN

TIMER3-CK_PSC

TIMER3-CNT 00 01 02 03 04 05 06 07 08 09

TIMER3-TIF

MS33135V1

14.3.16 Debug mode

When the microcontroller enters debug mode (Arm® Cortex®-M0 core - halted), the TIMx
counter either continues to work normally or stops, depending on DBG_TIMx_STOP
configuration bit in DBGMCU module.

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14.4 TIM3 registers

Refer to Section 1.2 on page 33 for a list of abbreviations used in register descriptions.
The peripheral registers can be accessed by half-words (16-bit) or words (32-bit).

14.4.1 TIM3 control register 1 (TIM3_CR1)

Address offset: 0x00
Reset value: 0x0000

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. CKD[1:0] ARPE CMS[1:0] DIR OPM URS UDIS CEN
rw rw rw rw rw rw rw rw rw rw

Bits 15:10 Reserved, must be kept at reset value.

Bits 9:8 CKD: Clock division
This bit-field indicates the division ratio between the timer clock (CK_INT) frequency and
sampling clock used by the digital filters (ETR, TIx),
00: tDTS = tCK_INT
01: tDTS = 2 × tCK_INT
10: tDTS = 4 × tCK_INT
11: Reserved
Bit 7 ARPE: Auto-reload preload enable
0: TIMx_ARR register is not buffered
1: TIMx_ARR register is buffered
Bits 6:5 CMS[1:0]: Center-aligned mode selection
00: Edge-aligned mode. The counter counts up or down depending on the direction bit
(DIR).
01: Center-aligned mode 1. The counter counts up and down alternatively. Output compare
interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set
only when the counter is counting down.
10: Center-aligned mode 2. The counter counts up and down alternatively. Output compare
interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set
only when the counter is counting up.
11: Center-aligned mode 3. The counter counts up and down alternatively. Output compare
interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set
both when the counter is counting up or down.
Note: It is not allowed to switch from edge-aligned mode to center-aligned mode as long as
the counter is enabled (CEN=1)
Bit 4 DIR: Direction
0: Counter used as upcounter
1: Counter used as downcounter
Note: This bit is read only when the timer is configured in Center-aligned mode or Encoder
mode.
Bit 3 OPM: One-pulse mode
0: Counter is not stopped at update event
1: Counter stops counting at the next update event (clearing the bit CEN)

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Bit 2 URS: Update request source

This bit is set and cleared by software to select the UEV event sources.
0: Any of the following events generate an update interrupt or DMA request if enabled.
These events can be:
– Counter overflow/underflow
– Setting the UG bit
– Update generation through the slave mode controller
1: Only counter overflow/underflow generates an update interrupt or DMA request if
enabled.
Bit 1 UDIS: Update disable
This bit is set and cleared by software to enable/disable UEV event generation.
0: UEV enabled. The Update (UEV) event is generated by one of the following events:
– Counter overflow/underflow
– Setting the UG bit
– Update generation through the slave mode controller
Buffered registers are then loaded with their preload values.
1: UEV disabled. The Update event is not generated, shadow registers keep their value
(ARR, PSC, CCRx). However the counter and the prescaler are reinitialized if the UG bit is
set or if a hardware reset is received from the slave mode controller.
Bit 0 CEN: Counter enable
0: Counter disabled
1: Counter enabled
Note: External clock, gated mode and encoder mode can work only if the CEN bit has been
previously set by software. However trigger mode can set the CEN bit automatically by
hardware.
CEN is cleared automatically in one-pulse mode, when an update event occurs.

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14.4.2 TIM3 control register 2 (TIM3_CR2)

Address offset: 0x04
Reset value: 0x0000

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. TI1S MMS[2:0] CCDS Res. Res. Res.
rw rw rw rw rw

Bits 15:8 Reserved, must be kept at reset value.

Bit 7 TI1S: TI1 selection
0: The TIMx_CH1 pin is connected to TI1 input
1: The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination)
See also Section 13.3.18: Interfacing with Hall sensors on page 266
Bits 6:4 MMS: Master mode selection
These bits allow to select the information to be sent in master mode to slave timers for
synchronization (TRGO). The combination is as follows:
000: Reset - the UG bit from the TIMx_EGR register is used as trigger output (TRGO). If the
reset is generated by the trigger input (slave mode controller configured in reset mode) then
the signal on TRGO is delayed compared to the actual reset.
001: Enable - the Counter enable signal, CNT_EN, is used as trigger output (TRGO). It is
useful to start several timers at the same time or to control a window in which a slave timer is
enabled. The Counter Enable signal is generated by a logic OR between CEN control bit
and the trigger input when configured in gated mode.
When the Counter Enable signal is controlled by the trigger input, there is a delay on TRGO,
except if the master/slave mode is selected (see the MSM bit description in TIMx_SMCR
register).
010: Update - The update event is selected as trigger output (TRGO). For instance a master
timer can then be used as a prescaler for a slave timer.
011: Compare Pulse - The trigger output send a positive pulse when the CC1IF flag is to be
set (even if it was already high), as soon as a capture or a compare match occurred.
(TRGO)
100: Compare - OC1REF signal is used as trigger output (TRGO)
101: Compare - OC2REF signal is used as trigger output (TRGO)
110: Compare - OC3REF signal is used as trigger output (TRGO)
111: Compare - OC4REF signal is used as trigger output (TRGO)
Bit 3 CCDS: Capture/compare DMA selection
0: CCx DMA request sent when CCx event occurs
1: CCx DMA requests sent when update event occurs
Bits 2:0 Reserved, must be kept at reset value.

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14.4.3 TIM3 slave mode control register (TIM3_SMCR)

Address offset: 0x08
Reset value: 0x0000

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETP ECE ETPS[1:0] ETF[3:0] MSM TS[2:0] OCCS SMS[2:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bit 15 ETP: External trigger polarity

This bit selects whether ETR or ETR is used for trigger operations
0: ETR is noninverted, active at high level or rising edge
1: ETR is inverted, active at low level or falling edge
Bit 14 ECE: External clock enable
This bit enables External clock mode 2.
0: External clock mode 2 disabled
1: External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF
signal.
1: Setting the ECE bit has the same effect as selecting external clock mode 1 with TRGI
connected to ETRF (SMS=111 and TS=111).
2: It is possible to simultaneously use external clock mode 2 with the following slave modes:
reset mode, gated mode and trigger mode. Nevertheless, TRGI must not be connected to
ETRF in this case (TS bits must not be 111).
3: If external clock mode 1 and external clock mode 2 are enabled at the same time, the
external clock input is ETRF.
Bits 13:12 ETPS[1:0]: External trigger prescaler
External trigger signal ETRP frequency must be at most 1/4 of CK_INT frequency. A prescaler
can be enabled to reduce ETRP frequency. It is useful when inputting fast external clocks.
00: Prescaler OFF
01: ETRP frequency divided by 2
10: ETRP frequency divided by 4
11: ETRP frequency divided by 8

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Bits 11:8 ETF[3:0]: External trigger filter

This bit-field defines the frequency used to sample ETRP signal and the length of the digital
filter applied to ETRP. The digital filter is made of an event counter in which N consecutive
events are needed to validate a transition on the output:
0000: No filter, sampling is done at fDTS
0001: fSAMPLING = fCK_INT, N = 2
0010: fSAMPLING = fCK_INT, N = 4
0011: fSAMPLING = fCK_INT, N = 8
0100: fSAMPLING = fDTS / 2, N = 6
0101: fSAMPLING = fDTS / 2, N = 8
0110: fSAMPLING = fDTS / 4, N = 6
0111: fSAMPLING = fDTS / 4, N = 8
1000: fSAMPLING = fDTS / 8, N = 6
1001: fSAMPLING = fDTS / 8, N = 8
1010: fSAMPLING = fDTS / 16, N = 5
1011: fSAMPLING = fDTS / 16, N = 6
1100: fSAMPLING = fDTS / 16, N = 8
1101: fSAMPLING = fDTS / 32, N = 5
1110: fSAMPLING = fDTS / 32, N = 6
1111: fSAMPLING = fDTS / 32, N = 8
Note: Care must be taken that fDTS is replaced in the formula by CK_INT when ETF[3:0] = 1,
2 or 3.
Bit 7 MSM: Master/Slave mode
0: No action
1: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect
synchronization between the current timer and its slaves (through TRGO). It is useful if we
want to synchronize several timers on a single external event.
Bits 6:4 TS: Trigger selection
This bit-field selects the trigger input to be used to synchronize the counter.
000: Internal Trigger 0 (ITR0).
001: Internal Trigger 1 (ITR1).
010: Internal Trigger 2 (ITR2).
011: Internal Trigger 3 (ITR3).
100: TI1 Edge Detector (TI1F_ED)
101: Filtered Timer Input 1 (TI1FP1)
110: Filtered Timer Input 2 (TI2FP2)
111: External Trigger input (ETRF)
See Table 48: TIM3 internal trigger connection for more details on ITRx meaning for each
Timer.
Note: These bits must be changed only when they are not used (e.g. when SMS=000) to
avoid wrong edge detections at the transition.
Bit 3 OCCS: OCREF clear selection.
This bit is used to select the OCREF clear source.
0:OCREF_CLR_INT is connected to the OCREF_CLR input
1: OCREF_CLR_INT is connected to ETRF

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Bits 2:0 SMS: Slave mode selection

When external signals are selected the active edge of the trigger signal (TRGI) is linked to the
polarity selected on the external input (see Input Control register and Control Register
description.
000: Slave mode disabled - if CEN = ‘1 then the prescaler is clocked directly by the internal
clock.
001: Encoder mode 1 - Counter counts up/down on TI1FP1 edge depending on TI2FP2
level.
010: Encoder mode 2 - Counter counts up/down on TI2FP2 edge depending on TI1FP1
level.
011: Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges
depending on the level of the other input.
100: Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter
and generates an update of the registers.
101: Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The
counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of
the counter are controlled.
110: Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not
reset). Only the start of the counter is controlled.
111: External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter.
Note: The gated mode must not be used if TI1F_ED is selected as the trigger input (TS=100).
Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the gated mode
checks the level of the trigger signal.
Note: The clock of the slave timer must be enabled prior to receive events from the master
timer, and must not be changed on-the-fly while triggers are received from the master
timer.

Table 48. TIM3 internal trigger connection

Slave TIM ITR0 (TS = 000) ITR2 (TS = 010) ITR3 (TS = 011)

TIM3 TIM1 TIM15 TIM14

14.4.4 TIM3 DMA/Interrupt enable register (TIM3_DIER)

Address offset: 0x0C
Reset value: 0x0000

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. TDE Res. CC4DE CC3DE CC2DE CC1DE UDE Res. TIE Res. CC4IE CC3IE CC2IE CC1IE UIE
rw rw rw rw rw rw rw rw rw rw rw rw

Bit 15 Reserved, must be kept at reset value.

Bit 14 TDE: Trigger DMA request enable
0: Trigger DMA request disabled.
1: Trigger DMA request enabled.
Bit 13 Reserved, must be kept at reset value.
Bit 12 CC4DE: Capture/Compare 4 DMA request enable
0: CC4 DMA request disabled.
1: CC4 DMA request enabled.

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Bit 11 CC3DE: Capture/Compare 3 DMA request enable

0: CC3 DMA request disabled.
1: CC3 DMA request enabled.
Bit 10 CC2DE: Capture/Compare 2 DMA request enable
0: CC2 DMA request disabled.
1: CC2 DMA request enabled.
Bit 9 CC1DE: Capture/Compare 1 DMA request enable
0: CC1 DMA request disabled.
1: CC1 DMA request enabled.
Bit 8 UDE: Update DMA request enable
0: Update DMA request disabled.
1: Update DMA request enabled.
Bit 7 Reserved, must be kept at reset value.
Bit 6 TIE: Trigger interrupt enable
0: Trigger interrupt disabled.
1: Trigger interrupt enabled.
Bit 5 Reserved, must be kept at reset value.
Bit 4 CC4IE: Capture/Compare 4 interrupt enable
0: CC4 interrupt disabled.
1: CC4 interrupt enabled.
Bit 3 CC3IE: Capture/Compare 3 interrupt enable
0: CC3 interrupt disabled
1: CC3 interrupt enabled
Bit 2 CC2IE: Capture/Compare 2 interrupt enable
0: CC2 interrupt disabled
1: CC2 interrupt enabled
Bit 1 CC1IE: Capture/Compare 1 interrupt enable
0: CC1 interrupt disabled
1: CC1 interrupt enabled
Bit 0 UIE: Update interrupt enable
0: Update interrupt disabled
1: Update interrupt enabled

14.4.5 TIM3 status register (TIM3_SR)

Address offset: 0x10
Reset value: 0x0000

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. CC4OF CC3OF CC2OF CC1OF Res. Res. TIF Res. CC4IF CC3IF CC2IF CC1IF UIF
rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0

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Bits 15:13 Reserved, must be kept at reset value.

Bit 12 CC4OF: Capture/Compare 4 overcapture flag
Refer to CC1OF description
Bit 11 CC3OF: Capture/Compare 3 overcapture flag
Refer to CC1OF description
Bit 10 CC2OF: Capture/compare 2 overcapture flag
Refer to CC1OF description
Bit 9 CC1OF: Capture/Compare 1 overcapture flag
This flag is set by hardware only when the corresponding channel is configured in input capture
mode. It is cleared by software by writing it to ‘0.
0: No overcapture has been detected
1: The counter value has been captured in TIMx_CCR1 register while CC1IF flag was
already set
Bits 8:7 Reserved, must be kept at reset value.
Bit 6 TIF: Trigger interrupt flag
This flag is set by hardware on trigger event (active edge detected on TRGI input when the
slave mode controller is enabled in all modes but gated mode. It is set when the counter starts
or stops when gated mode is selected. It is cleared by software.
0: No trigger event occurred
1: Trigger interrupt pending
Bit 5 Reserved, must be kept at reset value.
Bit 4 CC4IF: Capture/Compare 4 interrupt flag
Refer to CC1IF description
Bit 3 CC3IF: Capture/Compare 3 interrupt flag
Refer to CC1IF description

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Bit 2 CC2IF: Capture/Compare 2 interrupt flag

Refer to CC1IF description
Bit 1 CC1IF: Capture/compare 1 interrupt flag
If channel CC1 is configured as output:
This flag is set by hardware when the counter matches the compare value, with some
exception in center-aligned mode (refer to the CMS bits in the TIMx_CR1 register description).
It is cleared by software.
0: No match
1: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register.
When the contents of TIMx_CCR1 are greater than the contents of TIMx_ARR, the CC1IF bit
goes high on the counter overflow (in upcounting and up/down-counting modes) or underflow
(in downcounting mode)
If channel CC1 is configured as input:
This bit is set by hardware on a capture. It is cleared by software or by reading the
TIMx_CCR1 register.
0: No input capture occurred
1: The counter value has been captured in TIMx_CCR1 register (An edge has been detected
on IC1 which matches the selected polarity)
Bit 0 UIF: Update interrupt flag
This bit is set by hardware on an update event. It is cleared by software.
0: No update occurred.
1: Update interrupt pending.
This bit is set by hardware when the registers are updated:
At overflow or underflow and if UDIS=0 in the TIMx_CR1 register.
When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=0 and
UDIS=0 in the TIMx_CR1 register.
When CNT is reinitialized by a trigger event (refer to the synchro control register description), if
URS=0 and UDIS=0 in the TIMx_CR1 register.

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14.4.6 TIM3 event generation register (TIM3_EGR)

Address offset: 0x14
Reset value: 0x0000

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. TG Res. CC4G CC3G CC2G CC1G UG
w w w w w w

Bits 15:7 Reserved, must be kept at reset value.

Bit 6 TG: Trigger generation
This bit is set by software in order to generate an event, it is automatically cleared by hardware.
0: No action
1: The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if
enabled.
Bit 5 Reserved, must be kept at reset value.
Bit 4 CC4G: Capture/compare 4 generation
Refer to CC1G description
Bit 3 CC3G: Capture/compare 3 generation
Refer to CC1G description
Bit 2 CC2G: Capture/compare 2 generation
Refer to CC1G description
Bit 1 CC1G: Capture/compare 1 generation
This bit is set by software in order to generate an event, it is automatically cleared by hardware.
0: No action
1: A capture/compare event is generated on channel 1:
If channel CC1 is configured as output:
CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled.
If channel CC1 is configured as input:
The current value of the counter is captured in TIMx_CCR1 register. The CC1IF flag is set,
the corresponding interrupt or DMA request is sent if enabled. The CC1OF flag is set if the
CC1IF flag was already high.
Bit 0 UG: Update generation
This bit can be set by software, it is automatically cleared by hardware.
0: No action
1: Re-initialize the counter and generates an update of the registers. Note that the prescaler
counter is cleared too (anyway the prescaler ratio is not affected). The counter is cleared if
the center-aligned mode is selected or if DIR=0 (upcounting), else it takes the auto-reload
value (TIMx_ARR) if DIR=1 (downcounting).

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14.4.7 TIM3 capture/compare mode register 1 (TIM3_CCMR1)

Address offset: 0x18
Reset value: 0x0000
The channels can be used in input (capture mode) or in output (compare mode). The
direction of a channel is defined by configuring the corresponding CCxS bits. All the other
bits of this register have a different function in input and in output mode. For a given bit,
OCxx describes its function when the channel is configured in output, ICxx describes its
function when the channel is configured in input. So one must take care that the same bit
can have a different meaning for the input stage and for the output stage.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OC2CE OC2M[2:0] OC2PE OC2FE OC1CE OC1M[2:0] OC1PE OC1FE
CC2S[1:0] CC1S[1:0]
IC2F[3:0] IC2PSC[1:0] IC1F[3:0] IC1PSC[1:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Output compare mode

Bit 15 OC2CE: Output compare 2 clear enable

Bits 14:12 OC2M[2:0]: Output compare 2 mode
Bit 11 OC2PE: Output compare 2 preload enable
Bit 10 OC2FE: Output compare 2 fast enable
Bits 9:8 CC2S[1:0]: Capture/Compare 2 selection
This bit-field defines the direction of the channel (input/output) as well as the used input.
00: CC2 channel is configured as output
01: CC2 channel is configured as input, IC2 is mapped on TI2
10: CC2 channel is configured as input, IC2 is mapped on TI1
11: CC2 channel is configured as input, IC2 is mapped on TRC. This mode is working only if
an internal trigger input is selected through the TS bit (TIMx_SMCR register)
Note: CC2S bits are writable only when the channel is OFF (CC2E = 0 in TIMx_CCER).
Bit 7 OC1CE: Output compare 1 clear enable
OC1CE: Output Compare 1 Clear Enable
0: OC1Ref is not affected by the ETRF input
1: OC1Ref is cleared as soon as a High level is detected on ETRF input

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Bits 6:4 OC1M: Output compare 1 mode

These bits define the behavior of the output reference signal OC1REF from which OC1 and
OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends on
CC1P and CC1NP bits.
000: Frozen - The comparison between the output compare register TIMx_CCR1 and the
counter TIMx_CNT has no effect on the outputs.(this mode is used to generate a timing base).
001: Set channel 1 to active level on match. OC1REF signal is forced high when the counter
TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1).
010: Set channel 1 to inactive level on match. OC1REF signal is forced low when the
counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1).
011: Toggle - OC1REF toggles when TIMx_CNT=TIMx_CCR1.
100: Force inactive level - OC1REF is forced low.
101: Force active level - OC1REF is forced high.
110: PWM mode 1 - In upcounting, channel 1 is active as long as TIMx_CNT<TIMx_CCR1
else inactive. In downcounting, channel 1 is inactive (OC1REF=‘0) as long as
TIMx_CNT>TIMx_CCR1 else active (OC1REF=1).
111: PWM mode 2 - In upcounting, channel 1 is inactive as long as TIMx_CNT<TIMx_CCR1
else active. In downcounting, channel 1 is active as long as TIMx_CNT>TIMx_CCR1 else
inactive.
Note: 1: These bits can not be modified as long as LOCK level 3 has been programmed
(LOCK bits in TIMx_BDTR register) and CC1S=00 (the channel is configured in
output).
2: In PWM mode 1 or 2, the OCREF level changes only when the result of the
comparison changes or when the output compare mode switches from “frozen” mode
to “PWM” mode.
Bit 3 OC1PE: Output compare 1 preload enable
0: Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the
new value is taken in account immediately.
1: Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload
register. TIMx_CCR1 preload value is loaded in the active register at each update event.
Note: These bits can not be modified as long as LOCK level 3 has been programmed (LOCK
bits in TIMx_BDTR register) and CC1S=00 (the channel is configured in output).
Bit 2 OC1FE: Output compare 1 fast enable
This bit is used to accelerate the effect of an event on the trigger in input on the CC output.
0: CC1 behaves normally depending on counter and CCR1 values even when the trigger is
ON. The minimum delay to activate CC1 output when an edge occurs on the trigger input is
5 clock cycles.
1: An active edge on the trigger input acts like a compare match on CC1 output. Then, OC
is set to the compare level independently from the result of the comparison. Delay to sample
the trigger input and to activate CC1 output is reduced to 3 clock cycles. OCFE acts only if
the channel is configured in PWM1 or PWM2 mode.
Bits 1:0 CC1S: Capture/Compare 1 selection
This bit-field defines the direction of the channel (input/output) as well as the used input.
00: CC1 channel is configured as output.
01: CC1 channel is configured as input, IC1 is mapped on TI1.
10: CC1 channel is configured as input, IC1 is mapped on TI2.
11: CC1 channel is configured as input, IC1 is mapped on TRC. This mode is working only if
an internal trigger input is selected through TS bit (TIMx_SMCR register)
Note: CC1S bits are writable only when the channel is OFF (CC1E = 0 in TIMx_CCER).

Input capture mode

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Bits 15:12 IC2F: Input capture 2 filter

Bits 11:10 IC2PSC[1:0]: Input capture 2 prescaler
Bits 9:8 CC2S: Capture/compare 2 selection
This bit-field defines the direction of the channel (input/output) as well as the used input.
00: CC2 channel is configured as output.
01: CC2 channel is configured as input, IC2 is mapped on TI2.
10: CC2 channel is configured as input, IC2 is mapped on TI1.
11: CC2 channel is configured as input, IC2 is mapped on TRC. This mode is working only if
an internal trigger input is selected through TS bit (TIMx_SMCR register)
Note: CC2S bits are writable only when the channel is OFF (CC2E = 0 in TIMx_CCER).
Bits 7:4 IC1F: Input capture 1 filter
This bit-field defines the frequency used to sample TI1 input and the length of the digital filter
applied to TI1. The digital filter is made of an event counter in which N consecutive events are
needed to validate a transition on the output:
0000: No filter, sampling is done at fDTS
0001: fSAMPLING = fCK_INT, N = 2
0010: fSAMPLING = fCK_INT, N = 4
0011: fSAMPLING = fCK_INT, N = 8
0100: fSAMPLING = fDTS / 2, N = 6
0101: fSAMPLING = fDTS / 2, N = 8
0110: fSAMPLING = fDTS / 4, N = 6
0111: fSAMPLING = fDTS / 4, N = 8
1000: fSAMPLING = fDTS / 8, N = 6
1001: fSAMPLING = fDTS / 8, N = 8
1010: fSAMPLING = fDTS / 16, N = 5
1011: fSAMPLING = fDTS / 16, N = 6
1100: fSAMPLING = fDTS / 16, N = 8
1101: fSAMPLING = fDTS / 32, N = 5
1110: fSAMPLING = fDTS / 32, N = 6
1111: fSAMPLING = fDTS / 32, N = 8
Note: Care must be taken that fDTS is replaced in the formula by CK_INT when ICxF[3:0] = 1,
2 or 3.
Bits 3:2 IC1PSC: Input capture 1 prescaler
This bit-field defines the ratio of the prescaler acting on CC1 input (IC1).
The prescaler is reset as soon as CC1E=0 (TIMx_CCER register).
00: no prescaler, capture is done each time an edge is detected on the capture input
01: capture is done once every 2 events
10: capture is done once every 4 events
11: capture is done once every 8 events
Bits 1:0 CC1S: Capture/Compare 1 selection
This bit-field defines the direction of the channel (input/output) as well as the used input.
00: CC1 channel is configured as output
01: CC1 channel is configured as input, IC1 is mapped on TI1
10: CC1 channel is configured as input, IC1 is mapped on TI2
11: CC1 channel is configured as input, IC1 is mapped on TRC. This mode is working only if
an internal trigger input is selected through TS bit (TIMx_SMCR register)
Note: CC1S bits are writable only when the channel is OFF (CC1E = 0 in TIMx_CCER).

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14.4.8 TIM3 capture/compare mode register 2 (TIM3_CCMR2)

Address offset: 0x1C
Reset value: 0x0000
Refer to the above CCMR1 register description.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OC4CE OC4M[2:0] OC4PE OC4FE OC3CE OC3M[2:0] OC3PE OC3FE
CC4S[1:0] CC3S[1:0]
IC4F[3:0] IC4PSC[1:0] IC3F[3:0] IC3PSC[1:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Output compare mode

Bit 15 OC4CE: Output compare 4 clear enable

Bits 14:12 OC4M: Output compare 4 mode
Bit 11 OC4PE: Output compare 4 preload enable
Bit 10 OC4FE: Output compare 4 fast enable
Bits 9:8 CC4S: Capture/Compare 4 selection
This bit-field defines the direction of the channel (input/output) as well as the used input.
00: CC4 channel is configured as output
01: CC4 channel is configured as input, IC4 is mapped on TI4
10: CC4 channel is configured as input, IC4 is mapped on TI3
11: CC4 channel is configured as input, IC4 is mapped on TRC. This mode is working only if
an internal trigger input is selected through TS bit (TIMx_SMCR register)
Note: CC4S bits are writable only when the channel is OFF (CC4E = 0 in TIMx_CCER).
Bit 7 OC3CE: Output compare 3 clear enable
Bits 6:4 OC3M: Output compare 3 mode
Bit 3 OC3PE: Output compare 3 preload enable
Bit 2 OC3FE: Output compare 3 fast enable
Bits 1:0 CC3S: Capture/Compare 3 selection
This bit-field defines the direction of the channel (input/output) as well as the used input.
00: CC3 channel is configured as output
01: CC3 channel is configured as input, IC3 is mapped on TI3
10: CC3 channel is configured as input, IC3 is mapped on TI4
11: CC3 channel is configured as input, IC3 is mapped on TRC. This mode is working only if
an internal trigger input is selected through TS bit (TIMx_SMCR register)
Note: CC3S bits are writable only when the channel is OFF (CC3E = 0 in TIMx_CCER).

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Input capture mode

Bits 15:12 IC4F: Input capture 4 filter

Bits 11:10 IC4PSC: Input capture 4 prescaler
Bits 9:8 CC4S: Capture/Compare 4 selection
This bit-field defines the direction of the channel (input/output) as well as the used input.
00: CC4 channel is configured as output
01: CC4 channel is configured as input, IC4 is mapped on TI4
10: CC4 channel is configured as input, IC4 is mapped on TI3
11: CC4 channel is configured as input, IC4 is mapped on TRC. This mode is working only if
an internal trigger input is selected through TS bit (TIMx_SMCR register)
Note: CC4S bits are writable only when the channel is OFF (CC4E = 0 in TIMx_CCER).
Bits 7:4 IC3F: Input capture 3 filter
Bits 3:2 IC3PSC: Input capture 3 prescaler
Bits 1:0 CC3S: Capture/Compare 3 selection
This bit-field defines the direction of the channel (input/output) as well as the used input.
00: CC3 channel is configured as output
01: CC3 channel is configured as input, IC3 is mapped on TI3
10: CC3 channel is configured as input, IC3 is mapped on TI4
11: CC3 channel is configured as input, IC3 is mapped on TRC. This mode is working only if
an internal trigger input is selected through TS bit (TIMx_SMCR register)
Note: CC3S bits are writable only when the channel is OFF (CC3E = 0 in TIMx_CCER).

14.4.9 TIM3 capture/compare enable register (TIM3_CCER)

Address offset: 0x20
Reset value: 0x0000

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC4NP Res. CC4P CC4E CC3NP Res. CC3P CC3E CC2NP Res. CC2P CC2E CC1NP Res. CC1P CC1E
rw rw rw rw rw rw rw rw rw rw rw rw

Bit 15 CC4NP: Capture/Compare 4 output Polarity.

Refer to CC1NP description
Bit 14 Reserved, must be kept at reset value.
Bit 13 CC4P: Capture/Compare 4 output Polarity.
Refer to CC1P description
Bit 12 CC4E: Capture/Compare 4 output enable.
Refer to CC1E description
Bit 11 CC3NP: Capture/Compare 3 output Polarity.
Refer to CC1NP description
Bit 10 Reserved, must be kept at reset value.
Bit 9 CC3P: Capture/Compare 3 output Polarity.
Refer to CC1P description
Bit 8 CC3E: Capture/Compare 3 output enable.
Refer to CC1E description

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Bit 7 CC2NP: Capture/Compare 2 output Polarity.

Refer to CC1NP description
Bit 6 Reserved, must be kept at reset value.
Bit 5 CC2P: Capture/Compare 2 output Polarity.
Refer to CC1P description
Bit 4 CC2E: Capture/Compare 2 output enable.
Refer to CC1E description
Bit 3 CC1NP: Capture/Compare 1 output Polarity.
CC1 channel configured as output:
CC1NP must be kept cleared in this case.
CC1 channel configured as input:
This bit is used in conjunction with CC1P to define TI1FP1/TI2FP1 polarity. refer to CC1P
description.
Bit 2 Reserved, must be kept at reset value.
Bit 1 CC1P: Capture/Compare 1 output Polarity.
CC1 channel configured as output:
0: OC1 active high
1: OC1 active low
CC1 channel configured as input:
CC1NP/CC1P bits select TI1FP1 and TI2FP1 polarity for trigger or capture operations.
00: noninverted/rising edge
Circuit is sensitive to TIxFP1 rising edge (capture, trigger in reset, external clock or trigger
mode), TIxFP1 is not inverted (trigger in gated mode, encoder mode).
01: inverted/falling edge
Circuit is sensitive to TIxFP1 falling edge (capture, trigger in reset, external clock or trigger
mode), TIxFP1 is inverted (trigger in gated mode, encoder mode).
10: reserved, do not use this configuration.
11: noninverted/both edges
Circuit is sensitive to both TIxFP1 rising and falling edges (capture, trigger in reset, external
clock or trigger mode), TIxFP1 is not inverted (trigger in gated mode). This configuration
must not be used for encoder mode.
Bit 0 CC1E: Capture/Compare 1 output enable.
CC1 channel configured as output:
0: Off - OC1 is not active
1: On - OC1 signal is output on the corresponding output pin
CC1 channel configured as input:
This bit determines if a capture of the counter value can actually be done into the input
capture/compare register 1 (TIMx_CCR1) or not.
0: Capture disabled
1: Capture enabled

Table 49. Output control bit for standard OCx channels

CCxE bit OCx output state
0 Output Disabled (OCx=0, OCx_EN=0)
1 OCx=OCxREF + Polarity, OCx_EN=1

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Note: The state of the external IO pins connected to the standard OCx channels depends on the
OCx channel state and the GPIO registers.

14.4.10 TIM3 counter (TIM3_CNT)

Address offset: 0x24
Reset value: 0x0000 0000

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 15:0 CNT[15:0]: Low counter value

14.4.11 TIM3 prescaler (TIM3_PSC)

Address offset: 0x28
Reset value: 0x0000

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 15:0 PSC[15:0]: Prescaler value

The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1).
PSC contains the value to be loaded in the active prescaler register at each update event.

14.4.12 TIM3 auto-reload register (TIM3_ARR)

Address offset: 0x2C
Reset value: 0xFFFF FFFF

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 15:0 ARR[15:0]: Low Auto-reload value

ARR is the value to be loaded in the actual auto-reload register.
Refer to Section 14.3.1: Time-base unit on page 302 for more details about ARR update and
behavior.
The counter is blocked while the auto-reload value is null.

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14.4.13 TIM3 capture/compare register 1 (TIM3_CCR1)

Address offset: 0x34
Reset value: 0x0000 0000

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR1[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 15:0 CCR1[15:0]: Low Capture/Compare 1 value

If channel CC1 is configured as output:
CCR1 is the value to be loaded in the actual capture/compare 1 register (preload value).
It is loaded permanently if the preload feature is not selected in the TIMx_CCMR1 register (bit
OC1PE). Otherwise the preload value is copied in the active capture/compare 1 register when
an update event occurs.
The active capture/compare register contains the value to be compared to the counter
TIMx_CNT and signaled on OC1 output.
If channel CC1is configured as input:
CCR1 is the counter value transferred by the last input capture 1 event (IC1).

14.4.14 TIM3 capture/compare register 2 (TIM3_CCR2)

Address offset: 0x38
Reset value: 0x0000 0000

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR2[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 15:0 CCR2[15:0]: Low Capture/Compare 2 value

If channel CC2 is configured as output:
CCR2 is the value to be loaded in the actual capture/compare 2 register (preload value).
It is loaded permanently if the preload feature is not selected in the TIMx_CCMR2 register (bit
OC2PE). Else the preload value is copied in the active capture/compare 2 register when an
update event occurs.
The active capture/compare register contains the value to be compared to the counter
TIMx_CNT and signaled on OC2 output.
If channel CC2 is configured as input:
CCR2 is the counter value transferred by the last input capture 2 event (IC2).

14.4.15 TIM3 capture/compare register 3 (TIM3_CCR3)

Address offset: 0x3C
Reset value: 0x0000 0000

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR3[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

360/775 RM0360 Rev 5

RM0360 General-purpose timers (TIM3)

Bits 15:0 CCR3[15:0]: Low Capture/Compare 3 value

If channel CC3 is configured as output:
CCR3 is the value to be loaded in the actual capture/compare 3 register (preload value).
It is loaded permanently if the preload feature is not selected in the TIMx_CCMR3 register (bit
OC3PE). Else the preload value is copied in the active capture/compare 3 register when an
update event occurs.
The active capture/compare register contains the value to be compared to the counter
TIMx_CNT and signaled on OC3 output.
If channel CC3is configured as input:
CCR3 is the counter value transferred by the last input capture 3 event (IC3).

RM0360 Rev 5 361/775

366
General-purpose timers (TIM3) RM0360

14.4.16 TIM3 capture/compare register 4 (TIM3_CCR4)

Address offset: 0x40
Reset value: 0x0000 0000

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR4[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 15:0 CCR4[15:0]: Low Capture/Compare 4 value

1. If CC4 channel is configured as output (CC4S bits):
CCR4 is the value to be loaded in the actual capture/compare 4 register (preload value).
It is loaded permanently if the preload feature is not selected in the TIMx_CCMR4
register (bit OC4PE). Otherwise, the preload value is copied in the active
capture/compare 4 register when an update event occurs.
The active capture/compare register contains the value to be compared to the counter
TIMx_CNT and signaled on OC4 output.
2. If CC4 channel is configured as input (CC4S bits in TIMx_CCMR4 register):
CCR4 is the counter value transferred by the last input capture 4 event (IC4).

14.4.17 TIM3 DMA control register (TIM3_DCR)

Address offset: 0x48
Reset value: 0x0000

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. DBL[4:0] Res. Res. Res. DBA[4:0]
rw rw rw rw rw rw rw rw rw rw

Bits 15:13 Reserved, must be kept at reset value.

Bits 12:8 DBL[4:0]: DMA burst length
This 5-bit vector defines the number of DMA transfers (the timer recognizes a burst transfer
when a read or a write access is done to the TIMx_DMAR address).
00000: 1 transfer,
00001: 2 transfers,
00010: 3 transfers,
...
10001: 18 transfers.
Bits 7:5 Reserved, must be kept at reset value.
Bits 4:0 DBA[4:0]: DMA base address
This 5-bit vector defines the base-address for DMA transfers (when read/write access are done
through the TIMx_DMAR address). DBA is defined as an offset starting from the address of the
TIMx_CR1 register.
Example:
00000: TIMx_CR1,
00001: TIMx_CR2,
00010: TIMx_SMCR,
...
Example: Let us consider the following transfer: DBL = 7 transfers & DBA = TIMx_CR1. In this
case the transfer is done to/from 7 registers starting from the TIMx_CR1 address.

362/775 RM0360 Rev 5

RM0360 General-purpose timers (TIM3)

14.4.18 TIM3 DMA address for full transfer (TIM3_DMAR)

Address offset: 0x4C
Reset value: 0x0000

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAB[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 15:0 DMAB[15:0]: DMA register for burst accesses

A read or write operation to the DMAR register accesses the register located at the address
(TIMx_CR1 address) + (DBA + DMA index) x 4
where TIMx_CR1 address is the address of the control register 1, DBA is the DMA base
address configured in TIMx_DCR register, DMA index is automatically controlled by the DMA
transfer, and ranges from 0 to DBL (DBL configured in TIMx_DCR).

RM0360 Rev 5 363/775

366
General-purpose timers (TIM3) RM0360

Example of how to use the DMA burst feature

In this example the timer DMA burst feature is used to update the contents of the CCRx
registers (x = 2, 3, 4) with the DMA transferring half words into the CCRx registers.
This is done in the following steps:
1. Configure the corresponding DMA channel as follows:
– DMA channel peripheral address is the DMAR register address
– DMA channel memory address is the address of the buffer in the RAM containing
the data to be transferred by DMA into CCRx registers.
– Number of data to transfer = 3 (See note below).
– Circular mode disabled.
2. Configure the DCR register by configuring the DBA and DBL bit fields as follows:
DBL = 3 transfers, DBA = 0xE.
3. Enable the TIMx update DMA request (set the UDE bit in the DIER register).
4. Enable TIMx
5. Enable the DMA channel
For code example refer to the Appendix section A.8.20: Two timers synchronized by an
external trigger.
Note: This example is for the case where every CCRx register to be updated once. If every CCRx
register is to be updated twice for example, the number of data to transfer should be 6. Let
us take the example of a buffer in the RAM containing data1, data2, data3, data4, data5 and
data6. The data is transferred to the CCRx registers as follows: on the first update DMA
request, data1 is transferred to CCR2, data2 is transferred to CCR3, data3 is transferred to
CCR4 and on the second update DMA request, data4 is transferred to CCR2, data5 is
transferred to CCR3 and data6 is transferred to CCR4.

364/775 RM0360 Rev 5

 0x30
0x28
0x24
0x20
0x18
0x14
0x10
0x08
0x04
0x00

0x2C
0x1C
0x0C
Offset
RM0360

14.4.19

mode
mode
mode
mode

Reserved
TIM3_SR

TIM3_PSC
TIM3_CNT
TIM3_CR2
TIM3_CR1
Register

Reset value
Reset value
Reset value
Reset value
Reset value
Reset value

Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value

TIM3_EGR

TIM3_ARR
TIM3_DIER

TIM3_CCER
Input capture
Input capture
TIM3_SMCR

TIM3_CCMR2
TIM3_CCMR2
TIM3_CCMR1
TIM3_CCMR1

Output compare
Output compare

0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 31

0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 30

0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 29

0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 28

0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 27

0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 26
TIM3 register map

0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 25

0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 24

0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 23

0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 22

0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 21

0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 20

0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 19

0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 18

0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

RM0360 Rev 5
17

0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 16

0
0
0
0
0
0
0
0

Res. CC4NP O24CE OC2CE Res. Res. Res. ETP Res. Res. 15

0
0

0
0
0
0
0
0
0

Res. Res. Res. Res. TDE ECE Res. Res. 14

0
0
0
0
0
0
0
0

Res. CC4P Res. Res. Res. Res. Res. 13

[2:0]
[2:0]

IC4F[3:0]
IC2F[3:0]

OC4M
OC2M
[1:0]

0
0

0
0
0
0
0
0
0
0
0

Res. CC4E Res. CC4OF CC4DE Res. Res.

ETPS
TIM3 registers are mapped as described in the table below:

12

0
0

0
0
0
0
0

Res. CC3NP OC4PE OC2PE Res. CC3OF CC3DE Res. Res. 11

Table 50. TIM3 register map and reset values

IC4
IC2

[1:0]
[1:0]

PSC
PSC

0
0

0
0
0
0

Res. Res. OC4FE OC2FE Res. CC2OF CC2DE Res. Res. 10

0
0

0
0
0
0
0
0

Res. CC3P Res. CC1OF CC1DE Res. 9

ETF[3:0]

[1:0]
[1:0]
[1:0]
[1:0]
[1:0]
CKD

0
0

0
0
0
0
0

Res. CC3E Res. Res. UDE Res.

CC4S
CC4S
CC2S
CC2S

0
0
0
0
0
0

Res. CC2NP OC3CE OC1CE Res. Res. Res. MSM TI1S ARPE 7

PSC[15:0]
CNT[15:0]

ARR[15:0]
0
0

0
0
0

0
0
0
0

Res. Res. TG TIF TIE 6

[1:0]
CMS

0
0
0
0
0
0

Res. CC2P Res. Res. Res. 5

[2:0]
[2:0]

IC3F[3:0]
IC1F[3:0]

OC3M
OC1M
TS[2:0]

0
0

0
0
0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0
0
0
0
0

Res. CC2E CC4G CC4IF CC4IE DIR

MMS[2:0]

0
0

0
0
0
0
0
0
0
0

Res. CC1NP OC3PE OC1PE CC3G CC3IF CC3IE OCCS CCDS OPM 3
IC3
IC1

[1:0]
[1:0]

PSC
PSC

0
0

0
0
0
0
0
0

Res. Res. OC3FE OC1FE CC2G CC2IF CC2IE Res. URS 2

0
0

0
0
0
0

0
0
0

Res. CC1P CC1G CC1IF CC1IE Res. UDIS 1

[1:0]
[1:0]
[1:0]
[1:0]

0
0

0
0
0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0

0
0
0

Res. CC1E UG UIF UIE Res. CEN

SMS[2:0]

CC3S
CC3S
CC1S
CC1S

365/775
0
General-purpose timers (TIM3)

366
 0x48
0x44
0x40
0x38
0x34

0x4C
0x3C
Offset

366/775
Reserved
Register

Reset value
Reset value

Reset value
Reset value
Reset value
Reset value
Reset value

TIM3_DCR
TIM3_CCR1
TIM3_CCR1
TIM3_CCR1
TIM3_CCR1

TIM3_DMAR
Res. Res. Res. Res. Res. Res. Res. 31
Res. Res. Res. Res. Res. Res. Res. 30
Res. Res. Res. Res. Res. Res. Res. 29
Res. Res. Res. Res. Res. Res. Res. 28
Res. Res. Res. Res. Res. Res. Res.
General-purpose timers (TIM3)

27
Res. Res. Res. Res. Res. Res. Res. 26
Res. Res. Res. Res. Res. Res. Res. 25
Res. Res. Res. Res. Res. Res. Res. 24
Res. Res. Res. Res. Res. Res. Res. 23
Res. Res. Res. Res. Res. Res. Res. 22
Res. Res. Res. Res. Res. Res. Res. 21
Res. Res. Res. Res. Res. Res. Res. 20
Res. Res. Res. Res. Res. Res. Res. 19
Res. Res. Res. Res. Res. Res. Res. 18
Res. Res. Res. Res. Res. Res. Res.

RM0360 Rev 5
17
Res. Res. Res. Res. Res. Res. Res. 16
0
0
0
0
0

Res. Res. 15
0
0
0
0
0

Res. Res. 14
0
0
0
0
0

Res. Res. 13
0
0
0
0
0
0

Res. 12
0
0
0
0
0
0

Res. 11
0
0
0
0
0
0

Res. 10
0
DBL[4:0]

0
0
0
0
0

Res. 9
Refer to Section 2.2 on page 37 for the register boundary addresses.
0
0
0
0
0
0
Table 50. TIM3 register map and reset values (continued)

Res. 8
0
0
0
0
0

Res. Res. 7
CCR4[15:0]
CCR3[15:0]
CCR2[15:0]
CCR1[15:0]

DMAB[15:0]

0
0
0
0
0

Res. Res. 6
0
0
0
0
0

Res. Res. 5
0
0
0
0
0
0

Res. 4
0
0
0
0
0
0

Res. 3
0
0
0
0
0
0

Res. 2
0
0
0
0
0
0

DBA[4:0]

Res. 1
0
0
0
0
0
0

Res.
RM0360

0
RM0360 Basic timer (TIM6/TIM7)

15 Basic timer (TIM6/TIM7)

This section applies to STM32F030x8, STM32F070xB and STM32F030xC devices only.

TIM7 is available only on STM32F070xB and STM32F030xC devices.

15.1 TIM6/TIM7 introduction

The basic timer TIM6 consists of a 16-bit auto-reload counter driven by a programmable
prescaler.

15.2 TIM6/TIM7 main features

• 16-bit auto-reload upcounter
• 16-bit programmable prescaler used to divide (also “on the fly”) the counter clock
frequency by any factor between 1 and 65535
• Interrupt/DMA generation on the update event: counter overflow

Figure 139. Basic timer block diagram

Internal clock (CK_INT)

TIMxCLK from RCC Trigger
controller
Reset, enable, Count

Auto-reload register
U
UI
Stop, clear or up
U
CK_PSC PSC CK_CNT
+ CNT counter
prescaler

Notes:
Preload registers transferred
Reg
to active registers on U event
according to control bit

Event

Interrupt & DMA output

MS32645V1

RM0360 Rev 5 367/775

379
Basic timer (TIM6/TIM7) RM0360

15.3 TIM6/TIM7 functional description

15.3.1 Time-base unit
The main block of the programmable timer is a 16-bit upcounter with its related auto-reload
register. The counter clock can be divided by a prescaler.
The counter, the auto-reload register and the prescaler register can be written or read by
software. This is true even when the counter is running.
The time-base unit includes:
• Counter Register (TIMx_CNT)
• Prescaler Register (TIMx_PSC)
• Auto-Reload Register (TIMx_ARR)
The auto-reload register is preloaded. The preload register is accessed each time an
attempt is made to write or read the auto-reload register. The contents of the preload
register are transferred into the shadow register permanently or at each update event UEV,
depending on the auto-reload preload enable bit (ARPE) in the TIMx_CR1 register. The
update event is sent when the counter reaches the overflow value and if the UDIS bit equals
0 in the TIMx_CR1 register. It can also be generated by software. The generation of the
update event is described in detail for each configuration.
The counter is clocked by the prescaler output CK_CNT, which is enabled only when the
counter enable bit (CEN) in the TIMx_CR1 register is set.
Note that the actual counter enable signal CNT_EN is set 1 clock cycle after CEN.

Prescaler description
The prescaler can divide the counter clock frequency by any factor between 1 and 65536. It
is based on a 16-bit counter controlled through a 16-bit register (in the TIMx_PSC register).
It can be changed on the fly as the TIMx_PSC control register is buffered. The new
prescaler ratio is taken into account at the next update event.
Figure 140 and Figure 141 give some examples of the counter behavior when the prescaler
ratio is changed on the fly.

368/775 RM0360 Rev 5

RM0360 Basic timer (TIM6/TIM7)

Figure 140. Counter timing diagram with prescaler division change from 1 to 2

CK_PSC

CEN

Timerclock = CK_CNT

Counter register F7 F8 F9 FA FB FC 00 01 02 03

Update event (UEV)

Prescaler control register 0 1

Write a new value in TIMx_PSC

Prescaler buffer 0 1

Prescaler counter 0 0 1 0 1 0 1 0 1
MS31076V2

Figure 141. Counter timing diagram with prescaler division change from 1 to 4

CK_PSC

CEN

Timerclock = CK_CNT

F7 F8 F9 FA FB FC 00 01
Counter register

Update event (UEV)

0 3
Prescaler control register

Write a new value in TIMx_PSC

0 3
Prescaler buffer

0 0 1 2 3 0 1 2 3
Prescaler counter

MS31077V2

RM0360 Rev 5 369/775

379
Basic timer (TIM6/TIM7) RM0360

15.3.2 Counter modes

The counter counts from 0 to the auto-reload value (contents of the TIMx_ARR register),
then restarts from 0 and generates a counter overflow event.
An update event can be generate at each counter overflow or by setting the UG bit in the
TIMx_EGR register (by software or by using the slave mode controller).
The UEV event can be disabled by software by setting the UDIS bit in the TIMx_CR1
register. This avoids updating the shadow registers while writing new values into the preload
registers. In this way, no update event occurs until the UDIS bit has been written to 0,
however, the counter and the prescaler counter both restart from 0 (but the prescale rate
does not change). In addition, if the URS (update request selection) bit in the TIMx_CR1
register is set, setting the UG bit generates an update event UEV, but the UIF flag is not set
(so no interrupt or DMA request is sent).
When an update event occurs, all the registers are updated and the update flag (UIF bit in
the TIMx_SR register) is set (depending on the URS bit):
• The buffer of the prescaler is reloaded with the preload value (contents of the
TIMx_PSC register)
• The auto-reload shadow register is updated with the preload value (TIMx_ARR)
The following figures show some examples of the counter behavior for different clock
frequencies when TIMx_ARR = 0x36.

Figure 142. Counter timing diagram, internal clock divided by 1

CK_PSC

CNT_EN

Timerclock = CK_CNT

Counter register 31 32 33 34 35 36 00 01 02 03 04 05 06 07

Counter overflow

Update event (UEV)

Update interrupt flag

(UIF)

MS31078V2

370/775 RM0360 Rev 5

RM0360 Basic timer (TIM6/TIM7)

Figure 143. Counter timing diagram, internal clock divided by 2

CK_PSC

CNT_EN

Timerclock = CK_CNT

Counter register 0034 0035 0036 0000 0001 0002 0003

Counter overflow

Update event (UEV)

Update interrupt flag

(UIF)

MS31079V2

Figure 144. Counter timing diagram, internal clock divided by 4

CK_PSC

CNT_EN

Timerclock = CK_CNT

Counter register 0035 0036 0000 0001

Counter overflow

Update event (UEV)

Update interrupt flag

(UIF)

MS31080V2

RM0360 Rev 5 371/775

379
Basic timer (TIM6/TIM7) RM0360

Figure 145. Counter timing diagram, internal clock divided by N

CK_PSC

Timerclock = CK_CNT

Counter register 1F 20 00

Counter overflow

Update event (UEV)

Update interrupt flag

(UIF)

MS31081V2

Figure 146. Counter timing diagram, update event when ARPE = 0

(TIMx_ARR not preloaded)

CK_PSC

CEN

Timerclock = CK_CNT

Counter register 31 32 33 34 35 36 00 01 02 03 04 05 06 07

Counter overflow

Update event (UEV)

Update interrupt flag

(UIF)

Auto-reload preload
register FF 36

Write a new value in TIMx_ARR

MS31082V2

372/775 RM0360 Rev 5

RM0360 Basic timer (TIM6/TIM7)

Figure 147. Counter timing diagram, update event when ARPE=1

(TIMx_ARR preloaded)

CK_PSC

CEN

Timerclock = CK_CNT

Counter register F0 F1 F2 F3 F4 F5 00 01 02 03 04 05 06 07

Counter overflow

Update event (UEV)

Update interrupt flag

(UIF)
Auto-reload preload
F5 36
register

Auto-reload shadow
register F5 36

Write a new value in TIMx_ARR MS31083V2

RM0360 Rev 5 373/775

379
Basic timer (TIM6/TIM7) RM0360

15.3.3 Clock source

The counter clock is provided by the Internal clock (CK_INT) source.
The CEN (in the TIMx_CR1 register) and UG bits (in the TIMx_EGR register) are actual
control bits and can be changed only by software (except for UG that remains cleared
automatically). As soon as the CEN bit is written to 1, the prescaler is clocked by the internal
clock CK_INT.
Figure 148 shows the behavior of the control circuit and the upcounter in normal mode,
without prescaler.

Figure 148. Control circuit in normal mode, internal clock divided by 1

Internal clock

CEN=CNT_EN

UG

CNT_INIT

Counter clock = CK_CNT = CK_PSC

Counter register 31 32 33 34 35 36 00 01 02 03 04 05 06 07

MS31085V2

15.3.4 Debug mode

When the microcontroller enters the debug mode (Cortex™-M0 core - halted), the TIMx
counter either continues to work normally or stops, depending on the DBG_TIMx_STOP
configuration bit in the DBG module.

374/775 RM0360 Rev 5

RM0360 Basic timer (TIM6/TIM7)

15.4 TIM6/TIM7 registers

Refer to Section 1.2 on page 33 for a list of abbreviations used in register descriptions.
The peripheral registers can be accessed by half-words (16-bit) or words (32-bit).

15.4.1 TIM6/TIM7 control register 1 (TIMx_CR1)

Address offset: 0x00
Reset value: 0x0000

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. ARPE Res. Res. Res. OPM URS UDIS CEN
rw rw rw rw rw

Bits 15:8 Reserved, always read as 0.

Bit 7 ARPE: Auto-reload preload enable
0: TIMx_ARR register is not buffered.
1: TIMx_ARR register is buffered.
Bits 6:4 Reserved, always read as 0.
Bit 3 OPM: One-pulse mode
0: Counter is not stopped at update event
1: Counter stops counting at the next update event (clearing the CEN bit).
Bit 2 URS: Update request source
This bit is set and cleared by software to select the UEV event sources.
0: Any of the following events generates an update interrupt or DMA request if enabled.
These events can be:
– Counter overflow/underflow
– Setting the UG bit
– Update generation through the slave mode controller
1: Only counter overflow/underflow generates an update interrupt or DMA request if
enabled.
Bit 1 UDIS: Update disable
This bit is set and cleared by software to enable/disable UEV event generation.
0: UEV enabled. The Update (UEV) event is generated by one of the following events:
– Counter overflow/underflow
– Setting the UG bit
– Update generation through the slave mode controller
Buffered registers are then loaded with their preload values.
1: UEV disabled. The Update event is not generated, shadow registers keep their value
(ARR, PSC). However the counter and the prescaler are reinitialized if the UG bit is set or if
a hardware reset is received from the slave mode controller.
Bit 0 CEN: Counter enable
0: Counter disabled
1: Counter enabled
Note: Gated mode can work only if the CEN bit has been previously set by software.
However trigger mode can set the CEN bit automatically by hardware.
CEN is cleared automatically in one-pulse mode, when an update event occurs.

RM0360 Rev 5 375/775

379
Basic timer (TIM6/TIM7) RM0360

15.4.2 TIM6/TIM7 DMA/Interrupt enable register (TIMx_DIER)

Address offset: 0x0C
Reset value: 0x0000

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. UDE Res. Res. Res. Res. Res. Res. Res. UIE
rw rw

Bits 15:9 Reserved, must be kept at reset value.

Bit 8 UDE: Update DMA request enable
0: Update DMA request disabled.
1: Update DMA request enabled.
Bits 7:1 Reserved, must be kept at reset value.
Bit 0 UIE: Update interrupt enable
0: Update interrupt disabled.
1: Update interrupt enabled.

376/775 RM0360 Rev 5

RM0360 Basic timer (TIM6/TIM7)

15.4.3 TIM6/TIM7 status register (TIMx_SR)

Address offset: 0x10
Reset value: 0x0000

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. UIF
rc_w0

Bits 15:1 Reserved, must be kept at reset value.

Bit 0 UIF: Update interrupt flag
This bit is set by hardware on an update event. It is cleared by software.
0: No update occurred.
1: Update interrupt pending. This bit is set by hardware when the registers are updated:
–At overflow or underflow regarding the repetition counter value and if UDIS = 0 in the
TIMx_CR1 register.
–When CNT is reinitialized by software using the UG bit in the TIMx_EGR register, if
URS = 0 and UDIS = 0 in the TIMx_CR1 register.

15.4.4 TIM6/TIM7 event generation register (TIMx_EGR)

Address offset: 0x14
Reset value: 0x0000

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. UG
w

Bits 15:1 Reserved, must be kept at reset value.

Bit 0 UG: Update generation
This bit can be set by software, it is automatically cleared by hardware.
0: No action.
1: Re-initializes the timer counter and generates an update of the registers. Note that the
prescaler counter is cleared too (but the prescaler ratio is not affected).

15.4.5 TIM6/TIM7 counter (TIMx_CNT)

Address offset: 0x24
Reset value: 0x0000

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 15:0 CNT[15:0]: Counter value

RM0360 Rev 5 377/775

379
Basic timer (TIM6/TIM7) RM0360

15.4.6 TIM6/TIM7 prescaler (TIMx_PSC)

Address offset: 0x28
Reset value: 0x0000

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 15:0 PSC[15:0]: Prescaler value

The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1).
PSC contains the value to be loaded into the active prescaler register at each update event.

15.4.7 TIM6/TIM7 auto-reload register (TIMx_ARR)

Address offset: 0x2C
Reset value: 0xFFFF

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 15:0 ARR[15:0]: Auto-reload value

ARR is the value to be loaded into the actual auto-reload register.
Refer to Section 15.3.1: Time-base unit on page 368 for more details about ARR update and
behavior.
The counter is blocked while the auto-reload value is null.

378/775 RM0360 Rev 5

 0x28
0x24
0x14
0x10
0x00

0x2C
0x0C
Offset
15.4.8
RM0360

TIMx_SR
TIMx_CR1

TIMx_PSC
TIMx_CNT

TIMx_ARR
TIMx_EGR
Register

TIMx_DIER

Reset value
Reset value
Reset value
Reset value

Reset value
Reset value
Reset value
Res. Res. Res. Res. Res. Res. Res. 31
Res. Res. Res. Res. Res. Res. Res. 30
Res. Res. Res. Res. Res. Res. Res. 29
Res. Res. Res. Res. Res. Res. Res. 28
Res. Res. Res. Res. Res. Res. Res. 27
Res. Res. Res. Res. Res. Res. Res. 26
Res. Res. Res. Res. Res. Res. Res. 25
Res. Res. Res. Res. Res. Res. Res. 24
TIM6/TIM7 register map

Res. Res. Res. Res. Res. Res. Res. 23

Res. Res. Res. Res. Res. Res. Res. 22
Res. Res. Res. Res. Res. Res. Res. 21
Res. Res. Res. Res. Res. Res. Res. 20
Res. Res. Res. Res. Res. Res. Res. 19
Res. Res. Res. Res. Res. Res. Res. 18
Res. Res. Res. Res. Res. Res. Res.

RM0360 Rev 5
17
Res. Res. Res. Res. Res. Res. Res. 16

1
0
0 Res. Res. Res. Res. 15

1
0
0
Res. Res. Res. Res. 14

1
0
0

Res. Res. Res. Res. 13

1
0
0

Res. Res. Res. Res. 12

1
0
0

Res. Res. Res. Res. 11

1
0
0

Res. Res. Res. Res. 10

Table 51. TIM6/TIM7 register map and reset values

1
0
0

Res. Res. Res. Res. 9

Refer to Section 2.2 on page 37 for the register boundary addresses.

1
0
0
0

Res. Res. UDE Res. 8

1
0
0
0

Res. Res. Res. ARPE 7

PSC[15:0]
CNT[15:0]

ARR[15:0]

1
0
0

Res. Res. Res. Res. 6

1
0
0

Res. Res. Res. Res. 5

1
0
0

Res. Res. Res. Res. 4

1
0
0
0

Res. Res. Res. OPM 3

1
0
0
0

Res. Res. Res. URS 2

1
0
0
0

Res. Res. Res. UDIS 1

1
0
0
0
0
0
0

UG UIF UIE CEN

TIMx registers are mapped as 16-bit addressable registers as described in the table below:
Basic timer (TIM6/TIM7)

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0

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General-purpose timer (TIM14) RM0360

16 General-purpose timer (TIM14)

16.1 TIM14 introduction

The TIM14 general-purpose timer consists of a 16-bit auto-reload counter driven by a
programmable prescaler.
It may be used for a variety of purposes, including measuring the pulse lengths of input
signals (input capture) or generating output waveforms (output compare, PWM).
Pulse lengths and waveform periods can be modulated from a few microseconds to several
milliseconds using the timer prescaler and the RCC clock controller prescalers.
The TIM14 timer is completely independent, and does not share any resources. It can be
synchronized together as described in Section 14.3.15.

16.2 TIM14 main features

• 16-bit auto-reload upcounter
• 16-bit programmable prescaler used to divide the counter clock frequency by any factor
between 1 and 65535 (can be changed “on the fly”)
• independent channel for:
– Input capture
– Output compare
– PWM generation (edge-aligned mode)
• Interrupt generation on the following events:
– Update: counter overflow, counter initialization (by software)
– Input capture
– Output compare

380/775 RM0360 Rev 5

RM0360 General-purpose timer (TIM14)

Figure 149. General-purpose timer block diagram (TIM14)

Internal clock (CK_INT)

Trigger Enable
Controller counter

U Auto-reload register
UI
Stop, clear
U
CK_PSC PSC CK_CNT
+/- CNT counter
prescaler
C1I CC1I
TI1 TI1FP1 IC1 U
TIMx_CH1 Input filter & IC1PS OC1REF Output OC1
edge selector Prescaler Capture/compare 1 register TIMx_CH1
control

Notes:
Preload registers transferred
Reg
to active registers on U event
according to control bit

Event

Interrupt & DMA output ai17725d

16.3 TIM14 functional description

16.3.1 Time-base unit

The main block of the programmable general-purpose timer is a 16-bit upcounter with its
related auto-reload register. The counter clock can be divided by a prescaler.
The counter, the auto-reload register and the prescaler register can be written or read by
software. This is true even when the counter is running.
The time-base unit includes:
• Counter register (TIMx_CNT)
• Prescaler register (TIMx_PSC)
• Auto-reload register (TIMx_ARR)
The auto-reload register is preloaded. Writing to or reading from the auto-reload register
accesses the preload register. The content of the preload register are transferred into the
shadow register permanently or at each update event (UEV), depending on the auto-reload
preload enable bit (ARPE) in TIMx_CR1 register. The update event is sent when the counter
reaches the overflow and if the UDIS bit equals 0 in the TIMx_CR1 register. It can also be
generated by software. The generation of the update event is described in detailed for each
configuration.
The counter is clocked by the prescaler output CK_CNT, which is enabled only when the
counter enable bit (CEN) in TIMx_CR1 register is set (refer also to the slave mode controller
description to get more details on counter enabling).
Note that the counter starts counting 1 clock cycle after setting the CEN bit in the TIMx_CR1
register.

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467
General-purpose timer (TIM14) RM0360

Prescaler description
The prescaler can divide the counter clock frequency by any factor between 1 and 65536. It
is based on a 16-bit counter controlled through a 16-bit register (in the TIMx_PSC register).
It can be changed on the fly as this control register is buffered. The new prescaler ratio is
taken into account at the next update event.
Figure 151 and Figure 152 give some examples of the counter behavior when the prescaler
ratio is changed on the fly.

Figure 150. Counter timing diagram with prescaler division change from 1 to 2

CK_PSC

CEN

Timer clock = CK_CNT

Counter register F7 F8 F9 FA FB FC 00 01 02 03

Update event (UEV)

Prescaler control register 0 1

Write a new value in TIMx_PSC

Prescaler buffer 0 1

Prescaler counter 0 0 1 0 1 0 1 0 1

MS31453V1

Figure 151. Counter timing diagram with prescaler division change from 1 to 4

CK_PSC

CEN

Timer clock = CK_CNT

Counter register F7 F8 F9 FA FB FC 00 01

Update event (UEV)

Prescaler control register 0 3

Write a new value in TIMx_PSC

Prescaler buffer 0 3

Prescaler counter 0 0 1 2 3 0 1 2 3

MS31454V1

16.3.2 Counter operation

The counter counts from 0 to the auto-reload value (content of the TIMx_ARR register), then
restarts from 0 and generates a counter overflow event.

382/775 RM0360 Rev 5

RM0360 General-purpose timer (TIM14)

Setting the UG bit in the TIMx_EGR register also generates an update event.
The UEV event can be disabled by software by setting the UDIS bit in the TIMx_CR1
register. This is to avoid updating the shadow registers while writing new values in the
preload registers. Then no update event occurs until the UDIS bit has been written to 0.
However, the counter restarts from 0, as well as the counter of the prescaler (but the
prescale rate does not change). In addition, if the URS bit (update request selection) in
TIMx_CR1 register is set, setting the UG bit generates an update event UEV but without
setting the UIF flag (thus no interrupt is sent). This is to avoid generating both update and
capture interrupts when clearing the counter on the capture event.
When an update event occurs, all the registers are updated and the update flag (UIF bit in
TIMx_SR register) is set (depending on the URS bit):
• The auto-reload shadow register is updated with the preload value (TIMx_ARR),
• The buffer of the prescaler is reloaded with the preload value (content of the TIMx_PSC
register).
The following figures show some examples of the counter behavior for different clock
frequencies when TIMx_ARR=0x36.

Figure 152. Counter timing diagram, internal clock divided by 1

CK_PSC

CNT_EN

Timer clock = CK_CNT

Counter register 31 32 33 34 35 36 00 01 02 03 04 05 06 07

Counter overflow

Update event (UEV)

Update interrupt flag (UIF)

MS31455V1

Figure 153. Counter timing diagram, internal clock divided by 2

CK_PSC

CNT_EN

Timer clock = CK_CNT

Counter register 0034 0035 0036 0000 0001 0002 0003

Counter overflow

Update event (UEV)

Update interrupt flag (UIF)

MS31456V1

RM0360 Rev 5 383/775

467
General-purpose timer (TIM14) RM0360

Figure 154. Counter timing diagram, internal clock divided by 4

CK_PSC

CNT_EN

Timer clock = CK_CNT

Counter register 0035 0036 0000 0001

Counter overflow

Update event (UEV)

Update interrupt flag (UIF)

MS31457V1

Figure 155. Counter timing diagram, internal clock divided by N

CK_PSC

Timer clock = CK_CNT

Counter register 1F 20 00

Counter overflow

Update event (UEV)

Update interrupt flag (UIF)

MS31458V1

Figure 156. Counter timing diagram, update event when ARPE=0

(TIMx_ARR not preloaded)

CK_PSC

CEN

Timer clock = CK_CNT

Counter register 31 32 33 34 35 36 00 01 02 03 04 05 06 07

Counter overflow

Update event (UEV)

Update interrupt flag (UIF)

Auto-reload register FF 36

Write a new value in TIMx_ARR MS31459V1

384/775 RM0360 Rev 5

RM0360 General-purpose timer (TIM14)

Figure 157. Counter timing diagram, update event when ARPE=1

(TIMx_ARR preloaded)

CK_PSC

CEN

Timer clock = CK_CNT

Counter register F0 F1 F2 F3 F4 F5 00 01 02 03 04 05 06 07

Counter overflow

Update event (UEV)

Update interrupt flag (UIF)

Auto-reload preload register F5 36

Auto-reload shadow register F5 36

Write a new value in TIMx_ARR MS31460V1

16.3.3 Clock source

The counter clock is provided by the Internal clock (CK_INT) source.
The CEN (in the TIMx_CR1 register) and UG bits (in the TIMx_EGR register) are actual
control bits and can be changed only by software (except for UG that remains cleared
automatically). As soon as the CEN bit is written to 1, the prescaler is clocked by the internal
clock CK_INT.
Figure 158 shows the behavior of the control circuit and the upcounter in normal mode,
without prescaler.

Figure 158. Control circuit in normal mode, internal clock divided by 1

CK_INT

CEN=CNT_EN

UG

CNT_INIT

Counter clock = CK_CNT = CK_PSC

Counter register 31 32 33 34 35 36 00 01 02 03 04 05 06 07

MS31461V1

16.3.4 Capture/compare channels

Each Capture/Compare channel is built around a capture/compare register (including a
shadow register), a input stage for capture (with digital filter, multiplexing and prescaler) and
an output stage (with comparator and output control).

RM0360 Rev 5 385/775

467
General-purpose timer (TIM14) RM0360

Figure 159 to Figure 161 give an overview of one capture/compare channel.

The input stage samples the corresponding TIx input to generate a filtered signal TIxF.
Then, an edge detector with polarity selection generates a signal (TIxFPx) which can be
used as trigger input by the slave mode controller or as the capture command. It is
prescaled before the capture register (ICxPS).

Figure 159. Capture/compare channel (example: channel 1 input stage)

TI1F_ED
to the slave mode controller

TI1F_Rising 0
TI1 TI1F
filter Edge TI1FP1
01
fDTS downcounter Detector TI1F_Falling
1
TI2FP1 IC1 divider IC1PS
10
/1, /2, /4, /8
ICF[3:0] CC1P/CC1NP TRC
11
TIMx_CCMR1 TIMx_CCER (from slave mode
controller)
TI2F_rising 0
(from channel 2)
CC1S[1:0] ICPS[1:0] CC1E
TI2F_falling
1
(from channel 2) TIMx_CCMR1 TIMx_CCER

MS31462V1

The output stage generates an intermediate waveform which is then used for reference:
OCxRef (active high). The polarity acts at the end of the chain.

Figure 160. Capture/compare channel 1 main circuit

APB Bus

MCU-peripheral interface

Input mode 16/32-bit Output mode

CC1S[1]
CC1S[0] Capture/compare preload register
CC1S[1]

IC1PS Capture Compare CC1S[0]

CC1E transfer
OC1PE
compare shadow register OC1PE
CC1G UEV
Comparator (from time TIMx_CCMR1
TIMx_EGR base unit)
CNT>CCR1
Counter CNT=CCR1

MSv63030V1

386/775 RM0360 Rev 5

RM0360 General-purpose timer (TIM14)

Figure 161. Output stage of capture/compare channel (channel 1)

To the master
mode controller

CNT > CCR2

Output 0 Output
OC1_REF OC1
mode enable
CNT = CCR2
controller 1 circuit

CC1P

OC2M[2:0] TIMx_CCER CC1E TIMx_CCER

TIMx_CCMR1
ai17720

The capture/compare block is made of one preload register and one shadow register. Write
and read always access the preload register.
In capture mode, captures are actually done in the shadow register, which is copied into the
preload register.
In compare mode, the content of the preload register is copied into the shadow register
which is compared to the counter.

16.3.5 Input capture mode

In Input capture mode, the Capture/Compare Registers (TIMx_CCRx) are used to latch the
value of the counter after a transition detected by the corresponding ICx signal. When a
capture occurs, the corresponding CCXIF flag (TIMx_SR register) is set and an interrupt or
a DMA request can be sent if they are enabled. If a capture occurs while the CCxIF flag was
already high, then the over-capture flag CCxOF (TIMx_SR register) is set. CCxIF can be
cleared by software by writing it to ‘0’ or by reading the captured data stored in the
TIMx_CCRx register. CCxOF is cleared when it is written with 0.
The following example shows how to capture the counter value in TIMx_CCR1 when TI1
input rises. To do this, use the following procedure:
1. Select the active input: TIMx_CCR1 must be linked to the TI1 input, so write the CC1S
bits to ‘01’ in the TIMx_CCMR1 register. As soon as CC1S becomes different from ‘00’,
the channel is configured in input mode and the TIMx_CCR1 register becomes read-
only.
2. Program the appropriate input filter duration in relation with the signal connected to the
timer (when the input is one of the TIx (ICxF bits in the TIMx_CCMRx register). Let us
imagine that, when toggling, the input signal is not stable during at must 5 internal clock
cycles. We must program a filter duration longer than these 5 clock cycles. We can
validate a transition on TI1 when 8 consecutive samples with the new level have been

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467
General-purpose timer (TIM14) RM0360

detected (sampled at fDTS frequency). Then write IC1F bits to ‘0011’ in the
TIMx_CCMR1 register.
3. Select the edge of the active transition on the TI1 channel by programming CC1P and
CC1NP bits to ‘00’ in the TIMx_CCER register (rising edge in this case).
4. Program the input prescaler. In our example, we wish the capture to be performed at
each valid transition, so the prescaler is disabled (write IC1PS bits to ‘00’ in the
TIMx_CCMR1 register).
5. Enable capture from the counter into the capture register by setting the CC1E bit in the
TIMx_CCER register.
6. If needed, enable the related interrupt request by setting the CC1IE bit in the
TIMx_DIER register.
For code example refer to the Appendix section A.8.3: Input capture configuration.
When an input capture occurs:
• The TIMx_CCR1 register gets the value of the counter on the active transition.
• CC1IF flag is set (interrupt flag). CC1OF is also set if at least two consecutive captures
occurred whereas the flag was not cleared.
• An interrupt is generated depending on the CC1IE bit.
For code example refer to the Appendix section A.8.4: Input capture data management.
In order to handle the overcapture, it is recommended to read the data before the
overcapture flag. This is to avoid missing an overcapture which could happen after reading
the flag and before reading the data.
Note: IC interrupt requests can be generated by software by setting the corresponding CCxG bit in
the TIMx_EGR register.

16.3.6 Forced output mode

In output mode (CCxS bits = ‘00’ in the TIMx_CCMRx register), each output compare signal
(OCxREF and then OCx) can be forced to active or inactive level directly by software,
independently of any comparison between the output compare register and the counter.
To force an output compare signal (OCXREF/OCx) to its active level, one just needs to write
‘101’ in the OCxM bits in the corresponding TIMx_CCMRx register. Thus OCXREF is forced
high (OCxREF is always active high) and OCx get opposite value to CCxP polarity bit.
For example: CCxP=’0’ (OCx active high) => OCx is forced to high level.
The OCxREF signal can be forced low by writing the OCxM bits to ‘100’ in the
TIMx_CCMRx register.
The comparison between the TIMx_CCRx shadow register and the counter is still performed
and allows the flag to be set. Interrupt requests can be sent accordingly. This is described in
the output compare mode section below.

16.3.7 Output compare mode

This function is used to control an output waveform or to indicate when a period of time has
elapsed.
When a match is found between the capture/compare register and the counter, the output
compare function:

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RM0360 General-purpose timer (TIM14)

1. Assigns the corresponding output pin to a programmable value defined by the output
compare mode (OCxM bits in the TIMx_CCMRx register) and the output polarity (CCxP
bit in the TIMx_CCER register). The output pin can keep its level (OCXM=’000’), be set
active (OCxM=’001’), be set inactive (OCxM=’010’) or can toggle (OCxM=’011’) on
match.
2. Sets a flag in the interrupt status register (CCxIF bit in the TIMx_SR register).
3. Generates an interrupt if the corresponding interrupt mask is set (CCXIE bit in the
TIMx_DIER register).
The TIMx_CCRx registers can be programmed with or without preload registers using the
OCxPE bit in the TIMx_CCMRx register.
In output compare mode, the update event UEV has no effect on OCxREF and OCx output.
The timing resolution is one count of the counter. Output compare mode can also be used to
output a single pulse (in One-pulse mode).
Procedure:
1. Select the counter clock (internal, external, prescaler).
2. Write the desired data in the TIMx_ARR and TIMx_CCRx registers.
3. Set the CCxIE bit if an interrupt request is to be generated.
4. Select the output mode. For example:
– Write OCxM = ‘011’ to toggle OCx output pin when CNT matches CCRx
– Write OCxPE = ‘0’ to disable preload register
– Write CCxP = ‘0’ to select active high polarity
– Write CCxE = ‘1’ to enable the output
5. Enable the counter by setting the CEN bit in the TIMx_CR1 register.
For code example refer to the Appendix section A.8.7: Output compare configuration.
The TIMx_CCRx register can be updated at any time by software to control the output
waveform, provided that the preload register is not enabled (OCxPE=’0’, else TIMx_CCRx
shadow register is updated only at the next update event UEV). An example is given in
Figure 162.

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General-purpose timer (TIM14) RM0360

Figure 162. Output compare mode, toggle on OC1

Write 0xB201 in the CC1R register

TIMx_CNT 0039 003A 003B B200 B201

TIMx_CCR1 003A B201

OC1REF= OC1

Match detected on CCR1

Interrupt generated if enabled
MSv67583V1

16.3.8 PWM mode

Pulse Width Modulation mode allows to generate a signal with a frequency determined by
the value of the TIMx_ARR register and a duty cycle determined by the value of the
TIMx_CCRx register.
The PWM mode can be selected independently on each channel (one PWM per OCx
output) by writing ‘110’ (PWM mode 1) or ‘111’ (PWM mode 2) in the OCxM bits in the
TIMx_CCMRx register. The corresponding preload register must be enabled by setting the
OCxPE bit in the TIMx_CCMRx register, and eventually the auto-reload preload register by
setting the ARPE bit in the TIMx_CR1 register.
As the preload registers are transferred to the shadow registers only when an update event
occurs, before starting the counter, all registers must be initialized by setting the UG bit in
the TIMx_EGR register.
The OCx polarity is software programmable using the CCxP bit in the TIMx_CCER register.
It can be programmed as active high or active low. The OCx output is enabled by the CCxE
bit in the TIMx_CCER register. Refer to the TIMx_CCERx register description for more
details.
In PWM mode (1 or 2), TIMx_CNT and TIMx_CCRx are always compared to determine
whether TIMx_CNT ≤ TIMx_CCRx.
The timer is able to generate PWM in edge-aligned mode only since the counter is
upcounting.

PWM edge-aligned mode

In the following example, we consider PWM mode 1. The reference PWM signal OCxREF is
high as long as TIMx_CNT < TIMx_CCRx else it becomes low. If the compare value in
TIMx_CCRx is greater than the auto-reload value (in TIMx_ARR) then OCxREF is held at
‘1’. If the compare value is 0 then OCxRef is held at ‘0’. Figure 163 shows some edge-
aligned PWM waveforms in an example where TIMx_ARR=8.

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RM0360 General-purpose timer (TIM14)

Figure 163. Edge-aligned PWM waveforms (ARR=8)

Counter register 0 1 2 3 4 5 6 7 8 0 1

OCXREF
CCRx=4
CCxIF

OCXREF
CCRx=8
CCxIF

OCXREF ‘1’
CCRx>8
CCxIF

OCXREF ‘0’
CCRx=0
CCxIF

MS31093V1

For code example refer to the Appendix section A.8.8: Edge-aligned PWM configuration
example.

16.3.9 Debug mode

When the microcontroller enters debug mode (Cortex™-M0 core halted), the TIMx counter
either continues to work normally or stops, depending on DBG_TIMx_STOP configuration
bit in DBG module.

16.4 TIM14 registers

16.4.1 TIM14 control register 1 (TIM14_CR1)

Address offset: 0x00
Reset value: 0x0000

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. CKD[1:0] ARPE Res. Res. Res. Res. URS UDIS CEN
rw rw rw rw rw rw

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467
General-purpose timer (TIM14) RM0360

Bits 15:10 Reserved, must be kept at reset value.

Bits 9:8 CKD[1:0]: Clock division
This bit-field indicates the division ratio between the timer clock (CK_INT) frequency and
sampling clock used by the digital filters (ETR, TIx),
00: tDTS = tCK_INT
01: tDTS = 2 × tCK_INT
10: tDTS = 4 × tCK_INT
11: Reserved
Bit 7 ARPE: Auto-reload preload enable
0: TIMx_ARR register is not buffered
1: TIMx_ARR register is buffered
Bits 6:3 Reserved, must be kept at reset value.
Bit 2 URS: Update request source
This bit is set and cleared by software to select the update interrupt (UEV) sources.
0: Any of the following events generate an UEV if enabled:
– Counter overflow
– Setting the UG bit
1: Only counter overflow generates an UEV if enabled.
Bit 1 UDIS: Update disable
This bit is set and cleared by software to enable/disable update interrupt (UEV) event
generation.
0: UEV enabled. An UEV is generated by one of the following events:
– Counter overflow
– Setting the UG bit.
Buffered registers are then loaded with their preload values.
1: UEV disabled. No UEV is generated, shadow registers keep their value (ARR, PSC,
CCRx). The counter and the prescaler are reinitialized if the UG bit is set.
Bit 0 CEN: Counter enable
0: Counter disabled
1: Counter enabled

16.4.2 TIM14 interrupt enable register (TIM14_DIER)

Address offset: 0x0C
Reset value: 0x0000

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CC1IE UIE
rw rw

Bits 15:2 Reserved, must be kept at reset value.

Bit 1 CC1IE: Capture/Compare 1 interrupt enable
0: CC1 interrupt disabled
1: CC1 interrupt enabled
Bit 0 UIE: Update interrupt enable
0: Update interrupt disabled
1: Update interrupt enabled

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RM0360 General-purpose timer (TIM14)

16.4.3 TIM14 status register (TIM14_SR)

Address offset: 0x10
Reset value: 0x0000

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. CC1OF Res. Res. Res. Res. Res. Res. Res. CC1IF UIF
rc_w0 rc_w0 rc_w0

Bits 15:10 Reserved, must be kept at reset value.

Bit 9 CC1OF: Capture/Compare 1 overcapture flag
This flag is set by hardware only when the corresponding channel is configured in input
capture mode. It is cleared by software by writing it to ‘0’.
0: No overcapture has been detected.
1: The counter value has been captured in TIMx_CCR1 register while CC1IF flag was
already set
Bits 8:2 Reserved, must be kept at reset value.
Bit 1 CC1IF: Capture/compare 1 interrupt flag
Condtion: channel CC1 is configured as output
This flag is set by hardware when the counter matches the compare value. It is cleared by
software.
0: No match.
1: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register.
When the contents of TIMx_CCR1 are greater than the contents of TIMx_ARR, the CC1IF bit
goes high on the counter overflow.
Condition: channel CC1 is configured as input
This bit is set by hardware on a capture. It is cleared by software or by reading the
TIMx_CCR1 register.
0: No input capture occurred.
1: The counter value has been captured in TIMx_CCR1 register (an edge has been detected
on IC1 which matches the selected polarity).
Bit 0 UIF: Update interrupt flag
This bit is set by hardware on an update event. It is cleared by software.
0: No update occurred.
1: Update interrupt pending. This bit is set by hardware when the registers are updated:
– At overflow and if UDIS=’0’ in the TIMx_CR1 register.
– When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if
URS=’0’ and UDIS=’0’ in the TIMx_CR1 register.

16.4.4 TIM14 event generation register (TIM14_EGR)

Address offset: 0x14
Reset value: 0x0000

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CC1G UG
w w

RM0360 Rev 5 393/775

467
General-purpose timer (TIM14) RM0360

Bits 15:2 Reserved, must be kept at reset value.

Bit 1 CC1G: Capture/compare 1 generation
This bit is set by software in order to generate an event, it is automatically cleared by
hardware.
0: No action
1: A capture/compare event is generated on channel 1:
Condition: channel CC1 is configured as output
CC1IF flag is set, Corresponding interrupt or is sent if enabled.
Condition: channel CC1 is configured as input
The current value of the counter is captured in TIMx_CCR1 register. The CC1IF flag is set,
the corresponding interrupt is sent if enabled. The CC1OF flag is set if the CC1IF flag was
already high.
Bit 0 UG: Update generation
This bit can be set by software, it is automatically cleared by hardware.
0: No action
1: Re-initialize the counter and generates an update of the registers. Note that the prescaler
counter is cleared too (anyway the prescaler ratio is not affected). The counter is cleared.

16.4.5 TIM14 capture/compare mode register 1 [alternate] (TIM14_CCMR1)

Address offset: 0x18
Reset value: 0x0000
The same register can be used for input capture mode (this section) or for output compare
mode (next section).. The direction of a channel is defined by configuring the corresponding
CCxS bits. All the other bits of this register have a different function in input and in output
mode. For a given bit, OCxx describes its function when the channel is configured in output,
ICxx describes its function when the channel is configured in input. So one must take care
that the same bit can have a different meaning for the input stage and for the output stage

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. IC1F[3:0] IC1PSC[1:0] CC1S[1:0]
rw rw rw rw rw rw rw rw

Bits 15:8 Reserved, must be kept at reset value.

394/775 RM0360 Rev 5

RM0360 General-purpose timer (TIM14)

Bits 7:4 IC1F[3:0]: Input capture 1 filter

This bit-field defines the frequency used to sample TI1 input and the length of the digital filter
applied to TI1. The digital filter is made of an event counter in which N events are needed to
validate a transition on the output:
0000: No filter, sampling is done at fDTS
0001: fSAMPLING = fCK_INT, N = 2
0010: fSAMPLING = fCK_INT, N = 4
0011: fSAMPLING = fCK_INT, N = 8
0100: fSAMPLING = fDTS / 2, N = 6
0101: fSAMPLING = fDTS / 2, N = 8
0110: fSAMPLING = fDTS / 4, N = 6
0111: fSAMPLING = fDTS / 4, N = 8
1000: fSAMPLING = fDTS / 8, N = 6
1001: fSAMPLING = fDTS / 8, N = 8
1010: fSAMPLING = fDTS / 16, N = 5
1011: fSAMPLING = fDTS / 16, N = 6
1100: fSAMPLING = fDTS / 16, N = 8
1101: fSAMPLING = fDTS / 32, N = 5
1110: fSAMPLING = fDTS / 32, N = 6
1111: fSAMPLING = fDTS / 32, N = 8
Note: Care must be taken that fDTS is replaced in the formula by CK_INT when ICxF[3:0] = 1,
2 or 3.
Bits 3:2 IC1PSC[1:0]: Input capture 1 prescaler
This bit-field defines the ratio of the prescaler acting on CC1 input (IC1).
The prescaler is reset as soon as CC1E=’0’ (TIMx_CCER register).
00: no prescaler, capture is done each time an edge is detected on the capture input
01: capture is done once every 2 events
10: capture is done once every 4 events
11: capture is done once every 8 events
Bits 1:0 CC1S[1:0]: Capture/Compare 1 selection
This bit-field defines the direction of the channel (input/output) as well as the used input.
00: CC1 channel is configured as output
01: CC1 channel is configured as input, IC1 is mapped on TI1
Other: Reserved
Note: CC1S bits are writable only when the channel is OFF (CC1E = 0 in TIMx_CCER).

16.4.6 TIM14 capture/compare mode register 1 [alternate] (TIM14_CCMR1)

Address offset: 0x18
Reset value: 0x0000
The same register can be used for output compare mode (this section) or for input capture
mode (previous section). The direction of a channel is defined by configuring the
corresponding CCxS bits. All the other bits of this register have a different function in input
and in output mode. For a given bit, OCxx describes its function when the channel is
configured in output, ICxx describes its function when the channel is configured in input. So
one must take care that the same bit can have a different meaning for the input stage and
for the output stage.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. OC1M[2:0] OC1PE OC1FE CC1S[1:0]
rw rw rw rw rw rw rw

RM0360 Rev 5 395/775

467
General-purpose timer (TIM14) RM0360

Bits 15:7 Reserved, must be kept at reset value.

Bits 6:4 OC1M[2:0]: Output compare 1 mode
These bits define the behavior of the output reference signal OC1REF from which OC1 is
derived. OC1REF is active high whereas OC1 active level depends on CC1P bit.
000: Frozen. The comparison between the output compare register TIMx_CCR1 and the
counter TIMx_CNT has no effect on the outputs.
001: Set channel 1 to active level on match. OC1REF signal is forced high when the counter
TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1).
010: Set channel 1 to inactive level on match. OC1REF signal is forced low when the
counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1).
011: Toggle - OC1REF toggles when TIMx_CNT = TIMx_CCR1.
100: Force inactive level - OC1REF is forced low.
101: Force active level - OC1REF is forced high.
110: PWM mode 1 - Channel 1 is active as long as TIMx_CNT < TIMx_CCR1 else inactive.
111: PWM mode 2 - Channel 1 is inactive as long as TIMx_CNT < TIMx_CCR1 else active.
Note: In PWM mode 1 or 2, the OCREF level changes when the result of the comparison
changes or when the output compare mode switches from frozen to PWM mode.
Bit 3 OC1PE: Output compare 1 preload enable
0: Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the new
value is taken in account immediately.
1: Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload
register. TIMx_CCR1 preload value is loaded in the active register at each update event.
Note: The PWM mode can be used without validating the preload register only in one pulse
mode (OPM bit set in TIMx_CR1 register). Else the behavior is not guaranteed.
Bit 2 OC1FE: Output compare 1 fast enable
This bit is used to accelerate the effect of an event on the trigger in input on the CC output.
0: CC1 behaves normally depending on counter and CCR1 values even when the trigger is
ON. The minimum delay to activate CC1 output when an edge occurs on the trigger input
is 5 clock cycles.
1: An active edge on the trigger input acts like a compare match on CC1 output. OC is then
set to the compare level independently of the result of the comparison. Delay to sample
the trigger input and to activate CC1 output is reduced to 3 clock cycles. OC1FE acts only
if the channel is configured in PWM1 or PWM2 mode.
Bits 1:0 CC1S[1:0]: Capture/Compare 1 selection
This bit-field defines the direction of the channel (input/output) as well as the used input.
00: CC1 channel is configured as output.
01: CC1 channel is configured as input, IC1 is mapped on TI1.
10: Reserved
11: Reserved
Note: CC1S bits are writable only when the channel is OFF (CC1E = 0 in TIMx_CCER).

16.4.7 TIM14 capture/compare enable register (TIM14_CCER)

Address offset: 0x20
Reset value: 0x0000

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CC1NP Res. CC1P CC1E
rw rw rw

396/775 RM0360 Rev 5

RM0360 General-purpose timer (TIM14)

Bits 15:4 Reserved, must be kept at reset value.

Bit 3 CC1NP: Capture/Compare 1 complementary output Polarity.
CC1 channel configured as output: CC1NP must be kept cleared.
CC1 channel configured as input: CC1NP bit is used in conjunction with CC1P to define
TI1FP1 polarity (refer to CC1P description).
Bit 2 Reserved, must be kept at reset value.
Bit 1 CC1P: Capture/Compare 1 output Polarity.
Condition: CC1 channel configured as output
0: OC1 active high
1: OC1 active low
Condition: CC1 channel configured as input
The CC1P bit selects TI1FP1 and TI2FP1 polarity for trigger or capture operations.
00: noninverted/rising edge
Circuit is sensitive to TI1FP1 rising edge (capture mode), TI1FP1 is not inverted.
01: inverted/falling edge
Circuit is sensitive to TI1FP1 falling edge (capture mode), TI1FP1 is inverted.
10: reserved, do not use this configuration.
11: noninverted/both edges
Circuit is sensitive to both TI1FP1 rising and falling edges (capture mode), TI1FP1 is not
inverted.
Bit 0 CC1E: Capture/Compare 1 output enable.
Condition: CC1 channel configured as output:
0: Off - OC1 is not active
1: On - OC1 signal is output on the corresponding output pin
Condition: CC1 channel configured as input:
This bit determines if a capture of the counter value can actually be done into the input
capture/compare register 1 (TIMx_CCR1) or not.
0: Capture disabled
1: Capture enabled

Table 52. Output control bit for standard OCx channels

CCxE bit OCx output state
0 Output Disabled (OCx=’0’, OCx_EN=’0’)
1 OCx=OCxREF + Polarity, OCx_EN=’1’

Note: The state of the external I/O pins connected to the standard OCx channels depends on the
OCx channel state and the GPIO registers.

16.4.8 TIM14 counter (TIM14_CNT)

Address offset: 0x24
Reset value: 0x0000

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 15:0 CNT[15:0]: Counter value

RM0360 Rev 5 397/775

467
General-purpose timer (TIM14) RM0360

16.4.9 TIM14 prescaler (TIM14_PSC)

Address offset: 0x28
Reset value: 0x0000

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 15:0 PSC[15:0]: Prescaler value

The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1).
PSC contains the value to be loaded in the active prescaler register at each update event.

16.4.10 TIM14 auto-reload register (TIM14_ARR)

Address offset: 0x2C
Reset value: 0xFFFF

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 15:0 ARR[15:0]: Auto-reload value

ARR is the value to be loaded in the actual auto-reload register.
Refer to the Section 16.3.1: Time-base unit on page 381 for more details about ARR update
and behavior.
The counter is blocked while the auto-reload value is null.

16.4.11 TIM14 capture/compare register 1 (TIM14_CCR1)

Address offset: 0x34
Reset value: 0x0000

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR1[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 15:0 CCR1[15:0]: Capture/Compare 1 value

Condition: channel CC1 is configured as output
CCR1 is the value to be loaded in the actual capture/compare 1 register (preload value).
It is loaded permanently if the preload feature is not selected in the TIMx_CCMR1 register
(bit OC1PE). Else the preload value is copied in the active capture/compare 1 register when
an update event occurs.
The active capture/compare register contains the value to be compared to the counter
TIMx_CNT and signaled on OC1 output.
Condition: channel CC1is configured as input
CCR1 is the counter value transferred by the last input capture 1 event (IC1).

398/775 RM0360 Rev 5

RM0360 General-purpose timer (TIM14)

16.4.12 TIM14 option register (TIM14_OR)

Address offset: 0x50
Reset value: 0x0000

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. TI1_RMP[1:0]
rw rw

Bits 15:2 Reserved, must be kept at reset value.

Bits 1:0 TI1_RMP[1:0]: Timer Input 1 remap
Set and cleared by software.
00: TIM14 Channel1 is connected to the GPIO. Refer to the alternate function mapping in the
device datasheets.
01: TIM14 Channel1 is connected to the RTCCLK.
10: TIM14 Channel1 is connected to the HSE/32 Clock.
11: TIM14 Channel1 is connected to the microcontroller clock output (MCO), this selection is
controlled by the MCO[2:0] bits of the Clock configuration register (RCC_CFGR) (see
Section 7.4.2: Clock configuration register (RCC_CFGR)).

16.4.13 TIM14 register map

TIM14 registers are mapped as 16-bit addressable registers as described in the table
below:

Table 53. TIM14 register map and reset values

Offset Register
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12

10
11

9
8
7
6
5
4
3
2
1
0
ARPE
CKD

UDIS
CEN
URS
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.
Res.
Res.
Res.
TIM14_CR1
0x00 [1:0]
Reset value 0 0 0 0 0 0

0x08 Reserved Res.

CC1IE
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

UIE
TIM14_DIER
0x0C
Reset value 0 0
CC1OF

CC1IF
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.
Res.
Res.
Res.
Res.
Res.
Res.

UIF

TIM14_SR
0x10
Reset value 0 0 0
CC1G
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

UG

TIM14_EGR
0x14
Reset value 0 0
TIM14_CCMR1
OC1PE
OC1FE

OC1M CC1S
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Output compare
[2:0] [1:0]
mode
Reset value 0 0 0 0 0 0 0
0x18
TIM14_CCMR1 IC1
CC1S
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Input capture IC1F[3:0] PSC

[1:0]
mode [1:0]
Reset value 0 0 0 0 0 0 0 0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Reserved
0x1C
Reset value

RM0360 Rev 5 399/775

467
 0x50
0x34
0x30
0x28
0x24
0x20

0x4C
0x2C

0x38 to
Offset

400/775
Reserved
Reserved

TIM14_OR
Register

Reset value
Reset value
Reset value
Reset value
Reset value

Reset value
Reset value
Reset value
TIM14_CNT

TIM14_PSC

TIM14_ARR

TIM14_CCR1
TIM14_CCER

Res. Res. Res. Res. Res. Res. Res. Res. 31

Res. Res. Res. Res. Res. Res. Res. Res. 30
Res. Res. Res. Res. Res. Res. Res. Res. 29
Res. Res. Res. Res. Res. Res. Res. Res. 28
Res. Res. Res. Res. Res. Res. Res. Res.
General-purpose timer (TIM14)

27
Res. Res. Res. Res. Res. Res. Res. Res. 26
Res. Res. Res. Res. Res. Res. Res. Res. 25
Res. Res. Res. Res. Res. Res. Res. Res. 24
Res. Res. Res. Res. Res. Res. Res. Res. 23
Res. Res. Res. Res. Res. Res. Res. Res. 22
Res. Res. Res. Res. Res. Res. Res. Res. 21
Res. Res. Res. Res. Res. Res. Res. Res. 20
Res. Res. Res. Res. Res. Res. Res. Res. 19
Res. Res. Res. Res. Res. Res. Res. Res. 18

RM0360 Rev 5
Res. Res. Res. Res. Res. Res. Res. Res. 17
Res. Res. Res. Res. Res. Res. Res. Res. 16
0
1
0
0

Res. Res. Res. Res. 15

0
1
0
0

Res. Res. Res. Res. 14

0
1
0
0

Res. Res. Res. Res. 13

0
1
0
0

Res. Res. Res. Res. 12

0
1
0
0

Res. Res. Res. Res. 11

0
1
0
0

Res. Res. Res. Res. 10

0
1
0
0

Res. Res. Res. Res. 9

Refer to Section 2.2 on page 37 for the register boundary addresses.

0
1
0
0

Res. Res. Res. Res.

Table 53. TIM14 register map and reset values (continued)

8
0
1
0
0

Res. Res. Res. Res. 7

PSC[15:0]
CNT[15:0]

ARR[15:0]

CCR1[15:0]

0
1
0
0

Res. Res. Res. Res. 6

0
1
0
0

Res. Res. Res. Res. 5

0
1
0
0

Res. Res. Res. Res. 4

0
1
0
0
0

Res. Res. Res. CC1NP 3

0
1
0
0

Res. Res. Res. Res. 2

0
1
0
0

0
0

Res. Res. CC1P 1

TI1_RMP
0
1
0
0

0
0

Res. Res. CC1E

RM0360

0
RM0360 General-purpose timers (TIM15/16/17)

17 General-purpose timers (TIM15/16/17)

TIM15 is not available on STM32F030x4 and STM32F030x6 devices.

17.1 TIM15/16/17 introduction

The TIM15/16/17 timers consist of a 16-bit auto-reload counter driven by a programmable
prescaler.
They may be used for a variety of purposes, including measuring the pulse lengths of input
signals (input capture) or generating output waveforms (output compare, PWM,
complementary PWM with dead-time insertion).
Pulse lengths and waveform periods can be modulated from a few microseconds to several
milliseconds using the timer prescaler and the RCC clock controller prescalers.
The TIM15/16/17 timers are completely independent, and do not share any resources. The
TIM15 can be synchronized with other timers.

17.2 TIM15 main features

TIM15 includes the following features:
• 16-bit auto-reload upcounter
• 16-bit programmable prescaler used to divide (also “on the fly”) the counter clock
frequency by any factor between 1 and 65535
• Up to 2 independent channels for:
– Input capture
– Output compare
– PWM generation (Edge-aligned mode)
– One-pulse mode output
• Complementary outputs with programmable dead-time (for channel 1 only)
• Synchronization circuit to control the timer with external signals and to interconnect
several timers together
• Repetition counter to update the timer registers only after a given number of cycles of
the counter
• Break input to put the timer’s output signals in the reset state or a known state
• Interrupt/DMA generation on the following events:
– Update: counter overflow, counter initialization (by software or internal/external
trigger)
– Trigger event (counter start, stop, initialization or count by internal/external trigger)
– Input capture
– Output compare
– Break input (interrupt request)

RM0360 Rev 5 401/775

467
General-purpose timers (TIM15/16/17) RM0360

Figure 164. TIM15 block diagram

Internal clock (CK_INT)

CK_TIM1121314151617 from RCC Trigger
controller TRGO
to other timers
ITR0 TGI
ITR1 ITR Slave
ITR2 TRC TRGI controller Reset, enable, up, count
ITR3 mode
TI1F_ED
TI1FP1
TI2FP2

REP register
U UI
Auto-reload register
Repetition
Stop, clear or up/down U
counter
CK_PSC PSC CK_CNT +/- CNT counter
prescaler DTG registers
CC1I U CC1I TIMx_CH1
TI1FP1 OC1REF
TI1 Input filter & TI1FP2 IC1 IC1PS Capture/Compare 1 register Output OC1
TIMx_CH1 Prescaler DTG
edge detector control TIMx_CH1N
TRC
CC2I OC1N
U CC2I
TI2FP1
TI2 Input filter & IC2 Output OC2 TIMx_CH2
TIMx_CH2 TI2FP2 Prescaler
IC2PS Capture/Compare 2 register OC2REF
edge detector control
TRC

BRK BI
TIMx_BKIN Polarity selection

Internal break event sources

Notes:
Preload registers transferred
Reg
to active registers on U event
according to control bit

Event

Interrupt & DMA output

ai17330V2

402/775 RM0360 Rev 5

RM0360 General-purpose timers (TIM15/16/17)

17.3 TIM16 and TIM17 main features

The TIM16 and TIM17 timers include the following features:
• 16-bit auto-reload upcounter
• 16-bit programmable prescaler used to divide (also “on the fly”) the counter clock
frequency by any factor between 1 and 65535
• One channel for:
– Input capture
– Output compare
– PWM generation (Edge-aligned mode)
– One-pulse mode output
• Complementary outputs with programmable dead-time
• Repetition counter to update the timer registers only after a given number of cycles of
the counter
• Break input to put the timer’s output signals in the reset state or a known state
• Interrupt/DMA generation on the following events:
– Update: counter overflow
– Input capture
– Output compare
– Break input

RM0360 Rev 5 403/775

467
General-purpose timers (TIM15/16/17) RM0360

Figure 165. TIM16 and TIM17 block diagram

Internal clock (CK_INT)

Counter Enable (CEN)

REP register

Auto-reload register UI
U
Repetition
Stop, clear or up/down U
counter
CK_PSC PSC CK_CNT
+/- CNT counter
prescaler DTG registers
C1I CC1I
U TIMx_CH1
TI1 TI1FP1 IC1
TIMx_CH1 Input filter & IC1PS OC1REF
Prescaler Capture/compare 1 register Output OC1
edge selector DTG control TIMx_CH1N
OC1N

BRK BI
TIMx_BKIN Polarity selection

Internal break event sources

Notes:
Preload registers transferred
Reg
to active registers on U event
according to control bit

Event

Interrupt & DMA output

MS31415V5

17.4 TIM15/16/17 functional description

17.4.1 Time-base unit

The main block of the programmable general purpose timer is a 16-bit upcounter with its
related auto-reload register. The counter clock can be divided by a prescaler.
The counter, the auto-reload register and the prescaler register can be written or read by
software. This is true even when the counter is running.
The time-base unit includes:
• Counter register (TIMx_CNT)
• Prescaler register (TIMx_PSC)
• Auto-reload register (TIMx_ARR)
• Repetition counter register (TIMx_RCR)
The auto-reload register is preloaded. Writing to or reading from the auto-reload register
accesses the preload register. The content of the preload register are transferred into the
shadow register permanently or at each update event (UEV), depending on the auto-reload
preload enable bit (ARPE) in TIMx_CR1 register. The update event is sent when the counter
reaches the overflow (or underflow when downcounting) and if the UDIS bit equals 0 in the

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TIMx_CR1 register. It can also be generated by software. The generation of the update
event is described in detailed for each configuration.
The counter is clocked by the prescaler output CK_CNT, which is enabled only when the
counter enable bit (CEN) in TIMx_CR1 register is set (refer also to the slave mode controller
description to get more details on counter enabling).
Note that the counter starts counting 1 clock cycle after setting the CEN bit in the TIMx_CR1
register.

Prescaler description
The prescaler can divide the counter clock frequency by any factor between 1 and 65536. It
is based on a 16-bit counter controlled through a 16-bit register (in the TIMx_PSC register).
It can be changed on the fly as this control register is buffered. The new prescaler ratio is
taken into account at the next update event.
Figure 151 and Figure 152 give some examples of the counter behavior when the prescaler
ratio is changed on the fly:

Figure 166. Counter timing diagram with prescaler division change from 1 to 2

CK_PSC

CEN

Timerclock = CK_CNT

Counter register F7 F8 F9 FA FB FC 00 01 02 03

Update event (UEV)

Prescaler control register 0 1

Write a new value in TIMx_PSC

Prescaler buffer 0 1

Prescaler counter 0 0 1 0 1 0 1 0 1
MS31076V2

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Figure 167. Counter timing diagram with prescaler division change from 1 to 4

CK_PSC

CEN

Timerclock = CK_CNT

F7 F8 F9 FA FB FC 00 01
Counter register

Update event (UEV)

0 3
Prescaler control register

Write a new value in TIMx_PSC

0 3
Prescaler buffer

0 0 1 2 3 0 1 2 3
Prescaler counter

MS31077V2

17.4.2 Counter operation

The counter counts from 0 to the auto-reload value (content of the TIMx_ARR register), then
restarts from 0 and generates a counter overflow event.
If the repetition counter is used, the update event (UEV) is generated after upcounting is
repeated for the number of times programmed in the repetition counter register
(TIMx_RCR). Else the update event is generated at each counter overflow.
Setting the UG bit in the TIMx_EGR register (by software or by using the slave mode
controller) also generates an update event.
The UEV event can be disabled by software by setting the UDIS bit in the TIMx_CR1
register. This is to avoid updating the shadow registers while writing new values in the
preload registers. Then no update event occurs until the UDIS bit has been written to 0.
However, the counter restarts from 0, as well as the counter of the prescaler (but the
prescale rate does not change). In addition, if the URS bit (update request selection) in
TIMx_CR1 register is set, setting the UG bit generates an update event UEV but without
setting the UIF flag (thus no interrupt or DMA request is sent). This is to avoid generating
both update and capture interrupts when clearing the counter on the capture event.
When an update event occurs, all the registers are updated and the update flag (UIF bit in
TIMx_SR register) is set (depending on the URS bit):
• The repetition counter is reloaded with the content of TIMx_RCR register,
• The auto-reload shadow register is updated with the preload value (TIMx_ARR),
• The buffer of the prescaler is reloaded with the preload value (content of the TIMx_PSC
register).

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The following figures show some examples of the counter behavior for different clock
frequencies when TIMx_ARR=0x36.

Figure 168. Counter timing diagram, internal clock divided by 1

CK_PSC

CNT_EN

Timerclock = CK_CNT

Counter register 31 32 33 34 35 36 00 01 02 03 04 05 06 07

Counter overflow

Update event (UEV)

Update interrupt flag

(UIF)

MS31078V2

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Figure 169. Counter timing diagram, internal clock divided by 2

CK_PSC

CNT_EN

Timerclock = CK_CNT

Counter register 0034 0035 0036 0000 0001 0002 0003

Counter overflow

Update event (UEV)

Update interrupt flag

(UIF)

MS31079V2

Figure 170. Counter timing diagram, internal clock divided by 4

CK_PSC

CNT_EN

Timerclock = CK_CNT

Counter register 0035 0036 0000 0001

Counter overflow

Update event (UEV)

Update interrupt flag

(UIF)

MS31080V2

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Figure 171. Counter timing diagram, internal clock divided by N

CK_PSC

Timerclock = CK_CNT

Counter register 1F 20 00

Counter overflow

Update event (UEV)

Update interrupt flag

(UIF)

MS31081V2

Figure 172. Counter timing diagram, update event when ARPE=0

(TIMx_ARR not preloaded)

CK_PSC

CEN

Timerclock = CK_CNT

Counter register 31 32 33 34 35 36 00 01 02 03 04 05 06 07

Counter overflow

Update event (UEV)

Update interrupt flag

(UIF)

Auto-reload preload
register FF 36

Write a new value in TIMx_ARR

MS31082V2

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Figure 173. Counter timing diagram, update event when ARPE=1

(TIMx_ARR preloaded)

CK_PSC

CEN

Timerclock = CK_CNT

Counter register F0 F1 F2 F3 F4 F5 00 01 02 03 04 05 06 07

Counter overflow

Update event (UEV)

Update interrupt flag

(UIF)
Auto-reload preload
F5 36
register

Auto-reload shadow
register F5 36

Write a new value in TIMx_ARR MS31083V2

17.4.3 Repetition counter

Section 16.3.1: Time-base unit describes how the update event (UEV) is generated with
respect to the counter overflows/underflows. It is actually generated only when the repetition
counter has reached zero. This can be useful when generating PWM signals.
This means that data are transferred from the preload registers to the shadow registers
(TIMx_ARR auto-reload register, TIMx_PSC prescaler register, but also TIMx_CCRx
capture/compare registers in compare mode) every N counter overflows or underflows,
where N is the value in the TIMx_RCR repetition counter register.
The repetition counter is decremented at each counter overflow in upcounting mode.
The repetition counter is an auto-reload type; the repetition rate is maintained as defined by
the TIMx_RCR register value (refer to Figure 174). When the update event is generated by
software (by setting the UG bit in TIMx_EGR register) or by hardware through the slave
mode controller, it occurs immediately whatever the value of the repetition counter is and the
repetition counter is reloaded with the content of the TIMx_RCR register.

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Figure 174. Update rate examples depending on mode and TIMx_RCR register
settings

Edge-aligned mode

Upcounting

Counter
TIMx_CNT

TIMx_RCR = 0 UEV

TIMx_RCR = 1 UEV

TIMx_RCR = 2 UEV

TIMx_RCR = 3 UEV

TIMx_RCR = 3
and
re-synchronization UEV

(by SW)

UEV Update Event: preload registers transferred to active registers

and update interrupt generated.

17.4.4 Clock sources

The counter clock can be provided by the following clock sources:
• Internal clock (CK_INT)
• External clock mode1: external input pin (only for TIM15)
• Internal trigger inputs (ITRx) (only for TIM15): using one timer as the prescaler for
another timer, for example, TIM1 can be configured to act as a prescaler for TIM15.
Refer to Using one timer as prescaler for another for more details.

Internal clock source (CK_INT)

For TIM15 if the slave mode controller is disabled (SMS=000), then the CEN and UG bits (in
the TIMx_EGR register) are actual control bits and can be changed only by software (except
UG which remains cleared automatically). As soon as the CEN bit is written to 1, the
prescaler is clocked by the internal clock CK_INT.

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Figure 16.3.4 shows the behavior of the control circuit and the upcounter in normal mode,
without prescaler.

Figure 175. Control circuit in normal mode, internal clock divided by 1

Internal clock

CEN=CNT_EN

UG

CNT_INIT

Counter clock = CK_CNT = CK_PSC

Counter register 31 32 33 34 35 36 00 01 02 03 04 05 06 07

MS31085V2

External clock source mode 1

This mode is selected when SMS=111 in the TIMx_SMCR register. The counter can count at
each rising or falling edge on a selected input.

Figure 176. TI2 external clock connection example

TIMx_SMCR
TS[2:0]

or TI2F or
TI1F or Encoder
ITRx mode
0xx
TI1_ED
100 TRGI External clock
TI1FP1 mode 1 CK_PSC
TI2F_Rising 101
TI2 Edge 0 TI2FP2 ETRF External clock
Filter 110
detector 1 ETRF mode 2
TI2F_Falling 111
CK_INT Internal clock
mode
ICF[3:0] CC2P (internal clock)

TIMx_CCMR1 TIMx_CCER
ECE SMS[2:0]
TIMx_SMCR

MS31196V1

For example, to configure the upcounter to count in response to a rising edge on the TI2
input, use the following procedure:

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1. Configure channel 2 to detect rising edges on the TI2 input by writing CC2S = ‘01’ in
the TIMx_CCMR1 register.
2. Configure the input filter duration by writing the IC2F[3:0] bits in the TIMx_CCMR1
register (if no filter is needed, keep IC2F=0000).
3. Select rising edge polarity by writing CC2P=0 in the TIMx_CCER register.
4. Configure the timer in external clock mode 1 by writing SMS=111 in the TIMx_SMCR
register.
5. Select TI2 as the trigger input source by writing TS=110 in the TIMx_SMCR register.
6. Enable the counter by writing CEN=1 in the TIMx_CR1 register.
Note: The capture prescaler is not used for triggering, so it does not need to be configured.
For code example refer to the Appendix section A.8.1: Upcounter on TI2 rising edge.
When a rising edge occurs on TI2, the counter counts once and the TIF flag is set.
The delay between the rising edge on TI2 and the actual clock of the counter is due to the
resynchronization circuit on TI2 input.

Figure 177. Control circuit in external clock mode 1

TI2

CNT_EN

Counter clock = CK_CNT = CK_PSC

Counter register 34 35 36

TIF

Write TIF=0

MS31087V2

17.4.5 Capture/compare channels

Each Capture/Compare channel is built around a capture/compare register (including a
shadow register), a input stage for capture (with digital filter, multiplexing and prescaler) and
an output stage (with comparator and output control).
Figure 159 to Figure 181 give an overview of one Capture/Compare channel.
The input stage samples the corresponding TIx input to generate a filtered signal TIxF.
Then, an edge detector with polarity selection generates a signal (TIxFPx) which can be
used as trigger input by the slave mode controller or as the capture command. It is
prescaled before the capture register (ICxPS).

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Figure 178. Capture/compare channel (example: channel 1 input stage)

TI1F_ED
To the slave mode controller

TI1 TI1F_Rising
Filter TI1F Edge 0 TI1FP1
fDTS downcounter TI1F_Falling 01
detector 1
TI2FP1 IC1 Divider IC1PS
10
/1, /2, /4, /8
ICF[3:0] CC1P TRC
11
TIMx_CCMR1 TIMx_CCER (from slave mode
TI2F_Rising controller)
0
(from channel 2)
CC1S[1:0] ICPS[1:0] CC1E
TI2F_Falling
1
(from channel 2) TIMx_CCMR1 TIMx_CCER

MS31088V2

The output stage generates an intermediate waveform which is then used for reference:
OCxRef (active high). The polarity acts at the end of the chain.

Figure 179. Capture/compare channel 1 main circuit

APB Bus

MCU-peripheral interface

Input mode 16/32-bit Output mode

CC1S[1]
CC1S[0] Capture/compare preload register
CC1S[1]

IC1PS Capture Compare CC1S[0]

CC1E transfer
OC1PE
compare shadow register OC1PE
CC1G UEV
Comparator (from time TIMx_CCMR1
TIMx_EGR base unit)
CNT>CCR1
Counter CNT=CCR1

MSv63030V1

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Figure 180. Output stage of capture/compare channel (channel 1)

0 Output OC1
enable
‘0’ 1
x0 circuit
01
OC1_DT CC1P
CNT>CCR1 Output 11
OC1REF Dead-time TIM1_CCER
mode
CNT=CCR1 generator
controller OC1N_DT
11
10 0
Output OC1N
‘0’ 0x enable
1 circuit

CC1NE CC1E TIMx_CCER

OC1CE OC1M[3:0] DTG[7:0] CC1NE CC1E CC1NP MOE OSSI OSSR

TIMx_CCMR1 TIMx_BDTR TIMx_CCER TIMx_CCER TIMx_BDTR

MS33165V1

Figure 181. Output stage of capture/compare channel (channel 2 for TIM15)

To the master
mode controller

CNT > CCR2

Output 0 Output
OC2REF OC2
mode enable
CNT = CCR2
controller 1 circuit

CC2P

OC2M[2:0] TIM15_CCER CC2E TIM15_CCER

TIM15_CCMR2 MOE OSSI TIM15_BDTR

OIS2 TIM15_CR2

ai17334

The capture/compare block is made of one preload register and one shadow register. Write
and read always access the preload register.
In capture mode, captures are actually done in the shadow register, which is copied into the
preload register.
In compare mode, the content of the preload register is copied into the shadow register
which is compared to the counter.

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17.4.6 Input capture mode

In Input capture mode, the Capture/Compare Registers (TIMx_CCRx) are used to latch the
value of the counter after a transition detected by the corresponding ICx signal. When a
capture occurs, the corresponding CCXIF flag (TIMx_SR register) is set and an interrupt or
a DMA request can be sent if they are enabled. If a capture occurs while the CCxIF flag was
already high, then the over-capture flag CCxOF (TIMx_SR register) is set. CCxIF can be
cleared by software by writing it to ‘0’ or by reading the captured data stored in the
TIMx_CCRx register. CCxOF is cleared when it is written with 0.
The following example shows how to capture the counter value in TIMx_CCR1 when TI1
input rises. To do this, use the following procedure:
• Select the active input: TIMx_CCR1 must be linked to the TI1 input, so write the CC1S
bits to 01 in the TIMx_CCMR1 register. As soon as CC1S becomes different from 00,
the channel is configured in input and the TIMx_CCR1 register becomes read-only.
• Program the appropriate input filter duration in relation with the signal connected to the
timer (when the input is one of the TIx (ICxF bits in the TIMx_CCMRx register). Let’s
imagine that, when toggling, the input signal is not stable during at must 5 internal clock
cycles. We must program a filter duration longer than these 5 clock cycles. We can
validate a transition on TI1 when 8 consecutive samples with the new level have been
detected (sampled at fDTS frequency). Then write IC1F bits to 0011 in the
TIMx_CCMR1 register.
• Select the edge of the active transition on the TI1 channel by writing CC1P bit to 0 in
the TIMx_CCER register (rising edge in this case).
• Program the input prescaler. In our example, we wish the capture to be performed at
each valid transition, so the prescaler is disabled (write IC1PS bits to ‘00’ in the
TIMx_CCMR1 register).
• Enable capture from the counter into the capture register by setting the CC1E bit in the
TIMx_CCER register.
• If needed, enable the related interrupt request by setting the CC1IE bit in the
TIMx_DIER register, and/or the DMA request by setting the CC1DE bit in the
TIMx_DIER register.
For code example refer to the Appendix section A.8.3: Input capture configuration.
When an input capture occurs:
• The TIMx_CCR1 register gets the value of the counter on the active transition.
• CC1IF flag is set (interrupt flag). CC1OF is also set if at least two consecutive captures
occurred whereas the flag was not cleared.
• An interrupt is generated depending on the CC1IE bit.
• A DMA request is generated depending on the CC1DE bit.
For code example refer to the Appendix section A.8.4: Input capture data management.
In order to handle the overcapture, it is recommended to read the data before the
overcapture flag. This is to avoid missing an overcapture which could happen after reading
the flag and before reading the data.
Note: IC interrupt and/or DMA requests can be generated by software by setting the
corresponding CCxG bit in the TIMx_EGR register.

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17.4.7 PWM input mode (only for TIM15)

This mode is a particular case of input capture mode. The procedure is the same except:
• Two ICx signals are mapped on the same TIx input.
• These 2 ICx signals are active on edges with opposite polarity.
• One of the two TIxFP signals is selected as trigger input and the slave mode controller
is configured in reset mode.
For example, one can measure the period (in TIMx_CCR1 register) and the duty cycle (in
TIMx_CCR2 register) of the PWM applied on TI1 using the following procedure (depending
on CK_INT frequency and prescaler value):
• Select the active input for TIMx_CCR1: write the CC1S bits to 01 in the TIMx_CCMR1
register (TI1 selected).
• Select the active polarity for TI1FP1 (used both for capture in TIMx_CCR1 and counter
clear): write the CC1P bit to ‘0’ (active on rising edge).
• Select the active input for TIMx_CCR2: write the CC2S bits to 10 in the TIMx_CCMR1
register (TI1 selected).
• Select the active polarity for TI1FP2 (used for capture in TIMx_CCR2): write the CC2P
bit to '1' and the CC2NP bit to '0' (active on falling edge).
• Select the valid trigger input: write the TS bits to 101 in the TIMx_SMCR register
(TI1FP1 selected).
• Configure the slave mode controller in reset mode: write the SMS bits to 100 in the
TIMx_SMCR register.
• Enable the captures: write the CC1E and CC2E bits to ‘1’ in the TIMx_CCER register.
For code example refer to the Appendix section A.8.5: PWM input configuration.

Figure 182. PWM input mode timing

1. The PWM input mode can be used only with the TIMx_CH1/TIMx_CH2 signals due to the fact that only
TI1FP1 and TI2FP2 are connected to the slave mode controller.

17.4.8 Forced output mode

In output mode (CCxS bits = 00 in the TIMx_CCMRx register), each output compare signal
(OCxREF and then OCx/OCxN) can be forced to active or inactive level directly by software,
independently of any comparison between the output compare register and the counter.

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To force an output compare signal (OCXREF/OCx) to its active level, one just needs to write
101 in the OCxM bits in the corresponding TIMx_CCMRx register. Thus OCXREF is forced
high (OCxREF is always active high) and OCx get opposite value to CCxP polarity bit.
For example: CCxP=0 (OCx active high) => OCx is forced to high level.
The OCxREF signal can be forced low by writing the OCxM bits to 100 in the TIMx_CCMRx
register.
Anyway, the comparison between the TIMx_CCRx shadow register and the counter is still
performed and allows the flag to be set. Interrupt and DMA requests can be sent
accordingly. This is described in the output compare mode section below.

17.4.9 Output compare mode

This function is used to control an output waveform or indicating when a period of time has
elapsed.
When a match is found between the capture/compare register and the counter, the output
compare function:
• Assigns the corresponding output pin to a programmable value defined by the output
compare mode (OCxM bits in the TIMx_CCMRx register) and the output polarity (CCxP
bit in the TIMx_CCER register). The output pin can keep its level (OCXM=000), be set
active (OCxM=001), be set inactive (OCxM=010) or can toggle (OCxM=011) on match.
• Sets a flag in the interrupt status register (CCxIF bit in the TIMx_SR register).
• Generates an interrupt if the corresponding interrupt mask is set (CCXIE bit in the
TIMx_DIER register).
• Sends a DMA request if the corresponding enable bit is set (CCxDE bit in the
TIMx_DIER register, CCDS bit in the TIMx_CR2 register for the DMA request
selection).
The TIMx_CCRx registers can be programmed with or without preload registers using the
OCxPE bit in the TIMx_CCMRx register.
In output compare mode, the update event UEV has no effect on OCxREF and OCx output.
The timing resolution is one count of the counter. Output compare mode can also be used to
output a single pulse (in One-pulse mode).
Procedure:
1. Select the counter clock (internal, external, prescaler).
2. Write the desired data in the TIMx_ARR and TIMx_CCRx registers.
3. Set the CCxIE bit if an interrupt request is to be generated.
4. Select the output mode. For example:
– Write OCxM = 011 to toggle OCx output pin when CNT matches CCRx
– Write OCxPE = 0 to disable preload register
– Write CCxP = 0 to select active high polarity
– Write CCxE = 1 to enable the output
5. Enable the counter by setting the CEN bit in the TIMx_CR1 register.
For code example refer to the Appendix section A.8.2: Up counter on each 2 ETR rising
edges.
The TIMx_CCRx register can be updated at any time by software to control the output
waveform, provided that the preload register is not enabled (OCxPE=’0’, else TIMx_CCRx

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shadow register is updated only at the next update event UEV). An example is given in
Figure 162.

Figure 183. Output compare mode, toggle on OC1

Write 0xB201 in the CC1R register

TIMx_CNT 0039 003A 003B B200 B201

TIMx_CCR1 003A B201

OC1REF= OC1

Match detected on CCR1

Interrupt generated if enabled
MSv67583V1

17.4.10 PWM mode

Pulse Width Modulation mode allows to generate a signal with a frequency determined by
the value of the TIMx_ARR register and a duty cycle determined by the value of the
TIMx_CCRx register.
The PWM mode can be selected independently on each channel (one PWM per OCx
output) by writing ‘110’ (PWM mode 1) or ‘111’ (PWM mode 2) in the OCxM bits in the
TIMx_CCMRx register. The corresponding preload register must be enabled by setting the
OCxPE bit in the TIMx_CCMRx register, and eventually the auto-reload preload register by
setting the ARPE bit in the TIMx_CR1 register.
As the preload registers are transferred to the shadow registers only when an update event
occurs, before starting the counter, all registers must be initialized by setting the UG bit in
the TIMx_EGR register.
OCx polarity is software programmable using the CCxP bit in the TIMx_CCER register. It
can be programmed as active high or active low. OCx output is enabled by a combination of
the CCxE, CCxNE, MOE, OSSI and OSSR bits (TIMx_CCER and TIMx_BDTR registers).
Refer to the TIMx_CCER register description for more details.
In PWM mode (1 or 2), TIMx_CNT and TIMx_CCRx are always compared to determine
whether TIMx_CCRx ≤ TIMx_CNT.
In the following example, we consider PWM mode 1. The reference PWM signal OCxREF is
high as long as TIMx_CNT < TIMx_CCRx else it becomes low. If the compare value in
TIMx_CCRx is greater than the auto-reload value (in TIMx_ARR) then OCxREF is held at
‘1’. If the compare value is 0 then OCxRef is held at ‘0’. Figure 163 shows some edge-
aligned PWM waveforms in an example where TIMx_ARR=8.

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Figure 184. Edge-aligned PWM waveforms (ARR=8)

Counter register 0 1 2 3 4 5 6 7 8 0 1

OCXREF
CCRx=4
CCxIF

OCXREF
CCRx=8
CCxIF

OCXREF ‘1’
CCRx>8
CCxIF

OCXREF ‘0’
CCRx=0
CCxIF

MS31093V1

17.4.11 Complementary outputs and dead-time insertion

The TIM15/16/17 general-purpose timers can output one complementary signal and
manage the switching-off and switching-on of the outputs.
This time is generally known as dead-time and it has to be adjusted depending on the
devices that are connected to the outputs and their characteristics (intrinsic delays of level-
shifters, delays due to power switches...)
The polarity of the outputs (main output OCx or complementary OCxN) can be selected
independently for each output. This is done by writing to the CCxP and CCxNP bits in the
TIMx_CCER register.
The complementary signals OCx and OCxN are activated by a combination of several
control bits: the CCxE and CCxNE bits in the TIMx_CCER register and the MOE, OISx,
OISxN, OSSI and OSSR bits in the TIMx_BDTR and TIMx_CR2 registers. Refer to
Table 55: Output control bits for complementary OCx and OCxN channels with break feature
on page 443 for more details. In particular, the dead-time is activated when switching to the
IDLE state (MOE falling down to 0).
Dead-time insertion is enabled by setting both CCxE and CCxNE bits, and the MOE bit if the
break circuit is present. There is one 10-bit dead-time generator for each channel. From a
reference waveform OCxREF, it generates 2 outputs OCx and OCxN. If OCx and OCxN are
active high:
• The OCx output signal is the same as the reference signal except for the rising edge,
which is delayed relative to the reference rising edge.
• The OCxN output signal is the opposite of the reference signal except for the rising
edge, which is delayed relative to the reference falling edge.

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If the delay is greater than the width of the active output (OCx or OCxN) then the
corresponding pulse is not generated.
The following figures show the relationships between the output signals of the dead-time
generator and the reference signal OCxREF. (we suppose CCxP=0, CCxNP=0, MOE=1,
CCxE=1 and CCxNE=1 in these examples)

Figure 185. Complementary output with dead-time insertion

OCxREF

OCx
delay
OCxN
delay

MS31095V1

Figure 186. Dead-time waveforms with delay greater than the negative pulse

OCxREF

OCx

delay
OCxN

MS31096V1

Figure 187. Dead-time waveforms with delay greater than the positive pulse

OCxREF

OCx

OCxN

delay

MS31097V1

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The dead-time delay is the same for each of the channels and is programmable with the
DTG bits in the TIMx_BDTR register. Refer to Section 17.5.16: TIM15 break and dead-time
register (TIM15_BDTR) on page 446 for delay calculation.

Re-directing OCxREF to OCx or OCxN

In output mode (forced, output compare or PWM), OCxREF can be re-directed to the OCx
output or to OCxN output by configuring the CCxE and CCxNE bits in the TIMx_CCER
register.
This allows to send a specific waveform (such as PWM or static active level) on one output
while the complementary remains at its inactive level. Other alternative possibilities are to
have both outputs at inactive level or both outputs active and complementary with dead-
time.
Note: When only OCxN is enabled (CCxE=0, CCxNE=1), it is not complemented and becomes
active as soon as OCxREF is high. For example, if CCxNP=0 then OCxN=OCxRef. On the
other hand, when both OCx and OCxN are enabled (CCxE=CCxNE=1) OCx becomes
active when OCxREF is high whereas OCxN is complemented and becomes active when
OCxREF is low.

17.4.12 Using the break function

When using the break function, the output enable signals and inactive levels are modified
according to additional control bits (MOE, OSSI and OSSR bits in the TIMx_BDTR register,
OISx and OISxN bits in the TIMx_CR2 register). In any case, the OCx and OCxN outputs
cannot be set both to active level at a given time. Refer to Table 55: Output control bits for
complementary OCx and OCxN channels with break feature on page 443 for more details.
The source for break (BRK) channel can be an external source connected to the BKIN pin or
one of the following internal sources:
• the core LOCKUP output
• the PVD output
• the SRAM parity error signal
• a clock failure event generated by the CSS detector
When exiting from reset, the break circuit is disabled and the MOE bit is low. The break
function can be enabled by setting the BKE bit in the TIMx_BDTR register. The break input
polarity can be selected by configuring the BKP bit in the same register. BKE and BKP can
be modified at the same time. When the BKE and BKP bits are written, a delay of 1 APB
clock cycle is applied before the writing is effective. Consequently, it is necessary to wait 1
APB clock period to correctly read back the bit after the write operation.
Because MOE falling edge can be asynchronous, a resynchronization circuit has been
inserted between the actual signal (acting on the outputs) and the synchronous control bit
(accessed in the TIMx_BDTR register). It results in some delays between the asynchronous
and the synchronous signals. In particular, if MOE is set to 1 whereas it was low, a delay
must be inserted (dummy instruction) before reading it correctly. This is because the write
acts on the asynchronous signal whereas the read reflects the synchronous signal.

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When a break occurs (selected level on the break input):

• The MOE bit is cleared asynchronously, putting the outputs in inactive state, idle state
or in reset state (selected by the OSSI bit). This feature functions even if the MCU
oscillator is off.
• Each output channel is driven with the level programmed in the OISx bit in the
TIMx_CR2 register as soon as MOE=0. If OSSI=0 then the timer releases the enable
output else the enable output remains high.
• When complementary outputs are used:
– The outputs are first put in reset state inactive state (depending on the polarity).
This is done asynchronously so that it works even if no clock is provided to the
timer.
– If the timer clock is still present, then the dead-time generator is reactivated in
order to drive the outputs with the level programmed in the OISx and OISxN bits
after a dead-time. Even in this case, OCx and OCxN cannot be driven to their
active level together. Note that because of the resynchronization on MOE, the
dead-time duration is a bit longer than usual (around 2 ck_tim clock cycles).
– If OSSI=0 then the timer releases the enable outputs else the enable outputs
remain or become high as soon as one of the CCxE or CCxNE bits is high.
• The break status flag (BIF bit in the TIMx_SR register) is set. An interrupt can be
generated if the BIE bit in the TIMx_DIER register is set.
• If the AOE bit in the TIMx_BDTR register is set, the MOE bit is automatically set again
at the next update event UEV. This can be used to perform a regulation, for instance.
Else, MOE remains low until it is written with 1 again. In this case, it can be used for
security and the break input can be connected to an alarm from power drivers, thermal
sensors or any security components.
Note: The break inputs is acting on level. Thus, the MOE cannot be set while the break input is
active (neither automatically nor by software). In the meantime, the status flag BIF cannot
be cleared.
The break can be generated by the BRK input which has a programmable polarity and an
enable bit BKE in the TIMx_BDTR Register.
In addition to the break input and the output management, a write protection has been
implemented inside the break circuit to safeguard the application. It allows to freeze the
configuration of several parameters (dead-time duration, OCx/OCxN polarities and state
when disabled, OCxM configurations, break enable and polarity). The protection can be
selected among 3 levels with the LOCK bits in the TIMx_BDTR register. Refer to
Section 17.5.16: TIM15 break and dead-time register (TIM15_BDTR) on page 446. The
LOCK bits can be written only once after an MCU reset.
The Figure 188 shows an example of behavior of the outputs in response to a break.

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Figure 188. Output behavior in response to a break

BREAK (MOE )

OCxREF

OCx
(OCxN not implemented, CCxP=0, OISx=1)

OCx
(OCxN not implemented, CCxP=0, OISx=0)

OCx
(OCxN not implemented, CCxP=1, OISx=1)

OCx
(OCxN not implemented, CCxP=1, OISx=0)

OCx

OCxN delay delay delay

(CCxE=1, CCxP=0, OISx=0, CCxNE=1, CCxNP=0, OISxN=1)

OCx

OCxN delay delay delay

(CCxE=1, CCxP=0, OISx=1, CCxNE=1, CCxNP=1, OISxN=1)

OCx

OCxN delay
(CCxE=1, CCxP=0, OISx=0, CCxNE=0, CCxNP=0, OISxN=1)

OCx

OCxN delay
(CCxE=1, CCxP=0, OISx=1, CCxNE=0, CCxNP=0, OISxN=0)

OCx

OCxN
(CCxE=1, CCxP=0, CCxNE=0, CCxNP=0, OISx=OISxN=0 or OISx=OISxN=1)

MS31098V1

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17.4.13 One-pulse mode

One-pulse mode (OPM) is a particular case of the previous modes. It allows the counter to
be started in response to a stimulus and to generate a pulse with a programmable length
after a programmable delay.
Starting the counter can be controlled through the slave mode controller. Generating the
waveform can be done in output compare mode or PWM mode. One-pulse mode is selected
by setting the OPM bit in the TIMx_CR1 register. This makes the counter stop automatically
at the next update event UEV.
A pulse can be correctly generated only if the compare value is different from the counter
initial value. Before starting (when the timer is waiting for the trigger), the configuration must
be:
• In upcounting: CNT < CCRx ≤ ARR (in particular, 0 < CCRx)
• In downcounting: CNT > CCRx

Figure 189. Example of One-pulse mode

TI2

OC1REF
OC1

TIMx_ARR
Counter

TIMx_CCR1

0
t
tDELAY tPULSE
MSv67584V1

For example one may want to generate a positive pulse on OC1 with a length of tPULSE and
after a delay of tDELAY as soon as a positive edge is detected on the TI2 input pin.
Let’s use TI2FP2 as trigger 1:
• Map TI2FP2 to TI2 by writing CC2S=’01’ in the TIMx_CCMR1 register.
• TI2FP2 must detect a rising edge, write CC2P=’0’ in the TIMx_CCER register.
• Configure TI2FP2 as trigger for the slave mode controller (TRGI) by writing TS=’110’ in
the TIMx_SMCR register.
• TI2FP2 is used to start the counter by writing SMS to ‘110’ in the TIMx_SMCR register
(trigger mode).
For code example refer to the Appendix section A.8.16: One-Pulse mode.

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The OPM waveform is defined by writing the compare registers (taking into account the
clock frequency and the counter prescaler).
• The tDELAY is defined by the value written in the TIMx_CCR1 register.
• The tPULSE is defined by the difference between the auto-reload value and the compare
value (TIMx_ARR - TIMx_CCR1).
• Let’s say one want to build a waveform with a transition from ‘0’ to ‘1’ when a compare
match occurs and a transition from ‘1’ to ‘0’ when the counter reaches the auto-reload
value. To do this PWM mode 2 must be enabled by writing OC1M=111 in the
TIMx_CCMR1 register. Optionally the preload registers can be enabled by writing
OC1PE=’1’ in the TIMx_CCMR1 register and ARPE in the TIMx_CR1 register. In this
case one has to write the compare value in the TIMx_CCR1 register, the auto-reload
value in the TIMx_ARR register, generate an update by setting the UG bit and wait for
external trigger event on TI2. CC1P is written to ‘0’ in this example.
Since only 1 pulse is needed, a 1 must be written in the OPM bit in the TIMx_CR1 register to
stop the counter at the next update event (when the counter rolls over from the auto-reload
value back to 0).

Particular case: OCx fast enable

In One-pulse mode, the edge detection on TIx input set the CEN bit which enables the
counter. Then the comparison between the counter and the compare value makes the
output toggle. But several clock cycles are needed for these operations and it limits the
minimum delay tDELAY min we can get.
If one wants to output a waveform with the minimum delay, the OCxFE bit can be set in the
TIMx_CCMRx register. Then OCxRef (and OCx) are forced in response to the stimulus,
without taking in account the comparison. Its new level is the same as if a compare match
had occurred. OCxFE acts only if the channel is configured in PWM1 or PWM2 mode.
For code example refer to the part of code conditioned by PULSE_WITHOUT_DELAY > 0 in
the Appendix section A.8.16: One-Pulse mode.

17.4.14 TIM15 external trigger synchronization

This section applies to STM32F030x8, STM32F070xB and STM32F030xC devices only.
The TIM15 timer can be synchronized with an external trigger in several modes: Reset
mode, Gated mode and Trigger mode.

Slave mode: Reset mode

The counter and its prescaler can be reinitialized in response to an event on a trigger input.
Moreover, if the URS bit from the TIMx_CR1 register is low, an update event UEV is
generated. Then all the preloaded registers (TIMx_ARR, TIMx_CCRx) are updated.
In the following example, the upcounter is cleared in response to a rising edge on TI1 input:
• Configure the channel 1 to detect rising edges on TI1. Configure the input filter duration
(in this example, we do not need any filter, so we keep IC1F=0000). The capture
prescaler is not used for triggering, so it does not need to be configured. The CC1S bits

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select the input capture source only, CC1S = 01 in the TIMx_CCMR1 register. Write
CC1P=0 in TIMx_CCER register to validate the polarity (and detect rising edges only).
• Configure the timer in reset mode by writing SMS=100 in TIMx_SMCR register. Select
TI1 as the input source by writing TS=101 in TIMx_SMCR register.
• Start the counter by writing CEN=1 in the TIMx_CR1 register.
For code example refer to the Appendix section A.8.12: Reset mode.
The counter starts counting on the internal clock, then behaves normally until TI1 rising
edge. When TI1 rises, the counter is cleared and restarts from 0. In the meantime, the
trigger flag is set (TIF bit in the TIMx_SR register) and an interrupt request, or a DMA
request can be sent if enabled (depending on the TIE and TDE bits in TIMx_DIER register).
The following figure shows this behavior when the auto-reload register TIMx_ARR=0x36.
The delay between the rising edge on TI1 and the actual reset of the counter is due to the
resynchronization circuit on TI1 input.

Figure 190. Control circuit in reset mode

TI1

UG

Counter clock = ck_cnt = ck_psc

Counter register 30 31 32 33 34 35 36 00 01 02 03 00 01 02 03

TIF

MS31401V1

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Slave mode: Gated mode

The counter can be enabled depending on the level of a selected input.
In the following example, the upcounter counts only when TI1 input is low:
• Configure the channel 1 to detect low levels on TI1. Configure the input filter duration
(in this example, we do not need any filter, so we keep IC1F=0000). The capture
prescaler is not used for triggering, so it does not need to be configured. The CC1S bits
select the input capture source only, CC1S=01 in TIMx_CCMR1 register. Write
CC1P=1 in TIMx_CCER register to validate the polarity (and detect low level only).
• Configure the timer in gated mode by writing SMS=101 in TIMx_SMCR register. Select
TI1 as the input source by writing TS=101 in TIMx_SMCR register.
• Enable the counter by writing CEN=1 in the TIMx_CR1 register (in gated mode, the
counter doesn’t start if CEN=0, whatever is the trigger input level).
For code example refer to the Appendix section A.8.13: Gated mode.
The counter starts counting on the internal clock as long as TI1 is low and stops as soon as
TI1 becomes high. The TIF flag in the TIMx_SR register is set both when the counter starts
or stops.
The delay between the rising edge on TI1 and the actual stop of the counter is due to the
resynchronization circuit on TI1 input.

Figure 191. Control circuit in gated mode

TI1

cnt_en

Counter clock = ck_cnt = ck_psc

Counter register 30 31 32 33 34 35 36 37 38

TIF

Write TIF=0

MS31402V1

Slave mode: Trigger mode

The counter can start in response to an event on a selected input.
In the following example, the upcounter starts in response to a rising edge on TI2 input:
• Configure the channel 2 to detect rising edges on TI2. Configure the input filter duration
(in this example, we do not need any filter, so we keep IC2F=0000). The capture
prescaler is not used for triggering, so it does not need to be configured. The CC2S bits
are configured to select the input capture source only, CC2S=01 in TIMx_CCMR1

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register. Write CC2P=1 in TIMx_CCER register to validate the polarity (and detect low
level only).
• Configure the timer in trigger mode by writing SMS=110 in TIMx_SMCR register. Select
TI2 as the input source by writing TS=110 in TIMx_SMCR register.
For code example refer to the Appendix section A.8.14: Trigger mode.
When a rising edge occurs on TI2, the counter starts counting on the internal clock and the
TIF flag is set.
The delay between the rising edge on TI2 and the actual start of the counter is due to the
resynchronization circuit on TI2 input.

Figure 192. Control circuit in trigger mode

TI2

cnt_en

Counter clock = ck_cnt = ck_psc

Counter register 34 35 36 37 38

TIF

MS31403V1

The TIM timers are linked together internally for timer synchronization or chaining. Refer to
Section 14.3.15: Timer synchronization on page 336 for details.

17.4.15 Timer synchronization (TIM15)

This section applies to STM32F030x8 STM32F070xB and STM32F030xC devices only.
The TIM timers are linked together internally for timer synchronization or chaining. Refer to
Section 14.3.15: Timer synchronization on page 336 for details.

17.4.16 Debug mode

When the microcontroller enters debug mode (Cortex™-M0 core halted), the TIMx counter
either continues to work normally or stops, depending on DBG_TIMx_STOP configuration
bit in DBG module.

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17.5 TIM15 registers

Refer to Section 1.2 on page 33 for a list of abbreviations used in register descriptions.

17.5.1 TIM15 control register 1 (TIM15_CR1)

Address offset: 0x00
Reset value: 0x0000

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. CKD[1:0] ARPE Res. Res. Res. OPM URS UDIS CEN
rw rw rw rw rw rw rw

Bits 15:10 Reserved, must be kept at reset value.

Bits 9:8 CKD[1:0]: Clock division
This bit field indicates the division ratio between the timer clock (CK_INT) frequency and the
dead-time and sampling clock (tDTS) used by the dead-time generators and the digital filters
(TIx)
00: tDTS = tCK_INT
01: tDTS = 2*tCK_INT
10: tDTS = 4*tCK_INT
11: Reserved, do not program this value
Bit 7 ARPE: Auto-reload preload enable
0: TIMx_ARR register is not buffered
1: TIMx_ARR register is buffered
Bits 6:4 Reserved, must be kept at reset value.
Bit 3 OPM: One-pulse mode
0: Counter is not stopped at update event
1: Counter stops counting at the next update event (clearing the bit CEN)
Bit 2 URS: Update request source
This bit is set and cleared by software to select the UEV event sources.
0: Any of the following events generate an update interrupt if enabled. These events can be:
– Counter overflow/underflow
– Setting the UG bit
– Update generation through the slave mode controller
1: Only counter overflow/underflow generates an update interrupt if enabled

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Bit 1 UDIS: Update disable

This bit is set and cleared by software to enable/disable UEV event generation.
0: UEV enabled. The Update (UEV) event is generated by one of the following events:
– Counter overflow/underflow
– Setting the UG bit
– Update generation through the slave mode controller
Buffered registers are then loaded with their preload values.
1: UEV disabled. The Update event is not generated, shadow registers keep their value
(ARR, PSC, CCRx). However the counter and the prescaler are reinitialized if the UG bit
is set or if a hardware reset is received from the slave mode controller.
Bit 0 CEN: Counter enable
0: Counter disabled
1: Counter enabled
Note: External clock and gated mode can work only if the CEN bit has been previously set by
software. However trigger mode can set the CEN bit automatically by hardware.

17.5.2 TIM15 control register 2 (TIM15_CR2)

Address offset: 0x04
Reset value: 0x0000

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. OIS2 OIS1N OIS1 Res. MMS[2:0] CCDS CCUS Res. CCPC
rw rw rw rw rw rw rw rw rw

Bits 15:11 Reserved, must be kept at reset value.

Bit 10 OIS2: Output idle state 2 (OC2 output)
0: OC2=0 when MOE=0
1: OC2=1 when MOE=0
Note: This bit cannot be modified as long as LOCK level 1, 2 or 3 has been programmed
(LOCK bits in the TIMx_BKR register).
Bit 9 OIS1N: Output Idle state 1 (OC1N output)
0: OC1N=0 after a dead-time when MOE=0
1: OC1N=1 after a dead-time when MOE=0
Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed
(LOCK bits in TIMx_BKR register).
Bit 8 OIS1: Output Idle state 1 (OC1 output)
0: OC1=0 (after a dead-time if OC1N is implemented) when MOE=0
1: OC1=1 (after a dead-time if OC1N is implemented) when MOE=0
Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed
(LOCK bits in TIMx_BKR register).
Bit 7 Reserved, must be kept at reset value.

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Bits 6:4 MMS[2:0]: Master mode selection

These bits allow to select the information to be sent in master mode to slave timers for
synchronization (TRGO). The combination is as follows:
000: Reset - the UG bit from the TIMx_EGR register is used as trigger output (TRGO). If the
reset is generated by the trigger input (slave mode controller configured in reset mode)
then the signal on TRGO is delayed compared to the actual reset.
001: Enable - the Counter Enable signal CNT_EN is used as trigger output (TRGO). It is
useful to start several timers at the same time or to control a window in which a slave
timer is enable. The Counter Enable signal is generated by a logic OR between CEN
control bit and the trigger input when configured in gated mode. When the Counter
Enable signal is controlled by the trigger input, there is a delay on TRGO, except if the
master/slave mode is selected (see the MSM bit description in TIMx_SMCR register).
010: Update - The update event is selected as trigger output (TRGO). For instance a master
timer can then be used as a prescaler for a slave timer.
011: Compare Pulse - The trigger output send a positive pulse when the CC1IF flag is to be
set (even if it was already high), as soon as a capture or a compare match occurred.
(TRGO).
100: Compare - OC1REF signal is used as trigger output (TRGO).
101: Compare - OC2REF signal is used as trigger output (TRGO).
Bit 3 CCDS: Capture/compare DMA selection
0: CCx DMA request sent when CCx event occurs
1: CCx DMA requests sent when update event occurs
Bit 2 CCUS: Capture/compare control update selection
0: When capture/compare control bits are preloaded (CCPC=1), they are updated by setting
the COMG bit only.
1: When capture/compare control bits are preloaded (CCPC=1), they are updated by setting
the COMG bit or when an rising edge occurs on TRGI.
Note: This bit acts only on channels that have a complementary output.
Bit 1 Reserved, must be kept at reset value.
Bit 0 CCPC: Capture/compare preloaded control
0: CCxE, CCxNE and OCxM bits are not preloaded
1: CCxE, CCxNE and OCxM bits are preloaded, after having been written, they are updated
only when COM bit is set.
Note: This bit acts only on channels that have a complementary output.

17.5.3 TIM15 slave mode control register (TIM15_SMCR)

Address offset: 0x08
Reset value: 0x0000

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. MSM TS[2:0] Res. SMS[2:0]
rw rw rw rw rw rw rw

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Bits 15:8 Reserved, must be kept at reset value.

Bit 7 MSM: Master/slave mode
0: No action
1: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect
synchronization between the current timer and its slaves (through TRGO). It is useful if
we want to synchronize several timers on a single external event.
Bits 6:4 TS[2:0]: Trigger selection
This bit field selects the trigger input to be used to synchronize the counter.
000: Reserved
001: Internal Trigger 1 (ITR1)
010: Internal Trigger 2 (ITR2)
011: Internal Trigger 3 (ITR3)
100: TI1 Edge Detector (TI1F_ED)
101: Filtered Timer Input 1 (TI1FP1)
110: Filtered Timer Input 2 (TI2FP2)
See Table 54: TIMx Internal trigger connection for more details on ITRx meaning for each
Timer.
Note: These bits must be changed only when they are not used (e.g. when SMS=000) to
avoid wrong edge detections at the transition.
Bit 3 Reserved, must be kept at reset value.
Bits 2:0 SMS[2:0]: Slave mode selection
When external signals are selected the active edge of the trigger signal (TRGI) is linked to
the polarity selected on the external input (see Input Control register and Control Register
description.
000: Slave mode disabled - if CEN = ‘1’ then the prescaler is clocked directly by the internal
clock.
100: Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter
and generates an update of the registers.
101: Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The
counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop
of the counter are controlled.
110: Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not
reset). Only the start of the counter is controlled.
111: External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter.
Note: The gated mode must not be used if TI1F_ED is selected as the trigger input
(TS=’100’). Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the
gated mode checks the level of the trigger signal.

Table 54. TIMx Internal trigger connection

Slave TIM ITR1 (TS = 001) ITR2 (TS = 010) ITR3 (TS = 011)

TIM15 TIM3 TIM16_OC TIM17_OC

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17.5.4 TIM15 DMA/interrupt enable register (TIM15_DIER)

Address offset: 0x0C
Reset value: 0x0000

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. TDE Res. Res. Res. CC2DE CC1DE UDE BIE TIE COMIE Res. Res. CC2IE CC1IE UIE
rw rw rw rw rw rw rw rw rw rw

Bit 15 Reserved, must be kept at reset value.

Bit 14 TDE: Trigger DMA request enable
0: Trigger DMA request disabled
1: Trigger DMA request enabled
Bits 13:11 Reserved, must be kept at reset value.
Bit 10 CC2DE: Capture/Compare 2 DMA request enable
0: CC2 DMA request disabled
1: CC2 DMA request enabled
Bit 9 CC1DE: Capture/Compare 1 DMA request enable
0: CC1 DMA request disabled
1: CC1 DMA request enabled
Bit 8 UDE: Update DMA request enable
0: Update DMA request disabled
1: Update DMA request enabled
Bit 7 BIE: Break interrupt enable
0: Break interrupt disabled
1: Break interrupt enabled
Bit 6 TIE: Trigger interrupt enable
0: Trigger interrupt disabled
1: Trigger interrupt enabled
Bit 5 COMIE: COM interrupt enable
0: COM interrupt disabled
1: COM interrupt enabled
Bits 4:3 Reserved, must be kept at reset value.
Bit 2 CC2IE: Capture/Compare 2 interrupt enable
0: CC2 interrupt disabled
1: CC2 interrupt enabled
Bit 1 CC1IE: Capture/Compare 1 interrupt enable
0: CC1 interrupt disabled
1: CC1 interrupt enabled
Bit 0 UIE: Update interrupt enable
0: Update interrupt disabled
1: Update interrupt enabled

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17.5.5 TIM15 status register (TIM15_SR)

Address offset: 0x10
Reset value: 0x0000

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. CC2OF CC1OF Res. BIF TIF COMIF Res. Res. CC2IF CC1IF UIF
rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0

Bits 15:11 Reserved, must be kept at reset value.

Bit 10 CC2OF: Capture/Compare 2 overcapture flag
Refer to CC1OF description.
Bit 9 CC1OF: Capture/Compare 1 overcapture flag
This flag is set by hardware only when the corresponding channel is configured in input
capture mode. It is cleared by software by writing it to ‘0’.
0: No overcapture has been detected
1: The counter value has been captured in TIMx_CCR1 register while CC1IF flag was
already set
Bit 8 Reserved, must be kept at reset value.
Bit 7 BIF: Break interrupt flag
This flag is set by hardware as soon as the break input goes active. It can be cleared by
software if the break input is not active.
0: No break event occurred
1: An active level has been detected on the break input
Bit 6 TIF: Trigger interrupt flag
This flag is set by hardware on trigger event (active edge detected on TRGI input when the
slave mode controller is enabled in all modes but gated mode, both edges in case gated
mode is selected). It is cleared by software.
0: No trigger event occurred
1: Trigger interrupt pending
Bit 5 COMIF: COM interrupt flag
This flag is set by hardware on a COM event (once the capture/compare control bits –CCxE,
CCxNE, OCxM– have been updated). It is cleared by software by writing it to ‘0’.
0: No COM event occurred
1: COM interrupt pending
Bits 4:3 Reserved, must be kept at reset value.

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Bit 2 CC2IF: Capture/Compare 2 interrupt flag

refer to CC1IF description
Bit 1 CC1IF: Capture/Compare 1 interrupt flag
Condition: channel CC1 is configured as output
This flag is set by hardware when the counter matches the compare value, it is cleared by
software.
0: No match.
1: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register.
When the contents of TIMx_CCR1 are greater than the contents of TIMx_ARR, the
CC1IF bit goes high on the counter overflow (in upcounting and up/down-counting
modes) or underflow (in downcounting mode)
Condition: If channel CC1 is configured as input
This bit is set by hardware on a capture. It is cleared by software or by reading the
TIMx_CCR1 register.
0: No input capture occurred
1: The counter value has been captured in TIMx_CCR1 register (An edge has been
detected on IC1 which matches the selected polarity)
Bit 0 UIF: Update interrupt flag
This bit is set by hardware on an update event. It is cleared by software.
0: No update occurred.
1: Update interrupt pending. This bit is set by hardware when the registers are updated:
–At overflow regarding the repetition counter value (update if repetition counter = 0) and if
the UDIS=0 in the TIMx_CR1 register.
–When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=0
and UDIS=0 in the TIMx_CR1 register.
–When CNT is reinitialized by a trigger event (refer to Section 17.5.3: TIM15 slave mode
control register (TIM15_SMCR)), if URS=0 and UDIS=0 in the TIMx_CR1 register.

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17.5.6 TIM15 event generation register (TIM15_EGR)

Address offset: 0x14
Reset value: 0x0000

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. BG TG COMG Res. Res. CC2G CC1G UG
w w rw w w w

Bits 15:8 Reserved, must be kept at reset value.

Bit 7 BG: Break generation
This bit is set by software in order to generate an event, it is automatically cleared by
hardware.
0: No action
1: A break event is generated. MOE bit is cleared and BIF flag is set. Related interrupt or
DMA transfer can occur if enabled.
Bit 6 TG: Trigger generation
This bit is set by software in order to generate an event, it is automatically cleared by
hardware.
0: No action
1: The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if
enabled
Bit 5 COMG: Capture/Compare control update generation
This bit can be set by software, it is automatically cleared by hardware.
0: No action
1: When the CCPC bit is set, it is possible to update the CCxE, CCxNE and OCxM bits
Note: This bit acts only on channels that have a complementary output.
Bits 4:3 Reserved, must be kept at reset value.
Bit 2 CC2G: Capture/Compare 2 generation
Refer to CC1G description
Bit 1 CC1G: Capture/Compare 1 generation
This bit is set by software in order to generate an event, it is automatically cleared by
hardware.
0: No action
1: A capture/compare event is generated on channel 1:
Condition: channel CC1 is configured as output
CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled.
Condition: channel CC1 is configured as input
The current value of the counter is captured in TIMx_CCR1 register. The CC1IF flag is set,
the corresponding interrupt or DMA request is sent if enabled. The CC1OF flag is set if the
CC1IF flag was already high.
Bit 0 UG: Update generation
This bit can be set by software, it is automatically cleared by hardware.
0: No action.
1: Reinitialize the counter and generates an update of the registers. Note that the prescaler
counter is cleared too (anyway the prescaler ratio is not affected).

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17.5.7 TIM15 capture/compare mode register 1 [alternate] (TIM15_CCMR1)

Address offset: 0x18
Reset value: 0x0000
The same register can be used for input capture mode (this section) or for output compare
mode (next section). The direction of a channel is defined by configuring the corresponding
CCxS bits. All the other bits of this register have a different function in input and in output
mode. For a given bit, OCxx describes its function when the channel is configured in output,
ICxx describes its function when the channel is configured in input. So one must take care
that the same bit can have a different meaning for the input stage and for the output stage.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC2F[3:0] IC2PSC[1:0] CC2S[1:0] IC1F[3:0] IC1PSC[1:0] CC1S[1:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 15:12 IC2F[3:0]: Input capture 2 filter

Bits 11:10 IC2PSC[1:0]: Input capture 2 prescaler
Bits 9:8 CC2S[1:0]: Capture/Compare 2 selection
This bit-field defines the direction of the channel (input/output) as well as the used input.
00: CC2 channel is configured as output
01: CC2 channel is configured as input, IC2 is mapped on TI2
10: CC2 channel is configured as input, IC2 is mapped on TI1
11: CC2 channel is configured as input, IC2 is mapped on TRC. This mode is working only if an
internal trigger input is selected through TS bit (TIMx_SMCR register)
Note: CC2S bits are writable only when the channel is OFF (CC2E = ‘0’ in TIMx_CCER).

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Bits 7:4 IC1F[3:0]: Input capture 1 filter

This bit-field defines the frequency used to sample TI1 input and the length of the digital filter applied
to TI1. The digital filter is made of an event counter in which N consecutive events are needed to
validate a transition on the output:
0000: No filter, sampling is done at fDTS
0001: fSAMPLING = fCK_INT, N = 2
0010: fSAMPLING = fCK_INT, N = 4
0011: fSAMPLING = fCK_INT, N = 8
0100: fSAMPLING = fDTS / 2, N = 6
0101: fSAMPLING = fDTS / 2, N = 8
0110: fSAMPLING = fDTS / 4, N = 6
0111: fSAMPLING = fDTS / 4, N = 8
1000: fSAMPLING = fDTS / 8, N = 6
1001: fSAMPLING = fDTS / 8, N = 8
1010: fSAMPLING = fDTS / 16, N = 5
1011: fSAMPLING = fDTS / 16, N = 6
1100: fSAMPLING = fDTS / 16, N = 8
1101: fSAMPLING = fDTS / 32, N = 5
1110: fSAMPLING = fDTS / 32, N = 6
1111: fSAMPLING = fDTS / 32, N = 8
Note: Care must be taken that fDTS is replaced in the formula by CK_INT when ICxF[3:0] = 1, 2 or 3.
Bits 3:2 IC1PSC[1:0]: Input capture 1 prescaler
This bit-field defines the ratio of the prescaler acting on CC1 input (IC1).
The prescaler is reset as soon as CC1E=’0’ (TIMx_CCER register).
00: no prescaler, capture is done each time an edge is detected on the capture input
01: capture is done once every 2 events
10: capture is done once every 4 events
11: capture is done once every 8 events
Bits 1:0 CC1S[1:0]: Capture/Compare 1 Selection
This bit-field defines the direction of the channel (input/output) as well as the used input.
00: CC1 channel is configured as output
01: CC1 channel is configured as input, IC1 is mapped on TI1
10: CC1 channel is configured as input, IC1 is mapped on TI2
11: CC1 channel is configured as input, IC1 is mapped on TRC. This mode is working only if an
internal trigger input is selected through TS bit (TIMx_SMCR register)
Note: CC1S bits are writable only when the channel is OFF (CC1E = ‘0’ in TIMx_CCER).

17.5.8 TIM15 capture/compare mode register 1 [alternate] (TIM15_CCMR1)

Address offset: 0x18
Reset value: 0x0000
The same register can be used for output compare mode (this section) or for input capture
mode (previous section). The direction of a channel is defined by configuring the
corresponding CCxS bits. All the other bits of this register have a different function in input
and in output mode. For a given bit, OCxx describes its function when the channel is
configured in output, ICxx describes its function when the channel is configured in input. So
one must take care that the same bit can have a different meaning for the input stage and
for the output stage.

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15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OC2 OC2 OC1 OC1
Res. OC2M[2:0] CC2S[1:0] Res. OC1M[2:0] CC1S[1:0]
PE FE PE FE
rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bit 15 Reserved, must be kept at reset value.

Bits 14:12 OC2M[2:0]: Output Compare 2 mode
Bit 11 OC2PE: Output Compare 2 preload enable
Bit 10 OC2FE: Output Compare 2 fast enable
Bits 9:8 CC2S[1:0]: Capture/Compare 2 selection
This bit-field defines the direction of the channel (input/output) as well as the used input.
00: CC2 channel is configured as output.
01: CC2 channel is configured as input, IC2 is mapped on TI2.
10: CC2 channel is configured as input, IC2 is mapped on TI1.
11: CC2 channel is configured as input, IC2 is mapped on TRC. This mode is working only
if an internal trigger input is selected through the TS bit (TIMx_SMCR register)
Note: CC2S bits are writable only when the channel is OFF (CC2E = ‘0’ in TIMx_CCER).
Bit 7 Reserved, must be kept at reset value.
Bits 6:4 OC1M[2:0]: Output Compare 1 mode
These bits define the behavior of the output reference signal OC1REF from which OC1 and
OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends
on CC1P and CC1NP bits.
000: Frozen - The comparison between the output compare register TIMx_CCR1 and the
counter TIMx_CNT has no effect on the outputs.
001: Set channel 1 to active level on match. OC1REF signal is forced high when the counter
TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1).
010: Set channel 1 to inactive level on match. OC1REF signal is forced low when the
counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1).
011: Toggle - OC1REF toggles when TIMx_CNT=TIMx_CCR1.
100: Force inactive level - OC1REF is forced low.
101: Force active level - OC1REF is forced high.
110: PWM mode 1 - In upcounting, channel 1 is active as long as TIMx_CNT<TIMx_CCR1
else inactive. In downcounting, channel 1 is inactive (OC1REF=‘0’) as long as
TIMx_CNT>TIMx_CCR1 else active (OC1REF=’1’).
111: PWM mode 2 - In upcounting, channel 1 is inactive as long as
TIMx_CNT<TIMx_CCR1 else active. In downcounting, channel 1 is active as long as
TIMx_CNT>TIMx_CCR1 else inactive.
Note: These bits can not be modified as long as LOCK level 3 has been programmed (LOCK
bits in TIMx_BDTR register) and CC1S=’00’ (the channel is configured in output).
Note: In PWM mode 1 or 2, the OCREF level changes only when the result of the
comparison changes or when the output compare mode switches from “frozen” mode
to “PWM” mode.

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Bit 3 OC1PE: Output Compare 1 preload enable

0: Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the
new value is taken in account immediately.
1: Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload
register. TIMx_CCR1 preload value is loaded in the active register at each update event.
Note: These bits can not be modified as long as LOCK level 3 has been programmed (LOCK
bits in TIMx_BDTR register) and CC1S=’00’ (the channel is configured in output).
Bit 2 OC1FE: Output Compare 1 fast enable
This bit is used to accelerate the effect of an event on the trigger in input on the CC output.
0: CC1 behaves normally depending on counter and CCR1 values even when the trigger is
ON. The minimum delay to activate CC1 output when an edge occurs on the trigger input
is 5 clock cycles.
1: An active edge on the trigger input acts like a compare match on CC1 output. Then, OC is
set to the compare level independently of the result of the comparison. Delay to sample
the trigger input and to activate CC1 output is reduced to 3 clock cycles. OCFE acts only
if the channel is configured in PWM1 or PWM2 mode.
Bits 1:0 CC1S[1:0]: Capture/Compare 1 selection
This bit-field defines the direction of the channel (input/output) as well as the used input.
00: CC1 channel is configured as output.
01: CC1 channel is configured as input, IC1 is mapped on TI1.
10: CC1 channel is configured as input, IC1 is mapped on TI2.
11: CC1 channel is configured as input, IC1 is mapped on TRC. This mode is working only
if an internal trigger input is selected through TS bit (TIMx_SMCR register)
Note: CC1S bits are writable only when the channel is OFF (CC1E = ‘0’ in TIMx_CCER).

17.5.9 TIM15 capture/compare enable register (TIM15_CCER)

Address offset: 0x20
Reset value: 0x0000

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. CC2NP Res. CC2P CC2E CC1NP CC1NE CC1P CC1E
rw rw rw rw rw rw rw

Bits 15:8 Reserved, must be kept at reset value.

Bit 7 CC2NP: Capture/Compare 2 complementary output polarity
Refer to CC1NP description.
Bit 6 Reserved, must be kept at reset value.
Bit 5 CC2P: Capture/Compare 2 output polarity
Refer to CC1P description.
Bit 4 CC2E: Capture/Compare 2 output enable
Refer to CC1E description.

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Bit 3 CC1NP: Capture/Compare 1 complementary output polarity

0: OC1N active high
1: OC1N active low
Note: This bit is not writable as soon as LOCK level 2 or 3 has been programmed (LOCK bits
in TIMx_BDTR register) and CC1S=”00” (the channel is configured in output).
Bit 2 CC1NE: Capture/Compare 1 complementary output enable
0: Off - OC1N is not active. OC1N level is then function of MOE, OSSI, OSSR, OIS1, OIS1N
and CC1E bits.
1: On - OC1N signal is output on the corresponding output pin depending on MOE, OSSI,
OSSR, OIS1, OIS1N and CC1E bits.
Bit 1 CC1P: Capture/Compare 1 output polarity
Condition: CC1 channel configured as output
0: OC1 active high
1: OC1 active low
Condition: CC1 channel configured as input
The CC1NP/CC1P bits select the polarity of TI1FP1 and TI2FP1 for trigger or capture
operations.
00: Noninverted/rising edge: circuit is sensitive to TIxFP1's rising edge (capture, trigger in
reset or trigger mode), TIxFP1 is not inverted (trigger in gated mode).
01: Inverted/falling edge: circuit is sensitive to TIxFP1's falling edge (capture, trigger in
reset, or trigger mode), TIxFP1 is inverted (trigger in gated mode).
10: Reserved, do not use this configuration.
11: Noninverted/both edges: circuit is sensitive to both the rising and falling edges of TIxFP1
(capture, trigger in reset or trigger mode), TIxFP1 is not inverted (trigger in gated mode).
Note: This bit is not writable as soon as LOCK level 2 or 3 has been programmed (LOCK bits
in TIMx_BDTR register).
Bit 0 CC1E: Capture/Compare 1 output enable
Condition: CC1 channel configured as output
0: Off - OC1 is not active. OC1 level is then function of MOE, OSSI, OSSR, OIS1, OIS1N
and CC1NE bits.
1: On - OC1 signal is output on the corresponding output pin depending on MOE, OSSI,
OSSR, OIS1, OIS1N and CC1NE bits.
Condition: CC1 channel configured as input
This bit determines if a capture of the counter value can actually be done into the input
capture/compare register 1 (TIMx_CCR1) or not.
0: Capture disabled
1: Capture enabled

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Table 55. Output control bits for complementary OCx and OCxN channels with break feature
Control bits Output states(1)
MOE bit OSSI bit OSSR bit CCxE bit CCxNE bit OCx output state OCxN output state
Output Disabled (not driven Output Disabled (not driven by
0 0 0 by the timer) the timer)
OCx=0, OCx_EN=0 OCxN=0, OCxN_EN=0
Output Disabled (not driven OCxREF + Polarity
0 0 1 by the timer) OCxN=OCxREF xor CCxNP,
OCx=0, OCx_EN=0 OCxN_EN=1

OCxREF + Polarity Output Disabled (not driven by

0 1 0 OCx=OCxREF xor CCxP, the timer)
OCx_EN=1 OCxN=0, OCxN_EN=0

OCREF + Polarity + dead- Complementary to OCREF (not

0 1 1 time OCREF) + Polarity + dead-time
OCx_EN=1 OCxN_EN=1
1 X
Output Disabled (not driven Output Disabled (not driven by
1 0 0 by the timer) the timer)
OCx=CCxP, OCx_EN=0 OCxN=CCxNP, OCxN_EN=0
Off-State (output enabled OCxREF + Polarity
1 0 1 with inactive state) OCxN=OCxREF xor CCxNP,
OCx=CCxP, OCx_EN=1 OCxN_EN=1
OCxREF + Polarity Off-State (output enabled with
1 1 0 OCx=OCxREF xor CCxP, inactive state)
OCx_EN=1 OCxN=CCxNP, OCxN_EN=1

OCREF + Polarity + dead- Complementary to OCREF (not

1 1 1 time OCREF) + Polarity + dead-time
OCx_EN=1 OCxN_EN=1
0 0 0 Output Disabled (not driven by the timer)
0 0 1 Asynchronously: OCx=CCxP, OCx_EN=0, OCxN=CCxNP,
OCxN_EN=0
0 1 0
Then if the clock is present: OCx=OISx and OCxN=OISxN
0 1 1 after a dead-time, assuming that OISx and OISxN do not
correspond to OCX and OCxN both in active state.
0 1 X 0 0
1 0 1 Off-State (output enabled with inactive state)
1 1 0 Asynchronously: OCx=CCxP, OCx_EN=1, OCxN=CCxNP,
OCxN_EN=1
Then if the clock is present: OCx=OISx and OCxN=OISxN
1 1 1 after a dead-time, assuming that OISx and OISxN do not
correspond to OCX and OCxN both in active state
1. When both outputs of a channel are not used (CCxE = CCxNE = 0), the OISx, OISxN, CCxP and CCxNP bits must be kept
cleared.

Note: The state of the external I/O pins connected to the complementary OCx and OCxN channels
depends on the OCx and OCxN channel state and the GPIO and AFIO registers.

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17.5.10 TIM15 counter (TIM15_CNT)

Address offset: 0x24
Reset value: 0x0000

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 15:0 CNT[15:0]: Counter value

17.5.11 TIM15 prescaler (TIM15_PSC)

Address offset: 0x28
Reset value: 0x0000

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 15:0 PSC[15:0]: Prescaler value

The counter clock frequency (CK_CNT) is equal to fCK_PSC / (PSC[15:0] + 1).
PSC contains the value to be loaded in the active prescaler register at each update event
(including when the counter is cleared through UG bit of TIMx_EGR register or through trigger
controller when configured in “reset mode”).

17.5.12 TIM15 auto-reload register (TIM15_ARR)

Address offset: 0x2C
Reset value: 0xFFFF

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 15:0 ARR[15:0]: Auto-reload value

ARR is the value to be loaded in the actual auto-reload register.
Refer to the Section 16.3.1: Time-base unit on page 381 for more details about ARR update
and behavior.
The counter is blocked while the auto-reload value is null.

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17.5.13 TIM15 repetition counter register (TIM15_RCR)

Address offset: 0x30
Reset value: 0x0000

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. REP[7:0]
rw rw rw rw rw rw rw rw

Bits 15:8 Reserved, must be kept at reset value.

Bits 7:0 REP[7:0]: Repetition counter value
These bits allow the user to set-up the update rate of the compare registers (i.e. periodic
transfers from preload to active registers) when preload registers are enable, as well as the
update interrupt generation rate, if this interrupt is enable.
Each time the REP_CNT related downcounter reaches zero, an update event is generated
and it restarts counting from REP value. As REP_CNT is reloaded with REP value only at
the repetition update event U_RC, any write to the TIMx_RCR register is not taken in
account until the next repetition update event.
It means in PWM mode (REP+1) corresponds to the number of PWM periods in edge-
aligned mode.

17.5.14 TIM15 capture/compare register 1 (TIM15_CCR1)

Address offset: 0x34
Reset value: 0x0000

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR1[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 15:0 CCR1[15:0]: Capture/Compare 1 value

Condition: if channel CC1 is configured as output
CCR1 is the value to be loaded in the actual capture/compare 1 register (preload value).
It is loaded permanently if the preload feature is not selected in the TIMx_CCMR1 register
(bit OC1PE). Else the preload value is copied in the active capture/compare 1 register when
an update event occurs.
The active capture/compare register contains the value to be compared to the counter
TIMx_CNT and signaled on OC1 output.
Condition: if channel CC1 is configured as input
CCR1 is the counter value transferred by the last input capture 1 event (IC1).

17.5.15 TIM15 capture/compare register 2 (TIM15_CCR2)

Address offset: 0x38
Reset value: 0x0000

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR2[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

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Bits 15:0 CCR2[15:0]: Capture/Compare 2 value

Condition: channel CC2 is configured as output:
CCR2 is the value to be loaded in the actual capture/compare 2 register (preload value).
It is loaded permanently if the preload feature is not selected in the TIMx_CCMR2 register
(bit OC2PE). Else the preload value is copied in the active capture/compare 2 register when
an update event occurs.
The active capture/compare register contains the value to be compared to the counter
TIMx_CNT and signalled on OC2 output.
Condition: channel CC2 is configured as input:
CCR2 is the counter value transferred by the last input capture 2 event (IC2).

17.5.16 TIM15 break and dead-time register (TIM15_BDTR)

Address offset: 0x44
Reset value: 0x0000

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MOE AOE BKP BKE OSSR OSSI LOCK[1:0] DTG[7:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Note: As the bits AOE, BKP, BKE, OSSI, OSSR and DTG[7:0] can be write-locked depending on
the LOCK configuration, it can be necessary to configure all of them during the first write
access to the TIMx_BDTR register.

Bit 15 MOE: Main output enable

This bit is cleared asynchronously by hardware as soon as the break input is active. It is set
by software or automatically depending on the AOE bit. It is acting only on the channels
which are configured in output.
0: OC and OCN outputs are disabled or forced to idle state
1: OC and OCN outputs are enabled if their respective enable bits are set (CCxE, CCxNE in
TIMx_CCER register)
See OC/OCN enable description for more details (Section 17.5.9: TIM15 capture/compare
enable register (TIM15_CCER) on page 441).
Bit 14 AOE: Automatic output enable
0: MOE can be set only by software
1: MOE can be set by software or automatically at the next update event (if the break input is
not be active)
Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits
in TIMx_BDTR register).
Bit 13 BKP: Break polarity
0: Break input BRK is active low
1: Break input BRK is active high
Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits
in TIMx_BDTR register).
Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.

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Bit 12 BKE: Break enable

0: Break inputs (BRK and CCS clock failure event) disabled
1; Break inputs (BRK and CCS clock failure event) enabled
Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in
TIMx_BDTR register).
Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.
Bit 11 OSSR: Off-state selection for Run mode
This bit is used when MOE=1 on channels having a complementary output which are
configured as outputs. OSSR is not implemented if no complementary output is implemented
in the timer.
See OC/OCN enable description for more details (Section 17.5.9: TIM15 capture/compare
enable register (TIM15_CCER) on page 441).
0: When inactive, OC/OCN outputs are disabled (OC/OCN enable output signal=0)
1: When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1
or CCxNE=1. Then, OC/OCN enable output signal=1
Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK
bits in TIMx_BDTR register).
Bit 10 OSSI: Off-state selection for Idle mode
This bit is used when MOE=0 on channels configured as outputs.
See OC/OCN enable description for more details (Section 17.5.9: TIM15 capture/compare
enable register (TIM15_CCER) on page 441).
0: When inactive, OC/OCN outputs are disabled (OC/OCN enable output signal=0)
1: When inactive, OC/OCN outputs are forced first with their idle level as soon as CCxE=1 or
CCxNE=1. OC/OCN enable output signal=1)
Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK
bits in TIMx_BDTR register).
Bits 9:8 LOCK[1:0]: Lock configuration
These bits offer a write protection against software errors.
00: LOCK OFF - No bit is write protected
01: LOCK Level 1 = DTG bits in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2
register and BKE/BKP/AOE bits in TIMx_BDTR register can no longer be written
10: LOCK Level 2 = LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER
register, as long as the related channel is configured in output through the CCxS bits) as
well as OSSR and OSSI bits can no longer be written.
11: LOCK Level 3 = LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in
TIMx_CCMRx registers, as long as the related channel is configured in output through
the CCxS bits) can no longer be written.
Note: The LOCK bits can be written only once after the reset. Once the TIMx_BDTR register
has been written, their content is frozen until the next reset.

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Bits 7:0 DTG[7:0]: Dead-time generator setup

This bit-field defines the duration of the dead-time inserted between the complementary
outputs. DT correspond to this duration.
DTG[7:5]=0xx => DT=DTG[7:0]x tdtg with tdtg=tDTS
DTG[7:5]=10x => DT=(64+DTG[5:0])xtdtg with Tdtg=2xtDTS
DTG[7:5]=110 => DT=(32+DTG[4:0])xtdtg with Tdtg=8xtDTS
DTG[7:5]=111 => DT=(32+DTG[4:0])xtdtg with Tdtg=16xtDTS
Example if TDTS=125ns (8MHz), dead-time possible values are:
0 to 15875 ns by 125 ns steps,
16 µs to 31750 ns by 250 ns steps,
32 µs to 63 µs by 1 µs steps,
64 µs to 126 µs by 2 µs steps
Note: This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed
(LOCK bits in TIMx_BDTR register).

17.5.17 TIM15 DMA control register (TIM15_DCR)

Address offset: 0x48
Reset value: 0x0000

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. DBL[4:0] Res. Res. Res. DBA[4:0]
rw rw rw rw rw rw rw rw rw rw

Bits 15:13 Reserved, must be kept at reset value.

Bits 12:8 DBL[4:0]: DMA burst length
This 5-bit vector defines the length of DMA transfers (the timer recognizes a burst transfer
when a read or a write access is done to the TIMx_DMAR address).
00000: 1 transfer
00001: 2 transfers
00010: 3 transfers
...
10001: 18 transfers
Bits 7:5 Reserved, must be kept at reset value.
Bits 4:0 DBA[4:0]: DMA base address
This 5-bits vector defines the base-address for DMA transfers (when read/write access are
done through the TIMx_DMAR address). DBA is defined as an offset starting from the
address of the TIMx_CR1 register.
Example:
00000: TIMx_CR1
00001: TIMx_CR2
00010: TIMx_SMCR
...

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RM0360 General-purpose timers (TIM15/16/17)

17.5.18 TIM15 DMA address for full transfer (TIM15_DMAR)

Address offset: 0x4C
Reset value: 0x0000

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAB[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 15:0 DMAB[15:0]: DMA register for burst accesses

A read or write operation to the DMAR register accesses the register located at the address
(TIMx_CR1 address) + (DBA + DMA index) x 4
where TIMx_CR1 address is the address of the control register 1, DBA is the DMA base
address configured in TIMx_DCR register, DMA index is automatically controlled by the
DMA transfer, and ranges from 0 to DBL (DBL configured in TIMx_DCR).

17.5.19 TIM15 register map

TIM15 registers are mapped as 16-bit addressable registers as described in the table
below:

Table 56. TIM15 register map and reset values

Offset Register
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12

10
11

9
8
7
6
5
4
3
2
1
0
ARPE
CKD

UDIS
OPM

CEN
URS
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.
Res.
Res.
TIM15_CR1
0x00 [1:0]

Reset value 0 0 0 0 0 0 0
OIS1N

CCPC
CCDS
CCUS
OIS2

OIS1
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.

Res.
TIM15_CR2 MMS[2:0]
0x04
Reset value 0 0 0 0 0 0 0 0 0
MSM
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.
TIM15_SMCR TS[2:0] SMS[2:0]
0x08
Reset value 0 0 0 0 0 0 0
CC2DE
CC1DE

COMIE

CC2IE
CC1IE
UDE
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.
Res.
Res.

Res.
Res.
TDE

UIE
BIE
TIE

TIM15_DIER
0x0C
Reset value 0 0 0 0 0 0 0 0 0 0
CC2OF
CC1OF

COMIF

CC2IF
CC1IF
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.

Res.
Res.

UIF
BIF
TIF

TIM15_SR
0x10
Reset value 0 0 0 0 0 0 0 0
COMG

CC2G
CC1G
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.
Res.

UG

TIM15_EGR
BG
TG

0x14
Reset value 0 0 0 0 0 0
TIM15_CCMR1
OC2PE

OC1PE
OC2FE

OC1FE

OC2M CC2S OC1M CC1S

Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.

Output compare
[2:0] [1:0] [2:0] [1:0]
mode
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x18
TIM15_CCMR1 IC2 IC1
CC2S CC1S
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Input capture IC2F[3:0] PSC IC1F[3:0] PSC

[1:0] [1:0]
mode [1:0] [1:0]
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
CC2NP

CC1NP
CC1NE
CC2P
CC2E

CC1P
CC1E
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.

TIM15_CCER
0x20
Reset value 0 0 0 0 0 0 0

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Table 56. TIM15 register map and reset values (continued)

Offset Register

31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12

10
11

9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
TIM15_CNT CNT[15:0]
0x24
Reset value Res. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
TIM15_PSC PSC[15:0]
0x28
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
TIM15_ARR ARR[15:0]
0x2C
Reset value 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
TIM15_RCR REP[7:0]
0x30
Reset value 0 0 0 0 0 0 0 0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
TIM15_CCR1 CCR1[15:0]
0x34
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
TIM15_CCR2 CCR2[15:0]
0x38
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

OSSR
LOCK

OSSI
MOE
AOE
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

BKP
BKE
TIM15_BDTR DT[7:0]
0x44 [1:0]

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.
Res.
Res.
TIM15_DCR DBL[4:0] DBA[4:0]
0x48
Reset value 0 0 0 0 0 0 0 0 0 0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

TIM15_DMAR DMAB[15:0]
0x4C
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Refer to Section 2.2 on page 37 for the register boundary addresses.

17.6 TIM16/TIM17 registers

Refer to Section 1.2 on page 33 for a list of abbreviations used in register descriptions.

17.6.1 TIMx control register 1 (TIMx_CR1)(x = 16 to 17)

Address offset: 0x00
Reset value: 0x0000

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. CKD[1:0] ARPE Res. Res. Res. OPM URS UDIS CEN
rw rw rw rw rw rw rw

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RM0360 General-purpose timers (TIM15/16/17)

Bits 15:10 Reserved, must be kept at reset value.

Bits 9:8 CKD[1:0]: Clock division
This bit-field indicates the division ratio between the timer clock (CK_INT) frequency and the
dead-time and sampling clock (tDTS)used by the dead-time generators and the digital filters
(TIx),
00: tDTS=tCK_INT
01: tDTS=2*tCK_INT
10: tDTS=4*tCK_INT
11: Reserved, do not program this value
Bit 7 ARPE: Auto-reload preload enable
0: TIMx_ARR register is not buffered
1: TIMx_ARR register is buffered
Bits 6:4 Reserved, must be kept at reset value.
Bit 3 OPM: One pulse mode
0: Counter is not stopped at update event
1: Counter stops counting at the next update event (clearing the bit CEN)
Bit 2 URS: Update request source
This bit is set and cleared by software to select the UEV event sources.
0: Any of the following events generate an update interrupt or DMA request if enabled.
These events can be:
– Counter overflow/underflow
– Setting the UG bit
– Update generation through the slave mode controller
1: Only counter overflow/underflow generates an update interrupt or DMA request if
enabled.
Bit 1 UDIS: Update disable
This bit is set and cleared by software to enable/disable UEV event generation.
0: UEV enabled. The Update (UEV) event is generated by one of the following events:
– Counter overflow/underflow
– Setting the UG bit
– Update generation through the slave mode controller
Buffered registers are then loaded with their preload values.
1: UEV disabled. The Update event is not generated, shadow registers keep their value
(ARR, PSC, CCRx). However the counter and the prescaler are reinitialized if the UG bit
is set or if a hardware reset is received from the slave mode controller.
Bit 0 CEN: Counter enable
0: Counter disabled
1: Counter enabled

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17.6.2 TIMx control register 2 (TIMx_CR2)(x = 16 to 17)

Address offset: 0x04
Reset value: 0x0000

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. OIS1N OIS1 Res. Res. Res. Res. CCDS CCUS Res. CCPC
rw rw rw rw rw

Bits 15:10 Reserved, must be kept at reset value.

Bit 9 OIS1N: Output Idle state 1 (OC1N output)
0: OC1N=0 after a dead-time when MOE=0
1: OC1N=1 after a dead-time when MOE=0
Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed
(LOCK bits in TIMx_BKR register).
Bit 8 OIS1: Output Idle state 1 (OC1 output)
0: OC1=0 (after a dead-time if OC1N is implemented) when MOE=0
1: OC1=1 (after a dead-time if OC1N is implemented) when MOE=0
Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed
(LOCK bits in TIMx_BKR register).
Bits 7:4 Reserved, must be kept at reset value.
Bit 3 CCDS: Capture/compare DMA selection
0: CCx DMA request sent when CCx event occurs
1: CCx DMA requests sent when update event occurs
Bit 2 CCUS: Capture/compare control update selection
0: When capture/compare control bits are preloaded (CCPC=1), they are updated by setting
the COMG bit only.
1: When capture/compare control bits are preloaded (CCPC=1), they are updated by setting
the COMG bit or when an rising edge occurs on TRGI.
Note: This bit acts only on channels that have a complementary output.
Bit 1 Reserved, must be kept at reset value.
Bit 0 CCPC: Capture/compare preloaded control
0: CCxE, CCxNE and OCxM bits are not preloaded
1: CCxE, CCxNE and OCxM bits are preloaded, after having been written, they are updated
only when COM bit is set.
Note: This bit acts only on channels that have a complementary output.

17.6.3 TIMx DMA/interrupt enable register (TIMx_DIER)(x = 16 to 17)

Address offset: 0x0C
Reset value: 0x0000

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. CC1DE UDE BIE Res. COMIE Res. Res. Res. CC1IE UIE
rw rw rw rw rw rw

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RM0360 General-purpose timers (TIM15/16/17)

Bits 15:10 Reserved, must be kept at reset value.

Bit 9 CC1DE: Capture/Compare 1 DMA request enable
0: CC1 DMA request disabled
1: CC1 DMA request enabled
Bit 8 UDE: Update DMA request enable
0: Update DMA request disabled
1: Update DMA request enabled
Bit 7 BIE: Break interrupt enable
0: Break interrupt disabled
1: Break interrupt enabled
Bit 6 Reserved, must be kept at reset value.
Bit 5 COMIE: COM interrupt enable
0: COM interrupt disabled
1: COM interrupt enabled
Bits 4:2 Reserved, must be kept at reset value.
Bit 1 CC1IE: Capture/Compare 1 interrupt enable
0: CC1 interrupt disabled
1: CC1 interrupt enabled
Bit 0 UIE: Update interrupt enable
0: Update interrupt disabled
1: Update interrupt enabled

17.6.4 TIMx status register (TIMx_SR)(x = 16 to 17)

Address offset: 0x10
Reset value: 0x0000

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. CC1OF Res. BIF Res. COMIF Res. Res. Res. CC1IF UIF
rc_w0 rc_w0 rc_w0 rc_w0 rc_w0

Bits 15:10 Reserved, must be kept at reset value.

Bit 9 CC1OF: Capture/Compare 1 overcapture flag
This flag is set by hardware only when the corresponding channel is configured in input
capture mode. It is cleared by software by writing it to ‘0’.
0: No overcapture has been detected
1: The counter value has been captured in TIMx_CCR1 register while CC1IF flag was
already set
Bit 8 Reserved, must be kept at reset value.
Bit 7 BIF: Break interrupt flag
This flag is set by hardware as soon as the break input goes active. It can be cleared by
software if the break input is not active.
0: No break event occurred
1: An active level has been detected on the break input

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Bit 6 Reserved, must be kept at reset value.

Bit 5 COMIF: COM interrupt flag
This flag is set by hardware on a COM event (once the capture/compare control bits –CCxE,
CCxNE, OCxM– have been updated). It is cleared by software by writing it to ‘0’.
0: No COM event occurred
1: COM interrupt pending
Bits 4:2 Reserved, must be kept at reset value.
Bit 1 CC1IF: Capture/Compare 1 interrupt flag
Condition: channel CC1 is configured as output:
This flag is set by hardware when the counter matches the compare value, it is cleared by
software.
0: No match.
1: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register.
When the contents of TIMx_CCR1 are greater than the contents of TIMx_ARR, the
CC1IF bit goes high on the counter overflow (in upcounting and up/down-counting
modes) or underflow (in downcounting mode)
Condition: channel CC1 is configured as input:
This bit is set by hardware on a capture. It is cleared by software or by reading the
TIMx_CCR1 register.
0: No input capture occurred
1: The counter value has been captured in TIMx_CCR1 register (An edge has been
detected on IC1 which matches the selected polarity)
Bit 0 UIF: Update interrupt flag
This bit is set by hardware on an update event. It is cleared by software.
0: No update occurred.
1: Update interrupt pending. This bit is set by hardware when the registers are updated:
– At overflow regarding the repetition counter value (update if repetition counter = 0)
and if the UDIS=0 in the TIMx_CR1 register.
– When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if
URS=0 and UDIS=0 in the TIMx_CR1 register.

17.6.5 TIMx event generation register (TIMx_EGR)(x = 16 to 17)

Address offset: 0x14
Reset value: 0x0000

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. BG Res. COMG Res. Res. Res. CC1G UG
w w w w

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RM0360 General-purpose timers (TIM15/16/17)

Bits 15:8 Reserved, must be kept at reset value.

Bit 7 BG: Break generation
This bit is set by software in order to generate an event, it is automatically cleared by
hardware.
0: No action.
1: A break event is generated. MOE bit is cleared and BIF flag is set. Related interrupt or
DMA transfer can occur if enabled.
Bit 6 Reserved, must be kept at reset value.
Bit 5 COMG: Capture/Compare control update generation
This bit can be set by software, it is automatically cleared by hardware.
0: No action
1: When the CCPC bit is set, it is possible to update the CCxE, CCxNE and OCxM bits
Note: This bit acts only on channels that have a complementary output.
Bits 4:2 Reserved, must be kept at reset value.
Bit 1 CC1G: Capture/Compare 1 generation
This bit is set by software in order to generate an event, it is automatically cleared by
hardware.
0: No action.
1: A capture/compare event is generated on channel 1:
Condition: channel CC1 is configured as output:
CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled.
Condition: channel CC1 is configured as input:
The current value of the counter is captured in TIMx_CCR1 register. The CC1IF flag is set,
the corresponding interrupt or DMA request is sent if enabled. The CC1OF flag is set if the
CC1IF flag was already high.
Bit 0 UG: Update generation
This bit can be set by software, it is automatically cleared by hardware.
0: No action.
1: Reinitialize the counter and generates an update of the registers. Note that the prescaler
counter is cleared too (anyway the prescaler ratio is not affected).

17.6.6 TIMx capture/compare mode register 1 [alternate]

(TIMx_CCMR1)(x = 16 to 17)
Address offset: 0x18
Reset value: 0x0000
The same register can be used for input capture mode (this section) or for output compare
mode (next section). The direction of a channel is defined by configuring the corresponding
CCxS bits. All the other bits of this register have a different function in input and in output
mode. For a given bit, OCxx describes its function when the channel is configured in output,
ICxx describes its function when the channel is configured in input. So one must take care
that the same bit can have a different meaning for the input stage and for the output stage.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. IC1F[3:0] IC1PSC[1:0] CC1S[1:0]
rw rw rw rw rw rw rw rw

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General-purpose timers (TIM15/16/17) RM0360

Bits 15:8 Reserved, must be kept at reset value.

Bits 7:4 IC1F[3:0]: Input capture 1 filter
This bit-field defines the frequency used to sample TI1 input and the length of the digital filter applied
to TI1. The digital filter is made of an event counter in which N events are needed to validate a
transition on the output:
0000: No filter, sampling is done at fDTS
0001: fSAMPLING = fCK_INT, N = 2
0010: fSAMPLING = fCK_INT, N = 4
0011: fSAMPLING = fCK_INT, N = 8
0100: fSAMPLING = fDTS / 2, N = 6
0101: fSAMPLING = fDTS / 2, N = 8
0110: fSAMPLING = fDTS / 4, N = 6
0111: fSAMPLING = fDTS / 4, N = 8
1000: fSAMPLING = fDTS / 8, N = 6
1001: fSAMPLING = fDTS / 8, N = 8
1010: fSAMPLING = fDTS / 16, N = 5
1011: fSAMPLING = fDTS / 16, N = 6
1100: fSAMPLING = fDTS / 16, N = 8
1101: fSAMPLING = fDTS / 32, N = 5
1110: fSAMPLING = fDTS / 32, N = 6
1111: fSAMPLING = fDTS / 32, N = 8
Note: Care must be taken that fDTS is replaced in the formula by CK_INT when ICxF[3:0] = 1, 2 or 3.
Bits 3:2 IC1PSC[1:0]: Input capture 1 prescaler
This bit-field defines the ratio of the prescaler acting on CC1 input (IC1).
The prescaler is reset as soon as CC1E=’0’ (TIMx_CCER register).
00: no prescaler, capture is done each time an edge is detected on the capture input.
01: capture is done once every 2 events
10: capture is done once every 4 events
11: capture is done once every 8 events
Bits 1:0 CC1S[1:0]: Capture/Compare 1 Selection
This bit-field defines the direction of the channel (input/output) as well as the used input.
00: CC1 channel is configured as output
01: CC1 channel is configured as input, IC1 is mapped on TI1
10: CC1 channel is configured as input, IC1 is mapped on TI2
11: CC1 channel is configured as input, IC1 is mapped on TRC. This mode is working only if an
internal trigger input is selected through TS bit (TIMx_SMCR register)
Note: CC1S bits are writable only when the channel is OFF (CC1E = ‘0’ in TIMx_CCER).

17.6.7 TIMx capture/compare mode register 1 [alternate]

(TIMx_CCMR1)(x = 16 to 17)
Address offset: 0x18
Reset value: 0x0000
The same register can be used for output compare mode (this section) or for input capture
mode (previous section). The direction of a channel is defined by configuring the
corresponding CCxS bits. All the other bits of this register have a different function in input
and in output mode. For a given bit, OCxx describes its function when the channel is
configured in output, ICxx describes its function when the channel is configured in input. So

456/775 RM0360 Rev 5

RM0360 General-purpose timers (TIM15/16/17)

one must take care that the same bit can have a different meaning for the input stage and
for the output stage.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. OC1M[2:0] OC1PE OC1FE CC1S[1:0]
rw rw rw rw rw rw rw

Bits 15:7 Reserved, must be kept at reset value.

Bits 6:4 OC1M[2:0]: Output Compare 1 mode
These bits define the behavior of the output reference signal OC1REF from which OC1 and
OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends
on CC1P and CC1NP bits.
000: Frozen - The comparison between the output compare register TIMx_CCR1 and the
counter TIMx_CNT has no effect on the outputs.
001: Set channel 1 to active level on match. OC1REF signal is forced high when the
counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1).
010: Set channel 1 to inactive level on match. OC1REF signal is forced low when the
counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1).
011: Toggle - OC1REF toggles when TIMx_CNT=TIMx_CCR1.
100: Force inactive level - OC1REF is forced low.
101: Force active level - OC1REF is forced high.
110: PWM mode 1 - In upcounting, channel 1 is active as long as TIMx_CNT<TIMx_CCR1
else inactive. In downcounting, channel 1 is inactive (OC1REF=‘0’) as long as
TIMx_CNT>TIMx_CCR1 else active (OC1REF=’1’).
111: PWM mode 2 - In upcounting, channel 1 is inactive as long as
TIMx_CNT<TIMx_CCR1 else active. In downcounting, channel 1 is active as long as
TIMx_CNT>TIMx_CCR1 else inactive.
Note: These bits can not be modified as long as LOCK level 3 has been programmed (LOCK
bits in TIMx_BDTR register) and CC1S=’00’ (the channel is configured in output).
Note: In PWM mode 1 or 2, the OCREF level changes only when the result of the
comparison changes or when the output compare mode switches from “frozen” mode
to “PWM” mode.
Bit 3 OC1PE: Output Compare 1 preload enable
0: Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the
new value is taken in account immediately.
1: Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload
register. TIMx_CCR1 preload value is loaded in the active register at each update event.
Note: These bits can not be modified as long as LOCK level 3 has been programmed (LOCK
bits in TIMx_BDTR register) and CC1S=’00’ (the channel is configured in output).
Bit 2 OC1FE: Output Compare 1 fast enable
This bit is used to accelerate the effect of an event on the trigger in input on the CC output.
0: CC1 behaves normally depending on counter and CCR1 values even when the trigger is
ON. The minimum delay to activate CC1 output when an edge occurs on the trigger input
is 5 clock cycles.
1: An active edge on the trigger input acts like a compare match on CC1 output. Then, OC
is set to the compare level independently of the result of the comparison. Delay to
sample the trigger input and to activate CC1 output is reduced to 3 clock cycles. OC1FE
acts only if the channel is configured in PWM1 or PWM2 mode.

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Bits 1:0 CC1S[1:0]: Capture/Compare 1 selection

This bit-field defines the direction of the channel (input/output) as well as the used input.
00: CC1 channel is configured as output
01: CC1 channel is configured as input, IC1 is mapped on TI1
10: CC1 channel is configured as input, IC1 is mapped on TI2
11: CC1 channel is configured as input, IC1 is mapped on TRC. This mode is working only
if an internal trigger input is selected through TS bit (TIMx_SMCR register)
Note: CC1S bits are writable only when the channel is OFF (CC1E = ‘0’ in TIMx_CCER).

17.6.8 TIMx capture/compare enable register (TIMx_CCER)(x = 16 to 17)

Address offset: 0x20
Reset value: 0x0000

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CC1NP CC1NE CC1P CC1E
rw rw rw rw

Bits 15:4 Reserved, must be kept at reset value.

Bit 3 CC1NP: Capture/Compare 1 complementary output polarity
0: OC1N active high
1: OC1N active low
Note: This bit is not writable as soon as LOCK level 2 or 3 has been programmed (LOCK bits
in TIMx_BDTR register) and CC1S=”00” (the channel is configured in output).
Bit 2 CC1NE: Capture/Compare 1 complementary output enable
0: Off - OC1N is not active. OC1N level is then function of MOE, OSSI, OSSR, OIS1, OIS1N
and CC1E bits.
1: On - OC1N signal is output on the corresponding output pin depending on MOE, OSSI,
OSSR, OIS1, OIS1N and CC1E bits.
Bit 1 CC1P: Capture/Compare 1 output polarity
Condition: CC1 channel configured as output
0: OC1 active high
1: OC1 active low
Condition: CC1 channel configured as input
The CC1NP/CC1P bits select the polarity of TI1FP1 and TI2FP1 for capture operation.
00: Non-inverted/rising edge: circuit is sensitive to TIxFP1's rising edge TIxFP1 is not
inverted.
01: Inverted/falling edge: circuit is sensitive to TIxFP1's falling edge, TIxFP1 is inverted.
10: Reserved, do not use this configuration.
11: Non-inverted/both edges: circuit is sensitive to both the rising and falling edges of
TIxFP1, TIxFP1 is not inverted.
Note: This bit is not writable as soon as LOCK level 2 or 3 has been programmed (LOCK bits
in TIMx_BDTR register)

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RM0360 General-purpose timers (TIM15/16/17)

Bit 0 CC1E: Capture/Compare 1 output enable

Condition: CC1 channel configured as output
0: Off - OC1 is not active. OC1 level is then function of MOE, OSSI, OSSR, OIS1, OIS1N
and CC1NE bits.
1: On - OC1 signal is output on the corresponding output pin depending on MOE, OSSI,
OSSR, OIS1, OIS1N and CC1NE bits.
Condition: CC1 channel configured as input
This bit determines if a capture of the counter value can actually be done into the input
capture/compare register 1 (TIMx_CCR1) or not.
0: Capture disabled
1: Capture enabled

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Table 57. Output control bits for complementary OCx and OCxN channels with break
feature
Control bits Output states(1)
MOE OSSI OSSR CCxE CCxNE
OCx output state OCxN output state
bit bit bit bit bit
Output Disabled (not Output Disabled (not driven by
0 0 0 driven by the timer) the timer)
OCx=0, OCx_EN=0 OCxN=0, OCxN_EN=0
Output Disabled (not OCxREF + Polarity
0 0 1 driven by the timer) OCxN=OCxREF xor CCxNP,
OCx=0, OCx_EN=0 OCxN_EN=1

OCxREF + Polarity Output Disabled (not driven by

0 1 0 OCx=OCxREF xor CCxP, the timer)
OCx_EN=1 OCxN=0, OCxN_EN=0

OCREF + Polarity + dead- Complementary to OCREF (not

0 1 1 time OCREF) + Polarity + dead-time
OCx_EN=1 OCxN_EN=1
1 X
Output Disabled (not Output Disabled (not driven by
1 0 0 driven by the timer) the timer)
OCx=CCxP, OCx_EN=0 OCxN=CCxNP, OCxN_EN=0
Off-State (output enabled OCxREF + Polarity
1 0 1 with inactive state) OCxN=OCxREF xor CCxNP,
OCx=CCxP, OCx_EN=1 OCxN_EN=1
OCxREF + Polarity Off-State (output enabled with
1 1 0 OCx=OCxREF xor CCxP, inactive state)
OCx_EN=1 OCxN=CCxNP, OCxN_EN=1

OCREF + Polarity + dead- Complementary to OCREF (not

1 1 1 time OCREF) + Polarity + dead-time
OCx_EN=1 OCxN_EN=1
0 0 0 Output Disabled (not driven by the timer)
0 0 1 Asynchronously: OCx=CCxP, OCx_EN=0, OCxN=CCxNP,
OCxN_EN=0
0 1 0
Then if the clock is present: OCx=OISx and OCxN=OISxN
0 1 1 after a dead-time, assuming that OISx and OISxN do not
1 0 0 correspond to OCX and OCxN both in active state.
0 X
1 0 1 Off-State (output enabled with inactive state)
1 1 0 Asynchronously: OCx=CCxP, OCx_EN=1, OCxN=CCxNP,
OCxN_EN=1
Then if the clock is present: OCx=OISx and OCxN=OISxN
1 1 1 after a dead-time, assuming that OISx and OISxN do not
correspond to OCX and OCxN both in active state
1. When both outputs of a channel are not used (CCxE = CCxNE = 0), the OISx, OISxN, CCxP and CCxNP
bits must be kept cleared.

Note: The state of the external I/O pins connected to the complementary OCx and OCxN channels
depends on the OCx and OCxN channel state and the GPIO and AFIO registers.

460/775 RM0360 Rev 5

RM0360 General-purpose timers (TIM15/16/17)

17.6.9 TIMx counter (TIMx_CNT)(x = 16 to 17)

Address offset: 0x24
Reset value: 0x0000

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 15:0 CNT[15:0]: Counter value

17.6.10 TIMx prescaler (TIMx_PSC)(x = 16 to 17)

Address offset: 0x28
Reset value: 0x0000

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 15:0 PSC[15:0]: Prescaler value

The counter clock frequency (CK_CNT) is equal to fCK_PSC / (PSC[15:0] + 1).
PSC contains the value to be loaded in the active prescaler register at each update event
(including when the counter is cleared through UG bit of TIMx_EGR register or through
trigger controller when configured in “reset mode”).

17.6.11 TIMx auto-reload register (TIMx_ARR)(x = 16 to 17)

Address offset: 0x2C
Reset value: 0xFFFF

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 15:0 ARR[15:0]: Auto-reload value

ARR is the value to be loaded in the actual auto-reload register.
Refer to the Section 16.3.1: Time-base unit on page 381 for more details about ARR update
and behavior.
The counter is blocked while the auto-reload value is null.

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17.6.12 TIMx repetition counter register (TIMx_RCR)(x = 16 to 17)

Address offset: 0x30
Reset value: 0x0000

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. REP[7:0]
rw rw rw rw rw rw rw rw

Bits 15:8 Reserved, must be kept at reset value.

Bits 7:0 REP[7:0]: Repetition counter value
These bits allow the user to set-up the update rate of the compare registers (i.e. periodic
transfers from preload to active registers) when preload registers are enable, as well as the
update interrupt generation rate, if this interrupt is enable.
Each time the REP_CNT related downcounter reaches zero, an update event is generated
and it restarts counting from REP value. As REP_CNT is reloaded with REP value only at
the repetition update event U_RC, any write to the TIMx_RCR register is not taken in
account until the next repetition update event.
It means in PWM mode (REP+1) corresponds to the number of PWM periods in edge-
aligned mode.

17.6.13 TIMx capture/compare register 1 (TIMx_CCR1)(x = 16 to 17)

Address offset: 0x34
Reset value: 0x0000

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR1[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 15:0 CCR1[15:0]: Capture/Compare 1 value

Condition: channel CC1 is configured as output
CCR1 is the value to be loaded in the actual capture/compare 1 register (preload value).
It is loaded permanently if the preload feature is not selected in the TIMx_CCMR1 register
(bit OC1PE). Else the preload value is copied in the active capture/compare 1 register when
an update event occurs.
The active capture/compare register contains the value to be compared to the counter
TIMx_CNT and signaled on OC1 output.
Condition: channel CC1 is configured as input:
CCR1 is the counter value transferred by the last input capture 1 event (IC1).

17.6.14 TIMx break and dead-time register (TIMx_BDTR)(x = 16 to 17)

Address offset: 0x44
Reset value: 0x0000

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MOE AOE BKP BKE OSSR OSSI LOCK[1:0] DTG[7:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

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RM0360 General-purpose timers (TIM15/16/17)

Note: As the bits AOE, BKP, BKE, OSSI, OSSR and DTG[7:0] can be write-locked depending on
the LOCK configuration, it can be necessary to configure all of them during the first write
access to the TIMx_BDTR register.

Bit 15 MOE: Main output enable

This bit is cleared asynchronously by hardware as soon as the break input is active. It is set
by software or automatically depending on the AOE bit. It is acting only on the channels
which are configured in output.
0: OC and OCN outputs are disabled or forced to idle state
1: OC and OCN outputs are enabled if their respective enable bits are set (CCxE, CCxNE in
TIMx_CCER register)
See OC/OCN enable description for more details (Section 17.5.9: TIM15 capture/compare
enable register (TIM15_CCER) on page 441).
Bit 14 AOE: Automatic output enable
0: MOE can be set only by software
1: MOE can be set by software or automatically at the next update event (if the break input is
not be active)
Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits
in TIMx_BDTR register).
Bit 13 BKP: Break polarity
0: Break input BRK is active low
1: Break input BRK is active high
Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits
in TIMx_BDTR register).
Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.
Bit 12 BKE: Break enable
0: Break inputs (BRK and CCS clock failure event) disabled
1; Break inputs (BRK and CCS clock failure event) enabled
Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in
TIMx_BDTR register).
Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.
Bit 11 OSSR: Off-state selection for Run mode
This bit is used when MOE=1 on channels having a complementary output which are
configured as outputs. OSSR is not implemented if no complementary output is implemented
in the timer.
See OC/OCN enable description for more details (Section 17.5.9: TIM15 capture/compare
enable register (TIM15_CCER) on page 441).
0: When inactive, OC/OCN outputs are disabled (OC/OCN enable output signal=0)
1: When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1
or CCxNE=1. Then, OC/OCN enable output signal=1
Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK
bits in TIMx_BDTR register).

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467
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Bit 10 OSSI: Off-state selection for Idle mode

This bit is used when MOE=0 on channels configured as outputs.
See OC/OCN enable description for more details (Section 17.5.9: TIM15 capture/compare
enable register (TIM15_CCER) on page 441).
0: When inactive, OC/OCN outputs are disabled (OC/OCN enable output signal=0)
1: When inactive, OC/OCN outputs are forced first with their idle level as soon as CCxE=1 or
CCxNE=1. OC/OCN enable output signal=1)
Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK
bits in TIMx_BDTR register).
Bits 9:8 LOCK[1:0]: Lock configuration
These bits offer a write protection against software errors.
00: LOCK OFF - No bit is write protected
01: LOCK Level 1 = DTG bits in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2
register and BKE/BKP/AOE bits in TIMx_BDTR register can no longer be written.
10: LOCK Level 2 = LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER
register, as long as the related channel is configured in output through the CCxS bits) as
well as OSSR and OSSI bits can no longer be written.
11: LOCK Level 3 = LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in
TIMx_CCMRx registers, as long as the related channel is configured in output through
the CCxS bits) can no longer be written.
Note: The LOCK bits can be written only once after the reset. Once the TIMx_BDTR register
has been written, their content is frozen until the next reset.
Bits 7:0 DTG[7:0]: Dead-time generator setup
This bit-field defines the duration of the dead-time inserted between the complementary
outputs. DT correspond to this duration.
DTG[7:5]=0xx => DT=DTG[7:0]x tdtg with tdtg=tDTS
DTG[7:5]=10x => DT=(64+DTG[5:0])xtdtg with Tdtg=2xtDTS
DTG[7:5]=110 => DT=(32+DTG[4:0])xtdtg with Tdtg=8xtDTS
DTG[7:5]=111 => DT=(32+DTG[4:0])xtdtg with Tdtg=16xtDTS
Example if TDTS=125ns (8MHz), dead-time possible values are:
0 to 15875 ns by 125 ns steps,
16 µs to 31750 ns by 250 ns steps,
32 µs to 63 µs by 1 µs steps,
64 µs to 126 µs by 2 µs steps
Note: This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed
(LOCK bits in TIMx_BDTR register).

17.6.15 TIMx DMA control register (TIMx_DCR)(x = 16 to 17)

Address offset: 0x48
Reset value: 0x0000

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. DBL[4:0] Res. Res. Res. DBA[4:0]
rw rw rw rw rw rw rw rw rw rw

Bits 15:13 Reserved, must be kept at reset value.

464/775 RM0360 Rev 5

RM0360 General-purpose timers (TIM15/16/17)

Bits 12:8 DBL[4:0]: DMA burst length

This 5-bit vector defines the length of DMA transfers (the timer recognizes a burst transfer
when a read or a write access is done to the TIMx_DMAR address), i.e. the number of
transfers. Transfers can be in half-words or in bytes (see example below).
00000: 1 transfer
00001: 2 transfers
00010: 3 transfers
...
10001: 18 transfers.
Bits 7:5 Reserved, must be kept at reset value.
Bits 4:0 DBA[4:0]: DMA base address
This 5-bits vector defines the base-address for DMA transfers (when read/write access are
done through the TIMx_DMAR address). DBA is defined as an offset starting from the
address of the TIMx_CR1 register.
Example:
00000: TIMx_CR1
00001: TIMx_CR2
00010: TIMx_SMCR
...
Example: Let us consider the following transfer: DBL = 7 transfers and DBA = TIMx_CR1.
In this case the transfer is done to/from 7 registers starting from the TIMx_CR1 address.

17.6.16 TIMx DMA address for full transfer (TIMx_DMAR)(x = 16 to 17)

Address offset: 0x4C
Reset value: 0x0000

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAB[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 15:0 DMAB[15:0]: DMA register for burst accesses

A read or write access to the DMAR register accesses the register located at the address:
“(TIMx_CR1 address) + DBA + (DMA index)” in which:
TIMx_CR1 address is the address of the control register 1, DBA is the DMA base address
configured in TIMx_DCR register, DMA index is the offset automatically controlled by the
DMA transfer, depending on the length of the transfer DBL in the TIMx_DCR register.

Example of how to use the DMA burst feature

In this example the timer DMA burst feature is used to update the contents of the CCRx
registers (x = 2, 3, 4) with the DMA transferring half words into the CCRx registers.
This is done in the following steps:

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1. Configure the corresponding DMA channel as follows:

– DMA channel peripheral address is the DMAR register address
– DMA channel memory address is the address of the buffer in the RAM containing
the data to be transferred by DMA into CCRx registers.
– Number of data to transfer = 3 (See note below).
– Circular mode disabled.
2. Configure the DCR register by configuring the DBA and DBL bit fields as follows:
DBL = 3 transfers, DBA = 0xE.
3. Enable the TIMx update DMA request (set the UDE bit in the DIER register).
4. Enable TIMx
5. Enable the DMA channel
Note: This example is for the case where every CCRx register to be updated once. If every CCRx
register is to be updated twice for example, the number of data to transfer should be 6. Let
us take the example of a buffer in the RAM containing data1, data2, data3, data4, data5 and
data6. The data is transferred to the CCRx registers as follows: on the first update DMA
request, data1 is transferred to CCR2, data2 is transferred to CCR3, data3 is transferred to
CCR4 and on the second update DMA request, data4 is transferred to CCR2, data5 is
transferred to CCR3 and data6 is transferred to CCR4.

17.6.17 TIM16/TIM17 register map

TIM16 and TIM17 registers are mapped as 16-bit addressable registers as described in the
table below:

Table 58. TIM16/TIM17 register map and reset values

Offset Register
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12

10
11

9
8
7
6
5
4
3
2
1
0
ARPE

TIM16_CR1 and CKD

UDIS
OPM
URS

CEN
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.
Res.
Res.
0x00 TIM17_CR1 [1:0]

Reset value 0 0 0 0 0 0 0
OIS1N

CCDS
CCUS

CCPC
TIM16_CR2 and
OIS1
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.
Res.
Res.
Res.

Res.
0x04 TIM17_CR2

Reset value 0 0 0 0 0
TIM16_DIER
CC1DE

COMIE

CC1IE
UDE
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.

Res.
Res.
Res.

UIE
BIE

and
0x0C TIM17_DIER
Reset value 0 0 0 0 0 0
CC1OF

COMIF

CC1IF

TIM16_SR and
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.

Res.

Res.
Res.
Res.

UIF
BIF

0x10 TIM17_SR

Reset value 0 0 0 0 0
COMG

CC1G

TIM16_EGR and
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.

Res.
Res.
Res.

UG
BG

0x14 TIM17_EGR

Reset value 0 0 0 0

466/775 RM0360 Rev 5

 0x48
0x44
0x34
0x30
0x28
0x24
0x20
0x18

0x4C
0x2C
Offset
RM0360

and
and
and
and
and
and

mode
mode
Register

Reset value
Reset value
Reset value
Reset value
Reset value

Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
TIM17_CNT

TIM17_PSC

TIM17_DCR
TIM17_RCR
TIM17_ARR
Input capture

TIM17_CCR1
TIM16_CCR1

TIM16_BDTR

TIM17_BDTR
TIM16_CCER

TIM17_CCER

TIM17_DMAR
TIM16_DMAR
TIM17_CCMR1
TIM17_CCMR1

TIM16_CCMR1
TIM16_CCMR1

Output compare

TIM16_PSC and
TIM16_CNT and

TIM16_DCR and
TIM16_RCR and
TIM16_ARR and
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 31
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 30
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 29
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 28
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 27
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 26
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 25
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 24
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 23
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 22
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 21
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 20
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 19
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 18
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

RM0360 Rev 5
17
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 16

0
0
0
1
0
0

Res. MOE Res. Res. Res. Res. 15

0
0
0
1
0
0

Res. AOE Res. Res. Res. Res. 14

0
0
0
1
0
0

Res. BKP Res. Res. Res. Res. 13

0
0
0
0
1
0
0

BKE Res. Res. Res. Res. 12

0
0
0
0
1
0
0

OSSR Res. Res. Res. Res. 11

0
0
0
0
1
0
0

OSSI Res. Res. Res. Res. 10

0
DBL[4:0]

0
0
0
1
0
0

Res. Res. Res. Res. 9

Refer to Section 2.2 on page 37 for the register boundary addresses.

[1:0]

0
0
0
0
1
0
0

Res. Res. Res. Res.

LOCK
8

0
0
0
1
0
0

0
0

Res. Res. Res. 7

PSC[15:0]
CNT[15:0]

ARR[15:0]
Table 58. TIM16/TIM17 register map and reset values (continued)

CCR1[15:0]

DMAB[15:0]

0
0
0
1
0
0

0
0
0

Res. Res. 6

0
0
0
1
0
0

0
0
0

Res. Res. 5
[2:0]

IC1F[3:0]
OC1M

0
0
0
0
1
0
0

0
0
0

Res. 4

0
0
0
0
1
0
0

0
0
0
0

CC1NP OC1PE 3
DT[7:0]
REP[7:0]
IC1

[1:0]
PSC

0
0
0
0
1
0
0

0
0
0
0

CC1NE OC1FE 2

0
0
0
0
1
0
0

0
0
0
0

DBA[4:0]

CC1P 1
[1:0]
[1:0]

0
0
0
0
1
0
0

0
0
0
0

CC1E
CC1S
CC1S

0
General-purpose timers (TIM15/16/17)

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Infrared interface (IRTIM) RM0360

18 Infrared interface (IRTIM)

An infrared interface (IRTIM) for remote control is available on the device. It can be used
with an infrared LED to perform remote control functions.
It uses internal connections withTIM16 as shown in Figure 193.
To generate the infrared remote control signals, the IR interface must be enabled and TIM16
channel 1 (TIM16_OC1) must be properly configured to generate correct waveforms.
The infrared receiver can be implemented easily through a basic input capture mode.

Figure 193. IRTIM internal hardware connections

All standard IR pulse modulation modes can be obtained by programming the two timer
output compare channels.
is used to generate the high frequency carrier signal, while TIM16 generates the modulation
envelope.
The infrared function is output on the IR_OUT pin. The activation of this function is done
through the GPIOx_AFRx register by enabling the related alternate function bit.
The high sink LED driver capability (only available on the PB9 pin) can be activated through
the PB9_FMP bit in the SYSCFG_CFGR1 register and used to sink the high current needed
to directly control an infrared LED.
For code example refer to the Appendix section A.9.1: TIM16 and TIM17 configuration.

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RM0360 Independent watchdog (IWDG)

19 Independent watchdog (IWDG)

19.1 Introduction
The devices feature an embedded watchdog peripheral that offers a combination of high
safety level, timing accuracy and flexibility of use. The Independent watchdog peripheral
detects and solves malfunctions due to software failure, and triggers system reset when the
counter reaches a given timeout value.
The independent watchdog (IWDG) is clocked by its own dedicated low-speed clock (LSI)
and thus stays active even if the main clock fails.
The IWDG is best suited for applications that require the watchdog to run as a totally
independent process outside the main application, but have lower timing accuracy
constraints. For further information on the window watchdog, refer to Section 20: System
window watchdog (WWDG).

19.2 IWDG main features

• Free-running downcounter
• Clocked from an independent RC oscillator (can operate in Standby and Stop modes)
• Conditional reset
– Reset (if watchdog activated) when the downcounter value becomes lower than
0x000
– Reset (if watchdog activated) if the downcounter is reloaded outside the window

19.3 IWDG functional description

19.3.1 IWDG block diagram

Figure 194 shows the functional blocks of the independent watchdog module.

Figure 194. Independent watchdog block diagram

CORE
Prescaler register Status register Reload register Key register
IWDG_PR IWDG_SR IWDG_RLR IWDG_KR

12-bit reload value

LSI 8-bit
(40 kHz) prescaler
12-bit downcounter IWDG reset
VDD voltage domain

MS19944V2

1. The register interface is located in the CORE voltage domain. The watchdog function is located in the VDD
voltage domain, still functional in Stop and Standby modes.

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Independent watchdog (IWDG) RM0360

When the independent watchdog is started by writing the value 0x0000 CCCC in the IWDG
key register (IWDG_KR), the counter starts counting down from the reset value of 0xFFF.
When it reaches the end of count value (0x000) a reset signal is generated (IWDG reset).
Whenever the key value 0x0000 AAAA is written in the IWDG key register (IWDG_KR), the
IWDG_RLR value is reloaded in the counter and the watchdog reset is prevented.
Once running, the IWDG cannot be stopped.

19.3.2 Window option

The IWDG can also work as a window watchdog by setting the appropriate window in the
IWDG window register (IWDG_WINR).
If the reload operation is performed while the counter is greater than the value stored in the
IWDG window register (IWDG_WINR), then a reset is provided.
The default value of the IWDG window register (IWDG_WINR) is 0x0000 0FFF, so if it is not
updated, the window option is disabled.
As soon as the window value is changed, a reload operation is performed in order to reset
the downcounter to the IWDG reload register (IWDG_RLR) value and ease the cycle
number calculation to generate the next reload.

Configuring the IWDG when the window option is enabled

1. Enable the IWDG by writing 0x0000 CCCC in the IWDG key register (IWDG_KR).
2. Enable register access by writing 0x0000 5555 in the IWDG key register (IWDG_KR).
3. Write the IWDG prescaler by programming IWDG prescaler register (IWDG_PR) from
0 to 7.
4. Write the IWDG reload register (IWDG_RLR).
5. Wait for the registers to be updated (IWDG_SR = 0x0000 0000).
6. Write to the IWDG window register (IWDG_WINR). This automatically refreshes the
counter value in the IWDG reload register (IWDG_RLR).
Note: Writing the window value allows the counter value to be refreshed by the RLR when IWDG
status register (IWDG_SR) is set to 0x0000 0000.
For code example refer to the Appendix section A.12.2: IWDG configuration with window.

Configuring the IWDG when the window option is disabled

When the window option it is not used, the IWDG can be configured as follows:
1. Enable the IWDG by writing 0x0000 CCCC in the IWDG key register (IWDG_KR).
2. Enable register access by writing 0x0000 5555 in the IWDG key register (IWDG_KR).
3. Write the prescaler by programming the IWDG prescaler register (IWDG_PR) from 0 to
7.
4. Write the IWDG reload register (IWDG_RLR).
5. Wait for the registers to be updated (IWDG_SR = 0x0000 0000).
6. Refresh the counter value with IWDG_RLR (IWDG_KR = 0x0000 AAAA).
For code example refer to the Appendix section A.12.1: IWDG configuration.

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RM0360 Independent watchdog (IWDG)

19.3.3 Hardware watchdog

If the “Hardware watchdog” feature is enabled through the device option bits, the watchdog
is automatically enabled at power-on, and generates a reset unless the IWDG key register
(IWDG_KR) is written by the software before the counter reaches end of count or if the
downcounter is reloaded inside the window.

19.3.4 Register access protection

Write access to IWDG prescaler register (IWDG_PR), IWDG reload register (IWDG_RLR)
and IWDG window register (IWDG_WINR) is protected. To modify them, the user must first
write the code 0x0000 5555 in the IWDG key register (IWDG_KR). A write access to this
register with a different value breaks the sequence and register access is protected again.
This is the case of the reload operation (writing 0x0000 AAAA).
A status register is available to indicate that an update of the prescaler or of the
downcounter reload value or of the window value is ongoing.
For code example refer to the Appendix section A.12.1: IWDG configuration.

19.3.5 Debug mode

When the device enters Debug mode (core halted), the IWDG counter either continues to
work normally or stops, depending on the configuration of the corresponding bit in
DBGMCU freeze register.

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477
Independent watchdog (IWDG) RM0360

19.4 IWDG registers

Refer to Section 1.2 on page 33 for a list of abbreviations used in register descriptions.
The peripheral registers can be accessed by half-words (16-bit) or words (32-bit).

19.4.1 IWDG key register (IWDG_KR)

Address offset: 0x00
Reset value: 0x0000 0000 (reset by Standby mode)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
KEY[15:0]
w w w w w w w w w w w w w w w w

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 KEY[15:0]: Key value (write only, read 0x0000)
These bits must be written by software at regular intervals with the key value 0xAAAA,
otherwise the watchdog generates a reset when the counter reaches 0.
Writing the key value 0x5555 to enable access to the IWDG_PR, IWDG_RLR and
IWDG_WINR registers (see Section 19.3.4: Register access protection)
Writing the key value 0xCCCC starts the watchdog (except if the hardware watchdog option
is selected)

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RM0360 Independent watchdog (IWDG)

19.4.2 IWDG prescaler register (IWDG_PR)

Address offset: 0x04
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. PR[2:0]

rw rw rw

Bits 31:3 Reserved, must be kept at reset value.

Bits 2:0 PR[2:0]: Prescaler divider
These bits are write access protected see Section 19.3.4: Register access protection. They
are written by software to select the prescaler divider feeding the counter clock. PVU bit of
the IWDG status register (IWDG_SR) must be reset in order to be able to change the
prescaler divider.
000: divider /4
001: divider /8
010: divider /16
011: divider /32
100: divider /64
101: divider /128
110: divider /256
111: divider /256
Note: Reading this register returns the prescaler value from the VDD voltage domain. This
value may not be up to date/valid if a write operation to this register is ongoing. For this
reason the value read from this register is valid only when the PVU bit in the IWDG
status register (IWDG_SR) is reset.

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Independent watchdog (IWDG) RM0360

19.4.3 IWDG reload register (IWDG_RLR)

Address offset: 0x08
Reset value: 0x0000 0FFF (reset by Standby mode)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. RL[11:0]

rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:12 Reserved, must be kept at reset value.

Bits 11:0 RL[11:0]: Watchdog counter reload value
These bits are write access protected see Register access protection. They are written by
software to define the value to be loaded in the watchdog counter each time the value
0xAAAA is written in the IWDG key register (IWDG_KR). The watchdog counter counts
down from this value. The timeout period is a function of this value and the clock prescaler.
Refer to the datasheet for the timeout information.
The RVU bit in the IWDG status register (IWDG_SR) must be reset to be able to change the
reload value.
Note: Reading this register returns the reload value from the VDD voltage domain. This value
may not be up to date/valid if a write operation to this register is ongoing on it. For this
reason the value read from this register is valid only when the RVU bit in the IWDG
status register (IWDG_SR) is reset.

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RM0360 Independent watchdog (IWDG)

19.4.4 IWDG status register (IWDG_SR)

Address offset: 0x0C
Reset value: 0x0000 0000 (not reset by Standby mode)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. WVU RVU PVU

r r r

Bits 31:3 Reserved, must be kept at reset value.

Bit 2 WVU: Watchdog counter window value update
This bit is set by hardware to indicate that an update of the window value is ongoing. It is
reset by hardware when the reload value update operation is completed in the VDD voltage
domain (takes up to five RC 40 kHz cycles).
Window value can be updated only when WVU bit is reset.
Bit 1 RVU: Watchdog counter reload value update
This bit is set by hardware to indicate that an update of the reload value is ongoing. It is reset
by hardware when the reload value update operation is completed in the VDD voltage domain
(takes up to five RC 40 kHz cycles).
Reload value can be updated only when RVU bit is reset.
Bit 0 PVU: Watchdog prescaler value update
This bit is set by hardware to indicate that an update of the prescaler value is ongoing. It is
reset by hardware when the prescaler update operation is completed in the VDD voltage
domain (takes up to five RC 40 kHz cycles).
Prescaler value can be updated only when PVU bit is reset.

Note: If several reload, prescaler, or window values are used by the application, it is mandatory to
wait until RVU bit is reset before changing the reload value, to wait until PVU bit is reset
before changing the prescaler value, and to wait until WVU bit is reset before changing the
window value. However, after updating the prescaler and/or the reload/window value it is not
necessary to wait until RVU or PVU or WVU is reset before continuing code execution
except in case of low-power mode entry.

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Independent watchdog (IWDG) RM0360

19.4.5 IWDG window register (IWDG_WINR)

Address offset: 0x10
Reset value: 0x0000 0FFF (reset by Standby mode)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. WIN[11:0]

rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:12 Reserved, must be kept at reset value.

Bits 11:0 WIN[11:0]: Watchdog counter window value
These bits are write access protected, see Section 19.3.4, they contain the high limit of the
window value to be compared with the downcounter.
To prevent a reset, the downcounter must be reloaded when its value is lower than the
window register value and greater than 0x0
The WVU bit in the IWDG status register (IWDG_SR) must be reset in order to be able to
change the reload value.
Note: Reading this register returns the reload value from the VDD voltage domain. This value
may not be valid if a write operation to this register is ongoing. For this reason the value
read from this register is valid only when the WVU bit in the IWDG status register
(IWDG_SR) is reset.

476/775 RM0360 Rev 5

 0x10
0x08
0x04
0x00

0x0C
Offset
19.4.6
RM0360

name

IWDG_SR
IWDG_PR
IWDG_KR
Register

Reset value
Reset value
Reset value
Reset value
Reset value

IWDG_RLR

IWDG_WINR
Res. Res. Res. Res. Res. 31
Res. Res. Res. Res. Res. 30
Res. Res. Res. Res. Res. 29
Res. Res. Res. Res. Res. 28
Res. Res. Res. Res. Res. 27
Res. Res. Res. Res. Res. 26
Res. Res. Res. Res. Res.
IWDG register map

25
Res. Res. Res. Res. Res. 24
Res. Res. Res. Res. Res. 23
Res. Res. Res. Res. Res. 22
Res. Res. Res. Res. Res. 21
Res. Res. Res. Res. Res. 20
Res. Res. Res. Res. Res. 19
Res. Res. Res. Res. Res. 18
Res. Res. Res. Res. Res.

RM0360 Rev 5
17
Res. Res. Res. Res. Res. 16
0

Res. Res. Res. Res. 15

0

Res. Res. Res. Res. 14

0

Res. Res. Res. Res. 13

0

Res. Res. Res. Res. 12

1
1
0

Res. Res. 11
Table 59. IWDG register map and reset values

1
1
0

Res. Res. 10
The following table gives the IWDG register map and reset values.

1
1
0

Res. Res. 9
Refer to Section 2.2 on page 37 for the register boundary addresses.
1
1
0

Res. Res. 8
1
1
0

Res. Res. 7
KEY[15:0]

1
1
0

Res. Res. 6
1
1
0

Res. Res. 5
RL[11:0]

WIN[11:0]

1
1
0

Res. Res. 4
1
1
0

Res. Res. 3
1
1
0

0
0

WVU 2
1
1
0

0
0

RVU 1
PR[2:0]

1
1
0

0
0

PVU
Independent watchdog (IWDG)

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System window watchdog (WWDG) RM0360

20 System window watchdog (WWDG)

20.1 Introduction
The system window watchdog (WWDG) is used to detect the occurrence of a software fault,
usually generated by external interference or by unforeseen logical conditions, which
causes the application program to abandon its normal sequence.
The watchdog circuit generates an MCU reset on expiry of a programmed time period,
unless the program refreshes the contents of the down-counter before the T6 bit is cleared.
An MCU reset is also generated if the 7-bit down-counter value (in the control register) is
refreshed before the down-counter reaches the window register value. This implies that the
counter must be refreshed in a limited window.
The WWDG clock is prescaled from the APB clock and has a configurable time-window that
can be programmed to detect abnormally late or early application behavior.
The WWDG is best suited for applications requiring the watchdog to react within an
accurate timing window.

20.2 WWDG main features

• Programmable free-running down-counter
• Conditional reset
– Reset (if watchdog activated) when the down-counter value becomes lower than
0x40
– Reset (if watchdog activated) if the down-counter is reloaded outside the window
(see Figure 196)
• Early wake-up interrupt (EWI): triggered (if enabled and the watchdog activated) when
the down-counter is equal to 0x40

20.3 WWDG functional description

If the watchdog is activated (the WDGA bit is set in the WWDG_CR register), and when the
7-bit down-counter (T[6:0] bits) is decremented from 0x40 to 0x3F (T6 becomes cleared), it
initiates a reset. If the software reloads the counter while the counter is greater than the
value stored in the window register, then a reset is generated.
The application program must write in the WWDG_CR register at regular intervals during
normal operation to prevent an MCU reset. This operation can take place only when the
counter value is lower than or equal to the window register value, and higher than 0x3F. The
value to be stored in the WWDG_CR register must be between 0xFF and 0xC0.
Refer to Figure 195 for the WWDG block diagram.

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RM0360 System window watchdog (WWDG)

20.3.1 WWDG block diagram

Figure 195. Watchdog block diagram

Register interface CMP = 1 when WWDG

T[6:0] > W[6:0]
W[6:0]
APB bus

WWDG_CFR

CMP
wwdg_out_rst

WWDG_SR Write to WDGA

WWDG_CR
T6
readback

Logic
= 0x40 ?
WWDG_CR

T[6:0]
EWI wwdg_it
preload
cnt_out EWIF

7-bit downcounter (CNT)

pclk ÷ 4096 ÷ 2WDGTB

MS47214V2

20.3.2 Enabling the watchdog

The watchdog is always disabled after a reset. It is enabled by setting the WDGA bit in the
WWDG_CR register, then it cannot be disabled again except by a reset.

20.3.3 Controlling the down-counter

This down-counter is free-running, counting down even if the watchdog is disabled. When
the watchdog is enabled, the T6 bit must be set to prevent generating an immediate reset.
The T[5:0] bits contain the number of increments that represent the time delay before the
watchdog produces a reset. The timing varies between a minimum and a maximum value,
due to the unknown status of the prescaler when writing to the WWDG_CR register (see
Figure 196). The WWDG configuration register (WWDG_CFR) contains the high limit of the
window: to prevent a reset, the down-counter must be reloaded when its value is lower than
or equal to the window register value, and greater than 0x3F. Figure 196 describes the
window watchdog process.
Note: The T6 bit can be used to generate a software reset (the WDGA bit is set and the T6 bit is
cleared).

20.3.4 How to program the watchdog timeout

Use the formula in Figure 196 to calculate the WWDG timeout.

Warning: When writing to the WWDG_CR register, always write 1 in the

T6 bit to avoid generating an immediate reset.

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System window watchdog (WWDG) RM0360

Figure 196. Window watchdog timing diagram

CNT DownCounter
Refresh not allowed Refresh allowed

T[6:0]

W[6:0]

0x3F
Time
Tpclk x 4096 x 2WDGTB
0x41
0x40
0x3F

wwdg_ewit

EWIF = 0
wwdg_rst

T6 bit

MS47266V1

The formula to calculate the timeout value is given by:

WDGTB[1:0]
t WWDG = t PCLK × 4096 × 2 × ( T [ 5:0 ] + 1 ) ( ms )

where:
tWWDG: WWDG timeout
tPCLK: APB clock period measured in ms
4096: value corresponding to internal divider
As an example, if APB frequency is 48 MHz, WDGTB[1:0] is set to 3 and T[5:0] is set to 63:
3
t WWDG = ( 1 ⁄ 48000 ) × 4096 × 2 × ( 63 + 1 ) = 43.69ms

Refer to the datasheet for the minimum and maximum values of tWWDG.

20.3.5 Debug mode

When the device enters debug mode (processor halted), the WWDG counter either
continues to work normally or stops, depending on the configuration bit in DBG module. For
more details, refer to Section 26.9.2: Debug support for timers, watchdog and I2C.

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RM0360 System window watchdog (WWDG)

20.4 WWDG interrupts

The early wake-up interrupt (EWI) can be used if specific safety operations or data logging
must be performed before the reset is generated. To enable the early wake-up interrupt, the
application must:
• Write EWIF bit of WWDG_SR register to 0, to clear unwanted pending interrupt
• Write EWI bit of WWDG_CFR register to 1, to enable interrupt
When the down-counter reaches the value 0x40, a watchdog interrupt is generated, and the
corresponding interrupt service routine (ISR) can be used to trigger specific actions (such as
communications or data logging), before resetting the device.
In some applications, the EWI interrupt can be used to manage a software system check
and/or system recovery/graceful degradation, without generating a WWDG reset. In this
case the corresponding ISR must reload the WWDG counter to avoid the WWDG reset,
then trigger the required actions.
The watchdog interrupt is cleared by writing '0' to the EWIF bit in the WWDG_SR register.
Note: When the watchdog interrupt cannot be served (for example due to a system lock in a
higher priority task), the WWDG reset is eventually generated.

20.5 WWDG registers

Refer to Section 1.2 on page 33 for a list of abbreviations used in register descriptions.
The peripheral registers can be accessed by halfwords (16-bit) or words (32-bit).

20.5.1 WWDG control register (WWDG_CR)

Address offset: 0x000
Reset value: 0x0000 007F

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. WDGA T[6:0]

rs rw rw rw rw rw rw rw

Bits 31:8 Reserved, must be kept at reset value.

Bit 7 WDGA: Activation bit
This bit is set by software and only cleared by hardware after a reset. When WDGA = 1, the
watchdog can generate a reset.
0: Watchdog disabled
1: Watchdog enabled
Bits 6:0 T[6:0]: 7-bit counter (MSB to LSB)
These bits contain the value of the watchdog counter, decremented every
(4096 x 2WDGTB[1:0]) PCLK cycles. A reset is produced when it is decremented from 0x40 to
0x3F (T6 becomes cleared).

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20.5.2 WWDG configuration register (WWDG_CFR)

Address offset: 0x004
Reset value: 0x0000 007F

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. EWI WDGTB[1:0] W[6:0]

rs rw rw rw rw rw rw rw rw rw

Bits 31:10 Reserved, must be kept at reset value.

Bit 9 EWI: Early wake-up interrupt enable
Set by software and cleared by hardware after a reset. When set, an interrupt occurs
whenever the counter reaches the value 0x40.
Bits 8:7 WDGTB[1:0]: Timer base
The time base of the prescaler can be modified as follows:
00: CK counter clock (PCLK div 4096) div 1
01: CK counter clock (PCLK div 4096) div 2
10: CK counter clock (PCLK div 4096) div 4
11: CK counter clock (PCLK div 4096) div 8
Bits 6:0 W[6:0]: 7-bit window value
These bits contain the window value to be compared with the down-counter.

20.5.3 WWDG status register (WWDG_SR)

Address offset: 0x008
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. EWIF
rc_w0

Bits 31:1 Reserved, must be kept at reset value.

Bit 0 EWIF: Early wake-up interrupt flag
This bit is set by hardware when the counter has reached the value 0x40. It must be cleared
by software by writing 0. Writing 1 has no effect. This bit is also set if the interrupt is not
enabled.

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0x004
0x000
Offset
20.5.4
RM0360

name
Register

Reset value
Reset value
Reset value

WWDG_SR
WWDG_CR

WWDG_CFR
Res. Res. Res. 31
Res. Res. Res. 30
Res. Res. Res. 29
Res. Res. Res. 28
Res. Res. Res. 27
Res. Res. Res. 26
Res. Res. Res. 25
WWDG register map

Res. Res. Res. 24

Res. Res. Res. 23
Res. Res. Res. 22
Res. Res. Res. 21
Res. Res. Res. 20
Res. Res. Res. 19
Res. Res. Res. 18
Res. Res. Res.

RM0360 Rev 5
17
Res. Res. Res. 16
Res. Res. Res. 15
Res. Res. Res. 14
Res. Res. Res. 13
Res. Res. Res. 12
Res. Res. Res. 11
Table 60. WWDG register map and reset values

Res. Res. Res. 10

0

Res. EWI Res. 9

The following table gives the WWDG register map and reset values.

Refer to Section 2.2 on page 37 for the register boundary addresses.

0

Res. WDGTB1 Res. 8

0
0

Res. WDGTB0 WDGA 7

1
1

Res. 6
1
1

Res. 5
1
1

Res. 4
1
1

Res. 3
T[6:0]

W[6:0]

1
1

Res. 2
1
1

Res. 1
0
1
1

EWIF 0

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21 Real-time clock (RTC)

21.1 Introduction
The RTC provides an automatic wake-up to manage all low-power modes.
The real-time clock (RTC) is an independent BCD timer/counter. The RTC provides a time-
of-day clock/calendar with programmable alarm interrupt.
The RTC includes also a periodic programmable wake-up flag with interrupt capability.
Two 32-bit registers contain the seconds, minutes, hours (12- or 24-hour format), day (day
of week), date (day of month), month, and year, expressed in binary coded decimal format
(BCD). The sub-seconds value is also available in binary format.
Compensations for 28-, 29- (leap year), 30-, and 31-day months are performed
automatically. Daylight saving time compensation can also be performed.
Additional 32-bit registers contain the programmable alarm subseconds, seconds, minutes,
hours, day, and date.
A digital calibration feature is available to compensate for any deviation in crystal oscillator
accuracy.
After RTC domain reset, all RTC registers are protected against possible parasitic write
accesses.
As long as the supply voltage remains in the operating range, the RTC never stops,
regardless of the device status (Run mode, low-power mode or under reset).

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21.2 RTC main features

The RTC unit main features are the following (see Figure 197: RTC block diagram in
STM32F030x4/6, STM32F070x6 and STM32F030x8 devicesand Figure 198: RTC block
diagram for STM32F070xB and STM32F030xC devices):
• Calendar with subseconds, seconds, minutes, hours (12 or 24 format), day (day of
week), date (day of month), month, and year.
• Daylight saving compensation programmable by software.
• Programmable alarm with interrupt function. The alarm can be triggered by any
combination of the calendar fields.
• Automatic wake-up unit generating a periodic flag that triggers an automatic wake-up
interrupt.
• Reference clock detection: a more precise second source clock (50 or 60 Hz) can be
used to enhance the calendar precision.
• Accurate synchronization with an external clock using the subsecond shift feature.
• Digital calibration circuit (periodic counter correction): 0.95 ppm accuracy, obtained in a
calibration window of several seconds
• Time-stamp function for event saving
• Tamper detection event with configurable filter and internal pull-up
• Maskable interrupts/events:
– Alarm A
– Wake-up interrupt
– Time-stamp
– Tamper detection

21.3 RTC implementation

Table 61. STM32F0x0 RTC implementation(1)
STM32F030x4,
STM32F030x6 STM32F070xB
RTC Features
STM32F070x6 STM32F030xC
STM32F030x8

Periodic wake-up timer - X

RTC_TAMP1 X X
RTC_TAMP2 X X
RTC_TAMP3 - -
Alarm A X X
1. X = supported, ‘-’= not supported.

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21.4 RTC functional description

21.4.1 RTC block diagram

Figure 197. RTC block diagram in STM32F030x4/6,

STM32F070x6 and STM32F030x8 devices

RTC_TAMP2 RTC tamper

TAMPxF
RTC_TAMP1 control registers

RTC_TS Time stamp TSF

registers
RTC_REFIN

LSE (32.768 Hz)

HSE/32
LSI
RTCCLK

ck_apre ck_spre
RTC_CALR RTC_PRER (default 256 Hz) RTC_PRER (default 1 Hz)
Smooth Asynchronous Synchronous
calibration 7-bit prescaler 15-bit prescaler
(default = 128) (default = 256) Calendar
Shadow registers
Shadow register RTC_TR,
RTC_SSR RTC_DR

RTC_CALIB
Output RTC_OUT
control
RTC_ALARM

Alarm A
= ALRAF
RTC_ALRMAR
RTC_ALRMASSR
MS32633V1

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Figure 198. RTC block diagram for STM32F070xB

and STM32F030xC devices

RTC_TAMP2 RTC tamper

control TAMPxF
RTC_TAMP1
registers

RTC_TS Time stamp

TSF
registers
RTC_REFIN

LSE (32.768 Hz)

HSE/32
LSI
RTCCLK

ck_apre ck_spre
RTC_CALR RTC_PRER (default 256 Hz) RTC_PRER (default 1 Hz)
Smooth Asynchronous Synchronous
calibration 7-bit prescaler 15-bit prescaler
(default = 128) (default = 256) Calendar
Shadow registers
Shadow register RTC_TR,
RTC_SSR RTC_DR
WUCKSEL[1:0]
Prescaler
2, 4, 8, 16

RTC_CALIB
Output
RTC_OUT
RTC_ALARM control

RTC_WUTR
16-bit wakeup WUTF
auto reload timer

OSEL[1:0]

Alarm A
= ALRAF
RTC_ALRMAR
RTC_ALRMASSR

MSv36433V2

The RTC includes:

• One alarm
• Two tamper events from I/Os
• One timestamp event from I/O
• Tamper event detection can generate a timestamp event
• Output functions: RTC_OUT which selects one of the following two outputs:
– RTC_CALIB: 512 Hz or 1Hz clock output (with an LSE frequency of 32.768 kHz).
This output is enabled by setting the COE bit in the RTC_CR register.
– RTC_ALARM: Alarm A. This output is selected by configuring the OSEL[1:0] bits
in the RTC_CR register.
• Input functions:
– RTC_TS: timestamp event
– RTC_TAMP1: tamper1 event detection
– RTC_TAMP2: tamper2 event detection
– RTC_REFIN: 50 or 60 Hz reference clock input

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21.4.2 GPIOs controlled by the RTC

RTC_OUT, RTC_TS and RTC_TAMP1 are mapped on the same pin (PC13). PC13 pin
configuration is controlled by the RTC, whatever the PC13 GPIO configuration, except for
the RTC_ALARM output open-drain mode. In this particular case, the GPIO must be
configured as input. The RTC functions mapped on PC13 are available in all low-power
modes and in VBAT mode.
The selection of the RTC_ALARM output is performed through the RTC_TAFCR register as
follows: the PC13VALUE bit is used to select whether the RTC_ALARM output is configured
in push-pull or open drain mode.
When PC13 is not used as RTC function, it can be forced in output push-pull mode by
setting the PC13MODE bit in the RTC_TAFCR. The output data value is then given by the
PC13VALUE bit. In this case, PC13 output push-pull state and data are preserved in
Standby mode.
The output mechanism follows the priority order shown in Table 62.
When PC14 and PC15 are not used as LSE oscillator, they can be forced in output push-pull
mode by setting the PC14MODE and PC15MODE bits in the RTC_TAFCR register
respectively. The output data values are then given by PC14VALUE and PC15VALUE. In
this case, the PC14 and PC15 output push-pull states and data values are preserved in
Standby mode.
The output mechanism follows the priority order shown in Table 63 and Table 64.

Table 62. RTC pin PC13 configuration(1)

Pin RTC_ALARM RTC_CALIB RTC_TAMP1 RTC_TS
PC13MODE PC13VALUE
configuration output output input input
bit bit
and function enabled enabled enabled enabled

RTC_ALARM
1 Don’t care Don’t care Don’t care Don’t care 0
output OD
RTC_ALARM
1 Don’t care Don’t care Don’t care Don’t care 1
output PP
RTC_CALIB
0 1 Don’t care Don’t care Don’t care Don’t care
output PP
RTC_TAMP1
0 0 1 0 Don’t care Don’t care
input floating
RTC_TS and
RTC_TAMP1 0 0 1 1 Don’t care Don’t care
input floating
RTC_TS input
0 0 0 1 Don’t care Don’t care
floating
Output PP PC13 output
0 0 0 0 1
forced data value
Wake-up pin
or Standard 0 0 0 0 0 Don’t care
GPIO
1. OD: open drain; PP: push-pull.

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Table 63. LSE pin PC14 configuration (1)

Pin configuration and LSEON bit in LSEBYP bit in PC14MODE PC14VALUE
function RCC_BDCR register RCC_BDCR register bit bit

LSE oscillator 1 0 Don’t care Don’t care

LSE bypass 1 1 Don’t care Don’t care
PC14 output data
Output PP forced 0 Don’t care 1
value
Standard GPIO 0 Don’t care 0 Don’t care
1. OD: open drain; PP: push-pull.

Table 64. LSE pin PC15 configuration (1)

Pin configuration and LSEON bit in LSEBYP bit in PC15MODE PC15VALUE
function RCC_BDCR register RCC_BDCR register bit bit

LSE oscillator 1 0 Don’t care Don’t care

1 1 PC15 output data
Output PP forced 1
0 Don’t care value

Standard GPIO 0 Don’t care 0 Don’t care

1. OD: open drain; PP: push-pull.

21.4.3 Clock and prescalers

The RTC clock source (RTCCLK) is selected through the clock controller among the LSE
clock, the LSI oscillator clock, and the HSE clock. For more information on the RTC clock
source configuration, refer to .
A programmable prescaler stage generates a 1 Hz clock which is used to update the
calendar. To minimize power consumption, the prescaler is split into 2 programmable
prescalers (see Figure 197: RTC block diagram in STM32F030x4/6, STM32F070x6 and
STM32F030x8 devices):
• A 7-bit asynchronous prescaler configured through the PREDIV_A bits of the
RTC_PRER register.
• A 15-bit synchronous prescaler configured through the PREDIV_S bits of the
RTC_PRER register.
Note: When both prescalers are used, it is recommended to configure the asynchronous prescaler
to a high value to minimize consumption.
The asynchronous prescaler division factor is set to 128, and the synchronous division
factor to 256, to obtain an internal clock frequency of 1 Hz (ck_spre) with an LSE frequency
of 32.768 kHz.
The minimum division factor is 1 and the maximum division factor is 222.
This corresponds to a maximum input frequency of around 4 MHz.

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fck_apre is given by the following formula:

f RTCCLK
f CK_APRE = --------------------------------------
-
PREDIV_A + 1

The ck_apre clock is used to clock the binary RTC_SSR subseconds downcounter. When it
reaches 0, RTC_SSR is reloaded with the content of PREDIV_S.
fck_spre is given by the following formula:
f RTCCLK
f CK_SPRE = -----------------------------------------------------------------------------------------------
( PREDIV_S + 1 ) × ( PREDIV_A + 1 )

The ck_spre clock can be used either to update the calendar or as timebase for the 16-bit
wake-up auto-reload timer. To obtain short timeout periods, the 16-bit wake-up auto-reload
timer can also run with the RTCCLK divided by the programmable 4-bit asynchronous
prescaler (see Section 21.4.6: Periodic auto-wake-up for details).

21.4.4 Real-time clock and calendar

The RTC calendar time and date registers are accessed through shadow registers which
are synchronized with PCLK (APB clock). They can also be accessed directly in order to
avoid waiting for the synchronization duration.
• RTC_SSR for the subseconds
• RTC_TR for the time
• RTC_DR for the date
Every RTCCLK period, the current calendar value is copied into the shadow registers, and
the RSF bit of RTC_ISR register is set (see Section 21.7.4: RTC initialization and status
register (RTC_ISR)). The copy is not performed in Stop and Standby mode. When exiting
these modes, the shadow registers are updated after up to 1 RTCCLK period.
When the application reads the calendar registers, it accesses the content of the shadow
registers. It is possible to make a direct access to the calendar registers by setting the
BYPSHAD control bit in the RTC_CR register. By default, this bit is cleared, and the user
accesses the shadow registers.
When reading the RTC_SSR, RTC_TR or RTC_DR registers in BYPSHAD=0 mode, the
frequency of the APB clock (fAPB) must be at least 7 times the frequency of the RTC clock
(fRTCCLK).
The shadow registers are reset by system reset.

21.4.5 Programmable alarm

The RTC unit provides programmable alarm: Alarm A.
The programmable alarm function is enabled through the ALRAE bit in the RTC_CR
register. The ALRAF is set to 1 if the calendar subseconds, seconds, minutes, hours, date
or day match the values programmed in the alarm registers RTC_ALRMASSR and
RTC_ALRMAR. Each calendar field can be independently selected through the MSKx bits
of the RTC_ALRMAR register, and through the MASKSSx bits of the RTC_ALRMASSR
register. The alarm interrupt is enabled through the ALRAIE bit in the RTC_CR register.

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Caution: If the seconds field is selected (MSK1 bit reset in RTC_ALRMAR), the synchronous
prescaler division factor set in the RTC_PRER register must be at least 3 to ensure correct
behavior.
Alarm A (if enabled by bits OSEL[1:0] in RTC_CR register) can be routed to the
RTC_ALARM output. RTC_ALARM output polarity can be configured through bit POL the
RTC_CR register.

21.4.6 Periodic auto-wake-up

The periodic wake-up flag is generated by a 16-bit programmable auto-reload down-
counter. The wake-up timer range can be extended to 17 bits.
The wake-up function is enabled through the WUTE bit in the RTC_CR register.
The wake-up timer clock input can be:
• RTC clock (RTCCLK) divided by 2, 4, 8, or 16.
When RTCCLK is LSE(32.768 kHz), this allows to configure the wake-up interrupt
period from 122 µs to 32 s, with a resolution down to 61 µs.
• ck_spre (usually 1 Hz internal clock)
When ck_spre frequency is 1Hz, this allows to achieve a wake-up time from 1 s to
around 36 hours with one-second resolution. This large programmable time range is
divided in 2 parts:
– from 1s to 18 hours when WUCKSEL [2:1] = 10
– and from around 18h to 36h when WUCKSEL[2:1] = 11. In this last case 216 is
added to the 16-bit counter current value.When the initialization sequence is
complete (see Programming the wake-up timer on page 493), the timer starts
counting down.When the wake-up function is enabled, the down-counting remains
active in low-power modes. In addition, when it reaches 0, the WUTF flag is set in
the RTC_ISR register, and the wake-up counter is automatically reloaded with its
reload value (RTC_WUTR register value).
The WUTF flag must then be cleared by software.
When the periodic wake-up interrupt is enabled by setting the WUTIE bit in the RTC_CR
register, it can exit the device from low-power modes.
The periodic wake-up flag can be routed to the RTC_ALARM output provided it has been
enabled through bits OSEL[1:0] of RTC_CR register. RTC_ALARM output polarity can be
configured through the POL bit in the RTC_CR register.
System reset, as well as low-power modes (Sleep, Stop and Standby) have no influence on
the wake-up timer.

21.4.7 RTC initialization and configuration

RTC register access
The RTC registers are 32-bit registers. The APB interface introduces 2 wait-states in RTC
register accesses except on read accesses to calendar shadow registers when
BYPSHAD=0.

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RTC register write protection

After system reset, the RTC registers are protected against parasitic write access by
clearing the DBP bit in the PWR_CR register (refer to the power control section). DBP bit
must be set in order to enable RTC registers write access.
After RTC domain reset, all the RTC registers are write-protected. Writing to the RTC
registers is enabled by writing a key into the Write Protection register, RTC_WPR.
The following steps are required to unlock the write protection on all the RTC registers
except for RTC_TAFCR and RTC_ISR[13:8].
1. Write ‘0xCA’ into the RTC_WPR register.
2. Write ‘0x53’ into the RTC_WPR register.
Writing a wrong key reactivates the write protection.
The protection mechanism is not affected by system reset.

Calendar initialization and configuration

To program the initial time and date calendar values, including the time format and the
prescaler configuration, the following sequence is required:
1. Set INIT bit to 1 in the RTC_ISR register to enter initialization mode. In this mode, the
calendar counter is stopped and its value can be updated.
2. Poll INITF bit of in the RTC_ISR register. The initialization phase mode is entered when
INITF is set to 1. It takes around 2 RTCCLK clock cycles (due to clock synchronization).
3. To generate a 1 Hz clock for the calendar counter, program both the prescaler factors in
RTC_PRER register.
4. Load the initial time and date values in the shadow registers (RTC_TR and RTC_DR),
and configure the time format (12 or 24 hours) through the FMT bit in the RTC_CR
register.
5. Exit the initialization mode by clearing the INIT bit. The actual calendar counter value is
then automatically loaded and the counting restarts after 4 RTCCLK clock cycles.
When the initialization sequence is complete, the calendar starts counting.
Note: After a system reset, the application can read the INITS flag in the RTC_ISR register to
check if the calendar has been initialized or not. If this flag equals 0, the calendar has not
been initialized since the year field is set at its RTC domain reset default value (0x00).
To read the calendar after initialization, the software must first check that the RSF flag is set
in the RTC_ISR register.
For code example refer to the Appendix section A.13.1: RTC calendar configuration.

Daylight saving time

The daylight saving time management is performed through bits SUB1H, ADD1H, and BKP
of the RTC_CR register.
Using SUB1H or ADD1H, the software can subtract or add one hour to the calendar in one
single operation without going through the initialization procedure.
In addition, the software can use the BKP bit to memorize this operation.

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Programming the alarm

A similar procedure must be followed to program or update the programmable alarms.
1. Clear ALRAE in RTC_CR to disable Alarm A.
2. Program the Alarm A registers (RTC_ALRMASSR/RTC_ALRMAR).
3. Set ALRAE in the RTC_CR register to enable Alarm A again.
Note: Each change of the RTC_CR register is taken into account after around 2 RTCCLK clock
cycles due to clock synchronization.
For code example refer to the Appendix section A.13.2: RTC alarm configuration.

Programming the wake-up timer

The following sequence is required to configure or change the wake-up timer auto-reload
value (WUT[15:0] in RTC_WUTR):
1. Clear WUTE in RTC_CR to disable the wake-up timer.
2. Poll WUTWF until it is set in RTC_ISR to make sure the access to wake-up auto-reload
counter and to WUCKSEL[2:0] bits is allowed. It takes around 2 RTCCLK clock cycles
(due to clock synchronization).
3. Program the wake-up auto-reload value WUT[15:0], and the wake-up clock selection
(WUCKSEL[2:0] bits in RTC_CR). Set WUTE in RTC_CR to enable the timer again.
The wake-up timer restarts down-counting. The WUTWF bit is cleared up to 2 RTCCLK
clock cycles after WUTE is cleared, due to clock synchronization.
For code example refer to the Appendix section A.13.3: RTC WUT configuration.

21.4.8 Reading the calendar

When BYPSHAD control bit is cleared in the RTC_CR register
To read the RTC calendar registers (RTC_SSR, RTC_TR and RTC_DR) properly, the APB
clock frequency (fPCLK) must be equal to or greater than seven times the RTC clock
frequency (fRTCCLK). This ensures a secure behavior of the synchronization mechanism.
If the APB clock frequency is less than seven times the RTC clock frequency, the software
must read the calendar time and date registers twice. If the second read of the RTC_TR
gives the same result as the first read, this ensures that the data is correct. Otherwise a third
read access must be done. In any case the APB clock frequency must never be lower than
the RTC clock frequency.
The RSF bit is set in RTC_ISR register each time the calendar registers are copied into the
RTC_SSR, RTC_TR and RTC_DR shadow registers. The copy is performed every
RTCCLK cycle. To ensure consistency between the 3 values, reading either RTC_SSR or
RTC_TR locks the values in the higher-order calendar shadow registers until RTC_DR is
read. In case the software makes read accesses to the calendar in a time interval smaller
than 1 RTCCLK period: RSF must be cleared by software after the first calendar read, and
then the software must wait until RSF is set before reading again the RTC_SSR, RTC_TR
and RTC_DR registers.
After waking up from low-power mode (Stop or Standby), RSF must be cleared by software.
The software must then wait until it is set again before reading the RTC_SSR, RTC_TR and
RTC_DR registers.
The RSF bit must be cleared after wake-up and not before entering low-power mode.

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After a system reset, the software must wait until RSF is set before reading the RTC_SSR,
RTC_TR and RTC_DR registers. Indeed, a system reset resets the shadow registers to
their default values.
After an initialization (refer to Calendar initialization and configuration on page 492): the
software must wait until RSF is set before reading the RTC_SSR, RTC_TR and RTC_DR
registers.
After synchronization (refer to Section 21.4.10: RTC synchronization): the software must
wait until RSF is set before reading the RTC_SSR, RTC_TR and RTC_DR registers.
For code example refer to the Appendix section A.13.4: RTC read calendar.

When the BYPSHAD control bit is set in the RTC_CR register (bypass shadow
registers)
Reading the calendar registers gives the values from the calendar counters directly, thus
eliminating the need to wait for the RSF bit to be set. This is especially useful after exiting
from low-power modes (STOP or Standby), since the shadow registers are not updated
during these modes.
When the BYPSHAD bit is set to 1, the results of the different registers might not be
coherent with each other if an RTCCLK edge occurs between two read accesses to the
registers. Additionally, the value of one of the registers may be incorrect if an RTCCLK edge
occurs during the read operation. The software must read all the registers twice, and then
compare the results to confirm that the data is coherent and correct. Alternatively, the
software can just compare the two results of the least-significant calendar register.
Note: While BYPSHAD=1, instructions which read the calendar registers require one extra APB
cycle to complete.

21.4.9 Resetting the RTC

The calendar shadow registers (RTC_SSR, RTC_TR and RTC_DR) and some bits of the
RTC status register (RTC_ISR) are reset to their default values by all available system reset
sources.
On the contrary, the following registers are reset to their default values by a RTC domain
reset and are not affected by a system reset: the RTC current calendar registers, the RTC
control register (RTC_CR), the prescaler register (RTC_PRER), the RTC calibration register
(RTC_CALR), the RTC shift register (RTC_SHIFTR), the RTC timestamp registers
(RTC_TSSSR, RTC_TSTR and RTC_TSDR), the RTC tamper and alternate function
configuration register (RTC_TAFCR), the wake-up timer register (RTC_WUTR), the Alarm A
registers (RTC_ALRMASSR/RTC_ALRMAR).
In addition, when it is clocked by the LSE, the RTC keeps on running under system reset if
the reset source is different from the RTC domain reset one (refer to the RTC clock section
of the Reset and clock controller for details on the list of RTC clock sources not affected by
system reset). When a RTC domain reset occurs, the RTC is stopped and all the RTC
registers are set to their reset values.

21.4.10 RTC synchronization

The RTC can be synchronized to a remote clock with a high degree of precision. After
reading the sub-second field (RTC_SSR or RTC_TSSSR), a calculation can be made of the
precise offset between the times being maintained by the remote clock and the RTC. The

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RTC can then be adjusted to eliminate this offset by “shifting” its clock by a fraction of a
second using RTC_SHIFTR.
RTC_SSR contains the value of the synchronous prescaler counter. This allows one to
calculate the exact time being maintained by the RTC down to a resolution of
1 / (PREDIV_S + 1) seconds. As a consequence, the resolution can be improved by
increasing the synchronous prescaler value (PREDIV_S[14:0]. The maximum resolution
allowed (30.52 μs with a 32768 Hz clock) is obtained with PREDIV_S set to 0x7FFF.
However, increasing PREDIV_S means that PREDIV_A must be decreased in order to
maintain the synchronous prescaler output at 1 Hz. In this way, the frequency of the
asynchronous prescaler output increases, which may increase the RTC dynamic
consumption.
The RTC can be finely adjusted using the RTC shift control register (RTC_SHIFTR). Writing
to RTC_SHIFTR can shift (either delay or advance) the clock by up to a second with a
resolution of 1 / (PREDIV_S + 1) seconds. The shift operation consists of adding the
SUBFS[14:0] value to the synchronous prescaler counter SS[15:0]: this will delay the clock.
If at the same time the ADD1S bit is set, this results in adding one second and at the same
time subtracting a fraction of second, so this will advance the clock.
Caution: Before initiating a shift operation, the user must check that SS[15] = 0 in order to ensure that
no overflow will occur.
As soon as a shift operation is initiated by a write to the RTC_SHIFTR register, the SHPF
flag is set by hardware to indicate that a shift operation is pending. This bit is cleared by
hardware as soon as the shift operation has completed.
Caution: This synchronization feature is not compatible with the reference clock detection feature:
firmware must not write to RTC_SHIFTR when REFCKON=1.

21.4.11 RTC reference clock detection

The update of the RTC calendar can be synchronized to a reference clock, RTC_REFIN,
which is usually the mains frequency (50 or 60 Hz). The precision of the RTC_REFIN
reference clock should be higher than the 32.768 kHz LSE clock. When the RTC_REFIN
detection is enabled (REFCKON bit of RTC_CR set to 1), the calendar is still clocked by the
LSE, and RTC_REFIN is used to compensate for the imprecision of the calendar update
frequency (1 Hz).
Each 1 Hz clock edge is compared to the nearest RTC_REFIN clock edge (if one is found
within a given time window). In most cases, the two clock edges are properly aligned. When
the 1 Hz clock becomes misaligned due to the imprecision of the LSE clock, the RTC shifts
the 1 Hz clock a bit so that future 1 Hz clock edges are aligned. Thanks to this mechanism,
the calendar becomes as precise as the reference clock.
The RTC detects if the reference clock source is present by using the 256 Hz clock
(ck_apre) generated from the 32.768 kHz quartz. The detection is performed during a time
window around each of the calendar updates (every 1 s). The window equals 7 ck_apre
periods when detecting the first reference clock edge. A smaller window of 3 ck_apre
periods is used for subsequent calendar updates.
Each time the reference clock is detected in the window, the synchronous prescaler which
outputs the ck_spre clock is forced to reload. This has no effect when the reference clock
and the 1 Hz clock are aligned because the prescaler is being reloaded at the same
moment. When the clocks are not aligned, the reload shifts future 1 Hz clock edges a little
for them to be aligned with the reference clock.

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If the reference clock halts (no reference clock edge occurred during the 3 ck_apre window),
the calendar is updated continuously based solely on the LSE clock. The RTC then waits for
the reference clock using a large 7 ck_apre period detection window centered on the
ck_spre edge.
When the RTC_REFIN detection is enabled, PREDIV_A and PREDIV_S must be set to their
default values:
• PREDIV_A = 0x007F
• PREVID_S = 0x00FF
Note: RTC_REFIN clock detection is not available in Standby mode.

21.4.12 RTC smooth digital calibration

The RTC frequency can be digitally calibrated with a resolution of about 0.954 ppm with a
range from -487.1 ppm to +488.5 ppm. The correction of the frequency is performed using
series of small adjustments (adding and/or subtracting individual RTCCLK pulses). These
adjustments are fairly well distributed so that the RTC is well calibrated even when observed
over short durations of time.
The smooth digital calibration is performed during a cycle of about 220 RTCCLK pulses, or
32 seconds when the input frequency is 32768 Hz. This cycle is maintained by a 20-bit
counter, cal_cnt[19:0], clocked by RTCCLK.
The smooth calibration register (RTC_CALR) specifies the number of RTCCLK clock cycles
to be masked during the 32-second cycle:
• Setting the bit CALM[0] to 1 causes exactly one pulse to be masked during the 32-
second cycle.
• Setting CALM[1] to 1 causes two additional cycles to be masked
• Setting CALM[2] to 1 causes four additional cycles to be masked
• and so on up to CALM[8] set to 1 which causes 256 clocks to be masked.
Note: CALM[8:0] (RTC_CALR) specifies the number of RTCCLK pulses to be masked during the
32-second cycle. Setting the bit CALM[0] to ‘1’ causes exactly one pulse to be masked
during the 32-second cycle at the moment when cal_cnt[19:0] is 0x80000; CALM[1]=1
causes two other cycles to be masked (when cal_cnt is 0x40000 and 0xC0000); CALM[2]=1
causes four other cycles to be masked (cal_cnt = 0x20000/0x60000/0xA0000/ 0xE0000);
and so on up to CALM[8]=1 which causes 256 clocks to be masked (cal_cnt = 0xXX800).
While CALM allows the RTC frequency to be reduced by up to 487.1 ppm with fine
resolution, the bit CALP can be used to increase the frequency by 488.5 ppm. Setting CALP
to ‘1’ effectively inserts an extra RTCCLK pulse every 211 RTCCLK cycles, which means
that 512 clocks are added during every 32-second cycle.
Using CALM together with CALP, an offset ranging from -511 to +512 RTCCLK cycles can
be added during the 32-second cycle, which translates to a calibration range of -487.1 ppm
to +488.5 ppm with a resolution of about 0.954 ppm.
The formula to calculate the effective calibrated frequency (FCAL) given the input frequency
(FRTCCLK) is as follows:
FCAL = FRTCCLK x [1 + (CALP x 512 - CALM) / (220 + CALM - CALP x 512)]

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Calibration when PREDIV_A<3

The CALP bit can not be set to 1 when the asynchronous prescaler value (PREDIV_A bits in
RTC_PRER register) is less than 3. If CALP was already set to 1 and PREDIV_A bits are
set to a value less than 3, CALP is ignored and the calibration operates as if CALP was
equal to 0.
To perform a calibration with PREDIV_A less than 3, the synchronous prescaler value
(PREDIV_S) should be reduced so that each second is accelerated by 8 RTCCLK clock
cycles, which is equivalent to adding 256 clock cycles every 32 seconds. As a result,
between 255 and 256 clock pulses (corresponding to a calibration range from 243.3 to
244.1 ppm) can effectively be added during each 32-second cycle using only the CALM bits.
With a nominal RTCCLK frequency of 32768 Hz, when PREDIV_A equals 1 (division factor
of 2), PREDIV_S should be set to 16379 rather than 16383 (4 less). The only other
interesting case is when PREDIV_A equals 0, PREDIV_S should be set to 32759 rather
than 32767 (8 less).
If PREDIV_S is reduced in this way, the formula given the effective frequency of the
calibrated input clock is as follows:
FCAL = FRTCCLK x [1 + (256 - CALM) / (220 + CALM - 256)]
In this case, CALM[7:0] equals 0x100 (the midpoint of the CALM range) is the correct
setting if RTCCLK is exactly 32768.00 Hz.

Verifying the RTC calibration

RTC precision is ensured by measuring the precise frequency of RTCCLK and calculating
the correct CALM value and CALP values. An optional 1 Hz output is provided to allow
applications to measure and verify the RTC precision.
Measuring the precise frequency of the RTC over a limited interval can result in a
measurement error of up to 2 RTCCLK clock cycles over the measurement period,
depending on how the digital calibration cycle is aligned with the measurement period.
However, this measurement error can be eliminated if the measurement period is the same
length as the calibration cycle period. In this case, the only error observed is the error due to
the resolution of the digital calibration.
• By default, the calibration cycle period is 32 seconds.
Using this mode and measuring the accuracy of the 1 Hz output over exactly 32 seconds
guarantees that the measure is within 0.477 ppm (0.5 RTCCLK cycles over 32 seconds, due
to the limitation of the calibration resolution).
• CALW16 bit of the RTC_CALR register can be set to 1 to force a 16- second calibration
cycle period.
In this case, the RTC precision can be measured during 16 seconds with a maximum error
of 0.954 ppm (0.5 RTCCLK cycles over 16 seconds). However, since the calibration
resolution is reduced, the long term RTC precision is also reduced to 0.954 ppm: CALM[0]
bit is stuck at 0 when CALW16 is set to 1.
• CALW8 bit of the RTC_CALR register can be set to 1 to force a 8- second calibration
cycle period.
In this case, the RTC precision can be measured during 8 seconds with a maximum error of
1.907 ppm (0.5 RTCCLK cycles over 8s). The long term RTC precision is also reduced to
1.907 ppm: CALM[1:0] bits are stuck at 00 when CALW8 is set to 1.

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Re-calibration on-the-fly
The calibration register (RTC_CALR) can be updated on-the-fly while RTC_ISR/INITF=0, by
using the follow process:
1. Poll the RTC_ISR/RECALPF (re-calibration pending flag).
2. If it is set to 0, write a new value to RTC_CALR, if necessary. RECALPF is then
automatically set to 1
3. Within three ck_apre cycles after the write operation to RTC_CALR, the new calibration
settings take effect.
For code example refer to the Appendix section A.13.5: RTC calibration.

21.4.13 Time-stamp function

Time-stamp is enabled by setting the TSE bit of RTC_CR register to 1.
The calendar is saved in the time-stamp registers (RTC_TSSSR, RTC_TSTR, RTC_TSDR)
when a time-stamp event is detected on the RTC_TS pin.
When a time-stamp event occurs, the time-stamp flag bit (TSF) in RTC_ISR register is set.
By setting the TSIE bit in the RTC_CR register, an interrupt is generated when a time-stamp
event occurs.
If a new time-stamp event is detected while the time-stamp flag (TSF) is already set, the
time-stamp overflow flag (TSOVF) flag is set and the time-stamp registers (RTC_TSTR and
RTC_TSDR) maintain the results of the previous event.
Note: TSF is set 2 ck_apre cycles after the time-stamp event occurs due to synchronization
process.
There is no delay in the setting of TSOVF. This means that if two time-stamp events are
close together, TSOVF can be seen as '1' while TSF is still '0'. As a consequence, it is
recommended to poll TSOVF only after TSF has been set.
Caution: If a time-stamp event occurs immediately after the TSF bit is supposed to be cleared, then
both TSF and TSOVF bits are set.To avoid masking a time-stamp event occurring at the
same moment, the application must not write ‘0’ into TSF bit unless it has already read it to
‘1’.
Optionally, a tamper event can cause a time-stamp to be recorded. See the description of
the TAMPTS control bit in Section 21.7.15: RTC tamper and alternate function configuration
register (RTC_TAFCR).

21.4.14 Tamper detection

The RTC_TAMPx input events can be configured either for edge detection, or for level
detection with filtering.
The tamper detection can be configured for the following purpose:
• generate an interrupt, capable to wake-up from Stop and Standby modes

Tamper detection initialization

Each input can be enabled by setting the corresponding TAMPxE bits to 1 in the
RTC_TAFCR register.

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Each RTC_TAMPx tamper detection input is associated with a flag TAMPxF in the RTC_ISR
register.
The TAMPxF flag is asserted after the tamper event on the pin, with the latency provided
below:
• 3 ck_apre cycles when TAMPFLT differs from 0x0 (Level detection with filtering)
• 3 ck_apre cycles when TAMPTS=1 (Timestamp on tamper event)
• No latency when TAMPFLT=0x0 (Edge detection) and TAMPTS=0
A new tamper occurring on the same pin during this period and as long as TAMPxF is set
cannot be detected.
By setting the TAMPIE bit in the RTC_TAFCR register, an interrupt is generated when a
tamper detection event occurs. .

Timestamp on tamper event

With TAMPTS set to ‘1’, any tamper event causes a timestamp to occur. In this case, either
the TSF bit or the TSOVF bit are set in RTC_ISR, in the same manner as if a normal
timestamp event occurs. The affected tamper flag register TAMPxF is set at the same time
that TSF or TSOVF is set.

Edge detection on tamper inputs

If the TAMPFLT bits are “00”, the RTC_TAMPx pins generate tamper detection events when
either a rising edge or a falling edge is observed depending on the corresponding
TAMPxTRG bit. The internal pull-up resistors on the RTC_TAMPx inputs are deactivated
when edge detection is selected.
Caution: To avoid losing tamper detection events, the signal used for edge detection is logically
ANDed with the corresponding TAMPxE bit in order to detect a tamper detection event in
case it occurs before the RTC_TAMPx pin is enabled.
• When TAMPxTRG = 0: if the RTC_TAMPx is already high before tamper detection is
enabled (TAMPxE bit set to 1), a tamper event is detected as soon as the RTC_TAMPx
input is enabled, even if there was no rising edge on the RTC_TAMPx input after
TAMPxE was set.
• When TAMPxTRG = 1: if the RTC_TAMPx is already low before tamper detection is
enabled, a tamper event is detected as soon as the RTC_TAMPx input is enabled
(even if there was no falling edge on the RTC_TAMPx input after TAMPxE was set.

Level detection with filtering on RTC_TAMPx inputs

Level detection with filtering is performed by setting TAMPFLT to a non-zero value. A tamper
detection event is generated when either 2, 4, or 8 (depending on TAMPFLT) consecutive
samples are observed at the level designated by the TAMPxTRG bits.
The RTC_TAMPx inputs are precharged through the I/O internal pull-up resistance before
its state is sampled, unless disabled by setting TAMPPUDIS to 1,The duration of the
precharge is determined by the TAMPPRCH bits, allowing for larger capacitances on the
RTC_TAMPx inputs.
The trade-off between tamper detection latency and power consumption through the pull-up
can be optimized by using TAMPFREQ to determine the frequency of the sampling for level
detection.
Note: Refer to the datasheets for the electrical characteristics of the pull-up resistors.

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For code example refer to the Appendix sections: A.13.6: RTC tamper and time stamp
configuration and A.13.7: RTC tamper and time stamp.

21.4.15 Calibration clock output

When the COE bit is set to 1 in the RTC_CR register, a reference clock is provided on the
RTC_CALIB device output.
If the COSEL bit in the RTC_CR register is reset and PREDIV_A = 0x7F, the RTC_CALIB
frequency is fRTCCLK/64. This corresponds to a calibration output at 512 Hz for an RTCCLK
frequency at 32.768 kHz. The RTC_CALIB duty cycle is irregular: there is a light jitter on
falling edges. It is therefore recommended to use rising edges.
When COSEL is set and “PREDIV_S+1” is a non-zero multiple of 256 (i.e: PREDIV_S[7:0] =
0xFF), the RTC_CALIB frequency is fRTCCLK/(256 * (PREDIV_A+1)). This corresponds to a
calibration output at 1 Hz for prescaler default values (PREDIV_A = Ox7F, PREDIV_S =
0xFF), with an RTCCLK frequency at 32.768 kHz. The 1 Hz output is affected when a shift
operation is on going and may toggle during the shift operation (SHPF=1).
Note: When COSEL bit is cleared, the RTC_CALIB output is the output of the 6th stage of the
asynchronous prescaler.
When COSEL bit is set, the RTC_CALIB output is the output of the 8th stage of the
synchronous prescaler.
For code example refer to the Appendix section A.13.8: RTC clock output.

21.4.16 Alarm output

The OSEL[1:0] control bits in the RTC_CR register are used to activate the alarm output
RTC_ALARM, and to select the function which is output. These functions reflect the
contents of the corresponding flags in the RTC_ISR register.
The polarity of the output is determined by the POL control bit in RTC_CR so that the
opposite of the selected flag bit is output when POL is set to 1.

Alarm output
The RTC_ALARM pin can be configured in output open drain or output push-pull using
RTC_TAFCR register.
Note: Once the RTC_ALARM output is enabled, it has priority over RTC_CALIB (COE bit is don't
care and must be kept cleared).

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21.5 RTC low-power modes

Table 65. Effect of low-power modes on RTC
Mode Description

No effect
Sleep
RTC interrupts cause the device to exit the Sleep mode.
The RTC remains active when the RTC clock source is LSE or LSI. RTC alarm, RTC
Stop tamper event, RTC timestamp event, and RTC wake-up cause the device to exit the Stop
mode.
The RTC remains active when the RTC clock source is LSE or LSI. RTC alarm, RTC
Standby tamper event, RTC timestamp event, and RTC wake-up cause the device to exit the
Standby mode.

21.6 RTC interrupts

All RTC interrupts are connected to the EXTI controller. Refer to .
To enable RTC interrupt(s), the following sequence is required:
1. Configure and enable the NVIC line(s) corresponding to the RTC event(s) in interrupt
mode and select the rising edge sensitivity.
2. Configure and enable the RTC IRQ channel in the NVIC.
3. Configure the RTC to generate RTC interrupt(s).

Table 66. Interrupt control bits

Enable Exit the Exit the Exit the
Interrupt event Event flag control Sleep Stop Standby
bit mode mode mode

Alarm A ALRAF ALRAIE Yes Yes(1) Yes(1)

RTC_TS input (timestamp) TSF TSIE Yes Yes(1) Yes(1)
RTC_TAMP1 input detection TAMP1F TAMPIE Yes Yes(1) Yes(1)
RTC_TAMP2 input detection TAMP2F TAMPIE Yes Yes(1) Yes(1)
1. Wake-up from STOP and Standby modes is possible only when the RTC clock source is LSE or LSI.

21.7 RTC registers

Refer to Section 1.2 on page 33 of the reference manual for a list of abbreviations used in
register descriptions.
The peripheral registers can be accessed by words (32-bit).

21.7.1 RTC time register (RTC_TR)

The RTC_TR is the calendar time shadow register. This register must be written in
initialization mode only. Refer to Calendar initialization and configuration on page 492 and
Reading the calendar on page 493.

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This register is write protected. The write access procedure is described in RTC register
write protection on page 492.
Address offset: 0x00
RTC domain reset value: 0x0000 0000
System reset: 0x0000 0000 when BYPSHAD = 0. Not affected when BYPSHAD = 1.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. PM HT[1:0] HU[3:0]

rw rw rw rw rw rw rw

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. MNT[2:0] MNU[3:0] Res. ST[2:0] SU[3:0]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:23 Reserved, must be kept at reset value.

Bit 22 PM: AM/PM notation
0: AM or 24-hour format
1: PM
Bits 21:20 HT[1:0]: Hour tens in BCD format
Bits 19:16 HU[3:0]: Hour units in BCD format
Bit 15 Reserved, must be kept at reset value.
Bits 14:12 MNT[2:0]: Minute tens in BCD format
Bits 11:8 MNU[3:0]: Minute units in BCD format
Bit 7 Reserved, must be kept at reset value.
Bits 6:4 ST[2:0]: Second tens in BCD format
Bits 3:0 SU[3:0]: Second units in BCD format

21.7.2 RTC date register (RTC_DR)

The RTC_DR is the calendar date shadow register. This register must be written in
initialization mode only. Refer to Calendar initialization and configuration on page 492 and
Reading the calendar on page 493.
This register is write protected. The write access procedure is described in RTC register
write protection on page 492.
Address offset: 0x04
RTC domain reset value: 0x0000 2101
System reset: 0x0000 2101 when BYPSHAD = 0. Not affected when BYPSHAD = 1.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. YT[3:0] YU[3:0]

rw rw rw rw rw rw rw rw

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDU[2:0] MT MU[3:0] Res. Res. DT[1:0] DU[3:0]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw

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Bits 31:24 Reserved, must be kept at reset value.

Bits 23:20 YT[3:0]: Year tens in BCD format
Bits 19:16 YU[3:0]: Year units in BCD format
Bits 15:13 WDU[2:0]: Week day units
000: forbidden
001: Monday
...
111: Sunday
Bit 12 MT: Month tens in BCD format
Bits 11:8 MU[3:0]: Month units in BCD format
Bits 7:6 Reserved, must be kept at reset value.
Bits 5:4 DT[1:0]: Date tens in BCD format
Bits 3:0 DU[3:0]: Date units in BCD format

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21.7.3 RTC control register (RTC_CR)

Address offset: 0x08
RTC domain reset value: 0x0000 0000
System reset: not affected

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. COE OSEL[1:0] POL COSEL BKP SUB1H ADD1H
rw rw rw rw rw rw w w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BYPS
TSIE WUTIE Res. ALRAIE TSE WUTE Res. ALRAE Res. FMT REFCKON TSEDGE WUCKSEL[2:0]
HAD
rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:24 Reserved, must be kept at reset value.

Bit 23 COE: Calibration output enable
This bit enables the RTC_CALIB output
0: Calibration output disabled
1: Calibration output enabled
Bits 22:21 OSEL[1:0]: Output selection
These bits are used to select the flag to be routed to RTC_ALARM output
00: Output disabled
01: Alarm A output enabled
10: Reserved
11: Wake-up output enabled
Bit 20 POL: Output polarity
This bit is used to configure the polarity of RTC_ALARM output
0: The pin is high when ALRAF/WUTF is asserted (depending on OSEL[1:0])
1: The pin is low when ALRAF/WUTF is asserted (depending on OSEL[1:0]).
Bit 19 COSEL: Calibration output selection
When COE=1, this bit selects which signal is output on RTC_CALIB.
0: Calibration output is 512 Hz (with default prescaler setting)
1: Calibration output is 1 Hz (with default prescaler setting)
These frequencies are valid for RTCCLK at 32.768 kHz and prescalers at their default values
(PREDIV_A=127 and PREDIV_S=255). Refer to Section 21.4.15: Calibration clock output
Bit 18 BKP: Backup
This bit can be written by the user to memorize whether the daylight saving time change has
been performed or not.
Bit 17 SUB1H: Subtract 1 hour (winter time change)
When this bit is set, 1 hour is subtracted to the calendar time if the current hour is not 0. This
bit is always read as 0.
Setting this bit has no effect when current hour is 0.
0: No effect
1: Subtracts 1 hour to the current time. This can be used for winter time change outside
initialization mode.

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Bit 16 ADD1H: Add 1 hour (summer time change)

When this bit is set, 1 hour is added to the calendar time. This bit is always read as 0.
0: No effect
1: Adds 1 hour to the current time. This can be used for summer time change outside
initialization mode.
Bit 15 TSIE: Time-stamp interrupt enable
0: Time-stamp Interrupt disable
1: Time-stamp Interrupt enable
Bit 14 WUTIE: Wake-up timer interrupt enable
0: Wake-up timer interrupt disabled
1: Wake-up timer interrupt enabled
Bit 13 Reserved, must be kept at reset value.
Bit 12 ALRAIE: Alarm A interrupt enable
0: Alarm A interrupt disabled
1: Alarm A interrupt enabled
Bit 11 TSE: timestamp enable
0: timestamp disable
1: timestamp enable
Bit 10 WUTE: Wake-up timer enable
0: Wake-up timer disabled
1: Wake-up timer enabled
Note: When the wake-up timer is disabled, wait for WUTWF=1 before enabling it again.
Bit 9 Reserved, must be kept at reset value.
Bit 8 ALRAE: Alarm A enable
0: Alarm A disabled
1: Alarm A enabled
Bit 7 Reserved, must be kept at reset value.
Bit 6 FMT: Hour format
0: 24 hour/day format
1: AM/PM hour format
Bit 5 BYPSHAD: Bypass the shadow registers
0: Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken from
the shadow registers, which are updated once every two RTCCLK cycles.
1: Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken
directly from the calendar counters.
Note: If the frequency of the APB clock is less than seven times the frequency of RTCCLK,
BYPSHAD must be set to ‘1’.

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Bit 4 REFCKON: RTC_REFIN reference clock detection enable (50 or 60 Hz)

0: RTC_REFIN detection disabled
1: RTC_REFIN detection enabled
Note: PREDIV_S must be 0x00FF.
Bit 3 TSEDGE: Time-stamp event active edge
0: RTC_TS input rising edge generates a time-stamp event
1: RTC_TS input falling edge generates a time-stamp event
TSE must be reset when TSEDGE is changed to avoid unwanted TSF setting.
Bits 2:0 WUCKSEL[2:0]: Wake-up clock selection
000: RTC/16 clock is selected
001: RTC/8 clock is selected
010: RTC/4 clock is selected
011: RTC/2 clock is selected
10x: ck_spre (usually 1 Hz) clock is selected
11x: ck_spre (usually 1 Hz) clock is selected and 216 is added to the WUT counter value
(see note below)

Note: Bits 7, 6 and 4 of this register can be written in initialization mode only (RTC_ISR/INITF = 1).
WUT = Wake-up unit counter value. WUT = (0x0000 to 0xFFFF) + 0x10000 added when
WUCKSEL[2:1 = 11].
Bits 2 to 0 of this register can be written only when RTC_CR WUTE bit = 0 and RTC_ISR
WUTWF bit = 1.
It is recommended not to change the hour during the calendar hour increment as it could
mask the incrementation of the calendar hour.
ADD1H and SUB1H changes are effective in the next second.
This register is write protected. The write access procedure is described in RTC register
write protection on page 492.
Caution: TSE must be reset when TSEDGE is changed to avoid spuriously setting of TSF.

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21.7.4 RTC initialization and status register (RTC_ISR)

This register is write protected (except for RTC_ISR[13:8] bits). The write access procedure
is described in RTC register write protection on page 492.
Address offset: 0x0C
RTC domain reset value: 0x0000 0007
System reset: not affected except INIT, INITF, and RSF bits which are cleared to ‘0’

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. RECALPF
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. TAMP2F TAMP1F TSOVF TSF WUTF Res. ALRAF INIT INITF RSF INITS SHPF WUTWF Res. ALRAWF
rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rw r rc_w0 r r r r

Bits 31:17 Reserved, must be kept at reset value.

Bit 16 RECALPF: Recalibration pending Flag
The RECALPF status flag is automatically set to ‘1’ when software writes to the RTC_CALR
register, indicating that the RTC_CALR register is blocked. When the new calibration settings
are taken into account, this bit returns to ‘0’. Refer to Re-calibration on-the-fly.
Bit 15 Reserved, must be kept at reset value.
Bit 14 TAMP2F: RTC_TAMP2 detection flag
This flag is set by hardware when a tamper detection event is detected on the RTC_TAMP2
input.
It is cleared by software writing 0
Bit 13 TAMP1F: RTC_TAMP1 detection flag
This flag is set by hardware when a tamper detection event is detected on the RTC_TAMP1
input.
It is cleared by software writing 0
Bit 12 TSOVF: Time-stamp overflow flag
This flag is set by hardware when a time-stamp event occurs while TSF is already set.
This flag is cleared by software by writing 0. It is recommended to check and then clear
TSOVF only after clearing the TSF bit. Otherwise, an overflow might not be noticed if a time-
stamp event occurs immediately before the TSF bit is cleared.
Bit 11 TSF: Time-stamp flag
This flag is set by hardware when a time-stamp event occurs.
This flag is cleared by software by writing 0.
Bit 10 WUTF: Wake-up timer flag
This flag is set by hardware when the wake-up auto-reload counter reaches 0.
This flag is cleared by software by writing 0.
This flag must be cleared by software at least 1.5 RTCCLK periods before WUTF is set to 1
again.
Bit 9 Reserved, must be kept at reset value.

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Bit 8 ALRAF: Alarm A flag

This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the
Alarm A register (RTC_ALRMAR).
This flag is cleared by software by writing 0.
Bit 7 INIT: Initialization mode
0: Free running mode
1: Initialization mode used to program time and date register (RTC_TR and RTC_DR), and
prescaler register (RTC_PRER). Counters are stopped and start counting from the new
value when INIT is reset.
Bit 6 INITF: Initialization flag
When this bit is set to 1, the RTC is in initialization state, and the time, date and prescaler
registers can be updated.
0: Calendar registers update is not allowed
1: Calendar registers update is allowed
Bit 5 RSF: Registers synchronization flag
This bit is set by hardware each time the calendar registers are copied into the shadow
registers (RTC_SSR, RTC_TR and RTC_DR). This bit is cleared by hardware in initialization
mode, while a shift operation is pending (SHPF=1), or when in bypass shadow register mode
(BYPSHAD=1). This bit can also be cleared by software.
It is cleared either by software or by hardware in initialization mode.
0: Calendar shadow registers not yet synchronized
1: Calendar shadow registers synchronized
Bit 4 INITS: Initialization status flag
This bit is set by hardware when the calendar year field is different from 0 (RTC domain reset
state).
0: Calendar has not been initialized
1: Calendar has been initialized
Bit 3 SHPF: Shift operation pending
0: No shift operation is pending
1: A shift operation is pending
This flag is set by hardware as soon as a shift operation is initiated by a write to the
RTC_SHIFTR register. It is cleared by hardware when the corresponding shift operation has
been executed. Writing to the SHPF bit has no effect.
Bit 2 WUTWF: Wake-up timer write flag
This bit is set by hardware up to 2 RTCCLK cycles after the WUTE bit has been set to 0 in
RTC_CR, and is cleared up to 2 RTCCLK cycles after the WUTE bit has been set to 1. The
wake-up timer values can be changed when WUTE bit is cleared and WUTWF is set.
0: Wake-up timer configuration update not allowed
1: Wake-up timer configuration update allowed
Bit 1 Reserved, must be kept at reset value.
Bit 0 ALRAWF: Alarm A write flag
This bit is set by hardware when Alarm A values can be changed, after the ALRAE bit has
been set to 0 in RTC_CR.
It is cleared by hardware in initialization mode.
0: Alarm A update not allowed
1: Alarm A update allowed

Note: The bits ALRAF, WUTF and TSF are cleared 2 APB clock cycles after programming them to
0.

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RM0360 Real-time clock (RTC)

21.7.5 RTC prescaler register (RTC_PRER)

This register must be written in initialization mode only. The initialization must be performed
in two separate write accesses. Refer to Calendar initialization and configuration on
page 492.
This register is write protected. The write access procedure is described in RTC register
write protection on page 492.
Address offset: 0x10
RTC domain reset value: 0x007F 00FF
System reset: not affected

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. PREDIV_A[6:0]

rw rw rw rw rw rw rw

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. PREDIV_S[14:0]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:23 Reserved, must be kept at reset value.

Bits 22:16 PREDIV_A[6:0]: Asynchronous prescaler factor
This is the asynchronous division factor:
ck_apre frequency = RTCCLK frequency/(PREDIV_A+1)
Bit 15 Reserved, must be kept at reset value.
Bits 14:0 PREDIV_S[14:0]: Synchronous prescaler factor
This is the synchronous division factor:
ck_spre frequency = ck_apre frequency/(PREDIV_S+1)

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Real-time clock (RTC) RM0360

21.7.6 RTC wake-up timer register (RTC_WUTR)

This register can be written only when WUTWF is set to 1 in RTC_ISR.
This register is write protected. The write access procedure is described in RTC register
write protection on page 492.
Address offset: 0x14
RTC domain reset value: 0x0000 FFFF
System reset: not affected

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WUT[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 WUT[15:0]: Wake-up auto-reload value bits
When the wake-up timer is enabled (WUTE set to 1), the WUTF flag is set every (WUT[15:0]
+ 1) ck_wut cycles. The ck_wut period is selected through WUCKSEL[2:0] bits of the
RTC_CR register
When WUCKSEL[2] = 1, the wake-up timer becomes 17-bits and WUCKSEL[1] effectively
becomes WUT[16] the most-significant bit to be reloaded into the timer.
The first assertion of WUTF occurs (WUT+1) ck_wut cycles after WUTE is set. Setting
WUT[15:0] to 0x0000 with WUCKSEL[2:0] =011 (RTCCLK/2) is forbidden.

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RM0360 Real-time clock (RTC)

21.7.7 RTC alarm A register (RTC_ALRMAR)

This register can be written only when ALRAWF is set to 1 in RTC_ISR, or in initialization
mode.
This register is write protected. The write access procedure is described in RTC register
write protection on page 492.
Address offset: 0x1C
RTC domain reset value: 0x0000 0000
System reset: not affected

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MSK4 WDSEL DT[1:0] DU[3:0] MSK3 PM HT[1:0] HU[3:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MSK2 MNT[2:0] MNU[3:0] MSK1 ST[2:0] SU[3:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bit 31 MSK4: Alarm A date mask

0: Alarm A set if the date/day match
1: Date/day don’t care in Alarm A comparison
Bit 30 WDSEL: Week day selection
0: DU[3:0] represents the date units
1: DU[3:0] represents the week day. DT[1:0] is don’t care.
Bits 29:28 DT[1:0]: Date tens in BCD format.
Bits 27:24 DU[3:0]: Date units or day in BCD format.
Bit 23 MSK3: Alarm A hours mask
0: Alarm A set if the hours match
1: Hours don’t care in Alarm A comparison
Bit 22 PM: AM/PM notation
0: AM or 24-hour format
1: PM
Bits 21:20 HT[1:0]: Hour tens in BCD format.
Bits 19:16 HU[3:0]: Hour units in BCD format.
Bit 15 MSK2: Alarm A minutes mask
0: Alarm A set if the minutes match
1: Minutes don’t care in Alarm A comparison
Bits 14:12 MNT[2:0]: Minute tens in BCD format.
Bits 11:8 MNU[3:0]: Minute units in BCD format.
Bit 7 MSK1: Alarm A seconds mask
0: Alarm A set if the seconds match
1: Seconds don’t care in Alarm A comparison
Bits 6:4 ST[2:0]: Second tens in BCD format.
Bits 3:0 SU[3:0]: Second units in BCD format.

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Real-time clock (RTC) RM0360

21.7.8 RTC write protection register (RTC_WPR)

Address offset: 0x24
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. KEY[7:0]

w w w w w w w w

Bits 31:8 Reserved, must be kept at reset value.

Bits 7:0 KEY[7:0]: Write protection key
This byte is written by software.
Reading this byte always returns 0x00.
Refer to RTC register write protection for a description of how to unlock RTC register write
protection.

21.7.9 RTC sub second register (RTC_SSR)

Address offset: 0x28
RTC domain reset value: 0x0000 0000
System reset: 0x0000 0000 when BYPSHAD = 0. Not affected when BYPSHAD = 1.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SS[15:0]
r r r r r r r r r r r r r r r r

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 SS[15:0]: Sub second value
SS[15:0] is the value in the synchronous prescaler counter. The fraction of a second is given by
the formula below:
Second fraction = (PREDIV_S - SS) / (PREDIV_S + 1)
Note: SS can be larger than PREDIV_S only after a shift operation. In that case, the correct
time/date is one second less than as indicated by RTC_TR/RTC_DR.

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RM0360 Real-time clock (RTC)

21.7.10 RTC shift control register (RTC_SHIFTR)

This register is write protected. The write access procedure is described in RTC register
write protection on page 492.
Address offset: 0x2C
RTC domain reset value: 0x0000 0000
System reset: not affected

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADD1S Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. SUBFS[14:0]

w w w w w w w w w w w w w w w

Bit 31 ADD1S: Add one second

0: No effect
1: Add one second to the clock/calendar
This bit is write only and is always read as zero. Writing to this bit has no effect when a shift
operation is pending (when SHPF=1, in RTC_ISR).
This function is intended to be used with SUBFS (see description below) in order to effectively
add a fraction of a second to the clock in an atomic operation.
Bits 30:15 Reserved, must be kept at reset value.
Bits 14:0 SUBFS[14:0]: Subtract a fraction of a second
These bits are write only and is always read as zero. Writing to this bit has no effect when a
shift operation is pending (when SHPF=1, in RTC_ISR).
The value which is written to SUBFS is added to the synchronous prescaler counter. Since this
counter counts down, this operation effectively subtracts from (delays) the clock by:
Delay (seconds) = SUBFS / (PREDIV_S + 1)
A fraction of a second can effectively be added to the clock (advancing the clock) when the
ADD1S function is used in conjunction with SUBFS, effectively advancing the clock by:
Advance (seconds) = (1 - (SUBFS / (PREDIV_S + 1))).
Note: Writing to SUBFS causes RSF to be cleared. Software can then wait until RSF=1 to be
sure that the shadow registers have been updated with the shifted time.

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Real-time clock (RTC) RM0360

21.7.11 RTC timestamp time register (RTC_TSTR)

The content of this register is valid only when TSF is set to 1 in RTC_ISR. It is cleared when
TSF bit is reset.
Address offset: 0x30
RTC domain reset value: 0x0000 0000
System reset: not affected

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. PM HT[1:0] HU[3:0]

r r r r r r r

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. MNT[2:0] MNU[3:0] Res. ST[2:0] SU[3:0]

r r r r r r r r r r r r r r

Bits 31:23 Reserved, must be kept at reset value.

Bit 22 PM: AM/PM notation
0: AM or 24-hour format
1: PM
Bits 21:20 HT[1:0]: Hour tens in BCD format.
Bits 19:16 HU[3:0]: Hour units in BCD format.
Bit 15 Reserved, must be kept at reset value.
Bits 14:12 MNT[2:0]: Minute tens in BCD format.
Bits 11:8 MNU[3:0]: Minute units in BCD format.
Bit 7 Reserved, must be kept at reset value.
Bits 6:4 ST[2:0]: Second tens in BCD format.
Bits 3:0 SU[3:0]: Second units in BCD format.

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RM0360 Real-time clock (RTC)

21.7.12 RTC timestamp date register (RTC_TSDR)

The content of this register is valid only when TSF is set to 1 in RTC_ISR. It is cleared when
TSF bit is reset.
Address offset: 0x34
RTC domain reset value: 0x0000 0000
System reset: not affected

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDU[2:0] MT MU[3:0] Res. Res. DT[1:0] DU[3:0]

r r r r r r r r r r r r r r

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:13 WDU[2:0]: Week day units
Bit 12 MT: Month tens in BCD format
Bits 11:8 MU[3:0]: Month units in BCD format
Bits 7:6 Reserved, must be kept at reset value.
Bits 5:4 DT[1:0]: Date tens in BCD format
Bits 3:0 DU[3:0]: Date units in BCD format

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Real-time clock (RTC) RM0360

21.7.13 RTC time-stamp sub second register (RTC_TSSSR)

The content of this register is valid only when RTC_ISR/TSF is set. It is cleared when the
RTC_ISR/TSF bit is reset.
Address offset: 0x38
RTC domain reset value: 0x0000 0000
System reset: not affected

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SS[15:0]
r r r r r r r r r r r r r r r r

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 SS[15:0]: Sub second value
SS[15:0] is the value of the synchronous prescaler counter when the timestamp event
occurred.

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RM0360 Real-time clock (RTC)

21.7.14 RTC calibration register (RTC_CALR)

This register is write protected. The write access procedure is described in RTC register
write protection on page 492.
Address offset: 0x3C
RTC domain reset value: 0x0000 0000
System reset: not affected

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CALW
CALP CALW8 Res. Res. Res. Res. CALM[8:0]
16
rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:16 Reserved, must be kept at reset value.

Bit 15 CALP: Increase frequency of RTC by 488.5 ppm
0: No RTCCLK pulses are added.
1: One RTCCLK pulse is effectively inserted every 211 pulses (frequency increased by
488.5 ppm).
This feature is intended to be used in conjunction with CALM, which lowers the frequency of
the calendar with a fine resolution. if the input frequency is 32768 Hz, the number of RTCCLK
pulses added during a 32-second window is calculated as follows: (512 * CALP) - CALM.
Refer to Section 21.4.12: RTC smooth digital calibration.
Bit 14 CALW8: Use an 8-second calibration cycle period
When CALW8 is set to ‘1’, the 8-second calibration cycle period is selected.
Note: CALM[1:0] are stuck at “00” when CALW8=’1’. Refer to Section 21.4.12: RTC smooth
digital calibration.
Bit 13 CALW16: Use a 16-second calibration cycle period
When CALW16 is set to ‘1’, the 16-second calibration cycle period is selected.This bit must
not be set to ‘1’ if CALW8=1.
Note: CALM[0] is stuck at ‘0’ when CALW16=’1’. Refer to Section 21.4.12: RTC smooth
digital calibration.
Bits 12:9 Reserved, must be kept at reset value.
Bits 8:0 CALM[8:0]: Calibration minus
The frequency of the calendar is reduced by masking CALM out of 220 RTCCLK pulses (32
seconds if the input frequency is 32768 Hz). This decreases the frequency of the calendar
with a resolution of 0.9537 ppm.
To increase the frequency of the calendar, this feature should be used in conjunction with
CALP. See Section 21.4.12: RTC smooth digital calibration on page 496.

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21.7.15 RTC tamper and alternate function configuration register

(RTC_TAFCR)
Address offset: 0x40
RTC domain reset value: 0x0000 0000
System reset: not affected

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PC15 PC15 PC14 PC14 PC13 PC13
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
MODE VALUE MODE VALUE MODE VALUE

rw rw rw rw rw rw

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TAMPP TAMPPRCH TAMPT TAMP2 TAMP2 TAMP1 TAMP1
TAMPFLT[1:0] TAMPFREQ[2:0] Res. Res. TAMPIE
UDIS [1:0] S TRG E TRG E
rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:24 Reserved, must be kept at reset value.

Bit 23 PC15MODE: PC15 mode
0: PC15 is controlled by the GPIO configuration registers. Consequently PC15 is floating in
Standby mode.
1: PC15 is forced to push-pull output if LSE is disabled.
Bit 22 PC15VALUE: PC15 value
If the LSE is disabled and PC15MODE = 1, PC15VALUE configures the PC15 output data.
Bit 21 PC14MODE: PC14 mode
0: PC14 is controlled by the GPIO configuration registers. Consequently PC14 is floating in
Standby mode.
1: PC14 is forced to push-pull output if LSE is disabled.
Bit 20 PC14VALUE: PC14 value
If the LSE is disabled and PC14MODE = 1, PC14VALUE configures the PC14 output data.
Bit 19 PC13MODE: PC13 mode
0: PC13 is controlled by the GPIO configuration registers. Consequently PC13 is floating in
Standby mode.
1: PC13 is forced to push-pull output if all RTC functions are disabled.
Bit 18 PC13VALUE: RTC_ALARM output type/PC13 value
If PC13 is used to output RTC_ALARM, PC13VALUE configures the output configuration:
0: RTC_ALARM is an open-drain output
1: RTC_ALARM is a push-pull output
If all RTC functions are disabled and PC13MODE = 1, PC13VALUE configures the PC13
output data.
Bits 17:16 Reserved, must be kept at reset value.
Bit 15 TAMPPUDIS: RTC_TAMPx pull-up disable
This bit determines if each of the RTC_TAMPx pins are pre-charged before each sample.
0: Precharge RTC_TAMPx pins before sampling (enable internal pull-up)
1: Disable precharge of RTC_TAMPx pins.

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RM0360 Real-time clock (RTC)

Bits 14:13 TAMPPRCH[1:0]: RTC_TAMPx precharge duration

These bit determines the duration of time during which the pull-up/is activated before each
sample. TAMPPRCH is valid for each of the RTC_TAMPx inputs.
0x0: 1 RTCCLK cycle
0x1: 2 RTCCLK cycles
0x2: 4 RTCCLK cycles
0x3: 8 RTCCLK cycles
Bits 12:11 TAMPFLT[1:0]: RTC_TAMPx filter count
These bits determines the number of consecutive samples at the specified level (TAMP*TRG)
needed to activate a Tamper event. TAMPFLT is valid for each of the RTC_TAMPx inputs.
0x0: Tamper event is activated on edge of RTC_TAMPx input transitions to the active level
(no internal pull-up on RTC_TAMPx input).
0x1: Tamper event is activated after 2 consecutive samples at the active level.
0x2: Tamper event is activated after 4 consecutive samples at the active level.
0x3: Tamper event is activated after 8 consecutive samples at the active level.
Bits 10:8 TAMPFREQ[2:0]: Tamper sampling frequency
Determines the frequency at which each of the RTC_TAMPx inputs are sampled.
0x0: RTCCLK / 32768 (1 Hz when RTCCLK = 32768 Hz)
0x1: RTCCLK / 16384 (2 Hz when RTCCLK = 32768 Hz)
0x2: RTCCLK / 8192 (4 Hz when RTCCLK = 32768 Hz)
0x3: RTCCLK / 4096 (8 Hz when RTCCLK = 32768 Hz)
0x4: RTCCLK / 2048 (16 Hz when RTCCLK = 32768 Hz)
0x5: RTCCLK / 1024 (32 Hz when RTCCLK = 32768 Hz)
0x6: RTCCLK / 512 (64 Hz when RTCCLK = 32768 Hz)
0x7: RTCCLK / 256 (128 Hz when RTCCLK = 32768 Hz)
Bit 7 TAMPTS: Activate timestamp on tamper detection event
0: Tamper detection event does not cause a timestamp to be saved
1: Save timestamp on tamper detection event
TAMPTS is valid even if TSE=0 in the RTC_CR register.
Bits 6:5 Reserved, must be kept at reset value.
Bit 4 TAMP2TRG: Active level for RTC_TAMP2 input
if TAMPFLT != 00:
0: RTC_TAMP2 input staying low triggers a tamper detection event.
1: RTC_TAMP2 input staying high triggers a tamper detection event.
if TAMPFLT = 00:
0: RTC_TAMP2 input rising edge triggers a tamper detection event.
1: RTC_TAMP2 input falling edge triggers a tamper detection event.
Bit 3 TAMP2E: RTC_TAMP2 input detection enable
0: RTC_TAMP2 detection disabled
1: RTC_TAMP2 detection enabled

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Bit 2 TAMPIE: Tamper interrupt enable

0: Tamper interrupt disabled
1: Tamper interrupt enabled.
Bit 1 TAMP1TRG: Active level for RTC_TAMP1 input
If TAMPFLT != 00
0: RTC_TAMP1 input staying low triggers a tamper detection event.
1: RTC_TAMP1 input staying high triggers a tamper detection event.
if TAMPFLT = 00:
0: RTC_TAMP1 input rising edge triggers a tamper detection event.
1: RTC_TAMP1 input falling edge triggers a tamper detection event.
Bit 0 TAMP1E: RTC_TAMP1 input detection enable
0: RTC_TAMP1 detection disabled
1: RTC_TAMP1 detection enabled

Caution: When TAMPFLT = 0, TAMPxE must be reset when TAMPxTRG is changed to avoid
spuriously setting TAMPxF.

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RM0360 Real-time clock (RTC)

21.7.16 RTC alarm A sub second register (RTC_ALRMASSR)

This register can be written only when ALRAE is reset in RTC_CR register, or in initialization
mode.
This register is write protected. The write access procedure is described in RTC register
write protection on page 492
Address offset: 0x44
RTC domain reset value: 0x0000 0000
System reset: not affected

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. MASKSS[3:0] Res. Res. Res. Res. Res. Res. Res. Res.

rw rw rw rw

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. SS[14:0]

rw rw rw rw rw rw rw rw rw rw rw rw w rw rw

Bits 31:28 Reserved, must be kept at reset value.

Bits 27:24 MASKSS[3:0]: Mask the most-significant bits starting at this bit
0: No comparison on sub seconds for Alarm A. The alarm is set when the seconds unit is
incremented (assuming that the rest of the fields match).
1: SS[14:1] are don’t care in Alarm A comparison. Only SS[0] is compared.
2: SS[14:2] are don’t care in Alarm A comparison. Only SS[1:0] are compared.
3: SS[14:3] are don’t care in Alarm A comparison. Only SS[2:0] are compared.
...
12: SS[14:12] are don’t care in Alarm A comparison. SS[11:0] are compared.
13: SS[14:13] are don’t care in Alarm A comparison. SS[12:0] are compared.
14: SS[14] is don’t care in Alarm A comparison. SS[13:0] are compared.
15: All 15 SS bits are compared and must match to activate alarm.
The overflow bits of the synchronous counter (bits 15) is never compared. This bit can be
different from 0 only after a shift operation.
Bits 23:15 Reserved, must be kept at reset value.
Bits 14:0 SS[14:0]: Sub seconds value
This value is compared with the contents of the synchronous prescaler counter to determine if
Alarm A is to be activated. Only bits 0 up MASKSS-1 are compared.

21.7.17 RTC register map

Table 67. RTC register map and reset values

Register
Offset
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12

10
11

9
8
7
6
5
4
3
2
1
0

name
HT[1:0]
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.

Res.
PM

RTC_TR HU[3:0] MNT[2:0] MNU[3:0] ST[2:0] SU[3:0]

0x00

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

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 0x38
0x34
0x30
0x28
0x24
0x14
0x10
0x08
0x04

0x2C
0x1C
0x0C
Offset

522/775
name

RTC_CR
RTC_DR

RTC_ISR

RTC_SSR
RTC_WPR
Register

RTC_TSTR
Reset value

Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value

RTC_TSDR
RTC_PRER

RTC_WUTR

RTC_TSSSR
RTC_SHIFTR
RTC_ALRMAR

0
0
Res. Res. Res. ADD1S Res. Res. MSK4 Res. Res. Res. Res. Res. 31
Real-time clock (RTC)

0
Res. Res. Res. Res. Res. Res. WDSEL Res. Res. Res. Res. Res. 30

0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 29
DT[1:0]

0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 28

0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 27

0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 26

0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 25

DU[3:0]

0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 24

0
0
0

Res. Res. Res. Res. Res. Res. MSK3 Res. Res. Res. COE 23

0
0
1
0
0

Res. Res. PM Res. Res. Res. PM Res. Res. 22

OSEL[1:0]

0
0
1
0
0

Res. Res. Res. Res. Res. Res. Res. 21

YT[3:0]

HT[1:0] HT[1:0]

0
0
1
0
0

Res. Res. Res. Res. Res. Res. Res. POL 20

0
0
1
0

Res. Res. Res. Res. Res. Res. Res. COSEL 19

0
0
1
0
0

Res. Res. Res. Res. Res. Res. PREDIV_A[6:0] Res. BKP 18

0
0
1
0
0

Res. Res. Res. Res. Res. Res. Res. SUB1H

RM0360 Rev 5
17
YU[3:0]

HU[3:0]
HU[3:0]

0
0
1
0
0
0

Res. Res. Res. Res. Res. Res. RECALPF ADD1H 16

0
0
0
1
0
0
0

Res. Res. Res. MSK2 Res. TSIE 15

0
0
0
0

0
0
1
0
0
0
0

Res. .TAMP2F WUTIE 14

0
0
0
0

0
0
1
0
0
1

WDU[1:0]
WDU[2:0]

MNT[2:0] Res. TAMP1F Res. 13

0
0
0
0

0
0
1
0
0
0
0

MNT[2:0]
MT Res. TSOVF ALRAIE MT 12

0
0
0
0
0
1
0
0
0
0

Res. TSF TSE 11

0
0
0
0
0
1
0
0
0
0

Res. WUTF WUTE 10

0

0
0
0
0
0
1
0
0

Res. Res. Res. 9

MU[3:0]
MU[3:0]

MNU[3:0]
MNU[3:0]
Table 67. RTC register map and reset values (continued)

0
0
0
0
0
1
0
0
0
1

Res. ALRAF ALRAE 8

0

0
0
0
1
1
0

0
Res. Res. MSK1 INIT Res. Res. 7

SS[15:0]
SS[15:0]
WUT[15:0]

0
0
0
0
1
1
0
0

Res. 0 INITF FMT Res. 6

PREDIV_S[14:0]

SUBFS[14:0]

0
0
0
0

0
0
1
1
0
0
0

0
RSF BYPSHAD 5
DT[1:0] DT[1:0]

ST[2:0]
ST[2:0]

0
0
0
0

0
0
1
1
0
0
0

INITS REFCKON 4
KEY

0
0
0
0

0
0
1
1
0
0
0

SHPF TSEDGE 3

0
0

0
0
0
0
1
1
1
0
0

WUT WF 2

0
0
0
0

0
0
1
1
0
0

Res. WUCKSEL[2:0] 1

SU[3:0]
SU[3:0]

DU[3:0]
DU[3:0]

0
0
0
0
0
1
1
1
0
1

ALRAWF
RM0360

0
 0x44
0x40

0x4C
0x3C
Offset
RM0360

RTC_
name

RTC_ OR
Register

Reset value
Reset value
Reset value
Reset value
RTC_ CALR

ALRMASSR
RTC_TAFCR
Res. Res. Res. Res. 31
Res. Res. Res. Res. 30
Res. Res. Res. Res. 29
Res. Res. Res. Res. 28

0
Res. Res. Res. 27

0
Res. Res. Res. 26

[3:0]

0
Res. Res. Res. 25

MASKSS

0
Res. Res. Res. 24
0
Res. Res. PC15MODE Res. 23
0

Res. Res. PC15VALUE Res. 22

0

Res. Res. PC14MODE Res. 21

0

Res. Res. PC14VALUE Res. 20

0

Res. Res. PC13MODE Res. 19

0

Res. Res. PC13VALUE Res. 18

Res. Res. Res. Res.

RM0360 Rev 5
17
Res. Res. Res. Res. 16
0
0

Res. Res. TAMPPUDIS CALP 15

0
0
0

Res. CALW8 14
TAMPPRCH[1:0]
0
0
0

Res. CALW16 13
0
0

Res. Res. 12
TAMPFLT[1:0]
0
0

Res. Res. 11
0
0

Res. Res. 10
0
0

Res. TAMPFREQ[2:0] Res. 9

Refer to Section 2.2 on page 37 for the register boundary addresses.
Table 67. RTC register map and reset values (continued)

0
0
0

Res. 8
0
0
0

Res. TAMPTS 7
SS[14:0]

0
0

Res. Res. 6
0
0

Res. Res. 5
0
0
0

Res. TAMP2TRG 4
0
0
0

RTC_ALARM_TYPE TAMP2E
CALM[8:0]

3
0
0
0

TAMPIE 2
TSINSEL[1:0]
0
0
0

TAMP1TRG 1
0
0
0

Res. TAMP1E
Real-time clock (RTC)

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Inter-integrated circuit (I2C) interface RM0360

22 Inter-integrated circuit (I2C) interface

22.1 Introduction
The I2C (inter-integrated circuit) bus interface handles communications between the
microcontroller and the serial I2C bus. It provides multimaster capability, and controls all I2C
bus-specific sequencing, protocol, arbitration and timing. It supports Standard-mode (Sm),
Fast-mode (Fm) and Fast-mode Plus (Fm+).
The I2C bus interface is also SMBus (system management bus) and PMBus® (power
management bus) compatible.
DMA can be used to reduce CPU overload.

22.2 I2C main features

• I2C bus specification rev03 compatibility:
– Slave and master modes
– Multimaster capability
– Standard-mode (up to 100 kHz)
– Fast-mode (up to 400 kHz)
– Fast-mode Plus (up to 1 MHz)
– 7-bit and 10-bit addressing mode
– Multiple 7-bit slave addresses (2 addresses, 1 with configurable mask)
– All 7-bit addresses acknowledge mode
– General call
– Programmable setup and hold times
– Easy to use event management
– Optional clock stretching
– Software reset
• 1-byte buffer with DMA capability
• Programmable analog and digital noise filters
The following features are also available, depending upon product implementation (see
Section 22.3):
• SMBus specification rev 3.0 compatibility:
– Hardware PEC (packet error checking) generation and verification with ACK
control
– Command and data acknowledge control
– Address resolution protocol (ARP) support
– Host and device support
– SMBus alert
– Timeouts and idle condition detection
• PMBus rev 1.3 standard compatibility
• Independent clock: a choice of independent clock sources allowing the I2C
communication speed to be independent from the PCLK reprogramming

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22.3 I2C implementation

This manual describes the full set of features implemented in I2C1 I2C2 supports a smaller
set of features, but is otherwise identical to I2C1. The differences are listed below.

Table 68. STM32F0x0 I2C implementation

STM32F030x4,
STM32F070xB
STM32F030x6, STM32F030x8
(1) STM32F030xC
I2C features STM32F070x6

I2C1 I2C1 I2C2 I2C1 I2C2

7-bit addressing mode X X X X X

10-bit addressing mode X X X X X
Standard mode (up to 100 kbit/s) X X X X X
Fast-mode (up to 400 kbit/s) X X X X X
Fast-mode Plus with 20 mA output
X X - X -
drive I/Os (up to 1 Mbit/s)
Independent clock X X - X -
Wake-up from Stop mode - - - - -
SMBus/PMBus X X - X -
1. X = supported.

22.4 I2C functional description

In addition to receiving and transmitting data, this interface converts them from serial to
parallel format and vice versa. The interrupts are enabled or disabled by software. The
interface is connected to the I2C bus by a data pin (SDA) and by a clock pin (SCL). It can be
connected with a standard (up to 100 kHz), Fast-mode (up to 400 kHz) or Fast-mode Plus
(up to 1 MHz) I2C bus.
This interface can also be connected to an SMBus with data (SDA) and clock (SCL) pins.
If the SMBus feature is supported, the optional SMBus Alert pin (SMBA) is also available.

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22.4.1 I2C block diagram

The block diagram of the I2C interface is shown in Figure 199.

Figure 199. I2C block diagram

I2CCLK
i2c_ker_ck Data control
Digital Analog
Shift register noise noise GPIO
filter I2C_SDA
filter logic

SMBUS PEC
generation/check

Clock control
Master clock
generation Digital Analog
noise noise
Slave clock GPIO I2C_SCL
filter filter
stretching logic

SMBus timeout
check

SMBus alert
control/status I2C_SMBA

PCLK
i2c_pclk Registers

DT56356
APB bus

The I2C is clocked by an independent clock source, which allows the I2C to operate
independently from the PCLK frequency.
For I2C I/Os supporting 20 mA output current drive for Fast-mode Plus operation, the driving
capability is enabled through control bits in the system configuration controller (SYSCFG).
Refer to Section 22.3: I2C implementation.

22.4.2 I2C2 block diagram

The block diagram of the I2C2 interface is shown in Figure 200.

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Figure 200. I2C2 block diagram

22.4.3 I2C pins and internal signals

Table 69. I2C input/output pins
Pin name Signal type Description

I2C_SDA Bidirectional I2C data

I2C_SCL Bidirectional I2C clock
I2C_SMBA Bidirectional SMBus alert

Table 70. I2C internal input/output signals

Internal signal name Signal type Description

i2c_ker_ck Input I2C kernel clock, also named I2CCLK in this document
i2c_pclk Input I2C APB clock
i2c_it Output I2C interrupts, refer to Table 84 for the list of interrupt sources
i2c_rx_dma Output I2C receive data DMA request (I2C_RX)
i2c_tx_dma Output I2C transmit data DMA request (I2C_TX)

22.4.4 I2C clock requirements

The I2C kernel is clocked by I2CCLK.

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The I2CCLK period tI2CCLK must respect the following conditions:

• tI2CCLK < (tLOW - tfilters) / 4
• tI2CCLK < tHIGH
with:
tLOW: SCL low time and tHIGH: SCL high time
tfilters: when enabled, sum of the delays brought by the analog and by the digital filters.
The digital filter delay is DNF x tI2CCLK.
The PCLK clock period tPCLK must respect the condition:
• tPCLK < 4 / 3 tSCL (tSCL: SCL period)
Caution: When the I2C kernel is clocked by PCLK, this clock must respect the conditions for tI2CCLK.

22.4.5 Mode selection

The interface can operate in one of the four following modes:
• Slave transmitter
• Slave receiver
• Master transmitter
• Master receiver
By default, it operates in slave mode. The interface automatically switches from slave to
master when it generates a START condition, and from master to slave if an arbitration loss
or a STOP generation occurs, allowing multimaster capability.

Communication flow
In master mode, the I2C interface initiates a data transfer and generates the clock signal. A
serial data transfer always begins with a START condition, and ends with a STOP condition.
Both START and STOP conditions are generated in master mode by software.
In slave mode, the interface is capable of recognizing its own addresses (7- or 10-bit), and
the general call address. The general call address detection can be enabled or disabled by
software. The reserved SMBus addresses can be enabled also by software.
Data and addresses are transferred as 8-bit bytes, MSB first. The first byte(s) following the
START condition contains the address (one in 7-bit mode, two in 10-bit mode). The address
is always transmitted in master mode.
A ninth clock pulse follows the eight clock cycles of a byte transfer, during which the receiver
must send an acknowledge bit to the transmitter (see Figure 201).

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Figure 201. I2C bus protocol

SDA
MSB ACK

SCL
1 2 8 9

Start Stop
condition condition

MS19854V1

Acknowledge can be enabled or disabled by software. The I2C interface addresses can be
selected by software.

22.4.6 I2C initialization

Enabling and disabling the peripheral
The I2C peripheral clock must be configured and enabled in the clock controller, then the
I2C can be enabled by setting the PE bit in the I2C_CR1 register.
When the I2C is disabled (PE = 0), the I2C performs a software reset. Refer to
Section 22.4.7 for more details.

Noise filters
Before enabling the I2C peripheral by setting the PE bit in I2C_CR1 register, the user must
configure the noise filters, if needed. By default, an analog noise filter is present on the SDA
and SCL inputs. This filter is compliant with the I2C specification, which requires the
suppression of spikes with pulse width up to 50 ns in Fast-mode and Fast-mode Plus. The
user can disable this analog filter by setting the ANFOFF bit, and/or select a digital filter by
configuring the DNF[3:0] bit in the I2C_CR1 register.
When the digital filter is enabled, the level of the SCL or the SDA line is internally changed
only if it remains stable for more than DNF x I2CCLK periods. This allows to suppress
spikes with a programmable length of one to fifteen I2CCLK periods.

Table 71. Comparison of analog vs. digital filters

- Analog filter Digital filter

Pulse width of
≥ 50 ns Programmable length, from one to fifteen I2C peripheral clocks
suppressed spikes

Caution: The filter configuration cannot be changed when the I2C is enabled.

I2C timings

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The timings must be configured to guarantee correct data hold and setup times, in master
and slave modes. This is done by programming the PRESC[3:0], SCLDEL[3:0] and
SDADEL[3:0] bits in the I2C_TIMINGR register.
The STM32CubeMX tool calculates and provides the I2C_TIMINGR content in the I2C
configuration window.

Figure 202. Setup and hold timings

DATA HOLD TIME
SCL falling edge internal
detection

tSYNC1 SDADEL: SCL stretched low by the I2C

SDA output delay

SCL

SDA

tHD;DAT
Data hold time: in case of transmission, the data is sent on SDA output after
the SDADEL delay, if it is already available in I2C_TXDR.

DATA SETUP TIME

SCLDEL
SCL stretched low by the I2C

SCL

SDA

tSU;DAT
SU;STA
Data setup time: in case of transmission, the SCLDEL counter starts
when the data is sent on SDA output. MSv40108V1
MS49608V1

When the SCL falling edge is internally detected, a delay (tSDADEL, impacting the hold time
tHD;DAT) is inserted before sending SDA output: tSDADEL = SDADEL x tPRESC + tI2CCLK, where
tPRESC = (PRESC + 1) x tI2CCLK.

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The total SDA output delay is:

tSYNC1 + {[SDADEL x (PRESC + 1) + 1] x tI2CCLK}
tSYNC1 duration depends upon:
– SCL falling slope
– When enabled, input delay brought by the analog filter: tAF(min) < tAF < tAF(max)
– When enabled, input delay brought by the digital filter: tDNF = DNF x tI2CCLK
– Delay due to SCL synchronization to I2CCLK clock (two to three I2CCLK periods)
To bridge the undefined region of the SCL falling edge, the user must program SDADEL in
such a way that:
{tf (max) + tHD;DAT (min) - tAF(min) - [(DNF + 3) x tI2CCLK]} / {(PRESC + 1) x tI2CCLK} ≤ SDADEL
SDADEL ≤ {tHD;DAT (max) - tAF(max) - [(DNF + 4) x tI2CCLK]} / {(PRESC + 1) x tI2CCLK}
Note: tAF(min) / tAF(max) are part of the equation only when the analog filter is enabled. Refer to the
device datasheet for tAF values.
The maximum tHD;DAT can be 3.45 µs for Standard-mode, 0.9 µs for Fast-mode, 0.45 µs for
Fast-mode Plus. It must be lower than the maximum of tVD;DAT by a transition time. This
maximum must only be met if the device does not stretch the LOW period (tLOW) of the SCL
signal. If the clock stretches the SCL, the data must be valid by the set-up time before it
releases the clock.
The SDA rising edge is usually the worst case. In this case the previous equation becomes:
SDADEL ≤ {tVD;DAT (max) - tr (max) - tAF (max) - [(DNF + 4) x tI2CCLK]} / {(PRESC + 1) x tI2CCLK}.
Note: This condition can be violated when NOSTRETCH = 0, because the device stretches SCL
low to guarantee the set-up time, according to the SCLDEL value.
Refer to Table 72 for tf, tr, tHD;DAT, and tVD;DAT standard values.
• After tSDADEL, or after sending SDA output when the slave had to stretch the clock
because the data was not yet written in I2C_TXDR register, SCL line is kept at low level
during the setup time. This setup time is tSCLDEL = (SCLDEL + 1) x tPRESC, where
tPRESC = (PRESC + 1) x tI2CCLK. tSCLDEL impacts the setup time tSU;DAT.

To bridge the undefined region of the SDA transition (rising edge usually worst case), the
user must program SCLDEL in such a way that:
{[tr (max) + tSU;DAT (min)] / [(PRESC + 1)] x tI2CCLK]} - 1 ≤ SCLDEL
Refer to Table 72 for tr and tSU;DAT standard values.
The SDA and SCL transition time values to use are the ones in the application. Using the
maximum values from the standard increases the constraints for the SDADEL and SCLDEL
calculation, but ensures the feature, whatever the application.
Note: At every clock pulse, after SCL falling edge detection, the I2C master or slave stretches SCL
low during at least [(SDADEL + SCLDEL + 1) x (PRESC + 1) + 1] x tI2CCLK, in both
transmission and reception modes. In transmission mode, if the data is not yet written in
I2C_TXDR when SDADEL counter is finished, the I2C keeps on stretching SCL low until the
next data is written. Then new data MSB is sent on SDA output, and SCLDEL counter starts,
continuing stretching SCL low to guarantee the data setup time.
If NOSTRETCH = 1 in slave mode, the SCL is not stretched, hence the SDADEL must be
programmed so that it guarantees a sufficient setup time.

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Table 72. I2C-SMBus specification data setup and hold times

Standard-mode Fast-mode Fast-mode Plus
SMBus
(Sm) (Fm) (Fm+)
Symbol Parameter Unit
Min Max Min Max Min Max Min Max

tHD;DAT Data hold time 0 - 0 - 0 - 0.3 -

µs
tVD;DAT Data valid time - 3.45 - 0.9 - 0.45 - -
tSU;DAT Data setup time 250 - 100 - 50 - 250 -
Rise time of both
tr - 1000 - 300 - 120 - 1000
SDA and SCL signals ns
Fall time of both
tf - 300 - 300 - 120 - 300
SDA and SCL signals

Additionally, in master mode, the SCL clock high and low levels must be configured by
programming the PRESC[3:0], SCLH[7:0] and SCLL[7:0] bit fields in the I2C_TIMINGR
register.
• When the SCL falling edge is internally detected, a delay is inserted before releasing
the SCL output.
This delay is tSCLL = (SCLL + 1) x tPRESC where tPRESC = (PRESC + 1) x tI2CCLK.
tSCLL impacts the SCL low time tLOW.
• When the SCL rising edge is internally detected, a delay is inserted before forcing the
SCL output to low level. This delay is tSCLH = (SCLH + 1) x tPRESC, where
tPRESC = (PRESC+ 1) x tI2CCLK. tSCLH impacts the SCL high time tHIGH.

Refer to I2C master initialization for more details.

Caution: Changing the timing configuration is not allowed when the I2C is enabled.
The I2C slave NOSTRETCH mode must also be configured before enabling the peripheral.
Refer to I2C slave initialization for more details.
Caution: Changing the NOSTRETCH configuration is not allowed when the I2C is enabled.

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Figure 203. I2C initialization flow

Initial settings

Clear PE bit in I2C_CR1

Configure ANFOFF and DNF[3:0] in I2C_CR1

Configure PRESC[3:0], SDADEL[3:0], SCLDEL[3:0],

SCLH[7:0], and SCLL[7:0] in I2C_TIMINGR

Configure NOSTRETCH in I2C_CR1

Set PE bit in I2C_CR1

End
MS19847V3

22.4.7 Software reset

A software reset can be performed by clearing the PE bit in the I2C_CR1 register. In that
case I2C lines SCL and SDA are released. Internal states machines are reset and
communication control bits, as well as status bits, come back to their reset value. The
configuration registers are not impacted.
Impacted register bits:
1. I2C_CR2 register: START, STOP, NACK
2. I2C_ISR register: BUSY, TXE, TXIS, RXNE, ADDR, NACKF, TCR, TC, STOPF, BERR,
ARLO, OVR
In addition when the SMBus feature is supported:
1. I2C_CR2 register: PECBYTE
2. I2C_ISR register: PECERR, TIMEOUT, ALERT
PE must be kept low during at least three APB clock cycles to perform the software reset.
This is ensured by the following software sequence:
1. Write PE = 0
2. Check PE = 0
3. Write PE = 1

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22.4.8 Data transfer

The data transfer is managed through transmit and receive data registers and a shift
register.

Reception
The SDA input fills the shift register. After the eighth SCL pulse (when the complete data
byte is received), the shift register is copied into I2C_RXDR register if it is empty
(RXNE = 0). If RXNE = 1, meaning that the previous received data byte has not yet been
read, the SCL line is stretched low until I2C_RXDR is read. The stretch is inserted between
the eighth and ninth SCL pulse (before the acknowledge pulse).

Figure 204. Data reception

ACK pulse ACK pulse

legend:
SCL SCL
stretch
Shift register xx data1 xx data2 xx

RXNE

rd data0 rd data1

I2C_RXDR data0 data1 data2

MS19848V1

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Transmission
If the I2C_TXDR register is not empty (TXE = 0), its content is copied into the shift register
after the ninth SCL pulse (the acknowledge pulse). Then the shift register content is shifted
out on SDA line. If TXE = 1, meaning that no data is written yet in I2C_TXDR, SCL line is
stretched low until I2C_TXDR is written. The stretch is done after the ninth SCL pulse.

Figure 205. Data transmission

ACK pulse ACK pulse

legend:
SCL
SCL
stretch

data1

data2
Shift register xx xx xx

TXE

wr data1 wr data2

I2C_TXDR data0 data1 data2

MS19849V1

Hardware transfer management

The I2C features an embedded byte counter to manage byte transfer and to close the
communication in various modes, such as:
– NACK, STOP and ReSTART generation in master mode
– ACK control in slave receiver mode
– PEC generation/checking when SMBus feature is supported
The byte counter is always used in master mode. By default, it is disabled in slave mode.It
can be enabled by software by setting the SBC (slave byte control) bit in the I2C_CR1
register.
The number of bytes to be transferred is programmed in the NBYTES[7:0] bit field in the
I2C_CR2 register. If the number of bytes to be transferred (NBYTES) is greater than 255, or
if a receiver wants to control the acknowledge value of a received data byte, the reload
mode must be selected by setting the RELOAD bit in the I2C_CR2 register. In this mode,
the TCR flag is set when the number of bytes programmed in NBYTES is transferred, and
an interrupt is generated if TCIE is set. SCL is stretched as long as TCR flag is set. TCR is
cleared by software when NBYTES is written to a non-zero value.
When the NBYTES counter is reloaded with the last number of bytes, RELOAD bit must be
cleared.

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When RELOAD = 0 in master mode, the counter can be used in two modes:
• Automatic end (AUTOEND = 1 in the I2C_CR2 register). In this mode, the master
automatically sends a STOP condition once the number of bytes programmed in the
NBYTES[7:0] bit field is transferred.
• Software end (AUTOEND = 0 in the I2C_CR2 register). In this mode, software action
is expected once the number of bytes programmed in the NBYTES[7:0] bit field is
transferred; the TC flag is set and an interrupt is generated if the TCIE bit is set. The
SCL signal is stretched as long as the TC flag is set. The TC flag is cleared by software
when the START or STOP bit is set in the I2C_CR2 register. This mode must be used
when the master wants to send a RESTART condition.
Caution: The AUTOEND bit has no effect when the RELOAD bit is set.

Table 73. I2C configuration

Function SBC bit RELOAD bit AUTOEND bit

Master Tx/Rx NBYTES + STOP x 0 1

Master Tx/Rx + NBYTES + RESTART x 0 0
Slave Tx/Rx, all received bytes ACKed 0 x x
Slave Rx with ACK control 1 1 x

22.4.9 I2C slave mode

I2C slave initialization
To work in slave mode, the user must enable at least one slave address. Registers
I2C_OAR1 and I2C_OAR2 are available to program the slave own addresses OA1 and
OA2.
• OA1 can be configured either in 7-bit mode (by default), or in 10-bit addressing mode
by setting the OA1MODE bit in the I2C_OAR1 register.
OA1 is enabled by setting the OA1EN bit in the I2C_OAR1 register.
• If additional slave addresses are required, the second slave address OA2 can be
configured. Up to seven OA2 LSB can be masked by configuring the OA2MSK[2:0] bits
in the I2C_OAR2 register. Therefore for OA2MSK configured from 1 to 6, only
OA2[7:2], OA2[7:3], OA2[7:4], OA2[7:5], OA2[7:6] or OA2[7] are compared with the
received address. As soon as OA2MSK is not equal to 0, the address comparator for
OA2 excludes the I2C reserved addresses (0000 XXX and 1111 XXX), which are not
acknowledged. If OA2MSK = 7, all received 7-bit addresses are acknowledged (except
reserved addresses). OA2 is always a 7-bit address.
These reserved addresses can be acknowledged if they are enabled by the specific
enable bit, if they are programmed in the I2C_OAR1 or I2C_OAR2 register with
OA2MSK = 0.
OA2 is enabled by setting the OA2EN bit in the I2C_OAR2 register.
• The general call address is enabled by setting the GCEN bit in the I2C_CR1 register.
When the I2C is selected by one of its enabled addresses, the ADDR interrupt status flag is
set, and an interrupt is generated if the ADDRIE bit is set.
By default, the slave uses its clock stretching capability, which means that it stretches the
SCL signal at low level when needed, to perform software actions. If the master does not

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support clock stretching, the I2C must be configured with NOSTRETCH = 1 in the I2C_CR1
register.
After receiving an ADDR interrupt, if several addresses are enabled, the user must read the
ADDCODE[6:0] bits in the I2C_ISR register to check which address matched. DIR flag must
also be checked to know the transfer direction.

Slave clock stretching (NOSTRETCH = 0)

In default mode, the I2C slave stretches the SCL clock in the following situations:
• When the ADDR flag is set: the received address matches with one of the enabled
slave addresses. This stretch is released when the ADDR flag is cleared by software
setting the ADDRCF bit.
• In transmission, if the previous data transmission is completed and no new data is
written in I2C_TXDR register, or if the first data byte is not written when the ADDR flag
is cleared (TXE = 1). This stretch is released when the data is written to the I2C_TXDR
register.
• In reception when the I2C_RXDR register is not read yet and a new data reception is
completed. This stretch is released when I2C_RXDR is read.
• When TCR = 1 in Slave byte control mode, reload mode (SBC = 1 and RELOAD = 1),
meaning that the last data byte has been transferred. This stretch is released when
then TCR is cleared by writing a non-zero value in the NBYTES[7:0] field.
• After SCL falling edge detection, the I2C stretches SCL low during
[(SDADEL + SCLDEL + 1) x (PRESC+ 1) + 1] x tI2CCLK.

Slave without clock stretching (NOSTRETCH = 1)

When NOSTRETCH = 1 in the I2C_CR1 register, the I2C slave does not stretch the SCL
signal.
• The SCL clock is not stretched while the ADDR flag is set.
• In transmission, the data must be written in the I2C_TXDR register before the first SCL
pulse corresponding to its transfer occurs. If not, an underrun occurs, the OVR flag is
set in the I2C_ISR register and an interrupt is generated if the ERRIE bit is set in the
I2C_CR1 register. The OVR flag is also set when the first data transmission starts and
the STOPF bit is still set (has not been cleared). Therefore, if the user clears the
STOPF flag of the previous transfer only after writing the first data to be transmitted in
the next transfer, it ensures that the OVR status is provided, even for the first data to be
transmitted.
• In reception, the data must be read from the I2C_RXDR register before the ninth SCL
pulse (ACK pulse) of the next data byte occurs. If not, an overrun occurs, the OVR flag
is set in the I2C_ISR register, and an interrupt is generated if the ERRIE bit is set in the
I2C_CR1 register.

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Slave byte control mode

To allow byte ACK control in slave reception mode, the Slave byte control mode must be
enabled by setting the SBC bit in the I2C_CR1 register. This is required to be compliant with
SMBus standards.
The Reload mode must be selected to allow byte ACK control in slave reception mode
(RELOAD = 1). To get control of each byte, NBYTES must be initialized to 0x1 in the ADDR
interrupt subroutine, and reloaded to 0x1 after each received byte. When the byte is
received, the TCR bit is set, stretching the SCL signal low between the eighth and ninth SCL
pulses. The user can read the data from the I2C_RXDR register, and then decide to
acknowledge it or not by configuring the ACK bit in the I2C_CR2 register. The SCL stretch is
released by programming NBYTES to a non-zero value: the acknowledge or not-
acknowledge is sent, and the next byte can be received.
NBYTES can be loaded with a value greater than 0x1, and in this case, the reception flow is
continuous during NBYTES data reception.
Note: The SBC bit must be configured when the I2C is disabled, or when the slave is not
addressed, or when ADDR = 1.
The RELOAD bit value can be changed when ADDR = 1, or when TCR = 1.
Caution: The Slave byte control mode is not compatible with NOSTRETCH mode. Setting SBC when
NOSTRETCH = 1 is not allowed.

Figure 206. Slave initialization flow

Slave
initialization

Initial settings

Clear OA1EN and OA2EN in I2C_OAR1/I2C_OAR2

Configure OA1[9:0], OA1MODE, OA1EN, OA2[6:0],

OA2MSK[2:0], OA2EN, and GCEN

Optional: Configure SBC in I2C_CR1(1)

Enable interrupts and/or DMA in I2C_CR1

End
MS19850V3

1. SBC must be set to support SMBus features.

For a code example refer to A.11.3: I2C configured in slave mode.

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Slave transmitter
A transmit interrupt status (TXIS) is generated when the I2C_TXDR register becomes
empty. An interrupt is generated if the TXIE bit is set in the I2C_CR1 register.
The TXIS bit is cleared when the I2C_TXDR register is written with the next data byte to be
transmitted.
When a NACK is received, the NACKF bit is set in the I2C_ISR register, and an interrupt is
generated if the NACKIE bit is set in the I2C_CR1 register. The slave automatically releases
the SCL and SDA lines to let the master perform a STOP or a RESTART condition. The
TXIS bit is not set when a NACK is received.
When a STOP is received and the STOPIE bit is set in the I2C_CR1 register, the STOPF
flag is set in the I2C_ISR register and an interrupt is generated. In most applications, the
SBC bit is usually programmed to 0. In this case, If TXE = 0 when the slave address is
received (ADDR = 1), the user can choose either to send the content of the I2C_TXDR
register as the first data byte, or to flush the I2C_TXDR register by setting the TXE bit in
order to program a new data byte.
In Slave byte control mode (SBC = 1), the number of bytes to be transmitted must be
programmed in NBYTES in the address match interrupt subroutine (ADDR = 1). In this
case, the number of TXIS events during the transfer corresponds to the value programmed
in NBYTES.
Caution: When NOSTRETCH = 1, the SCL clock is not stretched while the ADDR flag is set, so the
user cannot flush the I2C_TXDR register content in the ADDR subroutine, to program the
first data byte. The first data byte to be sent must be previously programmed in the
I2C_TXDR register:
• This data can be the one written in the last TXIS event of the previous transmission
message.
• If this data byte is not the one to be sent, the I2C_TXDR register can be flushed by
setting the TXE bit in order to program a new data byte. The STOPF bit must be
cleared only after these actions, in order to guarantee that they are executed before the
first data transmission starts, following the address acknowledge.
If STOPF is still set when the first data transmission starts, an underrun error is
generated (the OVR flag is set).
If a TXIS event (transmit interrupt or transmit DMA request) is needed, the user must
set the TXIS bit in addition to the TXE bit, to generate the event.

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Figure 207. Transfer sequence flow for I2C slave transmitter, NOSTRETCH = 0

Slave
transmission

Slave initialization

No

I2C_ISR.ADDR
=1?

Yes
SCL
stretched
Read ADDCODE and DIR in I2C_ISR
Optional: Set I2C_ISR.TXE = 1
Set I2C_ICR.ADDRCF

No
I2C_ISR.TXIS
=1?

Yes

Write I2C_TXDR.TXDATA

MS19851V2

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Figure 208. Transfer sequence flow for I2C slave transmitter, NOSTRETCH = 1

Slave
transmission

Slave initialization

No
No
I2C_ISR.TXIS I2C_ISR.STOPF
=1? =1?

Yes Yes

Write I2C_TXDR.TXDATA Optional: Set I2C_ISR.TXE = 1

and I2C_ISR.TXIS=1

Set I2C_ICR.STOPCF

MS19852V2

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Figure 209. Transfer bus diagrams for I2C slave transmitter (mandatory events only)
legend:
Example I2C slave transmitter 3 bytes with 1st data flushed,
NOSTRETCH=0: transmission
ADDR TXIS TXIS TXIS TXIS reception

S Address A A A data3 NA P
SCL stretch
data1 data2

EV1 EV2 EV3 EV4 EV5

TXE

EV1: ADDR ISR: check ADDCODE and DIR, set TXE, set ADDRCF
EV2: TXIS ISR: wr data1
EV3: TXIS ISR: wr data2
EV4: TXIS ISR: wr data3
EV5: TXIS ISR: wr data4 (not sent)

legend :
Example I2C slave transmitter 3 bytes without 1st data flush,
NOSTRETCH=0: transmission
ADDR TXIS TXIS TXIS reception

SCL stretch
S Address A data1 A data2 A data3 NA P

EV1 EV2 EV3 EV4

TXE

EV1: ADDR ISR: check ADDCODE and DIR, set ADDRCF

EV2: TXIS ISR: wr data2
EV3: TXIS ISR: wr data3
EV4: TXIS ISR: wr data4 (not sent)

legend:
Example I2C slave transmitter 3 bytes, NOSTRETCH=1:
transmission
TXIS TXIS TXIS STOPF
reception

S Address A data1 A data2 A data3 NA P SCL stretch

EV1 EV2 EV3 EV4 EV5

TXE

EV1: wr data1
EV2: TXIS ISR: wr data2
EV3: TXIS ISR: wr data3
EV4: TXIS ISR: wr data4 (not sent)
EV5: STOPF ISR: (optional: set TXE and TXIS), set STOPCF

MS19853V2

For a code example refer to A.11.6: I2C slave transmitter.

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Slave receiver
RXNE is set in I2C_ISR when the I2C_RXDR is full, and generates an interrupt if RXIE is
set in I2C_CR1. RXNE is cleared when I2C_RXDR is read.
When a STOP is received and STOPIE is set in I2C_CR1, STOPF is set in I2C_ISR and an
interrupt is generated.

Figure 210. Transfer sequence flow for slave receiver with NOSTRETCH = 0

Slave reception

Slave initialization

No

I2C_ISR.ADDR
=1?

Yes
SCL
stretched
Read ADDCODE and DIR in I2C_ISR
Set I2C_ICR.ADDRCF

No
I2C_ISR.RXNE
=1?

Yes

Write I2C_RXDR.RXDATA

MS19855V2

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Figure 211. Transfer sequence flow for slave receiver with NOSTRETCH = 1

Slave reception

Slave initialization

No
No
I2C_ISR.RXNE I2C_ISR.STOPF
=1? =1?

Yes Yes

Read I2C_RXDR.RXDATA Set I2C_ICR.STOPCF

MS19856V2

Figure 212. Transfer bus diagrams for I2C slave receiver

(mandatory events only)

Example I2C slave receiver 3 bytes, NOSTRETCH = 0: Legend

Transmission
ADDR RXNE RXNE RXNE
Reception

S Address A data1 A data2 A data3 A SCL stretch

EV1 EV2 EV3 EV4

RXNE

EV1: ADDR ISR: check ADDCODE and DIR, set ADDRCF

EV2: RXNE ISR: rd data1
EV3: RXNE ISR: rd data2
EV4: RXNE ISR: rd data3

Example I2C slave receiver 3 bytes, NOSTRETCH = 1: Legend

Transmission
RXNE RXNE RXNE
Reception

S Address A data 1 A data 2 A data 3 A P SCL stretch

EV1 EV2 EV3

RXNE

EV1: RXNE ISR: rd data1

EV2: RXNE ISR: rd data2
EV3: RXNE ISR: rd data3
MS19857V4

For a code example refer to A.11.7: I2C slave receiver.

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22.4.10 I2C master mode

I2C master initialization
Before enabling the peripheral, the I2C master clock must be configured by setting the
SCLH and SCLL bits in the I2C_TIMINGR register.
The STM32CubeMX tool calculates and provides the I2C_TIMINGR content in the I2C
Configuration window.
A clock synchronization mechanism is implemented in order to support multi-master
environment and slave clock stretching.
In order to allow clock synchronization:
• The low level of the clock is counted using the SCLL counter, starting from the SCL low
level internal detection.
• The high level of the clock is counted using the SCLH counter, starting from the SCL
high level internal detection.
The I2C detects its own SCL low level after a tSYNC1 delay depending on the SCL falling
edge, SCL input noise filters (analog and digital), and SCL synchronization to the I2CxCLK
clock. The I2C releases SCL to high level once the SCLL counter reaches the value
programmed in the SCLL[7:0] bits in the I2C_TIMINGR register.
The I2C detects its own SCL high level after a tSYNC2 delay depending on the SCL rising
edge, SCL input noise filters (analog + digital) and SCL synchronization to I2CxCLK clock.
The I2C ties SCL to low level once the SCLH counter reaches the value programmed in the
SCLH[7:0] bits in the I2C_TIMINGR register.
Consequently the master clock period is:
tSCL = tSYNC1 + tSYNC2 + {[(SCLH+ 1) + (SCLL+ 1)] x (PRESC+ 1) x tI2CCLK}
The duration of tSYNC1 depends upon:
– SCL falling slope
– When enabled, input delay induced by the analog filter
– When enabled, input delay induced by the digital filter: DNF x tI2CCLK
– Delay due to SCL synchronization with I2CCLK clock (two to three I2CCLK
periods)
The duration of tSYNC2 depends upon:
– SCL rising slope
– When enabled, input delay induced by the analog filter
– When enabled, input delay induced by the digital filter: DNF x tI2CCLK
– Delay due to SCL synchronization with I2CCLK clock (two to three I2CCLK
periods)

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Figure 213. Master clock generation

SCL master clock generation

SCL high level detected

SCLH counter starts

tSYNC2 SCLH
SCLL
tSYNC1
SCL

SCL low level detected

SCL released
SCLL counter starts

SCL driven low

SCL master clock synchronization

SCL high level detected SCL high level detected SCL high level detected
SCLH counter starts SCLH counter starts SCLH counter starts

SCLH SCLH SCLH

SCLL SCLL

SCL driven low by SCL driven low by

another device another device
SCL low level detected
SCLL counter starts

SCL low level detected

SCLL counter starts SCL released

MS19858V1

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Caution: To be I2C or SMBus compliant, the master clock must respect the timings given in the
following table.

Table 74. I2C-SMBus specification clock timings

Standard- Fast-mode Fast-mode
SMBus
mode (Sm) (Fm) Plus (Fm+)
Symbol Parameter Unit
Min Max Min Max Min Max Min Max

fSCL SCL clock frequency - 100 - 400 - 1000 - 100 kHz

tHD:STA Hold time (repeated) START condition 4.0 - 0.6 - 0.26 - 4.0 -
Set-up time for a repeated START
tSU:STA 4.7 - 0.6 - 0.26 - 4.7 -
condition
tSU:STO Set-up time for STOP condition 4.0 - 0.6 - 0.26 - 4.0 -
µs
Bus free time between a STOP and
tBUF 4.7 - 1.3 - 0.5 - 4.7 -
START condition
tLOW Low period of the SCL clock 4.7 - 1.3 - 0.5 - 4.7 -
tHIGH Period of the SCL clock 4.0 - 0.6 - 0.26 - 4.0 50
tr Rise time of both SDA and SCL signals - 1000 - 300 - 120 - 1000
ns
tf Fall time of both SDA and SCL signals - 300 - 300 - 120 - 300

Note: SCLL and SCLH are also used to generate, respectively, the tBUF / tSU:STA and the
tHD:STA / tSU:STO timings.

Refer to Section 22.4.11 for examples of I2C_TIMINGR settings vs. I2CCLK frequency.

Master communication initialization (address phase)

To initiate the communication, program the following parameters for the addressed slave in
the I2C_CR2 register:
• Addressing mode (7-bit or 10-bit): ADD10
• Slave address to be sent: SADD[9:0]
• Transfer direction: RD_WRN
• In case of 10-bit address read: HEAD10R bit. HEAD10R must be configure to indicate
if the complete address sequence must be sent, or only the header in case of a
direction change.
• The number of bytes to be transferred: NBYTES[7:0]. If this number is equal to or
greater than 255 bytes, NBYTES[7:0] must initially be filled with 0xFF.
The user must then set the START bit in I2C_CR2 register. Changing all the above bits is
not allowed when START bit is set.
Then the master automatically sends the START condition followed by the slave address as
soon as it detects that the bus is free (BUSY = 0) and after a tBUF delay.
In case of an arbitration loss, the master automatically switches back to slave mode and can
acknowledge its own address if it is addressed as a slave.

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Note: The START bit is reset by hardware when the slave address is sent on the bus, whatever
the received acknowledge value. The START bit is also reset by hardware if an arbitration
loss occurs.
In 10-bit addressing mode, when the slave address first seven bits are NACKed by the
slave, the master relaunches automatically the slave address transmission until ACK is
received. In this case ADDRCF must be set if a NACK is received from the slave, to stop
sending the slave address.
If the I2C is addressed as a slave (ADDR = 1) while the START bit is set, the I2C switches to
slave mode, and the START bit is cleared, when the ADDRCF bit is set.
Note: The same procedure is applied for a repeated start condition. In this case BUSY = 1.

Figure 214. Master initialization flow

Master
initialization

Initial settings

Enable interrupts and/or DMA in I2C_CR1

End

MS19859V2

For code examples refer to A.11.1: I2C configured in master mode to receive and A.11.2:
I2C configured in master mode to transmit.

Initialization of a master receiver addressing a 10-bit address slave

• If the slave address is in 10-bit format, the user can choose to send the complete read
sequence by clearing the HEAD10R bit in the I2C_CR2 register. In this case the master
automatically sends the following complete sequence after the START bit is set:
(Re)Start + Slave address 10-bit header Write + Slave address second byte + (Re)Start
+ Slave address 10-bit header Read

Figure 215. 10-bit address read access with HEAD10R = 0

11110XX 0 11110XX 1

Slave address Slave address Slave address

S R/W A1 A2 Sr R/W A3 DATA A DATA A P
1st 7 bits 2nd byte 1st 7 bits

Write Read

MSv41066V1

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• If the master addresses a 10-bit address slave, transmits data to this slave and then
reads data from the same slave, a master transmission flow must be done first. Then a
repeated start is set with the 10-bit slave address configured with HEAD10R = 1. In this
case the master sends this sequence: ReStart + Slave address 10-bit header Read.

Figure 216. 10-bit address read access with HEAD10R = 1

11110XX 0

Slave address Slave address

S R/W A A DATA A DATA A/A
1st 7 bits 2nd byte

Write

11110XX 1
Slave address
Sr R/W A DATA A DATA A P
1st 7 bits

Read

MS19823V1

Master transmitter
In the case of a write transfer, the TXIS flag is set after each byte transmission, after the
ninth SCL pulse when an ACK is received.
A TXIS event generates an interrupt if the TXIE bit is set in the I2C_CR1 register. The flag is
cleared when the I2C_TXDR register is written with the next data byte to be transmitted.
The number of TXIS events during the transfer corresponds to the value programmed in
NBYTES[7:0]. If the total number of data bytes to be sent is greater than 255, reload mode
must be selected by setting the RELOAD bit in the I2C_CR2 register. In this case, when
NBYTES data have been transferred, the TCR flag is set and the SCL line is stretched low
until NBYTES[7:0] is written to a non-zero value.
The TXIS flag is not set when a NACK is received.
• When RELOAD = 0 and NBYTES data have been transferred:
– In automatic end mode (AUTOEND = 1), a STOP is automatically sent.
– In software end mode (AUTOEND = 0), the TC flag is set and the SCL line is
stretched low, to perform software actions:
A RESTART condition can be requested by setting the START bit in the I2C_CR2
register with the proper slave address configuration, and number of bytes to be
transferred. Setting the START bit clears the TC flag and the START condition is
sent on the bus.
A STOP condition can be requested by setting the STOP bit in the I2C_CR2
register. Setting the STOP bit clears the TC flag and the STOP condition is sent on
the bus.
• If a NACK is received: the TXIS flag is not set, and a STOP condition is automatically
sent after the NACK reception. the NACKF flag is set in the I2C_ISR register, and an
interrupt is generated if the NACKIE bit is set.

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Figure 217. Transfer sequence flow for I2C master transmitter for N ≤ 255 bytes

Master
transmission

Master initialization

NBYTES = N
AUTOEND = 0 for RESTART; 1 for STOP
Configure slave address
Set I2C_CR2.START

No

No
I2C_ISR.NACKF = I2C_ISR.TXIS
1? =1?

Yes Yes

Write I2C_TXDR
End

NBYTES No
transmitted?

Yes

Yes
I2C_ISR.TC =
1?

No Set I2C_CR2.START with

slave addess NBYTES ...

End

MS19860V2

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Figure 218. Transfer sequence flow for I2C master transmitter for N > 255 bytes

Master
transmission

Master initialization

NBYTES = 0xFF; N=N-255

RELOAD = 1
Configure slave address
Set I2C_CR2.START

No

No
I2C_ISR.NACKF I2C_ISR.TXIS
= 1? = 1?

Yes Yes

Write I2C_TXDR
End

No
NBYTES
transmitted ?

Yes

Yes
I2C_ISR.TC
= 1?

Set I2C_CR2.START
with slave addess No
NBYTES ...

I2C_ISR.TCR
= 1?

Yes
IF N< 256
NBYTES = N; N = 0; RELOAD = 0
AUTOEND = 0 for RESTART; 1 for STOP
End
ELSE
NBYTES = 0xFF; N = N-255
RELOAD = 1

MS19861V3

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Figure 219. Transfer bus diagrams for I2C master transmitter

(mandatory events only)

Example I2C master transmitter 2 bytes, automatic end mode (STOP)

legend:

TXIS TXIS transmission

reception
S Address A data1 A data2 A P
SCL stretch
INIT EV1 EV2

TXE

NBYTES xx 2

INIT: program Slave address, program NBYTES = 2, AUTOEND=1, set START

EV1: TXIS ISR: wr data1
EV2: TXIS ISR: wr data2

Example I2C master transmitter 2 bytes, software end mode (RESTART)

TXIS TXIS TC legend:

transmission
S Address A data1 A data2 A ReS Address
reception

INIT EV1 EV2 EV3 SCL stretch

TXE

NBYTES xx 2

INIT: program Slave address, program NBYTES = 2, AUTOEND=0, set START

EV1: TXIS ISR: wr data1
EV2: TXIS ISR: wr data2
EV3: TC ISR: program Slave address, program NBYTES = N, set START

MS19862V2

For a code example refer to A.11.4: I2C master transmitter.

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Master receiver
In the case of a read transfer, the RXNE flag is set after each byte reception, after the eighth
SCL pulse. An RXNE event generates an interrupt if the RXIE bit is set in the I2C_CR1
register. The flag is cleared when I2C_RXDR is read.
If the total number of data bytes to be received is greater than 255, reload mode must be
selected by setting the RELOAD bit in the I2C_CR2 register. In this case, when
NBYTES[7:0] data have been transferred, the TCR flag is set and the SCL line is stretched
low until NBYTES[7:0] is written to a non-zero value.
• When RELOAD = 0 and NBYTES[7:0] data have been transferred:
– In automatic end mode (AUTOEND = 1), a NACK and a STOP are automatically
sent after the last received byte.
– In software end mode (AUTOEND = 0), a NACK is automatically sent after the last
received byte, the TC flag is set and the SCL line is stretched low in order to allow
software actions:
A RESTART condition can be requested by setting the START bit in the I2C_CR2
register with the proper slave address configuration, and number of bytes to be
transferred. Setting the START bit clears the TC flag and the START condition,
followed by slave address, are sent on the bus.
A STOP condition can be requested by setting the STOP bit in the I2C_CR2
register. Setting the STOP bit clears the TC flag and the STOP condition is sent on
the bus.

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Figure 220. Transfer sequence flow for I2C master receiver for N ≤ 255 bytes

Master reception

Master initialization

NBYTES = N
AUTOEND = 0 for RESTART; 1 for STOP
Configure slave address
Set I2C_CR2.START

No
I2C_ISR.RXNE
=1?

Yes

Read I2C_RXDR

NBYTES No
received?

Yes

Yes
I2C_ISR.TC =
1?

No Set I2C_CR2.START with

slave addess NBYTES ...

End

MS19863V2

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Figure 221. Transfer sequence flow for I2C master receiver for N > 255 bytes

Master reception

Master initialization

NBYTES = 0xFF; N=N-255

RELOAD =1
Configure slave address
Set I2C_CR2.START

No
I2C_ISR.RXNE
=1?

Yes

Read I2C_RXDR

NBYTES No
received?

Yes

Yes
I2C_ISR.TC =
1?

Set I2C_CR2.START with

No
slave addess NBYTES ...
No
I2C_ISR.TCR
= 1?

Yes
IF N< 256
NBYTES =N; N=0;RELOAD=0
AUTOEND=0 for RESTART; 1 for STOP
ELSE
NBYTES =0xFF;N=N-255
RELOAD=1

End

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Figure 222. Transfer bus diagrams for I2C master receiver

(mandatory events only)

Example I2C master receiver 2 bytes, automatic end mode (STOP)

RXNE RXNE
legend:

S Address A data1 A data2 NA P transmission

reception
INIT EV1 EV2
SCL stretch
NBYTES xx 2

INIT: program Slave address, program NBYTES = 2, AUTOEND=1, set START

EV1: RXNE ISR: rd data1
EV2: RXNE ISR: rd data2

Example I2C master receiver 2 bytes, software end mode (RESTART)

RXNE RXNE TC legend:

transmission
S Address A data1 A data2 NA ReS Address
reception

INIT EV1 EV2 SCL stretch

NBYTES

xx 2 N

INIT: program Slave address, program NBYTES = 2, AUTOEND=0, set START

EV1: RXNE ISR: rd data1
EV2: RXNE ISR: read data2
EV3: TC ISR: program Slave address, program NBYTES = N, set START

MS19865V1

For a code example refer to A.11.5: I2C master receiver.

22.4.11 I2C_TIMINGR register configuration examples

The following tables provide examples of how to program the I2C_TIMINGR to obtain
timings compliant with the I2C specification. To get more accurate configuration values, use
the STM32CubeMX tool (I2C Configuration window).

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Table 75. Examples of timing settings for fI2CCLK = 8 MHz

Standard-mode (Sm) Fast-mode (Fm) Fast-mode Plus (Fm+)
Parameter
10 kHz 100 kHz 400 kHz 500 kHz

PRESC 0x1 0x1 0x0 0x0

SCLL 0xC7 0x13 0x9 0x6
tSCLL 200 x 250 ns = 50 µs 20 x 250 ns = 5.0 µs 10 x 125 ns = 1250 ns 7 x 125 ns = 875 ns
SCLH 0xC3 0xF 0x3 0x3
tSCLH 196 x 250 ns = 49 µs 16 x 250 ns = 4.0µs 4 x 125 ns = 500 ns 4 x 125 ns = 500 ns
(1) (2) (2) (3)
tSCL ~100 µs ~10 µs ~2.5 µs ~2.0 µs(4)
SDADEL 0x2 0x2 0x1 0x0
tSDADEL 2 x 250 ns = 500 ns 2 x 250 ns = 500 ns 1 x 125 ns = 125 ns 0 ns
SCLDEL 0x4 0x4 0x3 0x1
tSCLDEL 5 x 250 ns = 1250 ns 5 x 250 ns = 1250 ns 4 x 125 ns = 500 ns 2 x 125 ns = 250 ns
1. tSCL is greater than tSCLL + tSCLH due to SCL internal detection delay. Values provided for tSCL are examples only.
2. tSYNC1 + tSYNC2 minimum value is 4 x tI2CCLK = 500 ns. Example with tSYNC1 + tSYNC2 = 1000 ns.
3. tSYNC1 + tSYNC2 minimum value is 4 x tI2CCLK = 500 ns. Example with tSYNC1 + tSYNC2 = 750 ns.
4. tSYNC1 + tSYNC2 minimum value is 4 x tI2CCLK = 500 ns. Example with tSYNC1 + tSYNC2 = 655 ns.

Table 76. Examples of timing settings for fI2CCLK = 16 MHz

Standard-mode (Sm) Fast-mode (Fm) Fast-mode Plus (Fm+)
Parameter
10 kHz 100 kHz 400 kHz 1000 kHz

PRESC 0x3 0x3 0x1 0x0

SCLL 0xC7 0x13 0x9 0x4
tSCLL 200 x 250 ns = 50 µs 20 x 250 ns = 5.0 µs 10 x 125 ns = 1250 ns 5 x 62.5 ns = 312.5 ns
SCLH 0xC3 0xF 0x3 0x2
tSCLH 196 x 250 ns = 49 µs 16 x 250 ns = 4.0 µs 4 x 125 ns = 500 ns 3 x 62.5 ns = 187.5 ns
(1) µs(2) µs(2) µs(3) ~1.0 µs(4)
tSCL ~100 ~10 ~2.5
SDADEL 0x2 0x2 0x2 0x0
tSDADEL 2 x 250 ns = 500 ns 2 x 250 ns = 500 ns 2 x 125 ns = 250 ns 0 ns
SCLDEL 0x4 0x4 0x3 0x2
tSCLDEL 5 x 250 ns = 1250 ns 5 x 250 ns = 1250 ns 4 x 125 ns = 500 ns 3 x 62.5 ns = 187.5 ns
1. tSCL is greater than tSCLL + tSCLH due to SCL internal detection delay. Values provided for tSCL are examples only.
2. tSYNC1 + tSYNC2 minimum value is 4 x tI2CCLK = 250 ns. Example with tSYNC1 + tSYNC2 = 1000 ns.
3. tSYNC1 + tSYNC2 minimum value is 4 x tI2CCLK = 250 ns. Example with tSYNC1 + tSYNC2 = 750 ns.
4. tSYNC1 + tSYNC2 minimum value is 4 x tI2CCLK = 250 ns. Example with tSYNC1 + tSYNC2 = 500 ns.

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Table 77. Examples of timing settings for fI2CCLK = 48 MHz

Standard-mode (Sm) Fast-mode (Fm) Fast-mode Plus (Fm+)
Parameter
10 kHz 100 kHz 400 kHz 1000 kHz

PRESC 0xB 0xB 0x5 0x5

SCLL 0xC7 0x13 0x9 0x3
tSCLL 200 x 250 ns = 50 µs 20 x 250 ns = 5.0 µs 10 x 125 ns = 1250 ns 4 x 125 ns = 500 ns
SCLH 0xC3 0xF 0x3 0x1
tSCLH 196 x 250 ns = 49 µs 16 x 250 ns = 4.0 µs 4 x 125 ns = 500 ns 2 x 125 ns = 250 ns
(1) (2) (2) (3)
tSCL ~100 µs ~10 µs ~2.5 µs ~875 ns(4)
SDADEL 0x2 0x2 0x3 0x0
tSDADEL 2 x 250 ns = 500 ns 2 x 250 ns = 500 ns 3 x 125 ns = 375 ns 0 ns
SCLDEL 0x4 0x4 0x3 0x1
tSCLDEL 5 x 250 ns = 1250 ns 5 x 250 ns = 1250 ns 4 x 125 ns = 500 ns 2 x 125 ns = 250 ns
1. tSCL is greater than tSCLL + tSCLH due to the SCL internal detection delay. Values provided for tSCL are only examples.
2. tSYNC1 + tSYNC2 minimum value is 4x tI2CCLK = 83.3 ns. Example with tSYNC1 + tSYNC2 = 1000 ns
3. tSYNC1 + tSYNC2 minimum value is 4x tI2CCLK = 83.3 ns. Example with tSYNC1 + tSYNC2 = 750 ns
4. tSYNC1 + tSYNC2 minimum value is 4x tI2CCLK = 83.3 ns. Example with tSYNC1 + tSYNC2 = 250 ns

22.4.12 SMBus specific features

This section is relevant only when the SMBus feature is supported (refer to Section 22.3).

Introduction
The system management bus (SMBus) is a two-wire interface through which various
devices can communicate with each other and with the rest of the system. It is based on I2C
principles of operation. The SMBus provides a control bus for system and power
management related tasks.
This peripheral is compatible with the SMBus specification (http://smbus.org).
The system management bus specification refers to three types of devices
• A slave is a device that receives or responds to a command.
• A master is a device that issues commands, generates the clocks, and terminates the
transfer.
• A host is a specialized master that provides the main interface to the system’s CPU. A
host must be a master-slave and must support the SMBus host notify protocol. Only
one host is allowed in a system.
This peripheral can be configured as master or slave device, and also as a host.

Bus protocols
There are eleven possible command protocols for any given device. A device can use any
or all of them to communicate. The protocols are Quick Command, Send Byte, Receive
Byte, Write Byte, Write Word, Read Byte, Read Word, Process Call, Block Read, Block

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Write, and Block Write-Block Read Process Call. These protocols must be implemented by
the user software.
For more details on these protocols, refer to SMBus specification (http://smbus.org).

Address resolution protocol (ARP)

SMBus slave address conflicts can be resolved by dynamically assigning a new unique
address to each slave device. To provide a mechanism to isolate each device for the
purpose of address assignment, each device must implement a unique device identifier
(UDID). This 128-bit number is implemented by software.
This peripheral supports the Address Resolution Protocol (ARP). The SMBus Device
Default Address (0b1100 001) is enabled by setting SMBDEN bit in I2C_CR1 register. The
ARP commands must be implemented by the user software.
Arbitration is also performed in slave mode for ARP support.
For more details of the SMBus address resolution protocol, refer to SMBus specification
(http://smbus.org).

Received command and data acknowledge control

A SMBus receiver must be able to NACK each received command or data. In order to allow
the ACK control in slave mode, the Slave byte control mode must be enabled by setting
SBC bit in I2C_CR1 register. Refer to Slave byte control mode for more details.

Host notify protocol

This peripheral supports the host notify protocol by setting the SMBHEN bit in the I2C_CR1
register. In this case the host acknowledges the SMBus host address (0b0001 000).
When this protocol is used, the device acts as a master and the host as a slave.

SMBus alert
The SMBus ALERT optional signal is supported. A slave-only device can signal the host
through the SMBALERT# pin that it wants to talk. The host processes the interrupt and
simultaneously accesses all SMBALERT# devices through the alert response address
(0b0001 100). Only the device(s) which pulled SMBALERT# low acknowledges the alert
response address.
When configured as a slave device(SMBHEN = 0), the SMBA pin is pulled low by setting the
ALERTEN bit in the I2C_CR1 register. The Alert Response Address is enabled at the same
time.
When configured as a host (SMBHEN = 1), the ALERT flag is set in the I2C_ISR register
when a falling edge is detected on the SMBA pin and ALERTEN = 1. An interrupt is
generated if the ERRIE bit is set in the I2C_CR1 register. When ALERTEN = 0, the ALERT
line is considered high even if the external SMBA pin is low.
If the SMBus ALERT pin is not needed, the SMBA pin can be used as a standard GPIO if
ALERTEN = 0.

Packet error checking

A packet error checking mechanism has been introduced in the SMBus specification to
improve reliability and communication robustness. The packet error checking is
implemented by appending a packet error code (PEC) at the end of each message transfer.

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The PEC is calculated by using the C(x) = x8 + x2 + x + 1 CRC-8 polynomial on all the
message bytes (including addresses and read/write bits).
The peripheral embeds a hardware PEC calculator and allows a not acknowledge to be sent
automatically when the received byte does not match with the hardware calculated PEC.

Timeouts
This peripheral embeds hardware timers to be compliant with the three timeouts defined in
the SMBus specification.

Table 78. SMBus timeout specifications

Limits
Symbol Parameter Unit
Min Max

tTIMEOUT Detect clock low timeout 25 35

tLOW:SEXT(1) Cumulative clock low extend time (slave device) - 25 ms
tLOW:MEXT(2) Cumulative clock low extend time (master device) - 10
1. tLOW:SEXT is the cumulative time a given slave device is allowed to extend the clock cycles in one message
from the initial START to the STOP. It is possible that another slave device or the master also extends the
clock causing the combined clock low extend time to be greater than tLOW:SEXT. Therefore, this parameter is
measured with the slave device as the sole target of a full-speed master.
2. tLOW:MEXT is the cumulative time a master device is allowed to extend its clock cycles within each byte of a
message as defined from START-to-ACK, ACK-to-ACK, or ACK-to-STOP. It is possible that a slave device
or another master also extends the clock, causing the combined clock low time to be greater than tLOW:MEXT
on a given byte. Therefore, this parameter is measured with a full speed slave device as the sole target of
the master.

Figure 223. Timeout intervals for tLOW:SEXT, tLOW:MEXT

Start Stop
tLOW:SEXT

ClkAck ClkAck
tLOW:MEXT tLOW:MEXT tLOW:MEXT

SMBCLK

SMBDAT

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Bus idle detection

A master can assume that the bus is free if it detects that the clock and data signals have
been high for tIDLE > tHIGH,MAX (refer to I2C timings).
This timing parameter covers the condition where a master has been dynamically added to
the bus, and may not have detected a state transition on the SMBCLK or SMBDAT lines. In
this case, the master must wait long enough to ensure that a transfer is not currently in
progress. The peripheral supports a hardware bus idle detection.

22.4.13 SMBus initialization

This section is relevant only when SMBus feature is supported (see Section 22.3).
In addition to I2C initialization, some other specific initialization must be done to perform
SMBus communication.

Received command and data acknowledge control (slave mode)

A SMBus receiver must be able to NACK each received command or data. To allow ACK
control in slave mode, the Slave byte control mode must be enabled by setting the SBC bit
in the I2C_CR1 register. Refer to Slave byte control mode for more details.

Specific address (slave mode)

The specific SMBus addresses must be enabled if needed. Refer to Bus idle detection for
more details.
• The SMBus device default address (0b1100 001) is enabled by setting the SMBDEN
bit in the I2C_CR1 register.
• The SMBus host address (0b0001 000) is enabled by setting the SMBHEN bit in the
I2C_CR1 register.
• The alert response address (0b0001100) is enabled by setting the ALERTEN bit in the
I2C_CR1 register.

Packet error checking

PEC calculation is enabled by setting the PECEN bit in the I2C_CR1 register. Then the PEC
transfer is managed with the help of the hardware byte counter NBYTES[7:0] in the
I2C_CR2 register. The PECEN bit must be configured before enabling the I2C.
The PEC transfer is managed with the hardware byte counter, so the SBC bit must be set
when interfacing the SMBus in slave mode. The PEC is transferred after NBYTES - 1 data
have been transferred when the PECBYTE bit is set and the RELOAD bit is cleared. If
RELOAD is set, PECBYTE has no effect.
Caution: Changing the PECEN configuration is not allowed when the I2C is enabled.

Table 79. SMBus with PEC configuration

Mode SBC bit RELOAD bit AUTOEND bit PECBYTE bit

Master Tx/Rx NBYTES + PEC+ STOP x 0 1 1

Master Tx/Rx NBYTES + PEC + ReSTART x 0 0 1
Slave Tx/Rx with PEC 1 0 x 1

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Timeout detection
The timeout detection is enabled by setting the TIMOUTEN and TEXTEN bits in the
I2C_TIMEOUTR register. The timers must be programmed in such a way that they detect a
timeout before the maximum time given in the SMBus specification.
• tTIMEOUT check
To enable the tTIMEOUT check, the 12-bit TIMEOUTA[11:0] bits must be programmed
with the timer reload value, to check the tTIMEOUT parameter. The TIDLE bit must be
configured to 0 to detect the SCL low level timeout.
Then the timer is enabled by setting the TIMOUTEN in the I2C_TIMEOUTR register.
If SCL is tied low for a time greater than (TIMEOUTA + 1) x 2048 x tI2CCLK, the
TIMEOUT flag is set in the I2C_ISR register.
Refer to Table 80.
Caution: Changing the TIMEOUTA[11:0] bits and TIDLE bit configuration is not allowed when the
TIMEOUTEN bit is set.
• tLOW:SEXT and tLOW:MEXT check
Depending on if the peripheral is configured as a master or as a slave, the 12-bit
TIMEOUTB timer must be configured to check tLOW:SEXT for a slave, and tLOW:MEXT for a
master. As the standard specifies only a maximum, the user can choose the same
value for both. The timer is then enabled by setting the TEXTEN bit in the
I2C_TIMEOUTR register.
If the SMBus peripheral performs a cumulative SCL stretch for a time greater than
(TIMEOUTB + 1) x 2048 x tI2CCLK, and in the timeout interval described in Bus idle
detection section, the TIMEOUT flag is set in the I2C_ISR register.
Refer to Table 81
Caution: Changing the TIMEOUTB configuration is not allowed when the TEXTEN bit is set.

Bus idle detection

To enable the tIDLE check, the 12-bit TIMEOUTA[11:0] field must be programmed with the
timer reload value, to obtain the tIDLE parameter. The TIDLE bit must be configured to ‘1 to
detect both SCL and SDA high level timeout. The timer is then enabled by setting the
TIMOUTEN bit in the I2C_TIMEOUTR register.
If both the SCL and SDA lines remain high for a time greater than
(TIMEOUTA + 1) x 4 x tI2CCLK, the TIMEOUT flag is set in the I2C_ISR register.
Refer to Table 82.
Caution: Changing TIMEOUTA and TIDLE configuration is not allowed when TIMEOUTEN is set.

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22.4.14 SMBus: I2C_TIMEOUTR register configuration examples

This section is relevant only when SMBus feature is supported. Refer to Section 22.3.
• Configuring the maximum duration of tTIMEOUT to 25 ms:

Table 80. Examples of TIMEOUTA settings (max tTIMEOUT = 25 ms)

fI2CCLK TIMEOUTA[11:0] bits TIDLE bit TIMEOUTEN bit tTIMEOUT
8 MHz 0x61 0 1 98 x 2048 x 125 ns = 25 ms
16 MHz 0xC3 0 1 196 x 2048 x 62.5 ns = 25 ms
48 MHz 0x249 0 1 586 x 2048 x 20.08 ns = 25 ms

• Configuring the maximum duration of tLOW:SEXT and tLOW:MEXT to 8 ms:

Table 81. Examples of TIMEOUTB settings

fI2CCLK TIMEOUTB[11:0] bits TEXTEN bit tLOW:EXT
8 MHz 0x1F 1 32 x 2048 x 125 ns = 8 ms
16 MHz 0x3F 1 64 x 2048 x 62.5 ns = 8 ms
48 MHz 0xBB 1 188 x 2048 x 20.08 ns = 8 ms

• Configuring the maximum duration of tIDLE to 50 µs

Table 82. Examples of TIMEOUTA settings (max tIDLE = 50 µs)

fI2CCLK TIMEOUTA[11:0] bits TIDLE bit TIMEOUTEN bit tTIDLE
8 MHz 0x63 1 1 100 x 4 x 125 ns = 50 µs
16 MHz 0xC7 1 1 200 x 4 x 62.5 ns = 50 µs
48 MHz 0x257 1 1 600 x 4 x 20.08 ns = 50 µs

22.4.15 SMBus slave mode

This section is relevant only when the SMBus feature is supported (refer to Section 22.3).
In addition to I2C slave transfer management (refer to Section 22.4.9), additional software
flows are provided to support the SMBus.

SMBus slave transmitter

When the IP is used in SMBus, SBC must be programmed to 1 to enable the PEC
transmission at the end of the programmed number of data bytes. When the PECBYTE bit
is set, the number of bytes programmed in NBYTES[7:0] includes the PEC transmission. In
that case the total number of TXIS interrupts is NBYTES - 1, and the content of the
I2C_PECR register is automatically transmitted if the master requests an extra byte after the
NBYTES - 1 data transfer.
Caution: The PECBYTE bit has no effect when the RELOAD bit is set.

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Figure 224. Transfer sequence flow for SMBus slave transmitter N bytes + PEC

SMBus slave
transmission

Slave initialization

No

I2C_ISR.ADDR =
1?

Yes

Read ADDCODE and DIR in I2C_ISR SCL

I2C_CR2.NBYTES = N + 1 stretched
PECBYTE=1
Set I2C_ICR.ADDRCF

No
I2C_ISR.TXIS
=1?

Yes

Write I2C_TXDR.TXDATA

MS19867V2

Figure 225. Transfer bus diagrams for SMBus slave transmitter (SBC = 1)
legend:
Example SMBus slave transmitter 2 bytes + PEC,
transmission
ADDR TXIS TXIS reception

S Address A data1 A A PEC NA P

SCL stretch
data2

EV1 EV2 EV3

NBYTES 3

EV1: ADDR ISR: check ADDCODE, program NBYTES=3, set PECBYTE, set ADDRCF
EV2: TXIS ISR: wr data1
EV3: TXIS ISR: wr data2

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SMBus slave receiver

When the I2C is used in SMBus mode, SBC must be programmed to 1 to allow the PEC
checking at the end of the programmed number of data bytes. To allow the ACK control of
each byte, the reload mode must be selected (RELOAD = 1). Refer to Slave byte control
mode for more details.
To check the PEC byte, the RELOAD bit must be cleared and the PECBYTE bit must be set.
In this case, after NBYTES - 1 data have been received, the next received byte is compared
with the internal I2C_PECR register content. A NACK is automatically generated if the
comparison does not match, and an ACK is automatically generated if the comparison
matches, whatever the ACK bit value. Once the PEC byte is received, it is copied into the
I2C_RXDR register like any other data, and the RXNE flag is set.
In the case of a PEC mismatch, the PECERR flag is set and an interrupt is generated if the
ERRIE bit is set in the I2C_CR1 register.
If no ACK software control is needed, the user can program PECBYTE = 1 and, in the same
write operation, program NBYTES with the number of bytes to be received in a continuous
flow. After NBYTES - 1 are received, the next received byte is checked as being the PEC.
Caution: The PECBYTE bit has no effect when the RELOAD bit is set.

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Figure 226. Transfer sequence flow for SMBus slave receiver N bytes + PEC

SMBus slave
reception

Slave initialization

No

I2C_ISR.ADDR =
1?

Yes

Read ADDCODE and DIR in I2C_ISR SCL

I2C_CR2.NBYTES = 1, RELOAD =1 stretched
PECBYTE=1
Set I2C_ICR.ADDRCF

No
I2C_ISR.RXNE =1?
I2C_ISR.TCR = 1?

Yes
Read I2C_RXDR.RXDATA
Program I2C_CR2.NACK = 0
I2C_CR2.NBYTES = 1
N=N-1

No
N = 1?

Yes
Read I2C_RXDR.RXDATA
Program RELOAD = 0
NACK = 0 and NBYTES = 1

No
I2C_ISR.RXNE =1?

Yes
Read I2C_RXDR.RXDATA

End
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Figure 227. Bus transfer diagrams for SMBus slave receiver (SBC = 1)
legend:
Example SMBus slave receiver 2 bytes + PEC
transmission
ADDR RXNE RXNE RXNE
reception

S Address A data1 A data2 A PEC A P SCL stretch

EV1 EV2 EV3 EV4

NBYTES 3

EV1: ADDR ISR: check ADDCODE and DIR, program NBYTES = 3, PECBYTE=1, RELOAD=0, set ADDRCF
EV2: RXNE ISR: rd data1
EV3: RXNE ISR: rd data2
EV4: RXNE ISR: rd PEC

Example SMBus slave receiver 2 bytes + PEC, with ACK control legend :

(RELOAD=1/0) transmission
ADDR RXNE,TCR RXNE,TCR RXNE
reception

S Address A data1 A data2 A PEC A P SCL stretch

EV1 EV2 EV3 EV4

NBYTES 1

EV1: ADDR ISR: check ADDCODE and DIR, program NBYTES = 1, PECBYTE=1, RELOAD=1, set ADDRCF
EV2: RXNE-TCR ISR: rd data1, program NACK=0 and NBYTES = 1
EV3: RXNE-TCR ISR: rd data2, program NACK=0, NBYTES = 1 and RELOAD=0
EV4: RXNE-TCR ISR: rd PEC

MS19870V2

This section is relevant only when the SMBus feature is supported (refer to Section 22.3).
In addition to I2C master transfer management (refer to Section 22.4.10), additional
software flows are provided to support the SMBus.

SMBus master transmitter

When the SMBus master wants to transmit the PEC, the PECBYTE bit must be set and the
number of bytes must be programmed in the NBYTES[7:0] field, before setting the START
bit. In this case the total number of TXIS interrupts is NBYTES - 1. So if the PECBYTE bit is
set when NBYTES = 0x1, the content of the I2C_PECR register is automatically transmitted.
If the SMBus master wants to send a STOP condition after the PEC, automatic end mode
must be selected (AUTOEND = 1). In this case, the STOP condition automatically follows
the PEC transmission.
When the SMBus master wants to send a RESTART condition after the PEC, software
mode must be selected (AUTOEND = 0). In this case, once NBYTES - 1 have been

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transmitted, the I2C_PECR register content is transmitted and the TC flag is set after the
PEC transmission, stretching the SCL line low. The RESTART condition must be
programmed in the TC interrupt subroutine.
Caution: The PECBYTE bit has no effect when the RELOAD bit is set.

Figure 228. Bus transfer diagrams for SMBus master transmitter

Example SMBus master transmitter 2 bytes + PEC, automatic end mode (STOP)

TXIS TXIS
legend:

S Address A data1 A data2 A PEC A P transmission

reception
INIT EV1 EV2
SCL stretch
TXE

NBYTES xx 3

INIT: program Slave address, program NBYTES = 3, AUTOEND=1, set PECBYTE, set START
EV1: TXIS ISR: wr data1
EV2: TXIS ISR: wr data2

Example SMBus master transmitter 2 bytes + PEC, software end mode (RESTART)

TC legend:
TXIS TXIS
transmission
S Address A data1 A data2 A PEC A Rstart Address
reception

INIT EV1 EV2 EV3 SCL stretch

xx 3 N

NBYTES

INIT: program Slave address, program NBYTES = 3, AUTOEND=0, set PECBYTE, set START
EV1: TXIS ISR: wr data1
EV2: TXIS ISR: wr data2
EV3: TC ISR: program Slave address, program NBYTES = N, set START

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SMBus master receiver

When the SMBus master wants to receive the PEC followed by a STOP at the end of the
transfer, automatic end mode can be selected (AUTOEND = 1). The PECBYTE bit must be
set and the slave address must be programmed, before setting the START bit. In this case,
after NBYTES - 1 data have been received, the next received byte is automatically checked
versus the I2C_PECR register content. A NACK response is given to the PEC byte, followed
by a STOP condition.
When the SMBus master receiver wants to receive the PEC byte followed by a RESTART
condition at the end of the transfer, software mode must be selected (AUTOEND = 0). The
PECBYTE bit must be set and the slave address must be programmed, before setting the
START bit. In this case, after NBYTES - 1 data have been received, the next received byte
is automatically checked versus the I2C_PECR register content. The TC flag is set after the
PEC byte reception, stretching the SCL line low. The RESTART condition can be
programmed in the TC interrupt subroutine.
Caution: The PECBYTE bit has no effect when the RELOAD bit is set.

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Figure 229. Bus transfer diagrams for SMBus master receiver

Example SMBus master receiver 2 bytes + PEC, automatic end mode (STOP)

RXNE RXNE RXNE

legend:

S Address A data1 A data2 A PEC NA P transmission

reception
INIT EV1 EV2 EV3
SCL stretch
NBYTES xx 3

INIT: program Slave address, program NBYTES = 3, AUTOEND=1, set PECBYTE, set START
EV1: RXNE ISR: rd data1
EV2: RXNE ISR: rd data2
EV3: RXNE ISR: rd PEC

Example SMBus master receiver 2 bytes + PEC, software end mode (RESTART)

RXNE RXNE RXNE TC legend:

transmission
S Address A data1 A data2 A PEC NA Restart Address
reception

INIT EV1 EV2 EV3 EV4 SCL stretch

NBYTES

xx 3 N

INIT: program Slave address, program NBYTES = 3, AUTOEND=0, set PECBYTE, set START
EV1: RXNE ISR: rd data1
EV2: RXNE ISR: rd data2
EV3: RXNE ISR: read PEC
EV4: TC ISR: program Slave address, program NBYTES = N, set START

MS19872V2

22.4.16 Error conditions

The following errors are the conditions that can cause a communication fail.

Bus error (BERR)

A bus error is detected when a START or a STOP condition is detected and is not located
after a multiple of nine SCL clock pulses. A START or a STOP condition is detected when
an SDA edge occurs while SCL is high.
The bus error flag is set only if the I2C is involved in the transfer as master or addressed
slave (i.e not during the address phase in slave mode).
In case of a misplaced START or RESTART detection in slave mode, the I2C enters
address recognition state like for a correct START condition.

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When a bus error is detected, the BERR flag is set in the I2C_ISR register, and an interrupt
is generated if the ERRIE bit is set in the I2C_CR1 register.

Arbitration lost (ARLO)

An arbitration loss is detected when a high level is sent on the SDA line, but a low level is
sampled on the SCL rising edge.
• In master mode, arbitration loss is detected during the address phase, data phase and
data acknowledge phase. In this case, the SDA and SCL lines are released, the
START control bit is cleared by hardware and the master switches automatically to
slave mode.
• In slave mode, arbitration loss is detected during data phase and data acknowledge
phase. In this case, the transfer is stopped, and the SCL and SDA lines are released.
When an arbitration loss is detected, the ARLO flag is set in the I2C_ISR register, and an
interrupt is generated if the ERRIE bit is set in the I2C_CR1 register.

Overrun/underrun error (OVR)

An overrun or underrun error is detected in slave mode when NOSTRETCH = 1 and:
• In reception when a new byte is received and the RXDR register has not been read yet.
The new received byte is lost, and a NACK is automatically sent as a response to the
new byte.
• In transmission:
– When STOPF = 1 and the first data byte must be sent. The content of the
I2C_TXDR register is sent if TXE = 0, 0xFF if not.
– When a new byte must be sent and the I2C_TXDR register has not been written
yet, 0xFF is sent.
When an overrun or underrun error is detected, the OVR flag is set in the I2C_ISR register,
and an interrupt is generated if the ERRIE bit is set in the I2C_CR1 register.

Packet error checking error (PECERR)

This section is relevant only when the SMBus feature is supported (refer to Section 22.3).
A PEC error is detected when the received PEC byte does not match with the I2C_PECR
register content. A NACK is automatically sent after the wrong PEC reception.
When a PEC error is detected, the PECERR flag is set in the I2C_ISR register, and an
interrupt is generated if the ERRIE bit is set in the I2C_CR1 register.

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Timeout error (TIMEOUT)

This section is relevant only when the SMBus feature is supported (refer to Section 22.3).
A timeout error occurs for any of these conditions:
• TIDLE = 0 and SCL remained low for the time defined in the TIMEOUTA[11:0] bits: this
is used to detect an SMBus timeout.
• TIDLE = 1 and both SDA and SCL remained high for the time defined in the
TIMEOUTA [11:0] bits: this is used to detect a bus idle condition.
• Master cumulative clock low extend time reached the time defined in the
TIMEOUTB[11:0] bits (SMBus tLOW:MEXT parameter).
• Slave cumulative clock low extend time reached the time defined in TIMEOUTB[11:0]
bits (SMBus tLOW:SEXT parameter).
When a timeout violation is detected in master mode, a STOP condition is automatically
sent.
When a timeout violation is detected in slave mode, SDA and SCL lines are automatically
released.
When a timeout error is detected, the TIMEOUT flag is set in the I2C_ISR register, and an
interrupt is generated if the ERRIE bit is set in the I2C_CR1 register.

Alert (ALERT)
This section is relevant only when the SMBus feature is supported (refer to Section 22.3).
The ALERT flag is set when the I2C interface is configured as a Host (SMBHEN = 1), the
alert pin detection is enabled (ALERTEN = 1) and a falling edge is detected on the SMBA
pin. An interrupt is generated if the ERRIE bit is set in the I2C_CR1 register.

22.4.17 DMA requests

Transmission using DMA
DMA (direct memory access) can be enabled for transmission by setting the TXDMAEN bit
in the I2C_CR1 register. Data is loaded from an SRAM area configured using the DMA
peripheral (see Section 10: Direct memory access controller (DMA)) to the I2C_TXDR
register whenever the TXIS bit is set.
Only the data are transferred with DMA.
• In master mode: the initialization, the slave address, direction, number of bytes and
START bit are programmed by software (the transmitted slave address cannot be
transferred with DMA). When all data are transferred using DMA, the DMA must be
initialized before setting the START bit. The end of transfer is managed with the
NBYTES counter. Refer to Master transmitter.

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For a code example refer to A.11.8: I2C configured in master mode to transmit with DMA.
• In slave mode:
– With NOSTRETCH = 0, when all data are transferred using DMA, the DMA must
be initialized before the address match event, or in ADDR interrupt subroutine,
before clearing ADDR.
– With NOSTRETCH = 1, the DMA must be initialized before the address match
event.
• For instances supporting SMBus: the PEC transfer is managed with NBYTES counter.
Refer to SMBus slave transmitter and SMBus master transmitter.
Note: If DMA is used for transmission, the TXIE bit does not need to be enabled.

Reception using DMA

DMA (direct memory access) can be enabled for reception by setting the RXDMAEN bit in
the I2C_CR1 register. Data is loaded from the I2C_RXDR register to an SRAM area
configured using the DMA peripheral (refer to Section 10: Direct memory access controller
(DMA) on page 149) whenever the RXNE bit is set. Only the data (including PEC) are
transferred with DMA.
• In master mode, the initialization, the slave address, direction, number of bytes and
START bit are programmed by software. When all data are transferred using DMA, the
DMA must be initialized before setting the START bit. The end of transfer is managed
with the NBYTES counter..
• In slave mode with NOSTRETCH = 0, when all data are transferred using DMA, the
DMA must be initialized before the address match event, or in the ADDR interrupt
subroutine, before clearing the ADDR flag.
• If SMBus is supported (see Section 22.3) the PEC transfer is managed with the
NBYTES counter. Refer to SMBus slave receiver and SMBus master receiver.
Note: If DMA is used for reception, the RXIE bit does not need to be enabled.
For a code example refer to A.11.9: I2C configured in slave mode to receive with DMA.

22.4.18 Debug mode

When the microcontroller enters debug mode (core halted), the SMBus timeout either
continues to work normally or stops, depending on the DBG_I2Cx_SMBUS_TIMEOUT
configuration bits in the DBG module.

22.5 I2C low-power modes

Table 83. Effect of low-power modes on the I2C
Mode Description

No effect
Sleep
I2C interrupts cause the device to exit the Sleep mode.
The contents of I2C registers are kept. The I2C must be disabled before entering Stop
Stop
mode.
Standby The I2C peripheral is powered down and must be reinitialized after exiting Standby.

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22.6 I2C interrupts

The following table gives the list of I2C interrupt requests.

Table 84. I2C interrupt requests

Exit Exit Exit
Interrupt Interrupt Enable Interrupt clear
Event flag Sleep Stop Standby
acronym event control bit method
mode modes modes

Receive buffer not Read I2C_RXDR

RXNE RXIE
empty register
Transmit buffer Write I2C_TXDR
TXIS TXIE
interrupt status register
Stop detection
STOPF STOPIE Write STOPCF = 1
interrupt flag
No
Transfer complete Write I2C_CR2 with
TCR
I2C_EV reload NBYTES[7:0] ≠ 0 Yes No
TCIE
Write START = 1 or
Transfer complete TC
STOP = 1
Address matched ADDR ADDRIE Write ADDRCF=1
NACK reception NACKF NACKIE Write NACKCF=1
Bus error BERR Write BERRCF = 1
I2C_ER Arbitration loss ARLO ERRIE Write ARLOCF = 1 Yes No No
Overrun/underrun OVR Write OVRCF = 1
PEC error PECERR Write PECERRCF = 1
Timeout/ Write
I2C_ER TIMEOUT ERRIE Yes No No
tLOW error TIMEOUTCF = 1
SMBus alert ALERT Write ALERTCF = 1

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22.7 I2C registers

Refer to Section 1.2 on page 33 for the list of abbreviations used in register descriptions.
The registers are accessed by words (32-bit).

22.7.1 I2C control register 1 (I2C_CR1)

Address offset: 0x00
Reset value: 0x0000 0000
Access: no wait states, except if a write access occurs while a write access is ongoing. In
this case, wait states are inserted in the second write access, until the previous one is
completed. The latency of the second write access can be up to 2 x PCLK1 + 6 x I2CCLK.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PEC ALERT SMBD SMBH GC NO
Res. Res. Res. Res. Res. Res. Res. Res. SBC
EN EN EN EN EN Res. STRETCH

rw rw rw rw rw rw rw

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXDMA TXDMA ANF STOP NACK ADDR
Res. DNF[3:0] ERRIE TCIE RXIE TXIE PE
EN EN OFF IE IE IE
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:24 Reserved, must be kept at reset value.

Bit 23 PECEN: PEC enable
0: PEC calculation disabled
1: PEC calculation enabled
Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0.
Refer to Section 22.3.
Bit 22 ALERTEN: SMBus alert enable
0: The SMBus alert pin (SMBA) is not supported in host mode (SMBHEN = 1). In device
mode (SMBHEN = 0), the SMBA pin is released and the Alert Response Address header is
disabled (0001100x followed by NACK).
1: The SMBus alert pin is supported in host mode (SMBHEN = 1). In device mode (SMBHEN
= 0), the SMBA pin is driven low and the Alert Response Address header is enabled
(0001100x followed by ACK).
Note: When ALERTEN = 0, the SMBA pin can be used as a standard GPIO.
If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0.
Refer to Section 22.3.
Bit 21 SMBDEN: SMBus device default address enable
0: Device default address disabled. Address 0b1100001x is NACKed.
1: Device default address enabled. Address 0b1100001x is ACKed.
Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0.
Refer to Section 22.3.
Bit 20 SMBHEN: SMBus host address enable
0: Host address disabled. Address 0b0001000x is NACKed.
1: Host address enabled. Address 0b0001000x is ACKed.
Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0.
Refer to Section 22.3.

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Bit 19 GCEN: General call enable

0: General call disabled. Address 0b00000000 is NACKed.
1: General call enabled. Address 0b00000000 is ACKed.
Bit 18 Reserved, must be kept at reset value.
Bit 17 NOSTRETCH: Clock stretching disable
This bit is used to disable clock stretching in slave mode. It must be kept cleared in master
mode.
0: Clock stretching enabled
1: Clock stretching disabled
Note: This bit can be programmed only when the I2C is disabled (PE = 0).
Bit 16 SBC: Slave byte control
This bit is used to enable hardware byte control in slave mode.
0: Slave byte control disabled
1: Slave byte control enabled
Bit 15 RXDMAEN: DMA reception requests enable
0: DMA mode disabled for reception
1: DMA mode enabled for reception
Bit 14 TXDMAEN: DMA transmission requests enable
0: DMA mode disabled for transmission
1: DMA mode enabled for transmission
Bit 13 Reserved, must be kept at reset value.
Bit 12 ANFOFF: Analog noise filter OFF
0: Analog noise filter enabled
1: Analog noise filter disabled
Note: This bit can be programmed only when the I2C is disabled (PE = 0).
Bits 11:8 DNF[3:0]: Digital noise filter
These bits are used to configure the digital noise filter on SDA and SCL input. The digital
filter, filters spikes with a length of up to DNF[3:0] * tI2CCLK
0000: Digital filter disabled
0001: Digital filter enabled and filtering capability up to one tI2CCLK
...
1111: digital filter enabled and filtering capability up to fifteen tI2CCLK
Note: If the analog filter is enabled, the digital filter is added to it. This filter can be
programmed only when the I2C is disabled (PE = 0).
Bit 7 ERRIE: Error interrupts enable
0: Error detection interrupts disabled
1: Error detection interrupts enabled
Note: Any of these errors generate an interrupt:
Arbitration loss (ARLO)
Bus error detection (BERR)
Overrun/underrun (OVR)
Timeout detection (TIMEOUT)
PEC error detection (PECERR)
Alert pin event detection (ALERT)

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Bit 6 TCIE: Transfer complete interrupt enable

0: Transfer complete interrupt disabled
1: Transfer complete interrupt enabled
Note: Any of these events generate an interrupt:
Transfer complete (TC)
Transfer complete reload (TCR)
Bit 5 STOPIE: Stop detection interrupt enable
0: Stop detection (STOPF) interrupt disabled
1: Stop detection (STOPF) interrupt enabled
Bit 4 NACKIE: Not acknowledge received interrupt enable
0: Not acknowledge (NACKF) received interrupts disabled
1: Not acknowledge (NACKF) received interrupts enabled
Bit 3 ADDRIE: Address match interrupt enable (slave only)
0: Address match (ADDR) interrupts disabled
1: Address match (ADDR) interrupts enabled
Bit 2 RXIE: RX interrupt enable
0: Receive (RXNE) interrupt disabled
1: Receive (RXNE) interrupt enabled
Bit 1 TXIE: TX interrupt enable
0: Transmit (TXIS) interrupt disabled
1: Transmit (TXIS) interrupt enabled
Bit 0 PE: Peripheral enable
0: Peripheral disable
1: Peripheral enable
Note: When PE = 0, the I2C SCL and SDA lines are released. Internal state machines and
status bits are put back to their reset value. When cleared, PE must be kept low for at
least three APB clock cycles.

22.7.2 I2C control register 2 (I2C_CR2)

Address offset: 0x04
Reset value: 0x0000 0000
Access: no wait states, except if a write access occurs while a write access is ongoing. In
this case, wait states are inserted in the second write access until the previous one is
completed. The latency of the second write access can be up to 2 x PCLK1 + 6 x I2CCLK.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PEC AUTO RE
Res. Res. Res. Res. Res. NBYTES[7:0]
BYTE END LOAD

rs rw rw rw rw rw rw rw rw rw rw

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HEAD RD_
NACK STOP START ADD10 SADD[9:0]
10R WRN
rs rs rs rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:27 Reserved, must be kept at reset value.

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Bit 26 PECBYTE: Packet error checking byte

This bit is set by software, and cleared by hardware when the PEC is transferred, or when a
STOP condition or an Address matched is received, also when PE = 0.
0: No PEC transfer
1: PEC transmission/reception is requested
Note: Writing 0 to this bit has no effect.
This bit has no effect when RELOAD is set.
This bit has no effect in slave mode when SBC = 0.
Bit 25 AUTOEND: Automatic end mode (master mode)
This bit is set and cleared by software.
0: software end mode: TC flag is set when NBYTES data are transferred, stretching SCL low.
1: Automatic end mode: a STOP condition is automatically sent when NBYTES data are
transferred.
Note: This bit has no effect in slave mode or when the RELOAD bit is set.
Bit 24 RELOAD: NBYTES reload mode
This bit is set and cleared by software.
0: The transfer is completed after the NBYTES data transfer (STOP or RESTART follows).
1: The transfer is not completed after the NBYTES data transfer (NBYTES is reloaded). TCR
flag is set when NBYTES data are transferred, stretching SCL low.
Bits 23:16 NBYTES[7:0]: Number of bytes
The number of bytes to be transmitted/received is programmed there. This field is don’t care
in slave mode with SBC = 0.
Note: Changing these bits when the START bit is set is not allowed.
Bit 15 NACK: NACK generation (slave mode)
The bit is set by software, cleared by hardware when the NACK is sent, or when a STOP
condition or an Address matched is received, or when PE = 0.
0: an ACK is sent after current received byte.
1: a NACK is sent after current received byte.
Note: Writing 0 to this bit has no effect.
This bit is used only in slave mode: in master receiver mode, NACK is automatically
generated after last byte preceding STOP or RESTART condition, whatever the NACK
bit value.
When an overrun occurs in slave receiver NOSTRETCH mode, a NACK is
automatically generated, whatever the NACK bit value.
When hardware PEC checking is enabled (PECBYTE = 1), the PEC acknowledge value
does not depend on the NACK value.
Bit 14 STOP: Stop generation (master mode)
The bit is set by software, cleared by hardware when a STOP condition is detected, or when
PE = 0.
In master mode:
0: No Stop generation
1: Stop generation after current byte transfer
Note: Writing 0 to this bit has no effect.

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Bit 13 START: Start generation

This bit is set by software, and cleared by hardware after the Start followed by the address
sequence is sent, by an arbitration loss, by a timeout error detection, or when PE = 0. It can
also be cleared by software by writing 1 to the ADDRCF bit in the I2C_ICR register.
0: No Start generation
1: Restart/Start generation:
If the I2C is already in master mode with AUTOEND = 0, setting this bit generates a
Repeated start condition when RELOAD = 0, after the end of the NBYTES transfer.
Otherwise, setting this bit generates a START condition once the bus is free.
Note: Writing 0 to this bit has no effect.
The START bit can be set even if the bus is BUSY or I2C is in slave mode.
This bit has no effect when RELOAD is set.
Bit 12 HEAD10R: 10-bit address header only read direction (master receiver mode)
0: The master sends the complete 10-bit slave address read sequence: Start + 2 bytes 10-bit
address in write direction + restart + first seven bits of the 10-bit address in read direction.
1: The master sends only the first seven bits of the 10-bit address, followed by read direction.
Note: Changing this bit when the START bit is set is not allowed.
Bit 11 ADD10: 10-bit addressing mode (master mode)
0: The master operates in 7-bit addressing mode
1: The master operates in 10-bit addressing mode
Note: Changing this bit when the START bit is set is not allowed.
Bit 10 RD_WRN: Transfer direction (master mode)
0: Master requests a write transfer
1: Master requests a read transfer
Note: Changing this bit when the START bit is set is not allowed.
Bits 9:0 SADD[9:0]: Slave address (master mode)
In 7-bit addressing mode (ADD10 = 0):
SADD[7:1] must be written with the 7-bit slave address to be sent. Bits SADD[9], SADD[8]
and SADD[0] are don't care.
In 10-bit addressing mode (ADD10 = 1):
SADD[9:0] must be written with the 10-bit slave address to be sent.
Note: Changing these bits when the START bit is set is not allowed.

22.7.3 I2C own address 1 register (I2C_OAR1)

Address offset: 0x08
Reset value: 0x0000 0000
Access: no wait states, except if a write access occurs while a write access is ongoing. In
this case, wait states are inserted in the second write access until the previous one is
completed. The latency of the second write access can be up to 2 x PCLK1 + 6 x I2CCLK.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OA1
OA1EN Res. Res. Res. Res. OA1[9:0]
MODE

rw rw rw rw rw rw rw rw rw rw rw rw

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Bits 31:16 Reserved, must be kept at reset value.

Bit 15 OA1EN: Own address 1 enable
0: Own address 1 disabled. The received slave address OA1 is NACKed.
1: Own address 1 enabled. The received slave address OA1 is ACKed.
Bits 14:11 Reserved, must be kept at reset value.
Bit 10 OA1MODE: Own address 1 10-bit mode
0: Own address 1 is a 7-bit address.
1: Own address 1 is a 10-bit address.
Note: This bit can be written only when OA1EN = 0.
Bits 9:0 OA1[9:0]: Interface own slave address
7-bit addressing mode: OA1[7:1] contains the 7-bit own slave address. Bits OA1[9], OA1[8]
and OA1[0] are don't care.
10-bit addressing mode: OA1[9:0] contains the 10-bit own slave address.
Note: These bits can be written only when OA1EN = 0.

22.7.4 I2C own address 2 register (I2C_OAR2)

Address offset: 0x0C
Reset value: 0x0000 0000
Access: no wait states, except if a write access occurs while a write access is ongoing. In
this case, wait states are inserted in the second write access, until the previous one is
completed. The latency of the second write access can be up to 2x PCLK1 + 6 x I2CCLK.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

OA2EN Res. Res. Res. Res. OA2MSK[2:0] OA2[7:1] Res.

rw rw rw rw rw rw rw rw rw rw rw

Bits 31:16 Reserved, must be kept at reset value.

Bit 15 OA2EN: Own address 2 enable
0: Own address 2 disabled. The received slave address OA2 is NACKed.
1: Own address 2 enabled. The received slave address OA2 is ACKed.
Bits 14:11 Reserved, must be kept at reset value.

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Bits 10:8 OA2MSK[2:0]: Own address 2 masks

000: No mask
001: OA2[1] is masked and don’t care. Only OA2[7:2] are compared.
010: OA2[2:1] are masked and don’t care. Only OA2[7:3] are compared.
011: OA2[3:1] are masked and don’t care. Only OA2[7:4] are compared.
100: OA2[4:1] are masked and don’t care. Only OA2[7:5] are compared.
101: OA2[5:1] are masked and don’t care. Only OA2[7:6] are compared.
110: OA2[6:1] are masked and don’t care. Only OA2[7] is compared.
111: OA2[7:1] are masked and don’t care. No comparison is done, and all (except reserved)
7-bit received addresses are acknowledged.
Note: These bits can be written only when OA2EN = 0.
As soon as OA2MSK ≠ 0, the reserved I2C addresses (0b0000xxx and 0b1111xxx) are
not acknowledged, even if the comparison matches.
Bits 7:1 OA2[7:1]: Interface address
7-bit addressing mode: 7-bit address
Note: These bits can be written only when OA2EN = 0.
Bit 0 Reserved, must be kept at reset value.

22.7.5 I2C timing register (I2C_TIMINGR)

Address offset: 0x10
Reset value: 0x0000 0000
Access: no wait states

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRESC[3:0] Res. Res. Res. Res. SCLDEL[3:0] SDADEL[3:0]

rw rw rw rw rw rw rw rw rw rw rw rw

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SCLH[7:0] SCLL[7:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:28 PRESC[3:0]: Timing prescaler

This field is used to prescale I2CCLK to generate the clock period tPRESC used for data setup
and hold counters (refer to I2C timings), and for SCL high and low level counters (refer to I2C
master initialization).
tPRESC = (PRESC + 1) x tI2CCLK
Bits 27:24 Reserved, must be kept at reset value.
Bits 23:20 SCLDEL[3:0]: Data setup time
This field is used to generate a delay tSCLDEL between SDA edge and SCL rising edge. In
master and in slave modes with NOSTRETCH = 0, the SCL line is stretched low during
tSCLDEL.
tSCLDEL = (SCLDEL + 1) x tPRESC
Note: tSCLDEL is used to generate tSU:DAT timing.

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Bits 19:16 SDADEL[3:0]: Data hold time

This field is used to generate the delay tSDADEL between SCL falling edge and SDA edge. In
master and in slave modes with NOSTRETCH = 0, the SCL line is stretched low during
tSDADEL.
tSDADEL= SDADEL x tPRESC
Note: SDADEL is used to generate tHD:DAT timing.
Bits 15:8 SCLH[7:0]: SCL high period (master mode)
This field is used to generate the SCL high period in master mode.
tSCLH = (SCLH + 1) x tPRESC
Note: SCLH is also used to generate tSU:STO and tHD:STA timing.
Bits 7:0 SCLL[7:0]: SCL low period (master mode)
This field is used to generate the SCL low period in master mode.
tSCLL = (SCLL + 1) x tPRESC
Note: SCLL is also used to generate tBUF and tSU:STA timings.

Note: This register must be configured when the I2C is disabled (PE = 0).
Note: The STM32CubeMX tool calculates and provides the I2C_TIMINGR content in the I2C
Configuration window.

22.7.6 I2C timeout register (I2C_TIMEOUTR)

Address offset: 0x14
Reset value: 0x0000 0000
Access: no wait states, except if a write access occurs while a write access is ongoing. In
this case, wait states are inserted in the second write access until the previous one is
completed. The latency of the second write access can be up to 2 x PCLK1 + 6 x I2CCLK.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TEXTEN Res. Res. Res. TIMEOUTB[11:0]

rw rw rw rw rw rw rw rw rw rw rw rw rw

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TIMOUTEN Res. Res. TIDLE TIMEOUTA[11:0]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bit 31 TEXTEN: Extended clock timeout enable

0: Extended clock timeout detection is disabled
1: Extended clock timeout detection is enabled. When a cumulative SCL stretch for more
than tLOW:EXT is done by the I2C interface, a timeout error is detected (TIMEOUT = 1).
Bits 30:28 Reserved, must be kept at reset value.
Bits 27:16 TIMEOUTB[11:0]: Bus timeout B
This field is used to configure the cumulative clock extension timeout:
In master mode, the master cumulative clock low extend time (tLOW:MEXT) is detected
In slave mode, the slave cumulative clock low extend time (tLOW:SEXT) is detected
tLOW:EXT = (TIMEOUTB + TIDLE = 01) x 2048 x tI2CCLK
Note: These bits can be written only when TEXTEN = 0.

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Bit 15 TIMOUTEN: Clock timeout enable

0: SCL timeout detection is disabled
1: SCL timeout detection is enabled: when SCL is low for more than tTIMEOUT (TIDLE = 0) or
high for more than tIDLE (TIDLE = 1), a timeout error is detected (TIMEOUT = 1).
Bits 14:13 Reserved, must be kept at reset value.
Bit 12 TIDLE: Idle clock timeout detection
0: TIMEOUTA is used to detect SCL low timeout
1: TIMEOUTA is used to detect both SCL and SDA high timeout (bus idle condition)
Note: This bit can be written only when TIMOUTEN = 0.
Bits 11:0 TIMEOUTA[11:0]: Bus timeout A
This field is used to configure:
The SCL low timeout condition tTIMEOUT when TIDLE = 0
tTIMEOUT= (TIMEOUTA + 1) x 2048 x tI2CCLK
The bus idle condition (both SCL and SDA high) when TIDLE = 1
tIDLE= (TIMEOUTA + 1) x 4 x tI2CCLK
Note: These bits can be written only when TIMOUTEN = 0.

22.7.7 I2C interrupt and status register (I2C_ISR)

Address offset: 0x18
Reset value: 0x0000 0001
Access: no wait states

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. ADDCODE[6:0] DIR

r r r r r r r r

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TIME PEC
BUSY Res. ALERT OVR ARLO BERR TCR TC STOPF NACKF ADDR RXNE TXIS TXE
OUT ERR

r r r r r r r r r r r r r rs rs

Bits 31:24 Reserved, must be kept at reset value.

Bits 23:17 ADDCODE[6:0]: Address match code (slave mode)
These bits are updated with the received address when an address match event occurs
(ADDR = 1). In the case of a 10-bit address, ADDCODE provides the 10-bit header followed
by the two MSBs of the address.
Bit 16 DIR: Transfer direction (slave mode)
This flag is updated when an address match event occurs (ADDR = 1).
0: Write transfer, slave enters receiver mode.
1: Read transfer, slave enters transmitter mode.
Bit 15 BUSY: Bus busy
This flag indicates that a communication is in progress on the bus. It is set by hardware
when a START condition is detected, and cleared by hardware when a STOP condition is
detected, or when PE = 0.
Bit 14 Reserved, must be kept at reset value.

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Bit 13 ALERT: SMBus alert

This flag is set by hardware when SMBHEN = 1 (SMBus host configuration), ALERTEN = 1
and an SMBALERT event (falling edge) is detected on SMBA pin. It is cleared by software
by setting the ALERTCF bit.
Note: This bit is cleared by hardware when PE = 0.
Bit 12 TIMEOUT: Timeout or tLOW detection flag
This flag is set by hardware when a timeout or extended clock timeout occurred. It is cleared
by software by setting the TIMEOUTCF bit.
Note: This bit is cleared by hardware when PE = 0.
Bit 11 PECERR: PEC error in reception
This flag is set by hardware when the received PEC does not match with the PEC register
content. A NACK is automatically sent after the wrong PEC reception. It is cleared by
software by setting the PECCF bit.
Note: This bit is cleared by hardware when PE = 0.
Bit 10 OVR: Overrun/underrun (slave mode)
This flag is set by hardware in slave mode with NOSTRETCH = 1, when an
overrun/underrun error occurs. It is cleared by software by setting the OVRCF bit.
Note: This bit is cleared by hardware when PE = 0.
Bit 9 ARLO: Arbitration lost
This flag is set by hardware in case of arbitration loss. It is cleared by software by setting the
ARLOCF bit.
Note: This bit is cleared by hardware when PE = 0.
Bit 8 BERR: Bus error
This flag is set by hardware when a misplaced Start or STOP condition is detected whereas
the peripheral is involved in the transfer. The flag is not set during the address phase in slave
mode. It is cleared by software by setting the BERRCF bit.
Note: This bit is cleared by hardware when PE = 0.
Bit 7 TCR: Transfer complete reload
This flag is set by hardware when RELOAD = 1 and NBYTES data have been transferred. It
is cleared by software when NBYTES is written to a non-zero value.
Note: This bit is cleared by hardware when PE = 0.
This flag is only for master mode, or for slave mode when the SBC bit is set.
Bit 6 TC: Transfer complete (master mode)
This flag is set by hardware when RELOAD = 0, AUTOEND = 0 and NBYTES data have
been transferred. It is cleared by software when START bit or STOP bit is set.
Note: This bit is cleared by hardware when PE = 0.
Bit 5 STOPF: Stop detection flag
This flag is set by hardware when a STOP condition is detected on the bus and the
peripheral is involved in this transfer:
– as a master, provided that the STOP condition is generated by the peripheral.
– as a slave, provided that the peripheral has been addressed previously during this
transfer.
It is cleared by software by setting the STOPCF bit.
Note: This bit is cleared by hardware when PE = 0.

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Bit 4 NACKF: Not acknowledge received flag

This flag is set by hardware when a NACK is received after a byte transmission. It is cleared
by software by setting the NACKCF bit.
Note: This bit is cleared by hardware when PE = 0.
Bit 3 ADDR: Address matched (slave mode)
This bit is set by hardware as soon as the received slave address matched with one of the
enabled slave addresses. It is cleared by software by setting ADDRCF bit.
Note: This bit is cleared by hardware when PE = 0.
Bit 2 RXNE: Receive data register not empty (receivers)
This bit is set by hardware when the received data is copied into the I2C_RXDR register, and
is ready to be read. It is cleared when I2C_RXDR is read.
Note: This bit is cleared by hardware when PE = 0.
Bit 1 TXIS: Transmit interrupt status (transmitters)
This bit is set by hardware when the I2C_TXDR register is empty and the data to be
transmitted must be written in the I2C_TXDR register. It is cleared when the next data to be
sent is written in the I2C_TXDR register.
This bit can be written to 1 by software only when NOSTRETCH = 1, to generate a TXIS
event (interrupt if TXIE = 1 or DMA request if TXDMAEN = 1).
Note: This bit is cleared by hardware when PE = 0.
Bit 0 TXE: Transmit data register empty (transmitters)
This bit is set by hardware when the I2C_TXDR register is empty. It is cleared when the next
data to be sent is written in the I2C_TXDR register.
This bit can be written to 1 by software in order to flush the transmit data register I2C_TXDR.
Note: This bit is set by hardware when PE = 0.

22.7.8 I2C interrupt clear register (I2C_ICR)

Address offset: 0x1C
Reset value: 0x0000 0000
Access: no wait states

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ALERT TIMOUT PEC OVR ARLO BERR STOP NACK ADDR
Res. Res. Res. Res. Res. Res. Res.
CF CF CF CF CF CF CF CF CF

w w w w w w w w w

Bits 31:14 Reserved, must be kept at reset value.

Bit 13 ALERTCF: Alert flag clear
Writing 1 to this bit clears the ALERT flag in the I2C_ISR register.
Bit 12 TIMOUTCF: Timeout detection flag clear
Writing 1 to this bit clears the TIMEOUT flag in the I2C_ISR register.Refer to Section 22.3.
Bit 11 PECCF: PEC error flag clear
Writing 1 to this bit clears the PECERR flag in the I2C_ISR register.

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Bit 10 OVRCF: Overrun/underrun flag clear

Writing 1 to this bit clears the OVR flag in the I2C_ISR register.
Bit 9 ARLOCF: Arbitration lost flag clear
Writing 1 to this bit clears the ARLO flag in the I2C_ISR register.
Bit 8 BERRCF: Bus error flag clear
Writing 1 to this bit clears the BERRF flag in the I2C_ISR register.
Bits 7:6 Reserved, must be kept at reset value.
Bit 5 STOPCF: STOP detection flag clear
Writing 1 to this bit clears the STOPF flag in the I2C_ISR register.
Bit 4 NACKCF: Not acknowledge flag clear
Writing 1 to this bit clears the NACKF flag in I2C_ISR register.
Bit 3 ADDRCF: Address matched flag clear
Writing 1 to this bit clears the ADDR flag in the I2C_ISR register. Writing 1 to this bit also
clears the START bit in the I2C_CR2 register.
Bits 2:0 Reserved, must be kept at reset value.

22.7.9 I2C PEC register (I2C_PECR)

Address offset: 0x20
Reset value: 0x0000 0000
Access: no wait states

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res. Res. Res. Res. Res. Res. Res. Res. PEC[7:0]

r r r r r r r r

Bits 31:8 Reserved, must be kept at reset value.

Bits 7:0 PEC[7:0]: Packet error checking register
This field contains the internal PEC when PECEN=1.
The PEC is cleared by hardware when PE = 0.

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22.7.10 I2C receive data register (I2C_RXDR)

Address offset: 0x24
Reset value: 0x0000 0000
Access: no wait states

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. RXDATA[7:0]

r r r r r r r r

Bits 31:8 Reserved, must be kept at reset value.

Bits 7:0 RXDATA[7:0]: 8-bit receive data
Data byte received from the I2C bus

22.7.11 I2C transmit data register (I2C_TXDR)

Address offset: 0x28
Reset value: 0x0000 0000
Access: no wait states

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. TXDATA[7:0]

rw rw rw rw rw rw rw rw

Bits 31:8 Reserved, must be kept at reset value.

Bits 7:0 TXDATA[7:0]: 8-bit transmit data
Data byte to be transmitted to the I2C bus
Note: These bits can be written only when TXE = 1.

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 0x28
0x24
0x20
0x18
0x14
0x10
0x08
0x04
0x00

0x1C
0x0C
Offset

588/775
22.7.12

I2C_
I2C_
name

I2C_ISR

I2C_ICR
I2C_CR2
I2C_CR1

TIMINGR

I2C_TXDR
I2C_OAR2
I2C_OAR1

I2C_PECR

I2C_RXDR
Register

TIMEOUTR

Reset value
Reset value
Reset value
Reset value
Reset value

Reset value
Reset value
Reset value
Reset value
Reset value
Reset value

0
0
Res. Res. Res. Res. Res. TEXTEN Res. Res. Res. Res. 31

0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 30

0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 29

0
PRESC[3:0]
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 28

0
I2C register map

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 27

0
0
Res. Res. Res. Res. Res. Res. Res. Res. PECBYTE Res. 26

0
0
Res. Res. Res. Res. Res. Res. Res. Res. AUTOEND Res. 25
Inter-integrated circuit (I2C) interface

0
0
Res. Res. Res. Res. Res. Res. Res. Res. RELOAD Res. 24

0
0
0
0
0

Res. Res. Res. Res. Res. Res. PECEN 23

0
0
0
0
0

Res. Res. Res. Res. Res. Res. ALERTEN 22

[3:0]

0
0
0
0
0

Res. Res. Res. Res. Res. Res. SMBDEN 21

SCLDEL

0
0
0
0
0

Res. Res. Res. Res. Res. Res. SMBHEN 20

TIMEOUTB[11:0]

0
0
0
0
0

Res. Res. Res. Res. Res. Res. GCEN 19

ADDCODE[6:0]

0
0
0
0
NBYTES[7:0]

Res. Res. Res. Res. Res. Res. Res 18

RM0360 Rev 5
[3:0]

0
0
0
0
0

Res. Res. Res. Res. Res. Res. NOSTRETCH 17

SDADEL

0
0
0
0
0

Res. Res. Res. Res. DIR Res. Res. SBC 16

0
0

0
0
0
0
0

Res. Res. Res. Res. BUSY TIMOUTEN OA2EN OA1EN NACK RXDMAEN 15

0
0
0

Res. Res. Res. Res. Res. Res. Res. Res. STOP TXDMAEN 14

0
0
0

0
Res. Res. Res. ALERTCF ALERT Res. Res. Res. START Res. 13

0
0
0
0

0
0

Res. Res. Res. TIMOUTCF TIMEOUT TIDLE Res. Res. HEAD10R ANFOFF 12

0
0
0
0

0
0
Table 85. I2C register map and reset values

Res. Res. Res. PECCF PECERR Res. Res. ADD10 11

SCLH[7:0]

0
0
0
0
0
0

0
0

Res. Res. Res. OVRCF OVR OA1MODE RD_WRN 10

0
0
0
0
0
0

0
0

Res. Res. Res. ARLOCF ARLO 9

The table below provides the I2C register map and the reset values.

DNF[3:0]

K [2:0]
OA2MS

0
0
0
0
0
0

0
0

Res. Res. Res. BERRCF BERR 8

0
0
0
0
0
0
0

0
0
0
Res. TCR ERRIE 7

0
0
0
0
0
0
0

0
0
0
Res. TC TCIE 6

0
0
0
0
0
0
0

0
0
0
STOPCF STOPF STOPIE 5

0
0
0
0
0
0
0

0
0
0
NACKCF NACKF NACKIE 4
OA1[9:0]

TIMEOUTA[11:0]
SADD[9:0]

OA2[7:1]

0
0
0
0
0
0
0

0
0
0
ADDRCF ADDR ADDRIE 3

PEC[7:0]
SCLL[7:0]

TXDATA[7:0]
0
0
0
0
0
0
0

0
0
0

RXDATA[7:0]
Res. RXNE RXIE 2

0
0
0
0
0
0
0

0
0
0
Res. TXIS TXIE 1

1
0
0
0
0
0

0
0
0
0
RM0360

Res. TXE Res. PE

RM0360 Inter-integrated circuit (I2C) interface

Refer to Section 2.2 on page 37 for the register boundary addresses.

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23 Universal synchronous/asynchronous receiver

transmitter (USART/UART)

23.1 Introduction
The universal synchronous asynchronous receiver transmitter (USART) offers a flexible
means of Full-duplex data exchange with external equipment requiring an industry standard
NRZ asynchronous serial data format. The USART offers a very wide range of baud rates
using a programmable baud rate generator.
It supports synchronous one-way communication and Half-duplex Single-wire
communication, as well as multiprocessor communications. It also supports Modem
operations (CTS/RTS).
High speed data communication is possible by using the DMA (direct memory access) for
multibuffer configuration.

23.2 USART main features

• Full-duplex asynchronous communications
• NRZ standard format (mark/space)
• Configurable oversampling method by 16 or 8 to give flexibility between speed and
clock tolerance
• A common programmable transmit and receive baud rate of up to 6 Mbit/s when the
clock frequency is 48 MHz and oversampling is by 8
• Convenient baud rate programming
• Auto baud rate detection
• Programmable data word length (8 or 9 bits)
• Programmable data order with MSB-first or LSB-first shifting
• Configurable stop bits (1 or 2 stop bits)
• Synchronous mode and clock output for synchronous communications
• Single-wire Half-duplex communications
• Continuous communications using DMA
• Received/transmitted bytes are buffered in reserved SRAM using centralized DMA
• Separate enable bits for transmitter and receiver
• Separate signal polarity control for transmission and reception
• Swappable Tx/Rx pin configuration
• Hardware flow control for modem and RS-485 transceiver

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• Communication control/error detection flags

• Parity control:
– Transmits parity bit
– Checks parity of received data byte
• Fourteen interrupt sources with flags
• Multiprocessor communications
The USART enters Mute mode if the address does not match.
• Wake-up from Mute mode (by idle line detection or address mark detection)

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23.3 USART implementation

Table 86. STM32F0x0 USART features(1)

STM32F030x4,
STM32F030x8 STM32F070x6 STM32F070xB STM32F030xC
STM32F030x6

USART1/ USART2/
USART1/ USART2
USART modes/
USART1

USART1

USART2

USART1

USART2

USART3

USART4

USART3

USART4

USART5

USART6
features

Hardware flow
X X X X X X X X X X - -
control for modem
Continuous
communication X X X X X X X - X X X X
using DMA
Multiprocessor
X X X X X X X X X X X X
communication
Synchronous
X X X X X X X X X X X -
mode
Smartcard mode - - - - - - - - - - - -

Single-wire Half-
duplex X X X X X X X X X X X X
communication
IrDA SIR ENDEC
- - - - - - - - - - - -
block
LIN mode - - - - - - - - - - - -

Dual clock domain

and wake-up from - - - - - - - - - - - -
Stop mode
Receiver timeout
X X - X - X - - X - - -
interrupt
Modbus
- - - - - - - - - - - -
communication
Auto baud rate
detection
2 2 - 4 - 4 - - 4 - - -
(supported
modes)
Driver Enable X X X X X X X X X X X -

USART data
8 and 9 bits 7(2), 8 and 9 bits
length
1. X = supported.
2. In 7-bit data length mode, Smartcard mode, LIN master mode and Auto baud rate (0x7F and 0x55 frames) detection are not
supported.

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23.4 USART functional description

Any USART bidirectional communication requires a minimum of two pins: Receive data In
(RX) and Transmit data Out (TX):
• RX: Receive data Input.
This is the serial data input. Oversampling techniques are used for data recovery by
discriminating between valid incoming data and noise.
• TX: Transmit data Output.
When the transmitter is disabled, the output pin returns to its I/O port configuration.
When the transmitter is enabled and nothing is to be transmitted, the TX pin is at high
level. In Single-wire, this I/O is used to transmit and receive the data.
Serial data are transmitted and received through these pins in normal USART mode. The
frames are comprised of:
• An Idle Line prior to transmission or reception
• A start bit
• A data word (8 or 9 bits) least significant bit first
• 1, 2 stop bits indicating that the frame is complete
• The USART interface uses a baud rate generator
• A status register (USART_ISR)
• Receive and transmit data registers (USART_RDR, USART_TDR)
• A baud rate register (USART_BRR)
Refer to Section 23.7: USART registers on page 620 for the definitions of each bit.
The following pin is required to interface in synchronous mode:
• CK: Clock output. This pin outputs the transmitter data clock for synchronous
transmission corresponding to SPI master mode (no clock pulses on start bit and stop
bit, and a software option to send a clock pulse on the last data bit). In parallel, data
can be received synchronously on RX. This can be used to control peripherals that
have shift registers. The clock phase and polarity are software programmable.
The following pins are required in RS232 Hardware flow control mode:
• CTS: Clear To Send blocks the data transmission at the end of the current transfer
(when high)
• RTS: Request to send indicates that the USART is ready to receive data (when low).
The following pin is required in RS485 Hardware control mode:
• DE: Driver Enable activates the transmission mode of the external transceiver.
Note: DE and RTS share the same pin.

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Figure 230. USART block diagram

PRDATA PWDATA
Read Write DR (data register)
(CPU or DMA) (CPU or DMA)

Transmit shift register Receive shift register

Transmit data register Receive data register

(TDR) (RDR)

USART_GTPR register
GT PSC CK control CK

USART_CR3 register USART_CR2 register

USART_CR2 register
USART_CR1 register

RTS Hardware
/DE flow
CTS controller Receiver
clock
Transmit Receiver
control control

USART_CR1 register USART_ISR register

USART
interrupt
control

USART_BRR register
TE Transmitter
rate controller
/USARTDIV or 2/USARTDIV
(depending on the
Transmitter oversampling mode) BRR[15:0]
clock
(Note 1)

Receiver rate
fPCLK RE controller
Conventional baud rate generator

MS32634V6

1. For details on coding USARTDIV in the USART_BRR register, refer to Section 23.4.4: USART baud rate
generation.

23.4.1 USART character description

The word length can be selected as being either 8 or 9 bits by programming the M bit (M0:
bit 12) in the USART_CR1 register (see Figure 231).
• 8-bit character length: M0 = 0
• 9-bit character length: M0 = 1
By default, the signal (TX or RX) is in low state during the start bit. It is in high state during
the stop bit.
These values can be inverted, separately for each signal, through polarity configuration
control.

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An Idle character is interpreted as an entire frame of “1”s (the number of “1”s includes the
number of stop bits).
A Break character is interpreted on receiving “0”s for a frame period. At the end of the
break frame, the transmitter inserts 2 stop bits.
Transmission and reception are driven by a common baud rate generator, the clock for each
is generated when the enable bit is set respectively for the transmitter and receiver.
The details of each block is given below.

Figure 231. Word length programming

9-bit word length (M bit is set), 1 Stop bit

Possible
Data frame Parity Next data frame
bit
Next
Start Stop Start
bit Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 Bit8 bit bit

Clock **

Start
Idle frame bit

Break frame Start Stop

bit bit

** LBCL bit controls last data clock pulse

8-bit word length (M bit is reset), 1 Stop bit

Possible
Parity
Data frame bit
Next data frame
Start Next
Stop
bit Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 Start
bit
bit

Clock **

Start
Idle frame bit

Break frame Start Stop

bit bit

** LBCL bit controls last data clock pulse

MS19822V1

23.4.2 USART transmitter

The transmitter can send data words of either 8 or 9 bits depending on the M bit status. The
Transmit Enable bit (TE) must be set in order to activate the transmitter function. The data in
the transmit shift register is output on the TX pin and the corresponding clock pulses are
output on the CK pin.

Character transmission
During an USART transmission, data shifts out least significant bit first (default
configuration) on the TX pin. In this mode, the USART_TDR register consists of a buffer
(TDR) between the internal bus and the transmit shift register (see Figure 230).

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Every character is preceded by a start bit which is a logic level low for one bit period. The
character is terminated by a configurable number of stop bits.
The following stop bits are supported by USART: 1 and 2 stop bits.
Note: The TE bit must be set before writing the data to be transmitted to the USART_TDR.
The TE bit should not be reset during transmission of data. Resetting the TE bit during the
transmission will corrupt the data on the TX pin as the baud rate counters will get frozen.
The current data being transmitted is lost.
An idle frame is sent after the TE bit is enabled.
Configurable stop bits
The number of stop bits to be transmitted with every character can be programmed in
Control register 2, bits 13,12.
• 1 stop bit: This is the default value of number of stop bits.
• 2 stop bits: This is supported by normal USART, Single-wire and Modem modes.
An idle frame transmission will include the stop bits.
A break transmission will be 10 low bits (when M0= 0) or 11 low bits (when M0= 1) followed
by 2 stop bits (see Figure 232). It is not possible to transmit long breaks (break of length
greater than 10/11 low bits).

Figure 232. Configurable stop bits

8-bit data, 1 Stop bit

Possible
Data frame Next Next data frame
parity bit
start
Start bit Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 Stop
bit
bit
CLOCK **

** LBCL bit controls last data clock pulse

8-bit data, 1 1/2 Stop bits
Possible
Data frame Next Next data frame
parity bit
start
Start bit Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 1.5
bit
Stop
bits

8-bit data, 2 Stop bits

Possible
Data frame Next Next data frame
parity bit
start
Start bit Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 2
bit
Stop
bits
MSv31887V1

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RM0360 Universal synchronous/asynchronous receiver transmitter (USART/UART)

Character transmission procedure

1. Program the M bit in USART_CR1 to define the word length.
2. Select the desired baud rate using the USART_BRR register.
3. Program the number of stop bits in USART_CR2.
4. Enable the USART by writing the UE bit in USART_CR1 register to 1.
5. Select DMA enable (DMAT) in USART_CR3 if multibuffer communication is to take
place. Configure the DMA register as explained in multibuffer communication.
6. Set the TE bit in USART_CR1 to send an idle frame as first transmission.
7. Write the data to send in the USART_TDR register (this clears the TXE bit). Repeat this
for each data to be transmitted in case of single buffer.
8. After writing the last data into the USART_TDR register, wait until TC=1. This indicates
that the transmission of the last frame is complete. This is required for instance when
the USART is disabled or enters the Halt mode to avoid corrupting the last
transmission.
For code example, refer to A.15.1: USART transmitter configuration.

Single byte communication

Clearing the TXE bit is always performed by a write to the transmit data register.
The TXE bit is set by hardware and it indicates:
• The data has been moved from the USART_TDR register to the shift register and the
data transmission has started.
• The USART_TDR register is empty.
• The next data can be written in the USART_TDR register without overwriting the
previous data.
For code example, refer to A.15.2: USART transmit byte.
This flag generates an interrupt if the TXEIE bit is set.
When a transmission is taking place, a write instruction to the USART_TDR register stores
the data in the TDR register; next, the data is copied in the shift register at the end of the
currently ongoing transmission.
When no transmission is taking place, a write instruction to the USART_TDR register places
the data in the shift register, the data transmission starts, and the TXE bit is set.
If a frame is transmitted (after the stop bit) and the TXE bit is set, the TC bit goes high. An
interrupt is generated if the TCIE bit is set in the USART_CR1 register.
After writing the last data in the USART_TDR register, it is mandatory to wait for TC=1
before disabling the USART or causing the microcontroller to enter the low-power mode
(see Figure 233: TC/TXE behavior when transmitting).

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Figure 233. TC/TXE behavior when transmitting

Idle preamble Frame 1 Frame 2 Frame 3

TX line
Set by hardware Set by hardware
TXE flag cleared by software cleared by software Set by hardware

USART_DR F1 F2 F3
Set by hardware
TC flag

Software Software waits until TXE=1

enables the TC is not set TC is not set TC is set
and writes F2 into DR
USART because TXE=0 because TXE=0 because TXE=1

Software waits until

Software waits until TXE=1 Software waits until TC=1
and writes F1 into DR TXE=1 and writes
F3 into DR

ai17121b

For code example, refer to A.15.3: USART transfer complete.

Break characters
Setting the SBKRQ bit transmits a break character. The break frame length depends on the
M bit (see Figure 231).
If a ‘1’ is written to the SBKRQ bit, a break character is sent on the TX line after completing
the current character transmission. The SBKF bit is set by the write operation and it is reset
by hardware when the break character is completed (during the stop bits after the break
character). The USART inserts a logic 1 signal (STOP) for the duration of 2 bits at the end of
the break frame to guarantee the recognition of the start bit of the next frame.
In the case the application needs to send the break character following all previously
inserted data, including the ones not yet transmitted, the software should wait for the TXE
flag assertion before setting the SBKRQ bit.

Idle characters
Setting the TE bit drives the USART to send an idle frame before the first data frame.

23.4.3 USART receiver

The USART can receive data words of either 8 or 9 bits depending on the M bit in the
USART_CR1 register.

Start bit detection

The start bit detection sequence is the same when oversampling by 16 or by 8.
In the USART, the start bit is detected when a specific sequence of samples is recognized.
This sequence is: 1 1 1 0 X 0 X 0X 0X 0 X 0X 0.

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Figure 234. Start bit detection when oversampling by 16 or 8

Note: If the sequence is not complete, the start bit detection aborts and the receiver returns to the
idle state (no flag is set), where it waits for a falling edge.
The start bit is confirmed (RXNE flag set, interrupt generated if RXNEIE=1) if the 3 sampled
bits are at 0 (first sampling on the 3rd, 5th and 7th bits finds the 3 bits at 0 and second
sampling on the 8th, 9th and 10th bits also finds the 3 bits at 0).
The start bit is validated (RXNE flag set, interrupt generated if RXNEIE=1) but the NF noise
flag is set if,
a) for both samplings, 2 out of the 3 sampled bits are at 0 (sampling on the 3rd, 5th
and 7th bits and sampling on the 8th, 9th and 10th bits)
or
b) for one of the samplings (sampling on the 3rd, 5th and 7th bits or sampling on the
8th, 9th and 10th bits), 2 out of the 3 bits are found at 0.
If neither conditions a. or b. are met, the start detection aborts and the receiver returns to the
idle state (no flag is set).

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Character reception
During an USART reception, data shifts in least significant bit first (default configuration)
through the RX pin. In this mode, the USART_RDR register consists of a buffer (RDR)
between the internal bus and the receive shift register.
Character reception procedure
1. Program the M bit in USART_CR1 to define the word length.
2. Select the desired baud rate using the baud rate register USART_BRR
3. Program the number of stop bits in USART_CR2.
4. Enable the USART by writing the UE bit in USART_CR1 register to 1.
5. Select DMA enable (DMAR) in USART_CR3 if multibuffer communication is to take
place. Configure the DMA register as explained in multibuffer communication.
6. Set the RE bit USART_CR1. This enables the receiver which begins searching for a
start bit.
For code example, refer to A.15.4: USART receiver configuration.
When a character is received:
• The RXNE bit is set to indicate that the content of the shift register is transferred to the
RDR. In other words, data has been received and can be read (as well as its
associated error flags).
• An interrupt is generated if the RXNEIE bit is set.
• The error flags can be set if a frame error, noise or an overrun error has been detected
during reception. PE flag can also be set with RXNE.
• In multibuffer, RXNE is set after every byte received and is cleared by the DMA read of
the Receive data Register.
• In single buffer mode, clearing the RXNE bit is performed by a software read to the
USART_RDR register. The RXNE flag can also be cleared by writing 1 to the RXFRQ
in the USART_RQR register. The RXNE bit must be cleared before the end of the
reception of the next character to avoid an overrun error.
For code example, refer to A.15.5: USART receive byte.

Break character
When a break character is received, the USART handles it as a framing error.

Idle character
When an idle frame is detected, there is the same procedure as for a received data
character plus an interrupt if the IDLEIE bit is set.

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Overrun error
An overrun error occurs when a character is received when RXNE has not been reset. Data
can not be transferred from the shift register to the RDR register until the RXNE bit is
cleared.
The RXNE flag is set after every byte received. An overrun error occurs if RXNE flag is set
when the next data is received or the previous DMA request has not been serviced. When
an overrun error occurs:
• The ORE bit is set.
• The RDR content will not be lost. The previous data is available when a read to
USART_RDR is performed.
• The shift register are overwritten. After that point, any data received during overrun is
lost.
• An interrupt is generated if either the RXNEIE bit is set or EIE bit is set.
• The ORE bit is reset by setting the ORECF bit in the ICR register.
Note: The ORE bit, when set, indicates that at least 1 datum has been lost. There are two
possibilities:
- if RXNE=1, then the last valid data is stored in the receive register RDR and can be read,
- if RXNE=0, then it means that the last valid data has already been read and thus there is
nothing to be read in the RDR. This case can occur when the last valid data is read in the
RDR at the same time as the new (and lost) data is received.

Selecting the clock source and the proper oversampling method

The choice of the clock source is done through the Clock Control system (see Section Reset
and clock control (RCC))). The clock source must be chosen before enabling the USART
(by setting the UE bit).
The choice of the clock source must be done according to two criteria:
• Possible use of the USART in low-power mode
• Communication speed.
The clock source frequency is fCK.
The communication speed range (specially the maximum communication speed) is also
determined by the clock source.
The receiver implements different user-configurable oversampling techniques for data
recovery by discriminating between valid incoming data and noise. This allows a trade-off
between the maximum communication speed and noise/clock inaccuracy immunity.
The oversampling method can be selected by programming the OVER8 bit in the
USART_CR1 register and can be either 16 or 8 times the baud rate clock (Figure 235 and
Figure 236).
Depending on the application:
• Select oversampling by 8 (OVER8=1) to achieve higher speed (up to fCK/8). In this
case the maximum receiver tolerance to clock deviation is reduced (refer to
Section 23.4.5: Tolerance of the USART receiver to clock deviation on page 606)
• Select oversampling by 16 (OVER8=0) to increase the tolerance of the receiver to
clock deviations. In this case, the maximum speed is limited to maximum fCK/16 where
fCK is the clock source frequency.

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Programming the ONEBIT bit in the USART_CR3 register selects the method used to
evaluate the logic level. There are two options:
• The majority vote of the three samples in the center of the received bit. In this case,
when the 3 samples used for the majority vote are not equal, the NF bit is set
• A single sample in the center of the received bit
Depending on the application:
– select the three samples’ majority vote method (ONEBIT=0) when operating in a
noisy environment and reject the data when a noise is detected (refer to
Figure 87) because this indicates that a glitch occurred during the sampling.
– select the single sample method (ONEBIT=1) when the line is noise-free to
increase the receiver’s tolerance to clock deviations (see Section 23.4.5:
Tolerance of the USART receiver to clock deviation on page 606). In this case the
NF bit will never be set.
When noise is detected in a frame:
• The NF bit is set at the rising edge of the RXNE bit.
• The invalid data is transferred from the Shift register to the USART_RDR register.
• No interrupt is generated in case of single byte communication. However this bit rises
at the same time as the RXNE bit which itself generates an interrupt. In case of
multibuffer communication an interrupt is issued if the EIE bit is set in the USART_CR3
register.
The NF bit is reset by setting NFCF bit in ICR register.

Figure 235. Data sampling when oversampling by 16

RX line

sampled values
Sample clock 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

6/16
7/16 7/16
One bit time

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Figure 236. Data sampling when oversampling by 8

RX line

sampled values
Sample
clock (x8) 1 2 3 4 5 6 7 8

2/8
3/8 3/8
One bit time

MSv31153V1

Table 87. Noise detection from sampled data

Sampled value NE status Received bit value

000 0 0
001 1 0
010 1 0
011 1 1
100 1 0
101 1 1
110 1 1
111 0 1

Framing error
A framing error is detected when the stop bit is not recognized on reception at the expected
time, following either a de-synchronization or excessive noise.
When the framing error is detected:
• The FE bit is set by hardware
• The invalid data is transferred from the Shift register to the USART_RDR register.
• No interrupt is generated in case of single byte communication. However this bit rises
at the same time as the RXNE bit which itself generates an interrupt. In case of
multibuffer communication an interrupt is issued if the EIE bit is set in the USART_CR3
register.
The FE bit is reset by writing 1 to the FECF in the USART_ICR register.

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Configurable stop bits during reception

The number of stop bits to be received can be configured through the control bits of Control
Register 2 - it can be either 1 or 2 in normal mode.
• 1 stop bit: Sampling for 1 stop Bit is done on the 8th, 9th and 10th samples.
• 2 stop bits: Sampling for 2 stop bits is done on the 8th, 9th and 10th samples of the
first stop bit. If a framing error is detected during the first stop bit the framing error flag
is set. The second stop bit is not checked for framing error. The RXNE flag is set at the
end of the first stop bit.

23.4.4 USART baud rate generation

The baud rate for the receiver and transmitter (Rx and Tx) are both set to the same value as
programmed in the USART_BRR register.

Equation 1: Baud rate for standard USART (SPI mode included) (OVER8 = 0 or 1)
In case of oversampling by 16, the equation is:
f CK
Tx/Rx baud = --------------------------------
USARTDIV

In case of oversampling by 8, the equation is:

2 × f CK
Tx/Rx baud = --------------------------------
USARTDIV

USARTDIV is an unsigned fixed point number that is coded on the USART_BRR register.
• When OVER8 = 0, BRR = USARTDIV.
• When OVER8 = 1
– BRR[2:0] = USARTDIV[3:0] shifted 1 bit to the right.
– BRR[3] must be kept cleared.
– BRR[15:4] = USARTDIV[15:4]
Note: The baud counters are updated to the new value in the baud registers after a write operation
to USART_BRR. Hence the baud rate register value should not be changed during
communication.
In case of oversampling by 16 or 8, USARTDIV must be greater than or equal to 16d.

How to derive USARTDIV from USART_BRR register values

Example 1
To obtain 9600 baud with fCK = 8 MHz.
• In case of oversampling by 16:
USARTDIV = 8 000 000/9600
BRR = USARTDIV = 0d833 = 0x341
• In case of oversampling by 8:
USARTDIV = 2 * 8 000 000/9600
USARTDIV = 1666,66 (0d1667 = 0x683)
BRR[3:0] = 0x3 >> 1 = 0x1
BRR = 0x681

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Example 2
To obtain 921.6 kbaud with fCK = 48 MHz.
• In case of oversampling by 16:
USARTDIV = 48 000 000/921 600
BRR = USARTDIV = 52d = 34h
• In case of oversampling by 8:
USARTDIV = 2 * 48 000 000/921 600
USARTDIV = 104 (104d = 68h)
BRR[3:0] = USARTDIV[3:0] >> 1 = 8h >> 1 = 4h
BRR = 0x64

Table 88. Error calculation for programmed baud rates at fCK = 48 MHz in both cases of
oversampling by 16 or by 8(1)
Baud rate Oversampling by 16 (OVER8 = 0) Oversampling by 8 (OVER8 = 1)

% Error =
(Calculated -
S.No Desired Actual BRR Actual BRR % Error
Desired)B.Rate /
Desired B.Rate

2 2.4 KBps 2.4 KBps 0x4E20 0 2.4 KBps 0x9C40 0

3 9.6 KBps 9.6 KBps 0x1388 0 9.6 KBps 0x2710 0
4 19.2 KBps 19.2 KBps 0x9C4 0 19.2 KBps 0x1384 0
5 38.4 KBps 38.4 KBps 0x4E2 0 38.4 KBps 0x9C2 0
6 57.6 KBps 57.62 KBps 0x341 0.03 57.59 KBps 0x681 0.02
7 115.2 KBps 115.11 KBps 0x1A1 0.08 115.25 KBps 0x340 0.04
8 230.4 KBps 230.76KBps 0xD0 0.16 230.21 KBps 0x1A0 0.08
9 460.8 KBps 461.54KBps 0x68 0.16 461.54KBps 0xD0 0.16
10 921.6KBps 923.07KBps 0x34 0.16 923.07KBps 0x64 0.16
11 2 MBps 2 MBps 0x18 0 2 MBps 0x30 0
12 3 MBps 3 MBps 0x10 0 3 MBps 0x20 0
13 4MBps N.A N.A N.A 4MBps 0x14 0
14 5MBps N.A N.A N.A 5052.63KBps 0x11 1.05
15 6MBps N.A N.A N.A 6MBps 0x10 0
1. The lower the CPU clock the lower the accuracy for a particular baud rate. The upper limit of the achievable baud rate can
be fixed with these data.

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23.4.5 Tolerance of the USART receiver to clock deviation

The asynchronous receiver of the USART works correctly only if the total clock system
deviation is less than the tolerance of the USART receiver. The causes which contribute to
the total deviation are:
• DTRA: Deviation due to the transmitter error (which also includes the deviation of the
transmitter’s local oscillator)
• DQUANT: Error due to the baud rate quantization of the receiver
• DREC: Deviation of the receiver’s local oscillator
• DTCL: Deviation due to the transmission line (generally due to the transceivers which
can introduce an asymmetry between the low-to-high transition timing and the high-to-
low transition timing)

DTRA + DQUANT + DREC + DTCL < USART receiver′ s tolerance

The USART receiver can receive data correctly at up to the maximum tolerated
deviation specified in Table 89 and Table 90 depending on the following choices:
• 10- or 11-bit character length defined by the M bit in the USART_CR1 register
• Oversampling by 8 or 16 defined by the OVER8 bit in the USART_CR1 register
• Bits BRR[3:0] of USART_BRR register are equal to or different from 0000.
• Use of 1 bit or 3 bits to sample the data, depending on the value of the ONEBIT bit in
the USART_CR3 register.

Table 89. Tolerance of the USART receiver when BRR [3:0] = 0000
OVER8 bit = 0 OVER8 bit = 1
M bit
ONEBIT=0 ONEBIT=1 ONEBIT=0 ONEBIT=1

0 3.75% 4.375% 2.50% 3.75%

1 3.41% 3.97% 2.27% 3.41%

Table 90. Tolerance of the USART receiver when BRR [3:0] is different from 0000
OVER8 bit = 0 OVER8 bit = 1
M bit
ONEBIT=0 ONEBIT=1 ONEBIT=0 ONEBIT=1

0 3.33% 3.88% 2% 3%
1 3.03% 3.53% 1.82% 2.73%

Note: The data specified in Table 89,and Table 90 may slightly differ in the special case when the
received frames contain some Idle frames of exactly 10-bit durations when M = 0 (11-bit
durations when M = 1).

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23.4.6 USART auto baud rate detection

The USART is able to detect and automatically set the USART_BRR register value based
on the reception of one character. Automatic baud rate detection is useful under two
circumstances:
• The communication speed of the system is not known in advance
• The system is using a relatively low accuracy clock source and this mechanism allows
the correct baud rate to be obtained without measuring the clock deviation.
The clock source frequency must be compatible with the expected communication speed
(Oversampling by 16 must be selected for a baud rate between fCK/65535 and fCK/16).
Before activating the auto baud rate detection, the auto baud rate detection mode must be
chosen. There are various modes based on different character patterns.
They can be chosen through the ABRMOD[1:0] field in the USART_CR2 register. In these
auto baud rate modes, the baud rate is measured several times during the synchronization
data reception and each measurement is compared to the previous one.
These modes are:
• Mode 0: Any character starting with a bit at 1. In this case the USART measures the
duration of the Start bit (falling edge to rising edge).
• Mode 1: Any character starting with a 10xx bit pattern. In this case, the USART
measures the duration of the Start and of the 1st data bit. The measurement is done
falling edge to falling edge, ensuring better accuracy in the case of slow signal slopes.
In parallel, another check is performed for each intermediate transition of RX line. An
error is generated if the transitions on RX are not sufficiently synchronized with the
receiver (the receiver being based on the baud rate calculated on bit 0).
Prior to activating auto baud rate detection, the USART_BRR register must be initialized by
writing a non-zero baud rate value.
The automatic baud rate detection is activated by setting the ABREN bit in the USART_CR2
register. The USART will then wait for the first character on the RX line. The auto baud rate
operation completion is indicated by the setting of the ABRF flag in the USART_ISR
register. If the line is noisy, the correct baud rate detection cannot be guaranteed. In this
case the BRR value may be corrupted and the ABRE error flag is set. This also happens if
the communication speed is not compatible with the automatic baud rate detection range
(bit duration not between 16 and 65536 clock periods (oversampling by 16) and not between
8 and 65536 clock periods (oversampling by 8)).
The RXNE interrupt will signal the end of the operation.
At any later time, the auto baud rate detection may be relaunched by resetting the ABRF
flag (by writing a 0).
Note: If the USART is disabled (UE=0) during an auto baud rate operation, the BRR value may be
corrupted.

23.4.7 Multiprocessor communication using USART

In multiprocessor communication, the following bits are to be kept cleared:
• LINEN bit in the USART_CR2 register,
• HDSEL, IREN and SCEN bits in the USART_CR3 register.

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It is possible to perform multiprocessor communication with the USART (with several

USARTs connected in a network). For instance one of the USARTs can be the master, its TX
output connected to the RX inputs of the other USARTs. The others are slaves, their
respective TX outputs are logically ANDed together and connected to the RX input of the
master.
In multiprocessor configurations it is often desirable that only the intended message
recipient should actively receive the full message contents, thus reducing redundant USART
service overhead for all non addressed receivers.
The non addressed devices may be placed in mute mode by means of the muting function.
In order to use the mute mode feature, the MME bit must be set in the USART_CR1
register.
In mute mode:
• None of the reception status bits can be set.
• All the receive interrupts are inhibited.
• The RWU bit in USART_ISR register is set to 1. RWU can be controlled automatically
by hardware or by software, through the MMRQ bit in the USART_RQR register, under
certain conditions.
The USART can enter or exit from mute mode using one of two methods, depending on the
WAKE bit in the USART_CR1 register:
• Idle Line detection if the WAKE bit is reset,
• Address Mark detection if the WAKE bit is set.

Idle line detection (WAKE=0)

The USART enters mute mode when the MMRQ bit is written to 1 and the RWU is
automatically set.
It wakes up when an Idle frame is detected. Then the RWU bit is cleared by hardware but
the IDLE bit is not set in the USART_ISR register. An example of mute mode behavior using
Idle line detection is given in Figure 237.

Figure 237. Mute mode using Idle line detection

RXNE RXNE

RX Data 1 Data 2 Data 3 Data 4 IDLE Data 5 Data 6

RWU Mute mode Normal mode

MMRQ written to 1 Idle frame detected

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Note: If the MMRQ is set while the IDLE character has already elapsed, mute mode will not be
entered (RWU is not set).
If the USART is activated while the line is IDLE, the idle state is detected after the duration
of one IDLE frame (not only after the reception of one character frame).

4-bit/7-bit address mark detection (WAKE=1)

In this mode, bytes are recognized as addresses if their MSB is a ‘1’ otherwise they are
considered as data. In an address byte, the address of the targeted receiver is put in the 4
or 7 LSBs. The choice of 7 or 4-bit address detection is done using the ADDM7 bit. This 4-
bit/7-bit word is compared by the receiver with its own address which is programmed in the
ADD bits in the USART_CR2 register.
Note: In 7-bit and 9-bit data modes, address detection is done on 6-bit and 8-bit addresses
(ADD[5:0] and ADD[7:0]) respectively.
The USART enters mute mode when an address character is received which does not
match its programmed address. In this case, the RWU bit is set by hardware. The RXNE
flag is not set for this address byte and no interrupt or DMA request is issued when the
USART enters mute mode.
The USART also enters mute mode when the MMRQ bit is written to 1. The RWU bit is also
automatically set in this case.
The USART exits from mute mode when an address character is received which matches
the programmed address. Then the RWU bit is cleared and subsequent bytes are received
normally. The RXNE bit is set for the address character since the RWU bit has been
cleared.
An example of mute mode behavior using address mark detection is given in Figure 238.

Figure 238. Mute mode using address mark detection

In this example, the current address of the receiver is 1
(programmed in the USART_CR2 register)
RXNE RXNE RXNE

RX IDLE Addr=0 Data 1 Data 2 IDLE Addr=1 Data 3 Data 4 Addr=2 Data 5

RWU Mute mode Normal mode Mute mode

MMRQ written to 1 Matching address Non-matching address

(RXNE was cleared)

Non-matching address
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23.4.8 USART parity control

Parity control (generation of parity bit in transmission and parity checking in reception) can
be enabled by setting the PCE bit in the USART_CR1 register. Depending on the frame
length defined by the M bit, the possible USART frame formats are as listed in Table 91.

Table 91. Frame formats

M bit PCE bit USART frame(1)

0 0 | SB | 8-bit data | STB |

0 1 | SB | 7-bit data | PB | STB |
1 0 | SB | 9-bit data | STB |
1 1 | SB | 8-bit data PB | STB |
1. Legends: SB: start bit, STB: stop bit, PB: parity bit. In the data register, the PB is always taking the MSB
position (8th or 7th, depending on the M bits value).

Even parity
The parity bit is calculated to obtain an even number of “1s” inside the frame of the 7 or 8
LSB bits (depending on M bit value) and the parity bit.
As an example, if data=00110101, and 4 bits are set, then the parity bit is 0 if even parity is
selected (PS bit in USART_CR1 = 0).

Odd parity
The parity bit is calculated to obtain an odd number of “1s” inside the frame made of the 7 or
8 LSB bits (depending on M bit value) and the parity bit.
As an example, if data=00110101 and 4 bits set, then the parity bit is 1 if odd parity is
selected (PS bit in USART_CR1 = 1).

Parity checking in reception

If the parity check fails, the PE flag is set in the USART_ISR register and an interrupt is
generated if PEIE is set in the USART_CR1 register. The PE flag is cleared by software
writing 1 to the PECF in the USART_ICR register.

Parity generation in transmission

If the PCE bit is set in USART_CR1, then the MSB bit of the data written in the data register
is transmitted but is changed by the parity bit (even number of “1s” if even parity is selected
(PS=0) or an odd number of “1s” if odd parity is selected (PS=1)).
For code example, refer to A.15.6: USART synchronous mode.

23.4.9 USART synchronous mode

The synchronous mode is selected by writing the CLKEN bit in the USART_CR2 register to
1. In synchronous mode, the following bits must be kept cleared:
• SCEN, HDSEL and IREN bits in the USART_CR3 register.
In this mode, the USART can be used to control bidirectional synchronous serial
communications in master mode. The CK pin is the output of the USART transmitter clock.

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No clock pulses are sent to the CK pin during start bit and stop bit. Depending on the state
of the LBCL bit in the USART_CR2 register, clock pulses are, or are not, generated during
the last valid data bit (address mark). The CPOL bit in the USART_CR2 register is used to
select the clock polarity, and the CPHA bit in the USART_CR2 register is used to select the
phase of the external clock (see Figure 239, Figure 240 and Figure 241).
During the Idle state, preamble and send break, the external CK clock is not activated.
In synchronous mode the USART transmitter works exactly like in asynchronous mode. But
as CK is synchronized with TX (according to CPOL and CPHA), the data on TX is
synchronous.
In this mode the USART receiver works in a different manner compared to the
asynchronous mode. If RE=1, the data is sampled on CK (rising or falling edge, depending
on CPOL and CPHA), without any oversampling. A setup and a hold time must be
respected (which depends on the baud rate: 1/16 bit duration).
Note: The CK pin works in conjunction with the TX pin. Thus, the clock is provided only if the
transmitter is enabled (TE=1) and data is being transmitted (the data register USART_TDR
written). This means that it is not possible to receive synchronous data without transmitting
data.
The LBCL, CPOL and CPHA bits have to be selected when the USART is disabled (UE=0)
to ensure that the clock pulses function correctly.
For code example, refer to A.15.6: USART synchronous mode.

Figure 239. USART example of synchronous transmission

RX Data out
TX Data in
Synchronous device
USART
(slave SPI)

CK Clock

MSv31158V2

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Figure 240. USART data clock timing diagram (M=0)

Idle or preceding M=0 (8 data bits) Idle or next

transmission Start Stop transmission

Clock (CPOL=0, CPHA=0 *

Clock (CPOL=0, CPHA=1

*

Clock (CPOL=1, CPHA=0 *

Clock (CPOL=1, CPHA=1 *

Data on TX
0 1 2 3 4 5 6 7
(from master)
Start LSB MSB Stop
Data on RX
0 1 2 3 4 5 6 7
(from slave)
LSB MSB
*
Capture strobe
*LBCL bit controls last data pulse

MSv31159V1

Figure 241. USART data clock timing diagram (M=1)

Idle or
Idle or next
preceding Start M=1 (9 data bits) Stop
transmission
transmission

Clock (CPOL=0,
CPHA=0 *
Clock (CPOL=0,
CPHA=1 *

Clock (CPOL=1, *
CPHA=0
Clock (CPOL=1, *
CPHA=1

Data on TX
0 1 2 3 4 5 6 7 8
(from master)
Start LSB MSB Stop
Data on RX
0 1 2 3 4 5 6 7 8
(from slave)
LSB MSB
Capture *
strobe
*LBCL bit controls last data pulse

MSv31160V1

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Figure 242. RX data setup/hold time

CK
(capture strobe on CK rising
edge in this example)

Data on RX (from slave) Valid DATA bit

tSETUP tHOLD

tSETUP=tHOLD 1/16 bit time

MSv31161V2

23.4.10 USART Single-wire Half-duplex communication

Single-wire Half-duplex mode is selected by setting the HDSEL bit in the USART_CR3
register. In this mode, the following bits must be kept cleared:
• CLKEN bit in the USART_CR2 register,
• SCEN and IREN bits in the USART_CR3 register.
The USART can be configured to follow a Single-wire Half-duplex protocol where the TX
and RX lines are internally connected. The selection between half- and Full-duplex
communication is made with a control bit HDSEL in USART_CR3.
As soon as HDSEL is written to 1:
• The TX and RX lines are internally connected
• The RX pin is no longer used
• The TX pin is always released when no data is transmitted. Thus, it acts as a standard
I/O in idle or in reception. It means that the I/O must be configured so that TX is
configured as alternate function open-drain with an external pull-up.
Apart from this, the communication protocol is similar to normal USART mode. Any conflicts
on the line must be managed by software (by the use of a centralized arbiter, for instance).
In particular, the transmission is never blocked by hardware and continues as soon as data
is written in the data register while the TE bit is set.
For code example, refer to A.15.7: USART DMA.

23.4.11 USART continuous communication in DMA mode

The USART is capable of performing continuous communication using the DMA. The DMA
requests for Rx buffer and Tx buffer are generated independently.
Note: Please refer to Section 23.3: USART implementation on page 592 to determine if the DMA
mode is supported. If DMA is not supported, use the USART as explained in Section 23.4.2:
USART transmitter or Section 23.4.3: USART receiver. To perform continuous
communication, the user can clear the TXE/ RXNE flags In the USART_ISR register.
For code example, refer to A.15.7: USART DMA.

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Transmission using DMA

DMA mode can be enabled for transmission by setting DMAT bit in the USART_CR3
register. Data is loaded from a SRAM area configured using the DMA peripheral (refer to
Section 10: Direct memory access controller (DMA) on page 149) to the USART_TDR
register whenever the TXE bit is set. To map a DMA channel for USART transmission, use
the following procedure (x denotes the channel number):
1. Write the USART_TDR register address in the DMA control register to configure it as
the destination of the transfer. The data is moved to this address from memory after
each TXE event.
2. Write the memory address in the DMA control register to configure it as the source of
the transfer. The data is loaded into the USART_TDR register from this memory area
after each TXE event.
3. Configure the total number of bytes to be transferred to the DMA control register.
4. Configure the channel priority in the DMA register
5. Configure DMA interrupt generation after half/ full transfer as required by the
application.
6. Clear the TC flag in the USART_ISR register by setting the TCCF bit in the
USART_ICR register.
7. Activate the channel in the DMA register.
When the number of data transfers programmed in the DMA Controller is reached, the DMA
controller generates an interrupt on the DMA channel interrupt vector.
In transmission mode, once the DMA has written all the data to be transmitted (the TCIF flag
is set in the DMA_ISR register), the TC flag can be monitored to make sure that the USART
communication is complete. This is required to avoid corrupting the last transmission before
disabling the USART or entering Stop mode. Software must wait until TC=1. The TC flag
remains cleared during all data transfers and it is set by hardware at the end of transmission
of the last frame.

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Figure 243. Transmission using DMA

Idle preamble Frame 1 Frame 2 Frame 3

TX line

Set by hardware Set by hardware

TXE flag cleared by DMA read cleared by DMA read Set by hardware

DMA request Ignored by the DMA because

the transfer is complete

USART_TDR F1 F2 F3

TC flag Set by
hardware
DMA writes
USART_TDR
Cleared
DMA TCIF flag by
Set by hardware software
(transfer
complete)

Software The DMA

configures DMA DMA writes DMA writes DMA writes transfer is
to send 3 data F1 into F2 into F3 into complete Software waits until TC=1
blocks and USART_TDR USART_TDR USART_TDR (TCIF=1 in
enables USART DMA_ISR)

ai17192b

Reception using DMA

DMA mode can be enabled for reception by setting the DMAR bit in USART_CR3 register.
Data is loaded from the USART_RDR register to a SRAM area configured using the DMA
peripheral (refer to Section 10: Direct memory access controller (DMA) on page 149)
whenever a data byte is received. To map a DMA channel for USART reception, use the
following procedure:
1. Write the USART_RDR register address in the DMA control register to configure it as
the source of the transfer. The data is moved from this address to the memory after
each RXNE event.
2. Write the memory address in the DMA control register to configure it as the destination
of the transfer. The data is loaded from USART_RDR to this memory area after each
RXNE event.
3. Configure the total number of bytes to be transferred to the DMA control register.
4. Configure the channel priority in the DMA control register
5. Configure interrupt generation after half/ full transfer as required by the application.
6. Activate the channel in the DMA control register.
When the number of data transfers programmed in the DMA Controller is reached, the DMA
controller generates an interrupt on the DMA channel interrupt vector.

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Figure 244. Reception using DMA

Frame 1 Frame 2 Frame 3

TX line

Set by hardware
RXNE flag cleared by DMA read

DMA request

USART_RDR F1 F2 F3

DMA reads
USART_RDR
Cleared
DMA TCIF flag Set by hardware by
(transfer complete) software

Software configures the The DMA transfer

DMA to receive 3 data DMA reads F1 DMA reads F2 DMA reads F3 is complete
blocks and enables from USART_RDR from USART_RDR from USART_RDR (TCIF=1 in
the USART DMA_ISR)
ai17193c

Error flagging and interrupt generation in multibuffer communication

In multibuffer communication if any error occurs during the transaction the error flag is
asserted after the current byte. An interrupt is generated if the interrupt enable flag is set.
For framing error, overrun error and noise flag which are asserted with RXNE in single byte
reception, there is a separate error flag interrupt enable bit (EIE bit in the USART_CR3
register), which, if set, enables an interrupt after the current byte if any of these errors occur.

23.4.12 RS232 hardware flow control and RS485 driver enable

using USART
It is possible to control the serial data flow between 2 devices by using the CTS input and
the RTS output. The Figure 245 shows how to connect 2 devices in this mode:

Figure 245. Hardware flow control between 2 USARTs

USART 1 USART 2

TX RX
TX circuit RX circuit
CTS RTS

RX TX
RX circuit TX circuit
RTS CTS

MSv31169V2

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RS232 RTS and CTS flow control can be enabled independently by writing the RTSE and
CTSE bits respectively to 1 (in the USART_CR3 register).

RS232 RTS flow control

If the RTS flow control is enabled (RTSE=1), then RTS is deasserted (tied low) as long as
the USART receiver is ready to receive a new data. When the receive register is full, RTS is
asserted, indicating that the transmission is expected to stop at the end of the current frame.
Figure 246 shows an example of communication with RTS flow control enabled.

Figure 246. RS232 RTS flow control

Start Stop Start Stop

RX Data 1 Idle Data 2
bit bit bit bit

RTS

RXNE Data 1 read RXNE

Data 2 can now be transmitted

MSv68794V1

RS232 CTS flow control

If the CTS flow control is enabled (CTSE=1), then the transmitter checks the CTS input
before transmitting the next frame. If CTS is deasserted (tied low), then the next data is
transmitted (assuming that data is to be transmitted, in other words, if TXE=0), else the
transmission does not occur. when CTS is asserted during a transmission, the current
transmission is completed before the transmitter stops.
When CTSE=1, the CTSIF status bit is automatically set by hardware as soon as the CTS
input toggles. It indicates when the receiver becomes ready or not ready for communication.
An interrupt is generated if the CTSIE bit in the USART_CR3 register is set. Figure 247
shows an example of communication with CTS flow control enabled.

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Figure 247. RS232 CTS flow control

CTS CTS

CTS

Transmit data register

TDR Data 2 empty Data 3 empty

Stop Start Stop Start

TX Data 1 Data 2 Idle Data 3
bit bit bit bit

Writing data 3 in TDR Transmission of Data 3 is

delayed until CTS = 0
MSv68793V1

Note: For correct behavior, CTS must be deasserted at least 3 USART clock source periods
before the end of the current character. In addition it should be noted that the CTSCF flag
may not be set for pulses shorter than 2 x PCLK periods.
For code example, refer to A.15.8: USART hardware flow control.

RS485 Driver Enable

The driver enable feature is enabled by setting bit DEM in the USART_CR3 control register.
This allows the user to activate the external transceiver control, through the DE (Driver
Enable) signal. The assertion time is the time between the activation of the DE signal and
the beginning of the START bit. It is programmed using the DEAT [4:0] bit fields in the
USART_CR1 control register. The de-assertion time is the time between the end of the last
stop bit, in a transmitted message, and the de-activation of the DE signal. It is programmed
using the DEDT [4:0] bit fields in the USART_CR1 control register. The polarity of the DE
signal can be configured using the DEP bit in the USART_CR3 control register.
In USART, the DEAT and DEDT are expressed in sample time units (1/8 or 1/16 bit duration,
depending on the oversampling rate).

23.5 USART in low-power modes

Table 92. Effect of low-power modes on the USART
Mode Description

Sleep No effect. USART interrupt causes the device to exit Sleep mode.
The USART is not clocked. It is not functional in Stop mode but its
Stop
configuration is kept upon wake-up.
The USART is powered down and must be reinitialized when the device
Standby
has exited from Standby mode.

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23.6 USART interrupts

Table 93. USART interrupt requests
Enable Control
Interrupt event Event flag
bit

Transmit data register empty TXE TXEIE

CTS interrupt CTSIF CTSIE
Transmission Complete TC TCIE
Receive data register not empty (data ready to be read) RXNE
RXNEIE
Overrun error detected ORE
Idle line detected IDLE IDLEIE
Parity error PE PEIE
Noise Flag, Overrun error and Framing Error in multibuffer
NF or ORE or FE EIE
communication.
Character match CMF CMIE
Receiver timeout RTOF RTOIE

The USART interrupt events are connected to the same interrupt vector (see Figure 248).
• During transmission: Transmission Complete, Clear to Send, Transmit data Register
empty interrupt.
• During reception: Idle Line detection, Overrun error, Receive data register not empty,
Parity error, Noise Flag, Framing Error, Character match, etc.
These events generate an interrupt if the corresponding Enable Control Bit is set.

Figure 248. USART interrupt mapping diagram

TC
TCIE
TXE
TXEIE
CTSIF
CTSIE
IDLE
IDLEIE
RXNEIE USART
ORE interrupt
RXNEIE
RXNE
PE
PEIE
LBDF
LBDIE
FE
NF
ORE EIE
CMF
CMIE
RTOF
RTOIE

MSv32635V2

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23.7 USART registers

Refer to Section 1.2 on page 33 for a list of abbreviations used in register descriptions.
The peripheral registers have to be accessed by words (32 bits).

23.7.1 USART control register 1 (USART_CR1)

Address offset: 0x00
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. M1 Res. RTOIE DEAT[4:0] DEDT[4:0]
rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OVER8 CMIE MME M0 WAKE PCE PS PEIE TXEIE TCIE RXNEIE IDLEIE TE RE Res. UE
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:29 Reserved, must be kept at reset value.

Bit 28 M1: Word length
This bit, with bit 12 (M0), determines the word length. It is set or cleared by software.
M[1:0] = 00: 1 Start bit, 8 data bits, n stop bits
M[1:0] = 01: 1 Start bit, 9 data bits, n stop bits
M[1:0] = 10: Reserved
This bit can only be written when the USART is disabled (UE=0).
Bit 27 Reserved, must be kept at reset value.
Bit 26 RTOIE: Receiver timeout interrupt enable
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An USART interrupt is generated when the RTOF bit is set in the USART_ISR register.
Note: If the USART does not support the Receiver timeout feature, this bit is reserved and
must be kept at reset value. Section 23.3: USART implementation on page 592.
Bits 25:21 DEAT[4:0]: Driver Enable assertion time
This 5-bit value defines the time between the activation of the DE (Driver Enable) signal and
the beginning of the start bit. It is expressed in sample time units (1/8 or 1/16 bit duration,
depending on the oversampling rate).
This bit field can only be written when the USART is disabled (UE=0).
Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at
reset value. Please refer to Section 23.3: USART implementation on page 592.
Bits 20:16 DEDT[4:0]: Driver Enable de-assertion time
This 5-bit value defines the time between the end of the last stop bit, in a transmitted
message, and the de-activation of the DE (Driver Enable) signal. It is expressed in sample
time units (1/8 or 1/16 bit duration, depending on the oversampling rate).
If the USART_TDR register is written during the DEDT time, the new data is transmitted only
when the DEDT and DEAT times have both elapsed.
This bit field can only be written when the USART is disabled (UE=0).
Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at
reset value. Please refer to Section 23.3: USART implementation on page 592.

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Bit 15 OVER8: Oversampling mode

0: Oversampling by 16
1: Oversampling by 8
This bit can only be written when the USART is disabled (UE=0).
Note:
Bit 14 CMIE: Character match interrupt enable
This bit is set and cleared by software.
0: Interrupt is inhibited
1: A USART interrupt is generated when the CMF bit is set in the USART_ISR register.
Bit 13 MME: Mute mode enable
This bit activates the mute mode function of the USART. when set, the USART can switch
between the active and mute modes, as defined by the WAKE bit. It is set and cleared by
software.
0: Receiver in active mode permanently
1: Receiver can switch between mute mode and active mode.
Bit 12 M0: Word length
This bit determines the word length. It is set or cleared by software.
0: 1 Start bit, 8 data bits, n stop bits
1: 1 Start bit, 9 data bits, n stop bits
Bit 11 WAKE: Receiver wake-up method
This bit determines the USART wake-up method from Mute mode. It is set or cleared by
software.
0: Idle line
1: Address mark
This bit field can only be written when the USART is disabled (UE=0).
Bit 10 PCE: Parity control enable
This bit selects the hardware parity control (generation and detection). When the parity
control is enabled, the computed parity is inserted at the MSB position (9th bit if M=1; 8th bit
if M=0) and parity is checked on the received data. This bit is set and cleared by software.
Once it is set, PCE is active after the current byte (in reception and in transmission).
0: Parity control disabled
1: Parity control enabled
This bit field can only be written when the USART is disabled (UE=0).
Bit 9 PS: Parity selection
This bit selects the odd or even parity when the parity generation/detection is enabled (PCE
bit set). It is set and cleared by software. The parity is selected after the current byte.
0: Even parity
1: Odd parity
This bit field can only be written when the USART is disabled (UE=0).
Bit 8 PEIE: PE interrupt enable
This bit is set and cleared by software.
0: Interrupt is inhibited
1: A USART interrupt is generated whenever PE=1 in the USART_ISR register
Bit 7 TXEIE: interrupt enable
This bit is set and cleared by software.
0: Interrupt is inhibited
1: A USART interrupt is generated whenever TXE=1 in the USART_ISR register

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Bit 6 TCIE: Transmission complete interrupt enable

This bit is set and cleared by software.
0: Interrupt is inhibited
1: A USART interrupt is generated whenever TC=1 in the USART_ISR register
Bit 5 RXNEIE: RXNE interrupt enable
This bit is set and cleared by software.
0: Interrupt is inhibited
1: A USART interrupt is generated whenever ORE=1 or RXNE=1 in the USART_ISR
register
Bit 4 IDLEIE: IDLE interrupt enable
This bit is set and cleared by software.
0: Interrupt is inhibited
1: A USART interrupt is generated whenever IDLE=1 in the USART_ISR register
Bit 3 TE: Transmitter enable
This bit enables the transmitter. It is set and cleared by software.
0: Transmitter is disabled
1: Transmitter is enabled
During transmission, a “0” pulse on the TE bit (“0” followed by “1”) sends a preamble
(idle line) after the current word. In order to generate an idle character, the TE must not
be immediately written to 1.
Bit 2 RE: Receiver enable
This bit enables the receiver. It is set and cleared by software.
0: Receiver is disabled
1: Receiver is enabled and begins searching for a start bit
Bit 1 Reserved, must be kept at reset value.
Bit 0 UE: USART enable
When this bit is cleared, the USART prescalers and outputs are stopped immediately, and
current operations are discarded. The configuration of the USART is kept, but all the status
flags, in the USART_ISR are set to their default values. This bit is set and cleared by
software.
0: USART prescaler and outputs disabled, low-power mode
1: USART enabled
Note: In order to go into low-power mode without generating errors on the line, the TE bit
must be reset before and the software must wait for the TC bit in the USART_ISR to be
set before resetting the UE bit.
The DMA requests are also reset when UE = 0 so the DMA channel must be disabled
before resetting the UE bit.

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23.7.2 USART control register 2 (USART_CR2)

Address offset: 0x04
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MSBFI
ADD[7:4] ADD[3:0] RTOEN ABRMOD[1:0] ABREN DATAINV TXINV RXINV
RST
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

SWAP Res. STOP[1:0] CLKEN CPOL CPHA LBCL Res. Res. .Res. ADDM7 Res. Res. Res. Res.

rw rw rw rw rw rw rw rw

Bits 31:28 ADD[7:4]: Address of the USART node

This bit-field gives the address of the USART node or a character code to be recognized.
This is used in multiprocessor communication during Mute mode or Stop mode, for wake-up with 7-
bit address mark detection. The MSB of the character sent by the transmitter should be equal to 1.
It may also be used for character detection during normal reception, Mute mode inactive . In this
case, the whole received character (8-bit) is compared to the ADD[7:0] value and CMF flag is set on
match.
This bit field can only be written when reception is disabled (RE = 0) or the USART is disabled
(UE=0)
Bits 27:24 ADD[3:0]: Address of the USART node
This bit-field gives the address of the USART node or a character code to be recognized.
This is used in multiprocessor communication during Mute mode or Stop mode, for wake-up with
address mark detection.
This bit field can only be written when reception is disabled (RE = 0) or the USART is disabled
(UE=0)
Bit 23 RTOEN: Receiver timeout enable
This bit is set and cleared by software.
0: Receiver timeout feature disabled.
1: Receiver timeout feature enabled.
When this feature is enabled, the RTOF flag in the USART_ISR register is set if the RX line is idle
(no reception) for the duration programmed in the RTOR (receiver timeout register).
Note: If the USART does not support the Receiver timeout feature, this bit is reserved and must be
kept at reset value. Please refer to Section 23.3: USART implementation on page 592.
Bits 22:21 ABRMOD[1:0]: Auto baud rate mode
These bits are set and cleared by software.
00: Measurement of the start bit is used to detect the baud rate.
01: Falling edge to falling edge measurement. (the received frame must start with a single bit = 1 ->
Frame = Start10xxxxxx)
10: 0x7F frame detection.
11: 0x55 frame detection
This bit field can only be written when ABREN = 0 or the USART is disabled (UE=0).
Note: If DATAINV=1 and/or MSBFIRST=1 the patterns must be the same on the line, for example
0xAA for MSBFIRST)
If the USART does not support the auto baud rate feature, this bit is reserved and must be kept
at reset value. Please refer to Section 23.3: USART implementation on page 592.

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Bit 20 ABREN: Auto baud rate enable

This bit is set and cleared by software.
0: Auto baud rate detection is disabled.
1: Auto baud rate detection is enabled.
Note: If the USART does not support the auto baud rate feature, this bit is reserved and must be kept
at reset value. Please refer to Section 23.3: USART implementation on page 592.
Bit 19 MSBFIRST: Most significant bit first
This bit is set and cleared by software.
0: data is transmitted/received with data bit 0 first, following the start bit.
1: data is transmitted/received with the MSB (bit 7/8/9) first, following the start bit.
This bit field can only be written when the USART is disabled (UE=0).
Bit 18 DATAINV: Binary data inversion
This bit is set and cleared by software.
0: Logical data from the data register are send/received in positive/direct logic. (1=H, 0=L)
1: Logical data from the data register are send/received in negative/inverse logic. (1=L, 0=H). The
parity bit is also inverted.
This bit field can only be written when the USART is disabled (UE=0).
Bit 17 TXINV: TX pin active level inversion
This bit is set and cleared by software.
0: TX pin signal works using the standard logic levels (VDD =1/idle, Gnd=0/mark)
1: TX pin signal values are inverted. (VDD =0/mark, Gnd=1/idle).
This allows the use of an external inverter on the TX line.
This bit field can only be written when the USART is disabled (UE=0).
Bit 16 RXINV: RX pin active level inversion
This bit is set and cleared by software.
0: RX pin signal works using the standard logic levels (VDD =1/idle, Gnd=0/mark)
1: RX pin signal values are inverted. (VDD =0/mark, Gnd=1/idle).
This allows the use of an external inverter on the RX line.
This bit field can only be written when the USART is disabled (UE=0).
Bit 15 SWAP: Swap TX/RX pins
This bit is set and cleared by software.
0: TX/RX pins are used as defined in standard pinout
1: The TX and RX pins functions are swapped. This allows to work in the case of a cross-wired
connection to another USART.
This bit field can only be written when the USART is disabled (UE=0).
Bit 14 Reserved, must be kept at reset value.
Bits 13:12 STOP[1:0]: STOP bits
These bits are used for programming the stop bits.
00: 1 stop bit
01: Reserved
10: 2 stop bits
11: Reserved
This bit field can only be written when the USART is disabled (UE=0).

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Bit 11 CLKEN: Clock enable

This bit allows the user to enable the CK pin.
0: CK pin disabled
1: CK pin enabled
This bit can only be written when the USART is disabled (UE=0).
Note: If synchronous mode is not supported, this bit is reserved and must be kept at reset value.
Please refer to Section 23.3: USART implementation on page 592.

Bit 10 CPOL: Clock polarity

This bit allows the user to select the polarity of the clock output on the CK pin in synchronous mode.
It works in conjunction with the CPHA bit to produce the desired clock/data relationship
0: Steady low value on CK pin outside transmission window
1: Steady high value on CK pin outside transmission window
This bit can only be written when the USART is disabled (UE=0).
Note: If synchronous mode is not supported, this bit is reserved and must be kept at reset value.
Please refer to Section 23.3: USART implementation on page 592.
Bit 9 CPHA: Clock phase
This bit is used to select the phase of the clock output on the CK pin in synchronous mode. It works
in conjunction with the CPOL bit to produce the desired clock/data relationship (see Figure 240 and
Figure 241)
0: The first clock transition is the first data capture edge
1: The second clock transition is the first data capture edge
This bit can only be written when the USART is disabled (UE=0).
Note: If synchronous mode is not supported, this bit is reserved and must be kept at reset value.
Please refer to Section 23.3: USART implementation on page 592.
Bit 8 LBCL: Last bit clock pulse
This bit is used to select whether the clock pulse associated with the last data bit transmitted (MSB)
has to be output on the CK pin in synchronous mode.
0: The clock pulse of the last data bit is not output to the CK pin
1: The clock pulse of the last data bit is output to the CK pin
Caution: The last bit is the 7th or 8th or 9th data bit transmitted depending on the 7 or 8 or 9 bit
format selected by the M bit in the USART_CR1 register.
This bit can only be written when the USART is disabled (UE=0).
Note: If synchronous mode is not supported, this bit is reserved and must be kept at reset value.
Please refer to Section 23.3: USART implementation on page 592.
Bits 7:5 Reserved, must be kept at reset value.
Bit 4 ADDM7:7-bit Address Detection/4-bit Address Detection
This bit is for selection between 4-bit address detection or 7-bit address detection.
0: 4-bit address detection
1: 7-bit address detection (in 8-bit data mode)
This bit can only be written when the USART is disabled (UE=0)
Note: In 7-bit and 9-bit data modes, the address detection is done on 6-bit and 8-bit address
(ADD[5:0] and ADD[7:0]) respectively.
Bits 3:0 Reserved, must be kept at reset value.

Note: The 3 bits (CPOL, CPHA, LBCL) should not be written while the transmitter is enabled.

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23.7.3 USART control register 3 (USART_CR3)

Address offset: 0x08
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OVRDI ONEBI
DEP DEM DDRE CTSIE CTSE RTSE DMAT DMAR Res. Res. HDSEL Res. Res. EIE
S T
rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:25 Reserved, must be kept at reset value.

Bit 24 Reserved, must be kept at reset value.
Bit 23 Reserved, must be kept at reset value.
Bits 19:17 Reserved, must be kept at reset value.
Bit 16 Reserved, must be kept at reset value.
Bit 15 DEP: Driver enable polarity selection
0: DE signal is active high.
1: DE signal is active low.
This bit can only be written when the USART is disabled (UE=0).
Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at
reset value. Please refer to Section 23.3: USART implementation on page 592.
Bit 14 DEM: Driver enable mode
This bit allows the user to activate the external transceiver control, through the DE signal.
0: DE function is disabled.
1: DE function is enabled. The DE signal is output on the RTS pin.
This bit can only be written when the USART is disabled (UE=0).
Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at
reset value. Section 23.3: USART implementation on page 592.
Bit 13 DDRE: DMA Disable on Reception Error
0: DMA is not disabled in case of reception error. The corresponding error flag is set but
RXNE is kept 0 preventing from overrun. As a consequence, the DMA request is not
asserted, so the erroneous data is not transferred (no DMA request), but next correct
received data are transferred .
1: DMA is disabled following a reception error. The corresponding error flag is set, as well as
RXNE. The DMA request is masked until the error flag is cleared. This means that the
software must first disable the DMA request (DMAR = 0) or clear RXNE before clearing the
error flag.
This bit can only be written when the USART is disabled (UE=0).
Note: The reception errors are: parity error, framing error or noise error.

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Bit 12 OVRDIS: Overrun Disable

This bit is used to disable the receive overrun detection.
0: Overrun Error Flag, ORE, is set when received data is not read before receiving new data.
1: Overrun functionality is disabled. If new data is received while the RXNE flag is still set
the ORE flag is not set and the new received data overwrites the previous content of the
USART_RDR register.
This bit can only be written when the USART is disabled (UE=0).
Note: This control bit allows checking the communication flow without reading the data.
Bit 11 ONEBIT: One sample bit method enable
This bit allows the user to select the sample method. When the one sample bit method is
selected the noise detection flag (NF) is disabled.
0: Three sample bit method
1: One sample bit method
This bit can only be written when the USART is disabled (UE=0).
Note: ONEBIT feature applies only to data bits, It does not apply to Start bit.
Bit 10 CTSIE: CTS interrupt enable
0: Interrupt is inhibited
1: An interrupt is generated whenever CTSIF=1 in the USART_ISR register
Note: If the hardware flow control feature is not supported, this bit is reserved and must be
kept at reset value. Please refer to Section 23.3: USART implementation on page 592.
Bit 9 CTSE: CTS enable
0: CTS hardware flow control disabled
1: CTS mode enabled, data is only transmitted when the CTS input is deasserted (tied to 0).
If the CTS input is asserted while data is being transmitted, then the transmission is
completed before stopping. If data is written into the data register while CTS is asserted, the
transmission is postponed until CTS is deasserted.
This bit can only be written when the USART is disabled (UE=0)
Note: If the hardware flow control feature is not supported, this bit is reserved and must be
kept at reset value. Please refer to Section 23.3: USART implementation on page 592.
Bit 8 RTSE: RTS enable
0: RTS hardware flow control disabled
1: RTS output enabled, data is only requested when there is space in the receive buffer. The
transmission of data is expected to cease after the current character has been transmitted.
The RTS output is deasserted (pulled to 0) when data can be received.
This bit can only be written when the USART is disabled (UE=0).
Note: If the hardware flow control feature is not supported, this bit is reserved and must be
kept at reset value. Please refer to Section 23.3: USART implementation on page 592.
Bit 7 DMAT: DMA enable transmitter
This bit is set/reset by software
1: DMA mode is enabled for transmission
0: DMA mode is disabled for transmission
Bit 6 DMAR: DMA enable receiver
This bit is set/reset by software
1: DMA mode is enabled for reception
0: DMA mode is disabled for reception
Bits 5:4 Reserved, must be kept at reset value.

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Bit 3 HDSEL: Half-duplex selection

Selection of Single-wire Half-duplex mode
0: Half duplex mode is not selected
1: Half duplex mode is selected
This bit can only be written when the USART is disabled (UE=0).
Bits 2:1 Reserved, must be kept at reset value.
Bit 0 EIE: Error interrupt enable
Error Interrupt Enable Bit is required to enable interrupt generation in case of a framing
error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the USART_ISR register).
0: Interrupt is inhibited
1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the USART_ISR register.

23.7.4 USART baud rate register (USART_BRR)

This register can only be written when the USART is disabled (UE=0). It may be
automatically updated by hardware in auto baud rate detection mode.
Address offset: 0x0C
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BRR[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:4 BRR[15:4]
BRR[15:4] = USARTDIV[15:4]
Bits 3:0 BRR[3:0]
When OVER8 = 0, BRR[3:0] = USARTDIV[3:0].
When OVER8 = 1:
BRR[2:0] = USARTDIV[3:0] shifted 1 bit to the right.
BRR[3] must be kept cleared.

23.7.5 USART receiver timeout register (USART_RTOR)

Address offset: 0x14
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. RTO[23:16]
rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RTO[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

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Bits 31:24 Reserved, must be kept at reset value.

Bits 23:0 RTO[23:0]: Receiver timeout value
This bit-field gives the Receiver timeout value in terms of number of bit duration.
In standard mode, the RTOF flag is set if, after the last received character, no new start bit is
detected for more than the RTO value.
Note: This value must only be programmed once per received character.

Note: RTOR can be written on the fly. If the new value is lower than or equal to the counter, the
RTOF flag is set.
This register is reserved and forced by hardware to “0x00000000” when the Receiver
timeout feature is not supported. Please refer to Section 23.3: USART implementation on
page 592.

23.7.6 USART request register (USART_RQR)

Address offset: 0x18
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. RXFRQ MMRQ SBKRQ ABRRQ
w w w w

Bits 31:4 Reserved, must be kept at reset value.

Bit 3 RXFRQ: Receive data flush request
Writing 1 to this bit clears the RXNE flag.
This allows to discard the received data without reading it, and avoid an overrun condition.
Bit 2 MMRQ: Mute mode request
Writing 1 to this bit puts the USART in mute mode and sets the RWU flag.
Bit 1 SBKRQ: Send break request
Writing 1 to this bit sets the SBKF flag and request to send a BREAK on the line, as soon as
the transmit machine is available.
Note: In the case the application needs to send the break character following all previously
inserted data, including the ones not yet transmitted, the software should wait for the
TXE flag assertion before setting the SBKRQ bit.
Bit 0 ABRRQ: Auto baud rate request
Writing 1 to this bit resets the ABRF and ABRE flags in the USART_ISR and request an
automatic baud rate measurement on the next received data frame.
Note: If the USART does not support the auto baud rate feature, this bit is reserved and must
be kept at reset value. Please refer to Section 23.3: USART implementation on
page 592.

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23.7.7 USART interrupt and status register (USART_ISR)

Address offset: 0x1C
Reset value: 0x0200 00C0

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. RWU SBKF CMF BUSY
r r r r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ABRF ABRE Res. Res. RTOF CTS CTSIF Res. TXE TC RXNE IDLE ORE NF FE PE
r r r r r r r r r r r r r

Bits 31:25 Reserved, must be kept at reset value.

Bits 24:22 Reserved, must be kept at reset value.
Bit 21 Reserved, must be kept at reset value
Bit 20 Reserved, must be kept at reset value.
Bit 19 RWU: Receiver wake-up from Mute mode
This bit indicates if the USART is in mute mode. It is cleared/set by hardware when a wake-
up/mute sequence is recognized. The mute mode control sequence (address or IDLE) is
selected by the WAKE bit in the USART_CR1 register.
When wake-up on IDLE mode is selected, this bit can only be set by software, writing 1 to
the MMRQ bit in the USART_RQR register.
0: Receiver in active mode
1: Receiver in mute mode
Bit 18 SBKF: Send break flag
This bit indicates that a send break character was requested. It is set by software, by writing
1 to the SBKRQ bit in the USART_RQR register. It is automatically reset by hardware during
the stop bit of break transmission.
0: No break character is transmitted
1: Break character is transmitted
Bit 17 CMF: Character match flag
This bit is set by hardware, when the character defined by ADD[7:0] is received. It is cleared
by software, writing 1 to the CMCF in the USART_ICR register.
An interrupt is generated if CMIE=1in the USART_CR1 register.
0: No Character match detected
1: Character Match detected
Bit 16 BUSY: Busy flag
This bit is set and reset by hardware. It is active when a communication is ongoing on the
RX line (successful start bit detected). It is reset at the end of the reception (successful or
not).
0: USART is idle (no reception)
1: Reception on going

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Bit 15 ABRF: Auto baud rate flag

This bit is set by hardware when the automatic baud rate has been set (RXNE will also be
set, generating an interrupt if RXNEIE = 1) or when the auto baud rate operation was
completed without success (ABRE=1) (ABRE, RXNE and FE are also set in this case)
It is cleared by software, in order to request a new auto baud rate detection, by writing 1 to
the ABRRQ in the USART_RQR register.
Note: If the USART does not support the auto baud rate feature, this bit is reserved and kept
at reset value.
Bit 14 ABRE: Auto baud rate error
This bit is set by hardware if the baud rate measurement failed (baud rate out of range or
character comparison failed)
It is cleared by software, by writing 1 to the ABRRQ bit in the USART_RQR register.
Note: If the USART does not support the auto baud rate feature, this bit is reserved and kept
at reset value.
Bits 13:12 Reserved, must be kept at reset value.
Bit 11 RTOF: Receiver timeout
This bit is set by hardware when the timeout value, programmed in the RTOR register has
lapsed, without any communication. It is cleared by software, writing 1 to the RTOCF bit in
the USART_ICR register.
An interrupt is generated if RTOIE=1 in the USART_CR1 register.
0: Timeout value not reached
1: Timeout value reached without any data reception
Note: If a time equal to the value programmed in RTOR register separates 2 characters,
RTOF is not set. If this time exceeds this value + 2 sample times (2/16 or 2/8,
depending on the oversampling method), RTOF flag is set.
The counter counts even if RE = 0 but RTOF is set only when RE = 1. If the timeout has
already elapsed when RE is set, then RTOF is set.
If the USART does not support the Receiver timeout feature, this bit is reserved and
kept at reset value.
Bit 10 CTS: CTS flag
This bit is set/reset by hardware. It is an inverted copy of the status of the CTS input pin.
0: CTS line set
1: CTS line reset
Note: If the hardware flow control feature is not supported, this bit is reserved and kept at
reset value.
Bit 9 CTSIF: CTS interrupt flag
This bit is set by hardware when the CTS input toggles, if the CTSE bit is set. It is cleared by
software, by writing 1 to the CTSCF bit in the USART_ICR register.
An interrupt is generated if CTSIE=1 in the USART_CR3 register.
0: No change occurred on the CTS status line
1: A change occurred on the CTS status line
Note: If the hardware flow control feature is not supported, this bit is reserved and kept at
reset value.
Bit 8 Reserved, must be kept at reset value.

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Bit 7 TXE: Transmit data register empty

This bit is set by hardware when the content of the USART_TDR register has been
transferred into the shift register. It is cleared by a write to the USART_TDR register.
An interrupt is generated if the TXEIE bit =1 in the USART_CR1 register.
0: data is not transferred to the shift register
1: data is transferred to the shift register)
Note: This bit is used during single buffer transmission.
Bit 6 TC: Transmission complete
This bit is set by hardware if the transmission of a frame containing data is complete and if
TXE is set. An interrupt is generated if TCIE=1 in the USART_CR1 register. It is cleared by
software, writing 1 to the TCCF in the USART_ICR register or by a write to the USART_TDR
register.
An interrupt is generated if TCIE=1 in the USART_CR1 register.
0: Transmission is not complete
1: Transmission is complete
Note: If TE bit is reset and no transmission is on going, the TC bit is set immediately.
Bit 5 RXNE: Read data register not empty
This bit is set by hardware when the content of the RDR shift register has been transferred
to the USART_RDR register. It is cleared by a read to the USART_RDR register. The RXNE
flag can also be cleared by writing 1 to the RXFRQ in the USART_RQR register.
An interrupt is generated if RXNEIE=1 in the USART_CR1 register.
0: data is not received
1: Received data is ready to be read.
Bit 4 IDLE: Idle line detected
This bit is set by hardware when an Idle Line is detected. An interrupt is generated if
IDLEIE=1 in the USART_CR1 register. It is cleared by software, writing 1 to the IDLECF in
the USART_ICR register.
0: No Idle line is detected
1: Idle line is detected
Note: The IDLE bit will not be set again until the RXNE bit has been set (i.e. a new idle line
occurs).
If mute mode is enabled (MME=1), IDLE is set if the USART is not mute (RWU=0),
whatever the mute mode selected by the WAKE bit. If RWU=1, IDLE is not set.
Bit 3 ORE: Overrun error
This bit is set by hardware when the data currently being received in the shift register is
ready to be transferred into the RDR register while RXNE=1. It is cleared by a software,
writing 1 to the ORECF, in the USART_ICR register.
An interrupt is generated if RXNEIE=1 in the USART_CR1 register, or EIE = 1 in the
USART_CR3 register.
0: No overrun error
1: Overrun error is detected
Note: When this bit is set, the RDR register content is not lost but the shift register is
overwritten. An interrupt is generated if the ORE flag is set during multibuffer
communication if the EIE bit is set.
This bit is permanently forced to 0 (no overrun detection) when the OVRDIS bit is set in
the USART_CR3 register.

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Bit 2 NF: START bit Noise detection flag

This bit is set by hardware when noise is detected on a received frame. It is cleared by
software, writing 1 to the NFCF bit in the USART_ICR register.
0: No noise is detected
1: Noise is detected
Note: This bit does not generate an interrupt as it appears at the same time as the RXNE bit
which itself generates an interrupt. An interrupt is generated when the NF flag is set
during multibuffer communication if the EIE bit is set.
Note: When the line is noise-free, the NF flag can be disabled by programming the ONEBIT
bit to 1 to increase the USART tolerance to deviations (Refer to Section 23.4.5:
Tolerance of the USART receiver to clock deviation on page 606).
Bit 1 FE: Framing error
This bit is set by hardware when a de-synchronization, excessive noise or a break character
is detected. It is cleared by software, writing 1 to the FECF bit in the USART_ICR register.
An interrupt is generated if EIE = 1 in the USART_CR3 register.
0: No Framing error is detected
1: Framing error or break character is detected
Bit 0 PE: Parity error
This bit is set by hardware when a parity error occurs in receiver mode. It is cleared by
software, writing 1 to the PECF in the USART_ICR register.
An interrupt is generated if PEIE = 1 in the USART_CR1 register.
0: No parity error
1: Parity error

23.7.8 USART interrupt flag clear register (USART_ICR)

Address offset: 0x20
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CMCF Res.
rc_w1
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. RTOCF Res. CTSCF Res. Res. TCCF Res. IDLECF ORECF NCF FECF PECF
rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1

Bits 31:20 Reserved, must be kept at reset value.

Bits 19:18 Reserved, must be kept at reset value.
Bit 17 CMCF: Character match clear flag
Writing 1 to this bit clears the CMF flag in the USART_ISR register.
Bits 16:12 Reserved, must be kept at reset value.
Bit 11 RTOCF: Receiver timeout clear flag
Writing 1 to this bit clears the RTOF flag in the USART_ISR register.
Note: If the USART does not support the Receiver timeout feature, this bit is reserved and
must be kept at reset value. Please refer to Section 23.3: USART implementation on
page 592.
Bit 10 Reserved, must be kept at reset value.

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Bit 9 CTSCF: CTS clear flag

Writing 1 to this bit clears the CTSIF flag in the USART_ISR register.
Note: If the hardware flow control feature is not supported, this bit is reserved and must be
kept at reset value. Please refer to Section 23.3: USART implementation on page 592.
Bit 8 Reserved, must be kept at reset value.
Bit 7 Reserved, must be kept at reset value.
Bit 6 TCCF: Transmission complete clear flag
Writing 1 to this bit clears the TC flag in the USART_ISR register.
Bit 5 Reserved, must be kept at reset value.
Bit 4 IDLECF: Idle line detected clear flag
Writing 1 to this bit clears the IDLE flag in the USART_ISR register.
Bit 3 ORECF: Overrun error clear flag
Writing 1 to this bit clears the ORE flag in the USART_ISR register.
Bit 2 NCF: Noise detected clear flag
Writing 1 to this bit clears the NF flag in the USART_ISR register.
Bit 1 FECF: Framing error clear flag
Writing 1 to this bit clears the FE flag in the USART_ISR register.
Bit 0 PECF: Parity error clear flag
Writing 1 to this bit clears the PE flag in the USART_ISR register.

23.7.9 USART receive data register (USART_RDR)

Address offset: 0x24
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. RDR[8:0]
r r r r r r r r r

Bits 31:9 Reserved, must be kept at reset value.

Bits 8:0 RDR[8:0]: Receive data value
Contains the received data character.
The RDR register provides the parallel interface between the input shift register and the
internal bus (see Figure 230).
When receiving with the parity enabled, the value read in the MSB bit is the received parity
bit.

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23.7.10 USART transmit data register (USART_TDR)

Address offset: 0x28
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. TDR[8:0]
rw rw rw rw rw rw rw rw rw

Bits 31:9 Reserved, must be kept at reset value.

Bits 8:0 TDR[8:0]: Transmit data value
Contains the data character to be transmitted.
The TDR register provides the parallel interface between the internal bus and the output
shift register (see Figure 230).
When transmitting with the parity enabled (PCE bit set to 1 in the USART_CR1 register),
the value written in the MSB (bit 7 or bit 8 depending on the data length) has no effect
because it is replaced by the parity.
Note: This register must be written only when TXE=1.

23.7.11 USART register map

The table below gives the USART register map and reset values.
Table 94. USART register map and reset values

Register
Offset name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12

10
11

9
8
7
6
5
4
3
2
1
0
reset value
RXNEIE
OVER8
DEDT4
DEDT3
DEDT2
DEDT1
DEDT0

IDLEIE
DEAT4
DEAT3
DEAT2
DEAT1
DEAT0
RTOIE

WAKE

TXEIE
CMIE
MME

PEIE

TCIE
Res.
Res.
Res.

Res.

Res.
PCE

RE

UE
M1

M0

PS

TE

USART_CR1
0x00

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
MSBFIRST
ABRMOD1
ABRMOD0

DATAINV

ADDM7
RTOEN

ABREN

CLKEN
RXINV
TXINV

SWAP

CPHA
CPOL

LBCL

.Res.

STOP
Res.

Res.
Res.

Res.
Res.
Res.
Res.

USART_CR2 ADD[7:4] ADD[3:0]

[1:0]
0x04

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
OVRDIS
ONEBIT

HDSEL
DMAR
CTSIE
DDRE

DMAT
CTSE
RTSE
DEM
DEP
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.
Res.

Res.
Res.
EIE

USART_CR3
0x08

Reset value 0 0 0 0 0 0 0 0 0 0 0 0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

USART_BRR BRR[15:0]
0x0C
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

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0x24
0x20
0x18
0x14
0x10

0x1C
Offset

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name

Reserved
Register

Reset value
Reset value
Reset value
Reset value

Reset value
Reset value

USART_ISR

USART_ICR

USART_TDR
USART_RDR
USART_RQR
reset value

USART_RTOR
Res. Res. Res. Res. Res. Res. Res. 31
Res. Res. Res. Res. Res. Res. Res. 30
Res. Res. Res. Res. Res. Res. Res. 29
Res. Res. Res. Res. Res. Res. Res. 28
Res. Res. Res. Res. Res. Res. Res. 27
Res. Res. Res. Res. Res. Res. Res. 26
Res. Res. Res. Res. Res. Res. Res. 25
Res. Res. Res. Res. Res.
0
Res. Res. 24
Res. Res. Res. Res. Res. Res. 23
0

Res. Res. Res. Res. Res. Res. 22

0

Res. Res. Res. Res. Res. Res. 21

0

Res. Res. Res. Res. Res. Res. 20

0
0

Res. Res. Res. RWU Res. Res. 19

0
0

Res. Res. Res. SBKF Res. Res. 18

0
0
0

RM0360 Rev 5
Res. Res. CMCF CMF Res. Res. 17
0
0

Res. Res. Res. 0 BUSY Res. Res. 16

0

Res. Res. Res. ABRF Res. Res. 15

0
0

Res. Res. Res. ABRE Res. Res. 14

0

Res. Res. Res. Res. Res. Res. 13

0

Res. Res. 0 Res. Res. Res. Res. 12

0
0

Res. Res. RTOCF RTOF Res. Res. 11

RTO[23:0]

0
0

Res. Res. Res. CTS Res. Res. 10

Universal synchronous/asynchronous receiver transmitter (USART/UART)

0
0
0

Res. Res. CTSCF CTSIF Res. Res. 9

Refer to Section 2.2 on page 37 for the register boundary addresses.

0

Res. Res. Res. Res. 8

Table 94. USART register map and reset values (continued)

1
0

Res. TXE Res. Res. 7

0
1
0

TCCF TC Res. Res. 6

0
0

Res. RXNE Res. Res. 5

0
0
0

IDLECF IDLE Res. Res. 4

0
0
0

X X X X X X
X X X X X X

TDR[8:0]
RDR[8:0]

ORECF ORE RXFRQ Res. 3

0
0
0

X
X

NCF NF MMRQ Res. 2

0
0
0

X
X

FECF FE SBKRQ Res. 1

0
0
0

X
X

PECF PE ABRRQ Res. 0

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RM0360 Serial peripheral interface (SPI)

24 Serial peripheral interface (SPI)

24.1 Introduction
The SPI interface can be used to communicate with external devices using the SPI protocol.
SPI mode is selectable by software. SPI Motorola mode is selected by default after a device
reset.
The serial peripheral interface (SPI) protocol supports half-duplex, full-duplex and simplex
synchronous, serial communication with external devices. The interface can be configured
as master and in this case it provides the communication clock (SCK) to the external slave
device. The interface is also capable of operating in multimaster configuration.

24.2 SPI main features

• Master or slave operation
• Full-duplex synchronous transfers on three lines
• Half-duplex synchronous transfer on two lines (with bidirectional data line)
• Simplex synchronous transfers on two lines (with unidirectional data line)
• 4 to 16-bit data size selection
• Multimaster mode capability
• 8 master mode baud rate prescalers up to fPCLK/2
• Slave mode frequency up to fPCLK/2.
• NSS management by hardware or software for both master and slave: dynamic change
of master/slave operations
• Programmable clock polarity and phase
• Programmable data order with MSB-first or LSB-first shifting
• Dedicated transmission and reception flags with interrupt capability
• SPI bus busy status flag
• SPI Motorola support
• Hardware CRC feature for reliable communication:
– CRC value can be transmitted as last byte in Tx mode
– Automatic CRC error checking for last received byte
• Master mode fault, overrun flags with interrupt capability
• CRC Error flag
• Two 32-bit embedded Rx and Tx FIFOs with DMA capability
• Enhanced TI and NSS pulse modes support

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24.3 SPI implementation

The following table describes all the SPI instances and their features embedded in the
devices.

Table 95. STM32F0x0 SPI implementation

STM32F030x4,
STM32F070xB
STM32F030x6
STM32F030x8 STM32F030xC
SPI Features STM32F070x6

SPI1 SPI1 SPI2 SPI1 SPI2

Enhanced NSSP & TI modes Yes Yes Yes Yes Yes

Hardware CRC calculation Yes Yes Yes Yes Yes
from 4 to from 4 to from 4 to from 4 to from 4 to
Data size configurable
16-bit 16-bit 16-bit 16-bit 16-bit
Rx/Tx FIFO size 32-bit 32-bit 32-bit 32-bit 32-bit
I2S support No No No No No
Wake-up capability from Low-power Sleep Yes Yes Yes Yes Yes

24.4 SPI functional description

24.4.1 General description

The SPI allows synchronous, serial communication between the MCU and external devices.
Application software can manage the communication by polling the status flag or using
dedicated SPI interrupt. The main elements of SPI and their interactions are shown in the
following block diagram Figure 249.

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Figure 249. SPI block diagram

Address and data bus

Read

Rx
FIFO
CRC controller
MOSI
MISO Shift register
RXONLY
CRCEN
CPOL CRCNEXT
CPHA CRCL
Tx DS[0:3]
FIFO
Write Communication
BIDIOE
controller

Baud rate BR[2:0]

SCK Internal NSS
generator

NSS
NSS logic
MS30117V1

Four I/O pins are dedicated to SPI communication with external devices.
• MISO: Master In / Slave Out data. In the general case, this pin is used to transmit data
in slave mode and receive data in master mode.
• MOSI: Master Out / Slave In data. In the general case, this pin is used to transmit data
in master mode and receive data in slave mode.
• SCK: Serial Clock output pin for SPI masters and input pin for SPI slaves.
• NSS: Slave select pin. Depending on the SPI and NSS settings, this pin can be used to
either:
– select an individual slave device for communication
– synchronize the data frame or
– detect a conflict between multiple masters
See Section 24.4.5: Slave select (NSS) pin management for details.
The SPI bus allows the communication between one master device and one or more slave
devices. The bus consists of at least two wires - one for the clock signal and the other for
synchronous data transfer. Other signals can be added depending on the data exchange
between SPI nodes and their slave select signal management.

24.4.2 Communications between one master and one slave

The SPI allows the MCU to communicate using different configurations, depending on the
device targeted and the application requirements. These configurations use 2 or 3 wires
(with software NSS management) or 3 or 4 wires (with hardware NSS management).
Communication is always initiated by the master.

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Full-duplex communication
By default, the SPI is configured for full-duplex communication. In this configuration, the
shift registers of the master and slave are linked using two unidirectional lines between the
MOSI and the MISO pins. During SPI communication, data is shifted synchronously on the
SCK clock edges provided by the master. The master transmits the data to be sent to the
slave via the MOSI line and receives data from the slave via the MISO line. When the data
frame transfer is complete (all the bits are shifted) the information between the master and
slave is exchanged.

Figure 250. Full-duplex single master/ single slave application

MISO MISO
Rx shift register Tx shift register
MOSI MOSI
Tx shift register Rx shift register

SPI clock SCK SCK

generator
NSS(1) NSS (1)
Master Slave

MSv39623V1

1. The NSS pins can be used to provide a hardware control flow between master and slave. Optionally, the
pins can be left unused by the peripheral. Then the flow has to be handled internally for both master and
slave. For more details see Section 24.4.5: Slave select (NSS) pin management.

Half-duplex communication
The SPI can communicate in half-duplex mode by setting the BIDIMODE bit in the
SPIx_CR1 register. In this configuration, one single cross connection line is used to link the
shift registers of the master and slave together. During this communication, the data is
synchronously shifted between the shift registers on the SCK clock edge in the transfer
direction selected reciprocally by both master and slave with the BDIOE bit in their
SPIx_CR1 registers. In this configuration, the master’s MISO pin and the slave’s MOSI pin
are free for other application uses and act as GPIOs.

Figure 251. Half-duplex single master/ single slave application

(2)
MISO MISO
Rx shift register Tx shift register
MOSI Nȍ(3) (2)
Tx shift register MOSI Rx shift register

SPI clock SCK SCK

generator
NSS (1) NSS(1)
Master Slave

MSv39624V1

1. The NSS pins can be used to provide a hardware control flow between master and slave. Optionally, the
pins can be left unused by the peripheral. Then the flow has to be handled internally for both master and
slave. For more details see Section 24.4.5: Slave select (NSS) pin management.
2. In this configuration, the master’s MISO pin and the slave’s MOSI pin can be used as GPIOs.
3. A critical situation can happen when communication direction is changed not synchronously between two

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nodes working at bidirectionnal mode and new transmitter accesses the common data line while former
transmitter still keeps an opposite value on the line (the value depends on SPI configuration and
communication data). Both nodes then fight while providing opposite output levels on the common line
temporary till next node changes its direction settings correspondingly, too. It is suggested to insert a serial
resistance between MISO and MOSI pins at this mode to protect the outputs and limit the current blowing
between them at this situation.

Simplex communications
The SPI can communicate in simplex mode by setting the SPI in transmit-only or in receive-
only using the RXONLY bit in the SPIx_CR1 register. In this configuration, only one line is
used for the transfer between the shift registers of the master and slave. The remaining
MISO and MOSI pins pair is not used for communication and can be used as standard
GPIOs.
• Transmit-only mode (RXONLY=0): The configuration settings are the same as for full-
duplex. The application has to ignore the information captured on the unused input pin.
This pin can be used as a standard GPIO.
• Receive-only mode (RXONLY=1): The application can disable the SPI output function
by setting the RXONLY bit. In slave configuration, the MISO output is disabled and the
pin can be used as a GPIO. The slave continues to receive data from the MOSI pin
while its slave select signal is active (see 24.4.5: Slave select (NSS) pin management).
Received data events appear depending on the data buffer configuration. In the master
configuration, the MOSI output is disabled and the pin can be used as a GPIO. The
clock signal is generated continuously as long as the SPI is enabled. The only way to
stop the clock is to clear the RXONLY bit or the SPE bit and wait until the incoming
pattern from the MISO pin is finished and fills the data buffer structure, depending on its
configuration.

Figure 252. Simplex single master/single slave application (master in transmit-only/

slave in receive-only mode)

(2) MISO MISO

Rx shift register Tx shift register
MOSI MOSI
Tx shift register Rx shift register

SPI clock SCK SCK

generator
NSS(1) NSS(1)
Master Slave

MSv39625V1

1. The NSS pins can be used to provide a hardware control flow between master and slave. Optionally, the
pins can be left unused by the peripheral. Then the flow has to be handled internally for both master and
slave. For more details see Section 24.4.5: Slave select (NSS) pin management.
2. An accidental input information is captured at the input of transmitter Rx shift register. All the events
associated with the transmitter receive flow must be ignored in standard transmit only mode (e.g. OVR
flag).
3. In this configuration, both the MISO pins can be used as GPIOs.
Note: Any simplex communication can be alternatively replaced by a variant of the half-duplex
communication with a constant setting of the transaction direction (bidirectional mode is
enabled while BDIO bit is not changed).

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24.4.3 Standard multislave communication

In a configuration with two or more independent slaves, the master uses GPIO pins to
manage the chip select lines for each slave (see Figure 253). The master must select one of
the slaves individually by pulling low the GPIO connected to the slave NSS input. When this
is done, a standard master and dedicated slave communication is established.

Figure 253. Master and three independent slaves

NSS (1)

MISO MISO
Rx shift register Tx shift register
MOSI MOSI
Tx shift register Rx shift register

SPI clock SCK SCK

generator
IO1 NSS
Master Slave 1
IO2
IO3

MISO
Tx shift register
MOSI
Rx shift register
SCK

NSS
Slave 2

MISO
Tx shift register
MOSI
Rx shift register
SCK

NSS
Slave 3
MSv39626V1

1. NSS pin is not used on master side at this configuration. It has to be managed internally (SSM=1, SSI=1) to
prevent any MODF error.
2. As MISO pins of the slaves are connected together, all slaves must have the GPIO configuration of their
MISO pin set as alternate function open-drain (see I/O alternate function input/output section (GPIO)).

24.4.4 Multimaster communication

Unless SPI bus is not designed for a multimaster capability primarily, the user can use build
in feature which detects a potential conflict between two nodes trying to master the bus at
the same time. For this detection, NSS pin is used configured at hardware input mode.

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The connection of more than two SPI nodes working at this mode is impossible as only one
node can apply its output on a common data line at time.
When nodes are non active, both stay at slave mode by default. Once one node wants to
overtake control on the bus, it switches itself into master mode and applies active level on
the slave select input of the other node via dedicated GPIO pin. After the session is
completed, the active slave select signal is released and the node mastering the bus
temporary returns back to passive slave mode waiting for next session start.
If potentially both nodes raised their mastering request at the same time a bus conflict event
appears (see mode fault MODF event). Then the user can apply some simple arbitration
process (e.g. to postpone next attempt by predefined different time-outs applied at both
nodes).

Figure 254. Multimaster application

MISO MISO
Rx (Tx) shift register Rx (Tx) shift register
MOSI MOSI
Tx (Rx) shift register Tx (Rx) shift register

SPI clock SCK SCK SPI clock

generator generator
(1)
GPIO NSS

Master NSS(1) GPIO Master

(Slave) (Slave)

MSv39628V1

1. The NSS pin is configured at hardware input mode at both nodes. Its active level enables the MISO line
output control as the passive node is configured as a slave.

24.4.5 Slave select (NSS) pin management

In slave mode, the NSS works as a standard “chip select” input and lets the slave
communicate with the master. In master mode, NSS can be used either as output or input.
As an input it can prevent multimaster bus collision, and as an output it can drive a slave
select signal of a single slave.
Hardware or software slave select management can be set using the SSM bit in the
SPIx_CR1 register:
• Software NSS management (SSM = 1): in this configuration, slave select information
is driven internally by the SSI bit value in register SPIx_CR1. The external NSS pin is
free for other application uses.
• Hardware NSS management (SSM = 0): in this case, there are two possible
configurations. The configuration used depends on the NSS output configuration
(SSOE bit in register SPIx_CR1).
– NSS output enable (SSM=0,SSOE = 1): this configuration is only used when the
MCU is set as master. The NSS pin is managed by the hardware. The NSS signal
is driven low as soon as the SPI is enabled in master mode (SPE=1), and is kept
low until the SPI is disabled (SPE =0). A pulse can be generated between

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continuous communications if NSS pulse mode is activated (NSSP=1). The SPI

cannot work in multimaster configuration with this NSS setting.
– NSS output disable (SSM=0, SSOE = 0): if the microcontroller is acting as the
master on the bus, this configuration allows multimaster capability. If the NSS pin
is pulled low in this mode, the SPI enters master mode fault state and the device is
automatically reconfigured in slave mode. In slave mode, the NSS pin works as a
standard “chip select” input and the slave is selected while NSS line is at low level.

Figure 255. Hardware/software slave select management

SSI control bit

SSM control bit

NSS Master
Slave mode
Inp. mode
Vdd OK Non active

1 Vss Conflict Active

NSS Input
0
NSS GPIO
pin logic

NSS NSS Output

Output
Control (used in Master mode and NSS
HW management only)

SSOE control bit

NSS external logic NSS internal logic

MSv35526V6

24.4.6 Communication formats

During SPI communication, receive and transmit operations are performed simultaneously.
The serial clock (SCK) synchronizes the shifting and sampling of the information on the data
lines. The communication format depends on the clock phase, the clock polarity and the
data frame format. To be able to communicate together, the master and slaves devices must
follow the same communication format.

Clock phase and polarity controls

Four possible timing relationships may be chosen by software, using the CPOL and CPHA
bits in the SPIx_CR1 register. The CPOL (clock polarity) bit controls the idle state value of
the clock when no data is being transferred. This bit affects both master and slave modes. If
CPOL is reset, the SCK pin has a low-level idle state. If CPOL is set, the SCK pin has a
high-level idle state.

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If the CPHA bit is set, the second edge on the SCK pin captures the first data bit transacted
(falling edge if the CPOL bit is reset, rising edge if the CPOL bit is set). Data are latched on
each occurrence of this clock transition type. If the CPHA bit is reset, the first edge on the
SCK pin captures the first data bit transacted (falling edge if the CPOL bit is set, rising edge
if the CPOL bit is reset). Data are latched on each occurrence of this clock transition type.
The combination of CPOL (clock polarity) and CPHA (clock phase) bits selects the data
capture clock edge.
Figure 256, shows an SPI full-duplex transfer with the four combinations of the CPHA and
CPOL bits.
Note: Prior to changing the CPOL/CPHA bits the SPI must be disabled by resetting the SPE bit.
The idle state of SCK must correspond to the polarity selected in the SPIx_CR1 register (by
pulling up SCK if CPOL=1 or pulling down SCK if CPOL=0).

Figure 256. Data clock timing diagram

CPHA =1
CPOL = 1

CPOL = 0

MOSI(1) MSBit LSBit

MISO(1) MSBit LSBit

NSS (to slave)

Capture strobe

CPHA =0
CPOL = 1

CPOL = 0

MOSI(1) MSBit LSBit

MISO(1) MSBit LSBit

NSS (to slave)

Capture strobe
ai17154e

1. The order of data bits depends on LSBFIRST bit setting.

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Data frame format

The SPI shift register can be set up to shift out MSB-first or LSB-first, depending on the
value of the LSBFIRST bit. The data frame size is chosen by using the DS bits. It can be set
from 4-bit up to 16-bit length and the setting applies for both transmission and reception.
Whatever the selected data frame size, read access to the FIFO must be aligned with the
FRXTH level. When the SPIx_DR register is accessed, data frames are always right-aligned
into either a byte (if the data fits into a byte) or a half-word (see Figure 257). During
communication, only bits within the data frame are clocked and transferred.

Figure 257. Data alignment when data length is not equal to 8-bit or 16-bit
DS <= 8 bits: data is right-aligned on byte DS > 8 bits: data is right-aligned on 16 bit
Example: DS = 5 bit Example: DS = 14 bit

7 5 4 0 15 14 13 0
XXX Data frame TX XX Data frame TX

7 5 4 0 15 14 13 0
000 Data frame RX 00 Data frame RX

MS19589V2

Note: The minimum data length is 4 bits. If a data length of less than 4 bits is selected, it is forced
to an 8-bit data frame size.

24.4.7 Configuration of SPI

The configuration procedure is almost the same for master and slave. For specific mode
setups, follow the dedicated sections. When a standard communication is to be initialized,
perform these steps:
1. Write proper GPIO registers: Configure GPIO for MOSI, MISO and SCK pins.
2. Write to the SPI_CR1 register:
a) Configure the serial clock baud rate using the BR[2:0] bits (Note: 4).
b) Configure the CPOL and CPHA bits combination to define one of the four
relationships between the data transfer and the serial clock (CPHA must be
cleared in NSSP mode). (Note: 2 - except the case when CRC is enabled at TI
mode).
c) Select simplex or half-duplex mode by configuring RXONLY or BIDIMODE and
BIDIOE (RXONLY and BIDIMODE cannot be set at the same time).
d) Configure the LSBFIRST bit to define the frame format (Note: 2).
e) Configure the CRCL and CRCEN bits if CRC is needed (while SCK clock signal is
at idle state).
f) Configure SSM and SSI (Notes: 2 & 3).
g) Configure the MSTR bit (in multimaster NSS configuration, avoid conflict state on

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NSS if master is configured to prevent MODF error).

3. Write to SPI_CR2 register:
a) Configure the DS[3:0] bits to select the data length for the transfer.
b) Configure SSOE (Notes: 1 & 2 & 3).
c) Set the FRF bit if the TI protocol is required (keep NSSP bit cleared in TI mode).
d) Set the NSSP bit if the NSS pulse mode between two data units is required (keep
CHPA and TI bits cleared in NSSP mode).
e) Configure the FRXTH bit. The RXFIFO threshold must be aligned to the read
access size for the SPIx_DR register.
f) Initialize LDMA_TX and LDMA_RX bits if DMA is used in packed mode.
4. Write to SPI_CRCPR register: Configure the CRC polynomial if needed.
5. Write proper DMA registers: Configure DMA streams dedicated for SPI Tx and Rx in
DMA registers if the DMA streams are used.
Note: (1) Step is not required in slave mode.
(2) Step is not required in TI mode.
(3) Step is not required in NSSP mode.
(4) The step is not required in slave mode except slave working at TI mode
For code example refer to the Appendix sections A.14.1: SPI master configuration and
A.14.2: SPI slave configuration.

24.4.8 Procedure for enabling SPI

It is recommended to enable the SPI slave before the master sends the clock. If not,
undesired data transmission might occur. The data register of the slave must already
contain data to be sent before starting communication with the master (either on the first
edge of the communication clock, or before the end of the ongoing communication if the
clock signal is continuous). The SCK signal must be settled at an idle state level
corresponding to the selected polarity before the SPI slave is enabled.
The master at full-duplex (or in any transmit-only mode) starts to communicate when the
SPI is enabled and TXFIFO is not empty, or with the next write to TXFIFO.
In any master receive only mode (RXONLY = 1 or BIDIMODE = 1 & BIDIOE = 0), master
starts to communicate and the clock starts running immediately after SPI is enabled.
For handling DMA, follow the dedicated section.

24.4.9 Data transmission and reception procedures

RXFIFO and TXFIFO
All SPI data transactions pass through the 32-bit embedded FIFOs. This enables the SPI to
work in a continuous flow, and prevents overruns when the data frame size is short. Each
direction has its own FIFO called TXFIFO and RXFIFO. These FIFOs are used in all SPI
modes except for receiver-only mode (slave or master) with CRC calculation enabled (see
Section 24.4.14: CRC calculation).
The handling of FIFOs depends on the data exchange mode (duplex, simplex), data frame
format (number of bits in the frame), access size performed on the FIFO data registers (8-bit

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or 16-bit), and whether or not data packing is used when accessing the FIFOs (see
Section 24.4.13: TI mode).
A read access to the SPIx_DR register returns the oldest value stored in RXFIFO that has
not been read yet. A write access to the SPIx_DR stores the written data in the TXFIFO at
the end of a send queue. The read access must be always aligned with the RXFIFO
threshold configured by the FRXTH bit in SPIx_CR2 register. FTLVL[1:0] and FRLVL[1:0]
bits indicate the current occupancy level of both FIFOs.
A read access to the SPIx_DR register must be managed by the RXNE event. This event is
triggered when data is stored in RXFIFO and the threshold (defined by FRXTH bit) is
reached. When RXNE is cleared, RXFIFO is considered to be empty. In a similar way, write
access of a data frame to be transmitted is managed by the TXE event. This event is
triggered when the TXFIFO level is less than or equal to half of its capacity. Otherwise TXE
is cleared and the TXFIFO is considered as full. In this way, RXFIFO can store up to four
data frames, whereas TXFIFO can only store up to three when the data frame format is not
greater than 8 bits. This difference prevents possible corruption of 3x 8-bit data frames
already stored in the TXFIFO when software tries to write more data in 16-bit mode into
TXFIFO. Both TXE and RXNE events can be polled or handled by interrupts. See
Figure 259 through Figure 262.
Another way to manage the data exchange is to use DMA (see Communication using DMA
(direct memory addressing)).
If the next data is received when the RXFIFO is full, an overrun event occurs (see
description of OVR flag at Section 24.4.10: SPI status flags). An overrun event can be
polled or handled by an interrupt.
The BSY bit being set indicates ongoing transaction of a current data frame. When the clock
signal runs continuously, the BSY flag stays set between data frames at master but
becomes low for a minimum duration of one SPI clock at slave between each data frame
transfer.

Sequence handling
A few data frames can be passed at single sequence to complete a message. When
transmission is enabled, a sequence begins and continues while any data is present in the
TXFIFO of the master. The clock signal is provided continuously by the master until TXFIFO
becomes empty, then it stops waiting for additional data.
In receive-only modes, half-duplex (BIDIMODE=1, BIDIOE=0) or simplex (BIDIMODE=0,
RXONLY=1) the master starts the sequence immediately when both SPI is enabled and
receive-only mode is activated. The clock signal is provided by the master and it does not
stop until either SPI or receive-only mode is disabled by the master. The master receives
data frames continuously up to this moment.
While the master can provide all the transactions in continuous mode (SCK signal is
continuous) it has to respect slave capability to handle data flow and its content at anytime.
When necessary, the master must slow down the communication and provide either a
slower clock or separate frames or data sessions with sufficient delays. Be aware there is no
underflow error signal for master or slave in SPI mode, and data from the slave is always
transacted and processed by the master even if the slave could not prepare it correctly in
time. It is preferable for the slave to use DMA, especially when data frames are shorter and
bus rate is high.
Each sequence must be encased by the NSS pulse in parallel with the multislave system to
select just one of the slaves for communication. In a single slave system it is not necessary

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to control the slave with NSS, but it is often better to provide the pulse here too, to
synchronize the slave with the beginning of each data sequence. NSS can be managed by
both software and hardware (see Section 24.4.5: Slave select (NSS) pin management).
When the BSY bit is set it signifies an ongoing data frame transaction. When the dedicated
frame transaction is finished, the RXNE flag is raised. The last bit is just sampled and the
complete data frame is stored in the RXFIFO.

Procedure for disabling the SPI

When SPI is disabled, it is mandatory to follow the disable procedures described in this
paragraph. It is important to do this before the system enters a low-power mode when the
peripheral clock is stopped. Ongoing transactions can be corrupted in this case. In some
modes the disable procedure is the only way to stop continuous communication running.
Master in full-duplex or transmit only mode can finish any transaction when it stops
providing data for transmission. In this case, the clock stops after the last data transaction.
Special care must be taken in packing mode when an odd number of data frames are
transacted to prevent some dummy byte exchange (refer to Data packing section). Before
the SPI is disabled in these modes, the user must follow standard disable procedure. When
the SPI is disabled at the master transmitter while a frame transaction is ongoing or next
data frame is stored in TXFIFO, the SPI behavior is not guaranteed.
When the master is in any receive only mode, the only way to stop the continuous clock is to
disable the peripheral by SPE=0. This must occur in specific time window within last data
frame transaction just between the sampling time of its first bit and before its last bit transfer
starts (in order to receive a complete number of expected data frames and to prevent any
additional “dummy” data reading after the last valid data frame). Specific procedure must be
followed when disabling SPI in this mode.
Data received but not read remains stored in RXFIFO when the SPI is disabled, and must
be processed the next time the SPI is enabled, before starting a new sequence. To prevent
having unread data, ensure that RXFIFO is empty when disabling the SPI, by using the
correct disabling procedure, or by initializing all the SPI registers with a software reset via
the control of a specific register dedicated to peripheral reset (see the SPIiRST bits in the
RCC_APBiRSTR registers).
Standard disable procedure is based on pulling BSY status together with FTLVL[1:0] to
check if a transmission session is fully completed. This check can be done in specific cases,
too, when it is necessary to identify the end of ongoing transactions, for example:
• When NSS signal is managed by software and master has to provide proper end of
NSS pulse for slave, or
• When transactions’ streams from DMA or FIFO are completed while the last data frame
or CRC frame transaction is still ongoing in the peripheral bus.
The correct disable procedure is (except when receive only mode is used):
1. Wait until FTLVL[1:0] = 00 (no more data to transmit).
2. Wait until BSY=0 (the last data frame is processed).
3. Disable the SPI (SPE=0).
4. Read data until FRLVL[1:0] = 00 (read all the received data).
The correct disable procedure for certain receive only modes is:

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1. Interrupt the receive flow by disabling SPI (SPE=0) in the specific time window while
the last data frame is ongoing.
2. Wait until BSY=0 (the last data frame is processed).
3. Read data until FRLVL[1:0] = 00 (read all the received data).
Note: If packing mode is used and an odd number of data frames with a format less than or equal
to 8 bits (fitting into one byte) has to be received, FRXTH must be set when FRLVL[1:0] =
01, in order to generate the RXNE event to read the last odd data frame and to keep good
FIFO pointer alignment.

Data packing
When the data frame size fits into one byte (less than or equal to 8 bits), data packing is
used automatically when any read or write 16-bit access is performed on the SPIx_DR
register. The double data frame pattern is handled in parallel in this case. At first, the SPI
operates using the pattern stored in the LSB of the accessed word, then with the other half
stored in the MSB. Figure 258 provides an example of data packing mode sequence
handling. Two data frames are sent after the single 16-bit access the SPIx_DR register of
the transmitter. This sequence can generate just one RXNE event in the receiver if the
RXFIFO threshold is set to 16 bits (FRXTH=0). The receiver then has to access both data
frames by a single 16-bit read of SPIx_DR as a response to this single RXNE event. The
RxFIFO threshold setting and the following read access must be always kept aligned at the
receiver side, as data can be lost if it is not in line.
A specific problem appears if an odd number of such “fit into one byte” data frames must be
handled. On the transmitter side, writing the last data frame of any odd sequence with an 8-
bit access to SPIx_DR is enough. The receiver has to change the Rx_FIFO threshold level
for the last data frame received in the odd sequence of frames in order to generate the
RXNE event.

Figure 258. Packing data in FIFO for transmission and reception

NSS

SCK

TXFIFO MOSI RXFIFO

SPIx_DR
SPIx_DR 0x0A 0x0A 0x04 0x0A
0x04 0x0A 0x04 SPI fsm SPI fsm 0x04
& shift & shift 0x04 0x0A

16-bit access when write to data register 16-bit access when read from data register
SPI_DR= 0x040A when TxE=1 SPI_DR= 0x040A when RxNE=1

MS19590V1

Communication using DMA (direct memory addressing)

To operate at its maximum speed and to facilitate the data register read/write process
required to avoid overrun, the SPI features a DMA capability, which implements a simple
request/acknowledge protocol.

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A DMA access is requested when the TXDMAEN or RXDMAEN enable bit in the SPIx_CR2
register is set. Separate requests must be issued to the Tx and Rx buffers.
• In transmission, a DMA request is issued each time TXE is set to 1. The DMA then
writes to the SPIx_DR register.
• In reception, a DMA request is issued each time RXNE is set to 1. The DMA then reads
the SPIx_DR register.
See Figure 259 through Figure 262.
When the SPI is used only to transmit data, it is possible to enable only the SPI Tx DMA
channel. In this case, the OVR flag is set because the data received is not read. When the
SPI is used only to receive data, it is possible to enable only the SPI Rx DMA channel.
In transmission mode, when the DMA has written all the data to be transmitted (the TCIF
flag is set in the DMA_ISR register), the BSY flag can be monitored to ensure that the SPI
communication is complete. This is required to avoid corrupting the last transmission before
disabling the SPI or entering the Stop mode. The software must first wait until
FTLVL[1:0]=00 and then until BSY=0.
When starting communication using DMA, to prevent DMA channel management raising
error events, these steps must be followed in order:
1. Enable DMA Rx buffer in the RXDMAEN bit in the SPI_CR2 register, if DMA Rx is
used.
2. Enable DMA streams for Tx and Rx in DMA registers, if the streams are used.
3. Enable DMA Tx buffer in the TXDMAEN bit in the SPI_CR2 register, if DMA Tx is used.
4. Enable the SPI by setting the SPE bit.
For code example refer to the Appendix sections A.14.5: SPI master configuration with DMA
and A.14.6: SPI slave configuration with DMA.
To close communication it is mandatory to follow these steps in order:
1. Disable DMA streams for Tx and Rx in the DMA registers, if the streams are used.
2. Disable the SPI by following the SPI disable procedure.
3. Disable DMA Tx and Rx buffers by clearing the TXDMAEN and RXDMAEN bits in the
SPI_CR2 register, if DMA Tx and/or DMA Rx are used.

Packing with DMA

If the transfers are managed by DMA (TXDMAEN and RXDMAEN set in the SPIx_CR2
register) packing mode is enabled/disabled automatically depending on the PSIZE value
configured for SPI TX and the SPI RX DMA channel. If the DMA channel PSIZE value is
equal to 16-bit and SPI data size is less than or equal to 8-bit, then packing mode is
enabled. The DMA then automatically manages the write operations to the SPIx_DR
register.
If data packing mode is used and the number of data to transfer is not a multiple of two, the
LDMA_TX/LDMA_RX bits must be set. The SPI then considers only one data for the
transmission or reception to serve the last DMA transfer (for more details refer to Data
packing on page 650.)

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Communication diagrams
Some typical timing schemes are explained in this section. These schemes are valid no
matter if the SPI events are handled by polling, interrupts or DMA. For simplicity, the
LSBFIRST=0, CPOL=0 and CPHA=1 setting is used as a common assumption here. No
complete configuration of DMA streams is provided.
The following numbered notes are common for Figure 259 on page 653 through Figure 262
on page 656:
1. The slave starts to control MISO line as NSS is active and SPI is enabled, and is
disconnected from the line when one of them is released. Sufficient time must be
provided for the slave to prepare data dedicated to the master in advance before its
transaction starts.
At the master, the SPI peripheral takes control at MOSI and SCK signals (occasionally
at NSS signal as well) only if SPI is enabled. If SPI is disabled the SPI peripheral is
disconnected from GPIO logic, so the levels at these lines depends on GPIO setting
exclusively.
2. At the master, BSY stays active between frames if the communication (clock signal) is
continuous. At the slave, BSY signal always goes down for at least one clock cycle
between data frames.
3. The TXE signal is cleared only if TXFIFO is full.
4. The DMA arbitration process starts just after the TXDMAEN bit is set. The TXE
interrupt is generated just after the TXEIE is set. As the TXE signal is at an active level,
data transfers to TxFIFO start, until TxFIFO becomes full or the DMA transfer
completes.
5. If all the data to be sent can fit into TxFIFO, the DMA Tx TCIF flag can be raised even
before communication on the SPI bus starts. This flag always rises before the SPI
transaction is completed.
6. The CRC value for a package is calculated continuously frame by frame in the
SPIx_TXCRCR and SPIx_RXCRCR registers. The CRC information is processed after
the entire data package has completed, either automatically by DMA (Tx channel must
be set to the number of data frames to be processed) or by SW (the user must handle
CRCNEXT bit during the last data frame processing).
While the CRC value calculated in SPIx_TXCRCR is simply sent out by transmitter,
received CRC information is loaded into RxFIFO and then compared with the
SPIx_RXCRCR register content (CRC error flag can be raised here if any difference).
This is why the user must take care to flush this information from the FIFO, either by
software reading out all the stored content of RxFIFO, or by DMA when the proper
number of data frames is preset for Rx channel (number of data frames + number of
CRC frames) (see the settings at the example assumption).
7. In data packed mode, TxE and RxNE events are paired and each read/write access to
the FIFO is 16 bits wide until the number of data frames are even. If the TxFIFO is ¾
full FTLVL status stays at FIFO full level. That is why the last odd data frame cannot be
stored before the TxFIFO becomes ½ full. This frame is stored into TxFIFO with an 8-
bit access either by software or automatically by DMA when LDMA_TX control is set.
8. To receive the last odd data frame in packed mode, the Rx threshold must be changed
to 8-bit when the last data frame is processed, either by software setting FRXTH=1 or
automatically by a DMA internal signal when LDMA_RX is set.

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Figure 259. Master full-duplex communication

NSS

SCK

BSY 2 2

MOSI MSB DTx1 MSB DTx2 MSB DTx3

SPE

3 3
TXE

Enable Tx/Rx DMA or interrupts

DTx1 DTx2 DTx3 DMA or software control at Tx events

FTLVL 00 10 11 10 11 10 00

4
MISO DRx1 LSB DRx2 LSB DRx3 LSB

1 1
RXNE

DMA or software control at Rx events DRx1 DRx2 DRx3

FRLVL 00 10 00 10 00 10 00

DMA Tx TICF 5 DMA Rx TICF

MSv19266V2

Assumptions for master full-duplex communication example:

• Data size > 8 bit
If DMA is used:
• Number of Tx frames transacted by DMA is set to 3
• Number of Rx frames transacted by DMA is set to 3
See also : Communication diagrams on page 652 for details about common assumptions
and notes.

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Figure 260. Slave full-duplex communication

NSS

SCK

BSY 2

MISO MSB DTx1 MSB DTx2 MSB DTx3

1

SPE 1

3 3
TXE

4 Enable Tx/Rx DMA or interrupts

DTx1 DTx2 DTx3 DMA or software control at Tx events

FTLVL 00 10 11 10 11 10 00

MOSI DRx1 LSB DRx2 LSB DRx3 LSB

RXNE

DMA or software control at Rx events DRx1 DRx2 DRx3

FRLVL 00 10 00 10 00 10 00

DMA Tx TICF 5 DMA Rx TICF

MSv32123V2

Assumptions for slave full-duplex communication example:

• Data size > 8 bit
If DMA is used:
• Number of Tx frames transacted by DMA is set to 3
• Number of Rx frames transacted by DMA is set to 3
See also Communication diagrams on page 652 for details about common assumptions and
notes.
For code example refer to the Appendix section A.14.3: SPI full duplex communication.

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Figure 261. Master full-duplex communication with CRC

NSS

SCK

BSY 2

MOSI MSB DTx1 MSB DTx2 MSB CRC

SPE

TXE 3

Enable Tx/Rx DMA or interrupts

DTx1 DTx2 DMA or software control at Tx events

FTLVL 00 10 11 10 00

4
MISO DRx1 LSB DRx2 LSB CRC LSB

1 1
RXNE

DMA or software control at Rx events DRx1 DRx2 DRx3

FRLVL 00 10 00 10 00 10 00

DMA Tx TICF 5 DMA Rx TICF 6

MSv32124V2

Assumptions for master full-duplex communication with CRC example:

• Data size = 16 bit
• CRC enabled
If DMA is used:
• Number of Tx frames transacted by DMA is set to 2
• Number of Rx frames transacted by DMA is set to 3
See also : Communication diagrams on page 652 for details about common assumptions
and notes.

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Figure 262. Master full-duplex communication in packed mode

NSS

SCK

BSY 2
DTx1-2 DTx3-4 DTx5

MOSI 5 4 3 2 1 5 4 3 2 1 5 4 3 2 1 5 4 3 2 1 5 4 3 2 1

SPE

3 3
TXE

Enable Tx/Rx DMA or interrupts

DTx1-2 DTx3-4 DTx5 DMA or software control at Tx events

7

FTLVL 00 10 11 10 11 10 01 00

4
MISO 5 4 3 2 1 5 4 3 2 1 5 4 3 2 1 5 4 3 2 1 5 4 3 2 1

1 DRx1-2 DRx3-4 DRx5 1

RXNE

DMA or software control at Rx events DRx1-2 DRx3-4 FRTHX=1 DRx5

8
FRLVL 00 01 10 00 01 10 00 01 00

DMA Tx TICF 5 DMA Rx TICF

MSv32125V2

Assumptions for master full-duplex communication in packed mode example:

• Data size = 5 bit
• Read/write FIFO is performed mostly by 16-bit access
• FRXTH=0
If DMA is used:
• Number of Tx frames to be transacted by DMA is set to 3
• Number of Rx frames to be transacted by DMA is set to 3
• PSIZE for both Tx and Rx DMA channel is set to 16-bit
• LDMA_TX=1 and LDMA_RX=1
See also : Communication diagrams on page 652 for details about common assumptions
and notes.

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24.4.10 SPI status flags

Three status flags are provided for the application to completely monitor the state of the SPI
bus.

Tx buffer empty flag (TXE)

The TXE flag is set when transmission TXFIFO has enough space to store data to send.
TXE flag is linked to the TXFIFO level. The flag goes high and stays high until the TXFIFO
level is lower or equal to 1/2 of the FIFO depth. An interrupt can be generated if the TXEIE
bit in the SPIx_CR2 register is set. The bit is cleared automatically when the TXFIFO level
becomes greater than 1/2.

Rx buffer not empty (RXNE)

The RXNE flag is set depending on the FRXTH bit value in the SPIx_CR2 register:
• If FRXTH is set, RXNE goes high and stays high until the RXFIFO level is greater or
equal to 1/4 (8-bit).
• If FRXTH is cleared, RXNE goes high and stays high until the RXFIFO level is greater
than or equal to 1/2 (16-bit).
An interrupt can be generated if the RXNEIE bit in the SPIx_CR2 register is set.
The RXNE is cleared by hardware automatically when the above conditions are no longer
true.

Busy flag (BSY)

The BSY flag is set and cleared by hardware (writing to this flag has no effect).
When BSY is set, it indicates that a data transfer is in progress on the SPI (the SPI bus is
busy).
The BSY flag can be used in certain modes to detect the end of a transfer so that the
software can disable the SPI or its peripheral clock before entering a low-power mode which
does not provide a clock for the peripheral. This avoids corrupting the last transfer.
The BSY flag is also useful for preventing write collisions in a multimaster system.
The BSY flag is cleared under any one of the following conditions:
• When the SPI is correctly disabled
• When a fault is detected in Master mode (MODF bit set to 1)
• In Master mode, when it finishes a data transmission and no new data is ready to be
sent
• In Slave mode, when the BSY flag is set to '0' for at least one SPI clock cycle between
each data transfer.
Note: When the next transmission can be handled immediately by the master (e.g. if the master is
in Receive-only mode or its Transmit FIFO is not empty), communication is continuous and
the BSY flag remains set to '1' between transfers on the master side. Although this is not the
case with a slave, it is recommended to use always the TXE and RXNE flags (instead of the
BSY flags) to handle data transmission or reception operations.

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24.4.11 SPI error flags

An SPI interrupt is generated if one of the following error flags is set and interrupt is enabled
by setting the ERRIE bit.

Overrun flag (OVR)

An overrun condition occurs when data is received by a master or slave and the RXFIFO
has not enough space to store this received data. This can happen if the software or the
DMA did not have enough time to read the previously received data (stored in the RXFIFO)
or when space for data storage is limited e.g. the RXFIFO is not available when CRC is
enabled in receive only mode so in this case the reception buffer is limited into a single data
frame buffer (see Section 24.4.14: CRC calculation).
When an overrun condition occurs, the newly received value does not overwrite the
previous one in the RXFIFO. The newly received value is discarded and all data transmitted
subsequently is lost. Clearing the OVR bit is done by a read access to the SPI_DR register
followed by a read access to the SPI_SR register.

Mode fault (MODF)

Mode fault occurs when the master device has its internal NSS signal (NSS pin in NSS
hardware mode, or SSI bit in NSS software mode) pulled low. This automatically sets the
MODF bit. Master mode fault affects the SPI interface in the following ways:
• The MODF bit is set and an SPI interrupt is generated if the ERRIE bit is set.
• The SPE bit is cleared. This blocks all output from the device and disables the SPI
interface.
• The MSTR bit is cleared, thus forcing the device into slave mode.
Use the following software sequence to clear the MODF bit:
1. Make a read or write access to the SPIx_SR register while the MODF bit is set.
2. Then write to the SPIx_CR1 register.
To avoid any multiple slave conflicts in a system comprising several MCUs, the NSS pin
must be pulled high during the MODF bit clearing sequence. The SPE and MSTR bits can
be restored to their original state after this clearing sequence. As a security, hardware does
not allow the SPE and MSTR bits to be set while the MODF bit is set. In a slave device the
MODF bit cannot be set except as the result of a previous multimaster conflict.

CRC error (CRCERR)

This flag is used to verify the validity of the value received when the CRCEN bit in the
SPIx_CR1 register is set. The CRCERR flag in the SPIx_SR register is set if the value
received in the shift register does not match the receiver SPIx_RXCRCR value. The flag is
cleared by the software.

TI mode frame format error (FRE)

A TI mode frame format error is detected when an NSS pulse occurs during an ongoing
communication when the SPI is operating in slave mode and configured to conform to the TI
mode protocol. When this error occurs, the FRE flag is set in the SPIx_SR register. The SPI
is not disabled when an error occurs, the NSS pulse is ignored, and the SPI waits for the
next NSS pulse before starting a new transfer. The data may be corrupted since the error
detection may result in the loss of two data bytes.

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The FRE flag is cleared when SPIx_SR register is read. If the ERRIE bit is set, an interrupt
is generated on the NSS error detection. In this case, the SPI should be disabled because
data consistency is no longer guaranteed and communications should be reinitiated by the
master when the slave SPI is enabled again.

24.4.12 NSS pulse mode

This mode is activated by the NSSP bit in the SPIx_CR2 register and it takes effect only if
the SPI interface is configured as Motorola SPI master (FRF=0) with capture on the first
edge (SPIx_CR1 CPHA = 0, CPOL setting is ignored). When activated, an NSS pulse is
generated between two consecutive data frame transfers when NSS stays at high level for
the duration of one clock period at least. This mode allows the slave to latch data. NSSP
pulse mode is designed for applications with a single master-slave pair.
Figure 263 illustrates NSS pin management when NSSP pulse mode is enabled.

Figure 263. NSSP pulse generation in Motorola SPI master mode

Master continuous transfer (CPOL = 1; CPHA = 0; NSSP= 1)

sampling sampling sampling sampling sampling sampling

NSS
output

SCK
output

MOSI
output MSB LSB MSB LSB

MISO
input Do not care MSB LSB Do not care MSB LSB Do not care

tSCK tSCK tSCK tSCK tSCK

4-bits to 16-bits 4-bits to 16-bits

MS19838V1

Note: Similar behavior is encountered when CPOL = 0. In this case the sampling edge is the rising
edge of SCK, and NSS assertion and deassertion refer to this sampling edge.

24.4.13 TI mode
TI protocol in master mode
The SPI interface is compatible with the TI protocol. The FRF bit of the SPIx_CR2 register
can be used to configure the SPI to be compliant with this protocol.
The clock polarity and phase are forced to conform to the TI protocol requirements whatever
the values set in the SPIx_CR1 register. NSS management is also specific to the TI protocol
which makes the configuration of NSS management through the SPIx_CR1 and SPIx_CR2
registers (SSM, SSI, SSOE) impossible in this case.
In slave mode, the SPI baud rate prescaler is used to control the moment when the MISO
pin state changes to HiZ when the current transaction finishes (see Figure 264). Any baud
rate can be used, making it possible to determine this moment with optimal flexibility.
However, the baud rate is generally set to the external master clock baud rate. The delay for
the MISO signal to become HiZ (trelease) depends on internal resynchronization and on the

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baud rate value set in through the BR[2:0] bits in the SPIx_CR1 register. It is given by the
formula:

t baud_rate t baud_rate
- + 4 × t pclk < t release < ---------------------
--------------------- - + 6 × t pclk
2 2
If the slave detects a misplaced NSS pulse during a data frame transaction the TIFRE flag is
set.
If the data size is equal to 4-bits or 5-bits, the master in full-duplex mode or transmit-only
mode uses a protocol with one more dummy data bit added after LSB. TI NSS pulse is
generated above this dummy bit clock cycle instead of the LSB in each period.
This feature is not available for Motorola SPI communications (FRF bit set to 0).
Figure 264: TI mode transfer shows the SPI communication waveforms when TI mode is
selected.

Figure 264. TI mode transfer

NSS
g

t RELEASE
in

in

in
er

er

er
pl

pl

pl
gg

gg

gg
m

m
sa

sa

sa
tri

tri

tri

SCK

MOSI Do not care MSB LSB MSB LSB

MISO 1 or 0 MSB LSB MSB LSB

FRAME 1 FRAME 2

MS19835V2

24.4.14 CRC calculation

Two separate CRC calculators are implemented in order to check the reliability of
transmitted and received data. The SPI offers CRC8 or CRC16 calculation independently of
the frame data length, which can be fixed to 8-bit or 16-bit. For all the other data frame
lengths, no CRC is available.

CRC principle
CRC calculation is enabled by setting the CRCEN bit in the SPIx_CR1 register before the
SPI is enabled (SPE = 1). The CRC value is calculated using an odd programmable
polynomial on each bit. The calculation is processed on the sampling clock edge defined by
the CPHA and CPOL bits in the SPIx_CR1 register. The calculated CRC value is checked
automatically at the end of the data block as well as for transfer managed by CPU or by the
DMA. When a mismatch is detected between the CRC calculated internally on the received
data and the CRC sent by the transmitter, a CRCERR flag is set to indicate a data corruption
error. The right procedure for handling the CRC calculation depends on the SPI
configuration and the chosen transfer management.

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Note: The polynomial value should only be odd. No even values are supported.

CRC transfer managed by CPU

Communication starts and continues normally until the last data frame has to be sent or
received in the SPIx_DR register. Then CRCNEXT bit has to be set in the SPIx_CR1
register to indicate that the CRC frame transaction follows after the transaction of the
currently processed data frame. The CRCNEXT bit must be set before the end of the last
data frame transaction. CRC calculation is frozen during CRC transaction.
The received CRC is stored in the RXFIFO like a data byte or word. That is why in CRC
mode only, the reception buffer has to be considered as a single 16-bit buffer used to
receive only one data frame at a time.
A CRC-format transaction usually takes one more data frame to communicate at the end of
data sequence. However, when setting an 8-bit data frame checked by 16-bit CRC, two
more frames are necessary to send the complete CRC.
When the last CRC data is received, an automatic check is performed comparing the
received value and the value in the SPIx_RXCRC register. Software has to check the
CRCERR flag in the SPIx_SR register to determine if the data transfers were corrupted or
not. Software clears the CRCERR flag by writing '0' to it.
After the CRC reception, the CRC value is stored in the RXFIFO and must be read in the
SPIx_DR register in order to clear the RXNE flag.

CRC transfer managed by DMA

When SPI communication is enabled with CRC communication and DMA mode, the
transmission and reception of the CRC at the end of communication is automatic (with the
exception of reading CRC data in receive only mode). The CRCNEXT bit does not have to
be handled by the software. The counter for the SPI transmission DMA channel has to be
set to the number of data frames to transmit excluding the CRC frame. On the receiver side,
the received CRC value is handled automatically by DMA at the end of the transaction but
user must take care to flush out received CRC information from RXFIFO as it is always
loaded into it. In full-duplex mode, the counter of the reception DMA channel can be set to
the number of data frames to receive including the CRC, which means, for example, in the
specific case of an 8-bit data frame checked by 16-bit CRC:
DMA_RX = Numb_of_data + 2
In receive only mode, the DMA reception channel counter should contain only the amount of
data transferred, excluding the CRC calculation. Then based on the complete transfer from
DMA, all the CRC values must be read back by software from FIFO as it works as a single
buffer in this mode.
At the end of the data and CRC transfers, the CRCERR flag in the SPIx_SR register is set if
corruption occurred during the transfer.
If packing mode is used, the LDMA_RX bit needs managing if the number of data is odd.

Resetting the SPIx_TXCRC and SPIx_RXCRC values

The SPIx_TXCRC and SPIx_RXCRC values are cleared automatically when new data is
sampled after a CRC phase. This allows the use of DMA circular mode (not available in
receive-only mode) in order to transfer data without any interruption, (several data blocks
covered by intermediate CRC checking phases).

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If the SPI is disabled during a communication the following sequence must be followed:
1. Disable the SPI
2. Clear the CRCEN bit
3. Enable the CRCEN bit
4. Enable the SPI
Note: When the SPI interface is configured as a slave, the NSS internal signal needs to be kept
low during transaction of the CRC phase once the CRCNEXT signal is released. That is why
the CRC calculation cannot be used at NSS Pulse mode when NSS hardware mode should
be applied at slave normally.
At TI mode, despite the fact that clock phase and clock polarity setting is fixed and
independent on SPIx_CR1 register, the corresponding setting CPOL=0 CPHA=1 has to be
kept at the SPIx_CR1 register anyway if CRC is applied. In addition, the CRC calculation
has to be reset between sessions by SPI disable sequence with re-enable the CRCEN bit
described above at both master and slave side, else CRC calculation can be corrupted at
this specific mode.

24.5 SPI interrupts

During SPI communication an interrupt can be generated by the following events:
• Transmit TXFIFO ready to be loaded
• Data received in Receive RXFIFO
• Master mode fault
• Overrun error
• TI frame format error
• CRC protocol error

Interrupts can be enabled and disabled separately.

Table 96. SPI interrupt requests

Interrupt event Event flag Enable Control bit

Transmit TXFIFO ready to be loaded TXE TXEIE

Data received in RXFIFO RXNE RXNEIE
Master Mode fault event MODF
Overrun error OVR
ERRIE
TI frame format error FRE
CRC protocol error CRCERR

For code example refer to the Appendix section A.14.4: SPI interrupt.

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24.6 SPI registers

The peripheral registers can be accessed by half-words (16-bit) or words (32-bit). SPI_DR
in addition can be accessed by 8-bit access.

24.6.1 SPI control register 1 (SPIx_CR1)

Address offset: 0x00
Reset value: 0x0000

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BIDI CRC CRCN RX LSB
BIDIOE CRCL SSM SSI SPE BR[2:0] MSTR CPOL CPHA
MODE EN EXT ONLY FIRST
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bit 15 BIDIMODE: Bidirectional data mode enable.

This bit enables half-duplex communication using common single bidirectional data line.
Keep RXONLY bit clear when bidirectional mode is active.
0: 2-line unidirectional data mode selected
1: 1-line bidirectional data mode selected
Note:
Bit 14 BIDIOE: Output enable in bidirectional mode
This bit combined with the BIDIMODE bit selects the direction of transfer in bidirectional
mode.
0: Output disabled (receive-only mode)
1: Output enabled (transmit-only mode)
Note: In master mode, the MOSI pin is used and in slave mode, the MISO pin is used.

Bit 13 CRCEN: Hardware CRC calculation enable

0: CRC calculation disabled
1: CRC calculation enabled
Note: This bit should be written only when SPI is disabled (SPE = ‘0’) for correct operation.

Bit 12 CRCNEXT: Transmit CRC next

0: Next transmit value is from Tx buffer.
1: Next transmit value is from Tx CRC register.
Note: This bit has to be written as soon as the last data is written in the SPIx_DR register.

Bit 11 CRCL: CRC length

This bit is set and cleared by software to select the CRC length.
0: 8-bit CRC length
1: 16-bit CRC length
Note: This bit should be written only when SPI is disabled (SPE = ‘0’) for correct operation.

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Bit 10 RXONLY: Receive only mode enabled.

This bit enables simplex communication using a single unidirectional line to receive data
exclusively. Keep BIDIMODE bit clear when receive only mode is active.This bit is also
useful in a multislave system in which this particular slave is not accessed, the output from
the accessed slave is not corrupted.
0: Full-duplex (Transmit and receive)
1: Output disabled (Receive-only mode)

Bit 9 SSM: Software slave management

When the SSM bit is set, the NSS pin input is replaced with the value from the SSI bit.
0: Software slave management disabled
1: Software slave management enabled
Note: This bit is not used in SPI TI mode.
Bit 8 SSI: Internal slave select
This bit has an effect only when the SSM bit is set. The value of this bit is forced onto the
NSS pin and the I/O value of the NSS pin is ignored.
Note: This bit is not used in SPI TI mode.
Bit 7 LSBFIRST: Frame format
0: data is transmitted / received with the MSB first
1: data is transmitted / received with the LSB first
Note: 1. This bit should not be changed when communication is ongoing.
2. This bit is not used in SPI TI mode.
Bit 6 SPE: SPI enable
0: Peripheral disabled
1: Peripheral enabled
Note: When disabling the SPI, follow the procedure described in Procedure for disabling the
SPI on page 649.

Bits 5:3 BR[2:0]: Baud rate control

000: fPCLK/2
001: fPCLK/4
010: fPCLK/8
011: fPCLK/16
100: fPCLK/32
101: fPCLK/64
110: fPCLK/128
111: fPCLK/256
Note: These bits should not be changed when communication is ongoing.

Bit 2 MSTR: Master selection

0: Slave configuration
1: Master configuration
Note: This bit should not be changed when communication is ongoing.

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Bit 1 CPOL: Clock polarity

0: CK to 0 when idle
1: CK to 1 when idle
Note: This bit should not be changed when communication is ongoing.
This bit is not used in SPI TI mode except the case when CRC is applied at TI mode.
Bit 0 CPHA: Clock phase
0: The first clock transition is the first data capture edge
1: The second clock transition is the first data capture edge
Note: This bit should not be changed when communication is ongoing.
This bit is not used in SPI TI mode except the case when CRC is applied at TI mode.

24.6.2 SPI control register 2 (SPIx_CR2)

Address offset: 0x04
Reset value: 0x0700

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LDMA LDMA FRXT
Res. DS[3:0] TXEIE RXNEIE ERRIE FRF NSSP SSOE TXDMAEN RXDMAEN
_TX _RX H
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bit 15 Reserved, must be kept at reset value.

Bit 14 LDMA_TX: Last DMA transfer for transmission
This bit is used in data packing mode, to define if the total number of data to transmit by DMA
is odd or even. It has significance only if the TXDMAEN bit in the SPIx_CR2 register is set
and if packing mode is used (data length =< 8-bit and write access to SPIx_DR is 16-bit
wide). It has to be written when the SPI is disabled (SPE = 0 in the SPIx_CR1 register).
0: Number of data to transfer is even
1: Number of data to transfer is odd
Note: Refer to Procedure for disabling the SPI on page 649 if the CRCEN bit is set.

Bit 13 LDMA_RX: Last DMA transfer for reception

This bit is used in data packing mode, to define if the total number of data to receive by DMA
is odd or even. It has significance only if the RXDMAEN bit in the SPIx_CR2 register is set
and if packing mode is used (data length =< 8-bit and write access to SPIx_DR is 16-bit
wide). It has to be written when the SPI is disabled (SPE = 0 in the SPIx_CR1 register).
0: Number of data to transfer is even
1: Number of data to transfer is odd
Note: Refer to Procedure for disabling the SPI on page 649 if the CRCEN bit is set.

Bit 12 FRXTH: FIFO reception threshold

This bit is used to set the threshold of the RXFIFO that triggers an RXNE event
0: RXNE event is generated if the FIFO level is greater than or equal to 1/2 (16-bit)
1: RXNE event is generated if the FIFO level is greater than or equal to 1/4 (8-bit)

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Bits 11:8 DS[3:0]: Data size

These bits configure the data length for SPI transfers.
0000: Not used
0001: Not used
0010: Not used
0011: 4-bit
0100: 5-bit
0101: 6-bit
0110: 7-bit
0111: 8-bit
1000: 9-bit
1001: 10-bit
1010: 11-bit
1011: 12-bit
1100: 13-bit
1101: 14-bit
1110: 15-bit
1111: 16-bit
If software attempts to write one of the “Not used” values, they are forced to the value “0111”
(8-bit)

Bit 7 TXEIE: Tx buffer empty interrupt enable

0: TXE interrupt masked
1: TXE interrupt not masked. Used to generate an interrupt request when the TXE flag is set.
Bit 6 RXNEIE: RX buffer not empty interrupt enable
0: RXNE interrupt masked
1: RXNE interrupt not masked. Used to generate an interrupt request when the RXNE flag is
set.
Bit 5 ERRIE: Error interrupt enable
This bit controls the generation of an interrupt when an error condition occurs (CRCERR,
OVR, MODF in SPI mode, FRE at TI mode).
0: Error interrupt is masked
1: Error interrupt is enabled
Bit 4 FRF: Frame format
0: SPI Motorola mode
1 SPI TI mode
Note: This bit must be written only when the SPI is disabled (SPE=0).

Bit 3 NSSP: NSS pulse management

This bit is used in master mode only. it allows the SPI to generate an NSS pulse between two
consecutive data when doing continuous transfers. In the case of a single data transfer, it
forces the NSS pin high level after the transfer.
It has no meaning if CPHA = ’1’, or FRF = ’1’.
0: No NSS pulse
1: NSS pulse generated
Note: 1. This bit must be written only when the SPI is disabled (SPE=0).
2. This bit is not used in SPI TI mode.

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Bit 2 SSOE: SS output enable

0: SS output is disabled in master mode and the SPI interface can work in multimaster
configuration
1: SS output is enabled in master mode and when the SPI interface is enabled. The SPI
interface cannot work in a multimaster environment.
Note: This bit is not used in SPI TI mode.
Bit 1 TXDMAEN: Tx buffer DMA enable
When this bit is set, a DMA request is generated whenever the TXE flag is set.
0: Tx buffer DMA disabled
1: Tx buffer DMA enabled
Bit 0 RXDMAEN: Rx buffer DMA enable
When this bit is set, a DMA request is generated whenever the RXNE flag is set.
0: Rx buffer DMA disabled
1: Rx buffer DMA enabled

24.6.3 SPI status register (SPIx_SR)

Address offset: 0x08
Reset value: 0x0002

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CRCE
Res. Res. Res. FTLVL[1:0] FRLVL[1:0] FRE BSY OVR MODF Res. Res. TXE RXNE
RR
r r r r r r r r rc_w0 r r

Bits 15:13 Reserved, must be kept at reset value.

Bits 12:11 FTLVL[1:0]: FIFO transmission level
These bits are set and cleared by hardware.
00: FIFO empty
01: 1/4 FIFO
10: 1/2 FIFO
11: FIFO full (considered as FULL when the FIFO threshold is greater than 1/2)

Bits 10:9 FRLVL[1:0]: FIFO reception level

These bits are set and cleared by hardware.
00: FIFO empty
01: 1/4 FIFO
10: 1/2 FIFO
11: FIFO full
Note: These bits are not used in SPI receive-only mode while CRC calculation is enabled.
Bit 8 FRE: Frame format error
This flag is used for SPI in TI slave mode. Refer to Section 24.4.11: SPI error flags.
This flag is set by hardware and reset when SPIx_SR is read by software.
0: No frame format error
1: A frame format error occurred

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Bit 7 BSY: Busy flag

0: SPI not busy
1: SPI is busy in communication or Tx buffer is not empty
This flag is set and cleared by hardware.
Note: The BSY flag must be used with caution: refer to Section 24.4.10: SPI status flags and
Procedure for disabling the SPI on page 649.
Bit 6 OVR: Overrun flag
0: No overrun occurred
1: Overrun occurred
This flag is set by hardware and reset by a software sequence.
Bit 5 MODF: Mode fault
0: No mode fault occurred
1: Mode fault occurred
This flag is set by hardware and reset by a software sequence. Refer to Section : Mode fault
(MODF) on page 658 for the software sequence.

Bit 4 CRCERR: CRC error flag

0: CRC value received matches the SPIx_RXCRCR value
1: CRC value received does not match the SPIx_RXCRCR value
Note: This flag is set by hardware and cleared by software writing 0.

Bits 3:2 Reserved, must be kept at reset value.

Bit 1 TXE: Transmit buffer empty
0: Tx buffer not empty
1: Tx buffer empty
Bit 0 RXNE: Receive buffer not empty
0: Rx buffer empty
1: Rx buffer not empty

24.6.4 SPI data register (SPIx_DR)

Address offset: 0x0C
Reset value: 0x0000

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DR[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 15:0 DR[15:0]: Data register

Data received or to be transmitted
The data register serves as an interface between the Rx and Tx FIFOs. When the data
register is read, RxFIFO is accessed while the write to data register accesses TxFIFO (See
Section 24.4.9: Data transmission and reception procedures).
Note: Data is always right-aligned. Unused bits are ignored when writing to the register, and
read as zero when the register is read. The Rx threshold setting must always
correspond with the read access currently used.

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24.6.5 SPI CRC polynomial register (SPIx_CRCPR)

Address offset: 0x10
Reset value: 0x0007
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CRCPOLY[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 15:0 CRCPOLY[15:0]: CRC polynomial register

This register contains the polynomial for the CRC calculation.
The CRC polynomial (0x0007) is the reset value of this register. Another polynomial can be
configured as required.

Note: The polynomial value should be odd only. No even value is supported.

24.6.6 SPI Rx CRC register (SPIx_RXCRCR)

Address offset: 0x14
Reset value: 0x0000

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXCRC[15:0]
r r r r r r r r r r r r r r r r

Bits 15:0 RXCRC[15:0]: Rx CRC register

When CRC calculation is enabled, the RXCRC[15:0] bits contain the computed CRC value of
the subsequently received bytes. This register is reset when the CRCEN bit in SPIx_CR1
register is written to 1. The CRC is calculated serially using the polynomial programmed in
the SPIx_CRCPR register.
Only the 8 LSB bits are considered when the CRC frame format is set to be 8-bit length
(CRCL bit in the SPIx_CR1 is cleared). CRC calculation is done based on any CRC8
standard.
The entire 16-bits of this register are considered when a 16-bit CRC frame format is selected
(CRCL bit in the SPIx_CR1 register is set). CRC calculation is done based on any CRC16
standard.
A read to this register when the BSY Flag is set could return an incorrect value.

24.6.7 SPI Tx CRC register (SPIx_TXCRCR)

Address offset: 0x18
Reset value: 0x0000

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXCRC[15:0]
r r r r r r r r r r r r r r r r

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Bits 15:0 TXCRC[15:0]: Tx CRC register

When CRC calculation is enabled, the TXCRC[7:0] bits contain the computed CRC value of
the subsequently transmitted bytes. This register is reset when the CRCEN bit of SPIx_CR1
is written to 1. The CRC is calculated serially using the polynomial programmed in the
SPIx_CRCPR register.
Only the 8 LSB bits are considered when the CRC frame format is set to be 8-bit length
(CRCL bit in the SPIx_CR1 is cleared). CRC calculation is done based on any CRC8
standard.
The entire 16-bits of this register are considered when a 16-bit CRC frame format is selected
(CRCL bit in the SPIx_CR1 register is set). CRC calculation is done based on any CRC16
standard.
A read to this register when the BSY flag is set could return an incorrect value.

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24.6.8 SPI register map

Table 97 shows the SPI register map and reset values.

Table 97. SPI register map and reset values

Offset Register name

15

14

13

12

10
11

0
reset value

BIDIMODE

CRCNEXT

LSBFIRST
RXONLY
CRCEN
BIDIOE

MSTR

CPHA
CRCL

CPOL
SSM

SPE
SSI
SPIx_CR1 BR [2:0]
0x00

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RXDMAEN
TXDMAEN
LDMA_RX
LDMA_TX

RXNEIE
FRXTH

ERRIE
TXEIE

SSOE
NSSP
Res.

FRF
SPIx_CR2 DS[3:0]
0x04

Reset value 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0

FRLVL[1:0]
FTLVL[1:0]

CRCERR
MODF

RXNE
OVR
Res.

Res.

Res.

Res.

Res.
FRE

BSY

TXE
SPIx_SR
0x08

Reset value 0 0 0 0 0 0 0 0 0 1 0

SPIx_DR DR[15:0]
0x0C
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SPIx_CRCPR CRCPOLY[15:0]
0x10
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1

SPIx_RXCRCR RXCRC[15:0]
0x14
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SPIx_TXCRCR TXCRC[15:0]
0x18
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Refer to Section 2.2 on page 37 for the register boundary addresses.

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25 Universal serial bus full-speed device interface (USB)

This section applies to STM32F070x6 and STM32F070xB devices only.

25.1 Introduction
The USB peripheral implements an interface between a full-speed USB 2.0 bus and the
APB bus.
USB suspend/resume are supported, which allows to stop the device clocks for low-power
consumption.

25.2 USB main features

• USB specification version 2.0 full-speed compliant
• Configurable number of endpoints from 1 to 8
• 1024 bytes of dedicated packet buffer memory SRAM
• Cyclic redundancy check (CRC) generation/checking, Non-return-to-zero Inverted
(NRZI) encoding/decoding and bit-stuffing
• Isochronous transfers support
• Double-buffered bulk/isochronous endpoint support
• USB Suspend/Resume operations
• Frame locked clock pulse generation
• USB 2.0 Link Power Management support
• Battery Charging Specification Revision 1.2 support
• USB connect / disconnect capability (controllable embedded pull-up resistor on
USB_DP line)

25.3 USB implementation

Table 98 describes the USB implementation in the devices.

Table 98. STM32F0x0 USB implementation

STM32F070x6,
STM32F070xB
USB features(1)
USB

Number of endpoints 8
Size of dedicated packet buffer memory SRAM 1024 bytes
Dedicated packet buffer memory SRAM access scheme 2 x 16 bits / word
USB 2.0 Link Power Management (LPM) support X
Battery Charging Detection (BCD) support X
Embedded pull-up resistor on USB_DP line X

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1. X= supported

25.4 USB functional description

Figure 265 shows the block diagram of the USB peripheral.

Figure 265. USB peripheral block diagram

DP DM NOE

USB PHY USB clock

Embedded Analog (48 MHz)
BCD
pull-up transceiver PCLK

Clock Control
RX-TX
Suspend recovery registers and logic
timer Control Endpoint Interrupt
S.I.E. selection registers and logic

Packet
buffer
Endpoint Endpoint
interface
registers registers

Packet Register
Register Interrupt
Arbiter buffer mapper
mapper mapper
memory

APB wrapper

APB interface

PCLK APB bus IRQs to NVIC

MSv32120V2

The USB peripheral provides an USB-compliant connection between the host PC and the
function implemented by the microcontroller. Data transfer between the host PC and the
system memory occurs through a dedicated packet buffer memory accessed directly by the
USB peripheral. This dedicated memory size is 1024 bytes, and up to 16 mono-directional
or 8 bidirectional endpoints can be used. The USB peripheral interfaces with the USB host,
detecting token packets, handling data transmission/reception, and processing handshake
packets as required by the USB standard. Transaction formatting is performed by the
hardware, including CRC generation and checking.

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Each endpoint is associated with a buffer description block indicating where the
endpoint-related memory area is located, how large it is or how many bytes must be
transmitted. When a token for a valid function/endpoint pair is recognized by the USB
peripheral, the related data transfer (if required and if the endpoint is configured) takes
place. The data buffered by the USB peripheral is loaded in an internal 16-bit register and
memory access to the dedicated buffer is performed. When all the data has been
transferred, if needed, the proper handshake packet over the USB is generated or expected
according to the direction of the transfer.
At the end of the transaction, an endpoint-specific interrupt is generated, reading status
registers and/or using different interrupt response routines. The microcontroller can
determine:
• which endpoint has to be served,
• which type of transaction took place, if errors occurred (bit stuffing, format, CRC,
protocol, missing ACK, over/underrun, etc.).
Special support is offered to isochronous transfers and high throughput bulk transfers,
implementing a double buffer usage, which allows to always have an available buffer for the
USB peripheral while the microcontroller uses the other one.
The unit can be placed in low-power mode (SUSPEND mode), by writing in the control
register, whenever required. At this time, all static power dissipation is avoided, and the USB
clock can be slowed down or stopped. The detection of activity at the USB inputs, while in
low-power mode, wakes the device up asynchronously. A special interrupt source can be
connected directly to a wake-up line to allow the system to immediately restart the normal
clock generation and/or support direct clock start/stop.

25.4.1 Description of USB blocks

The USB peripheral implements all the features related to USB interfacing, which include
the following blocks:
• USB Physical Interface (USB PHY): This block is maintaining the electrical interface to
an external USB host. It contains the differential analog transceiver itself, controllable
embedded pull-up resistor (connected to USB_DP line) and support for Battery
Charging Detection (BCD), multiplexed on same USB_DP and USB_DM lines. The
output enable control signal of the analog transceiver (active low) is provided externally
on USB_NOE. It can be used to drive some activity LED or to provide information about
the actual communication direction to some other circuitry.
• Serial Interface Engine (SIE): The functions of this block include: synchronization
pattern recognition, bit-stuffing, CRC generation and checking, PID
verification/generation, and handshake evaluation. It must interface with the USB
transceivers and uses the virtual buffers provided by the packet buffer interface for
local data storage. This unit also generates signals according to USB peripheral
events, such as Start of Frame (SOF), USB_Reset, Data errors etc. and to Endpoint
related events like end of transmission or correct reception of a packet; these signals
are then used to generate interrupts.
• Timer: This block generates a start-of-frame locked clock pulse and detects a global
suspend (from the host) when no traffic has been received for 3 ms.
• Packet Buffer Interface: This block manages the local memory implementing a set of
buffers in a flexible way, both for transmission and reception. It can choose the proper
buffer according to requests coming from the SIE and locate them in the memory
addresses pointed by the Endpoint registers. It increments the address after each

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exchanged byte until the end of packet, keeping track of the number of exchanged
bytes and preventing the buffer to overrun the maximum capacity.
• Endpoint-Related Registers: Each endpoint has an associated register containing the
endpoint type and its current status. For mono-directional/single-buffer endpoints, a
single register can be used to implement two distinct endpoints. The number of
registers is 8, allowing up to 16 mono-directional/single-buffer or up to 7 double-buffer
endpoints in any combination. For example the USB peripheral can be programmed to
have 4 double buffer endpoints and 8 single-buffer/mono-directional endpoints.
• Control Registers: These are the registers containing information about the status of
the whole USB peripheral and used to force some USB events, such as resume and
power-down.
• Interrupt Registers: These contain the Interrupt masks and a record of the events. They
can be used to inquire an interrupt reason, the interrupt status or to clear the status of a
pending interrupt.
Note: * Endpoint 0 is always used for control transfer in single-buffer mode.
The USB peripheral is connected to the APB bus through an APB interface, containing the
following blocks:
• Packet Memory: This is the local memory that physically contains the Packet Buffers. It
can be used by the Packet Buffer interface, which creates the data structure and can
be accessed directly by the application software. The size of the Packet Memory is
1024 bytes, structured as 512 half-words of 16 bits.
• Arbiter: This block accepts memory requests coming from the APB bus and from the
USB interface. It resolves the conflicts by giving priority to APB accesses, while always
reserving half of the memory bandwidth to complete all USB transfers. This time-duplex
scheme implements a virtual dual-port SRAM that allows memory access, while an
USB transaction is happening. Multiword APB transfers of any length are also allowed
by this scheme.
• Register Mapper: This block collects the various byte-wide and bit-wide registers of the
USB peripheral in a structured 16-bit wide half-word set addressed by the APB.
• APB Wrapper: This provides an interface to the APB for the memory and register. It
also maps the whole USB peripheral in the APB address space.
• Interrupt Mapper: This block is used to select how the possible USB events can
generate interrupts and map them to the NVIC.

25.5 Programming considerations

In the following sections, the expected interactions between the USB peripheral and the
application program are described, in order to ease application software development.

25.5.1 Generic USB device programming

This part describes the main tasks required of the application software in order to obtain
USB compliant behavior. The actions related to the most general USB events are taken into
account and paragraphs are dedicated to the special cases of double-buffered endpoints
and Isochronous transfers. Apart from system reset, action is always initiated by the USB
peripheral, driven by one of the USB events described below.

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25.5.2 System and power-on reset

Upon system and power-on reset, the first operation the application software should perform
is to provide all required clock signals to the USB peripheral and subsequently de-assert its
reset signal so to be able to access its registers. The whole initialization sequence is
hereafter described.
As a first step application software needs to activate register macrocell clock and de-assert
macrocell specific reset signal using related control bits provided by device clock
management logic.
After that, the analog part of the device related to the USB transceiver must be switched on
using the PDWN bit in CNTR register, which requires a special handling. This bit is intended
to switch on the internal voltage references that supply the port transceiver. This circuit has
a defined startup time (tSTARTUP specified in the datasheet) during which the behavior of the
USB transceiver is not defined. It is thus necessary to wait this time, after setting the PDWN
bit in the CNTR register, before removing the reset condition on the USB part (by clearing
the FRES bit in the CNTR register). Clearing the ISTR register then removes any spurious
pending interrupt before any other macrocell operation is enabled.
At system reset, the microcontroller must initialize all required registers and the packet
buffer description table, to make the USB peripheral able to properly generate interrupts and
data transfers. All registers not specific to any endpoint must be initialized according to the
needs of application software (choice of enabled interrupts, chosen address of packet
buffers, etc.). Then the process continues as for the USB reset case (see further
paragraph).

USB reset (RESET interrupt)

When this event occurs, the USB peripheral is put in the same conditions it is left by the
system reset after the initialization described in the previous paragraph: communication is
disabled in all endpoint registers (the USB peripheral will not respond to any packet). As a
response to the USB reset event, the USB function must be enabled, having as USB
address 0, implementing only the default control endpoint (endpoint address is 0 too). This
is accomplished by setting the Enable Function (EF) bit of the USB_DADDR register and
initializing the EP0R register and its related packet buffers accordingly. During USB
enumeration process, the host assigns a unique address to this device, which must be
written in the ADD[6:0] bits of the USB_DADDR register, and configures any other
necessary endpoint.
When a RESET interrupt is received, the application software is responsible to enable again
the default endpoint of USB function 0 within 10 ms from the end of reset sequence which
triggered the interrupt.

Structure and usage of packet buffers

Each bidirectional endpoint may receive or transmit data from/to the host. The received data
is stored in a dedicated memory buffer reserved for that endpoint, while another memory
buffer contains the data to be transmitted by the endpoint. Access to this memory is
performed by the packet buffer interface block, which delivers a memory access request
and waits for its acknowledgment. Since the packet buffer memory has to be accessed by
the microcontroller also, an arbitration logic takes care of the access conflicts, using half
APB cycle for microcontroller access and the remaining half for the USB peripheral access.
In this way, both the agents can operate as if the packet memory is a dual-port SRAM,
without being aware of any conflict even when the microcontroller is performing back-to-

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back accesses. The USB peripheral logic uses a dedicated clock. The frequency of this
dedicated clock is fixed by the requirements of the USB standard at 48 MHz, and this can be
different from the clock used for the interface to the APB bus. Different clock configurations
are possible where the APB clock frequency can be higher or lower than the USB peripheral
one.
Note: Due to USB data rate and packet memory interface requirements, the APB clock must have
a minimum frequency of 10 MHz to avoid data overrun/underrun problems.
Each endpoint is associated with two packet buffers (usually one for transmission and the
other one for reception). Buffers can be placed anywhere inside the packet memory
because their location and size is specified in a buffer description table, which is also
located in the packet memory at the address indicated by the USB_BTABLE register. Each
table entry is associated to an endpoint register and it is composed of four 16-bit half-words
so that table start address must always be aligned to an 8-byte boundary (the lowest three
bits of USB_BTABLE register are always “000”). Buffer descriptor table entries are
described in the Section 25.6.2: Buffer descriptor table. If an endpoint is unidirectional and it
is neither an Isochronous nor a double-buffered bulk, only one packet buffer is required (the
one related to the supported transfer direction). Other table locations related to unsupported
transfer directions or unused endpoints, are available to the user. Isochronous and double-
buffered bulk endpoints have special handling of packet buffers (Refer to Section 25.5.4:
Isochronous transfers and Section 25.5.3: Double-buffered endpoints respectively). The
relationship between buffer description table entries and packet buffer areas is depicted in
Figure 266.

Figure 266. Packet buffer areas with examples of buffer description table locations

Buffer for
double-buffered
IN Endpoint 3
0001_1110 (1E) COUNT3_TX_1
0001_1100 (1C) ADDR3_TX_1
Buffer for
0001_1010 (1A) COUNT3_TX_0
double-buffered
0001_1000 (18) ADDR3_TX_0 OUT Endpoint 2
0001_0110 (16) COUNT2_RX_1
0001_0100 (14) ADDR2_RX_1
Transmission
0001_0010 (12) COUNT2_RX_0 buffer for
0001_0000 (10) ADDR2_RX_0 single-buffered
0000_1110 (0E) COUNT1_RX Endpoint 1
0000_1100 (0C) ADDR1_RX
0000_1010 (0A) COUNT1_TX Reception buffer
0000_1000 (08) ADDR1_TX for
0000_0110 (06) COUNT0_RX Endpoint 0
0000_0100 (04) ADDR0_RX Transmission
0000_0010 (02) COUNT0_TX buffer for
0000_0000 (00) ADDR0_TX Endpoint 0

Buffer description table locations Packet buffers

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Each packet buffer is used either during reception or transmission starting from the bottom.
The USB peripheral will never change the contents of memory locations adjacent to the
allocated memory buffers; if a packet bigger than the allocated buffer length is received
(buffer overrun condition) the data are copied to the memory only up to the last available
location.

Endpoint initialization
The first step to initialize an endpoint is to write appropriate values to the
ADDRn_TX/ADDRn_RX registers so that the USB peripheral finds the data to be
transmitted already available and the data to be received can be buffered. The EP_TYPE
bits in the USB_EPnR register must be set according to the endpoint type, eventually using
the EP_KIND bit to enable any special required feature. On the transmit side, the endpoint
must be enabled using the STAT_TX bits in the USB_EPnR register and COUNTn_TX must
be initialized. For reception, STAT_RX bits must be set to enable reception and
COUNTn_RX must be written with the allocated buffer size using the BL_SIZE and
NUM_BLOCK fields. Unidirectional endpoints, except Isochronous and double-buffered bulk
endpoints, need to initialize only bits and registers related to the supported direction. Once
the transmission and/or reception are enabled, register USB_EPnR and locations
ADDRn_TX/ADDRn_RX, COUNTn_TX/COUNTn_RX (respectively), should not be modified
by the application software, as the hardware can change their value on the fly. When the
data transfer operation is completed, notified by a CTR interrupt event, they can be
accessed again to re-enable a new operation.

IN packets (data transmission)

When receiving an IN token packet, if the received address matches a configured and valid
endpoint, the USB peripheral accesses the contents of ADDRn_TX and COUNTn_TX
locations inside the buffer descriptor table entry related to the addressed endpoint. The
content of these locations is stored in its internal 16 bit registers ADDR and COUNT (not
accessible by software). The packet memory is accessed again to read the first byte to be
transmitted (Refer to Structure and usage of packet buffers on page 676) and starts sending
a DATA0 or DATA1 PID according to USB_EPnR bit DTOG_TX. When the PID is
completed, the first byte, read from buffer memory, is loaded into the output shift register to
be transmitted on the USB bus. After the last data byte is transmitted, the computed CRC is
sent. If the addressed endpoint is not valid, a NAK or STALL handshake packet is sent
instead of the data packet, according to STAT_TX bits in the USB_EPnR register.
The ADDR internal register is used as a pointer to the current buffer memory location while
COUNT is used to count the number of remaining bytes to be transmitted. Each half-word
read from the packet buffer memory is transmitted over the USB bus starting from the least
significant byte. Transmission buffer memory is read starting from the address pointed by
ADDRn_TX for COUNTn_TX/2 half-words. If a transmitted packet is composed of an odd
number of bytes, only the lower half of the last half-word accessed is used.
On receiving the ACK receipt by the host, the USB_EPnR register is updated in the
following way: DTOG_TX bit is toggled, the endpoint is made invalid by setting
STAT_TX=10 (NAK) and bit CTR_TX is set. The application software must first identify the
endpoint, which is requesting microcontroller attention by examining the EP_ID and DIR bits
in the USB_ISTR register. Servicing of the CTR_TX event starts clearing the interrupt bit;
the application software then prepares another buffer full of data to be sent, updates the
COUNTn_TX table location with the number of byte to be transmitted during the next
transfer, and finally sets STAT_TX to ‘11 (VALID) to re-enable transmissions. While the
STAT_TX bits are equal to ‘10 (NAK), any IN request addressed to that endpoint is NAKed,

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indicating a flow control condition: the USB host will retry the transaction until it succeeds. It
is mandatory to execute the sequence of operations in the above mentioned order to avoid
losing the notification of a second IN transaction addressed to the same endpoint
immediately following the one which triggered the CTR interrupt.

OUT and SETUP packets (data reception)

These two tokens are handled by the USB peripheral more or less in the same way; the
differences in the handling of SETUP packets are detailed in the following paragraph about
control transfers. When receiving an OUT/SETUP PID, if the address matches a valid
endpoint, the USB peripheral accesses the contents of the ADDRn_RX and COUNTn_RX
locations inside the buffer descriptor table entry related to the addressed endpoint. The
content of the ADDRn_RX is stored directly in its internal register ADDR. While COUNT is
now reset and the values of BL_SIZE and NUM_BLOCK bit fields, which are read within
COUNTn_RX content are used to initialize BUF_COUNT, an internal 16 bit counter, which is
used to check the buffer overrun condition (all these internal registers are not accessible by
software). Data bytes subsequently received by the USB peripheral are packed in half-
words (the first byte received is stored as least significant byte) and then transferred to the
packet buffer starting from the address contained in the internal ADDR register while
BUF_COUNT is decremented and COUNT is incremented at each byte transfer. When the
end of DATA packet is detected, the correctness of the received CRC is tested and only if no
errors occurred during the reception, an ACK handshake packet is sent back to the
transmitting host.
In case of wrong CRC or other kinds of errors (bit-stuff violations, frame errors, etc.), data
bytes are still copied in the packet memory buffer, at least until the error detection point, but
ACK packet is not sent and the ERR bit in USB_ISTR register is set. However, there is
usually no software action required in this case: the USB peripheral recovers from reception
errors and remains ready for the next transaction to come. If the addressed endpoint is not
valid, a NAK or STALL handshake packet is sent instead of the ACK, according to bits
STAT_RX in the USB_EPnR register and no data is written in the reception memory buffers.
Reception memory buffer locations are written starting from the address contained in the
ADDRn_RX for a number of bytes corresponding to the received data packet length, CRC
included (i.e. data payload length + 2), or up to the last allocated memory location, as
defined by BL_SIZE and NUM_BLOCK, whichever comes first. In this way, the USB
peripheral never writes beyond the end of the allocated reception memory buffer area. If the
length of the data packet payload (actual number of bytes used by the application) is greater
than the allocated buffer, the USB peripheral detects a buffer overrun condition. in this case,
a STALL handshake is sent instead of the usual ACK to notify the problem to the host, no
interrupt is generated and the transaction is considered failed.
When the transaction is completed correctly, by sending the ACK handshake packet, the
internal COUNT register is copied back in the COUNTn_RX location inside the buffer
description table entry, leaving unaffected BL_SIZE and NUM_BLOCK fields, which
normally do not require to be re-written, and the USB_EPnR register is updated in the
following way: DTOG_RX bit is toggled, the endpoint is made invalid by setting STAT_RX =
‘10 (NAK) and bit CTR_RX is set. If the transaction has failed due to errors or buffer overrun
condition, none of the previously listed actions take place. The application software must
first identify the endpoint, which is requesting microcontroller attention by examining the
EP_ID and DIR bits in the USB_ISTR register. The CTR_RX event is serviced by first
determining the transaction type (SETUP bit in the USB_EPnR register); the application
software must clear the interrupt flag bit and get the number of received bytes reading the
COUNTn_RX location inside the buffer description table entry related to the endpoint being

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processed. After the received data is processed, the application software should set the
STAT_RX bits to ‘11 (Valid) in the USB_EPnR, enabling further transactions. While the
STAT_RX bits are equal to ‘10 (NAK), any OUT request addressed to that endpoint is
NAKed, indicating a flow control condition: the USB host will retry the transaction until it
succeeds. It is mandatory to execute the sequence of operations in the above mentioned
order to avoid losing the notification of a second OUT transaction addressed to the same
endpoint following immediately the one which triggered the CTR interrupt.

Control transfers
Control transfers are made of a SETUP transaction, followed by zero or more data stages,
all of the same direction, followed by a status stage (a zero-byte transfer in the opposite
direction). SETUP transactions are handled by control endpoints only and are very similar to
OUT ones (data reception) except that the values of DTOG_TX and DTOG_RX bits of the
addressed endpoint registers are set to 1 and 0 respectively, to initialize the control transfer,
and both STAT_TX and STAT_RX are set to ‘10 (NAK) to let software decide if subsequent
transactions must be IN or OUT depending on the SETUP contents. A control endpoint must
check SETUP bit in the USB_EPnR register at each CTR_RX event to distinguish normal
OUT transactions from SETUP ones. A USB device can determine the number and
direction of data stages by interpreting the data transferred in the SETUP stage, and is
required to STALL the transaction in the case of errors. To do so, at all data stages before
the last, the unused direction should be set to STALL, so that, if the host reverses the
transfer direction too soon, it gets a STALL as a status stage.
While enabling the last data stage, the opposite direction should be set to NAK, so that, if
the host reverses the transfer direction (to perform the status stage) immediately, it is kept
waiting for the completion of the control operation. If the control operation completes
successfully, the software will change NAK to VALID, otherwise to STALL. At the same time,
if the status stage is an OUT, the STATUS_OUT (EP_KIND in the USB_EPnR register) bit
should be set, so that an error is generated if a status transaction is performed with not-zero
data. When the status transaction is serviced, the application clears the STATUS_OUT bit
and sets STAT_RX to VALID (to accept a new command) and STAT_TX to NAK (to delay a
possible status stage immediately following the next setup).
Since the USB specification states that a SETUP packet cannot be answered with a
handshake different from ACK, eventually aborting a previously issued command to start
the new one, the USB logic doesn’t allow a control endpoint to answer with a NAK or STALL
packet to a SETUP token received from the host.
When the STAT_RX bits are set to ‘01 (STALL) or ‘10 (NAK) and a SETUP token is
received, the USB accepts the data, performing the required data transfers and sends back
an ACK handshake. If that endpoint has a previously issued CTR_RX request not yet
acknowledged by the application (i.e. CTR_RX bit is still set from a previously completed
reception), the USB discards the SETUP transaction and does not answer with any
handshake packet regardless of its state, simulating a reception error and forcing the host to
send the SETUP token again. This is done to avoid losing the notification of a SETUP
transaction addressed to the same endpoint immediately following the transaction, which
triggered the CTR_RX interrupt.

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25.5.3 Double-buffered endpoints

All different endpoint types defined by the USB standard represent different traffic models,
and describe the typical requirements of different kind of data transfer operations. When
large portions of data are to be transferred between the host PC and the USB function, the
bulk endpoint type is the most suited model. This is because the host schedules bulk
transactions so as to fill all the available bandwidth in the frame, maximizing the actual
transfer rate as long as the USB function is ready to handle a bulk transaction addressed to
it. If the USB function is still busy with the previous transaction when the next one arrives, it
will answer with a NAK handshake and the host PC will issue the same transaction again
until the USB function is ready to handle it, reducing the actual transfer rate due to the
bandwidth occupied by re-transmissions. For this reason, a dedicated feature called
‘double-buffering’ can be used with bulk endpoints.
When ‘double-buffering’ is activated, data toggle sequencing is used to select, which buffer
is to be used by the USB peripheral to perform the required data transfers, using both
‘transmission’ and ‘reception’ packet memory areas to manage buffer swapping on each
successful transaction in order to always have a complete buffer to be used by the
application, while the USB peripheral fills the other one. For example, during an OUT
transaction directed to a ‘reception’ double-buffered bulk endpoint, while one buffer is being
filled with new data coming from the USB host, the other one is available for the
microcontroller software usage (the same would happen with a ‘transmission’ double-
buffered bulk endpoint and an IN transaction).
Since the swapped buffer management requires the usage of all 4 buffer description table
locations hosting the address pointer and the length of the allocated memory buffers, the
USB_EPnR registers used to implement double-buffered bulk endpoints are forced to be
used as unidirectional ones. Therefore, only one STAT bit pair must be set at a value
different from ‘00 (Disabled): STAT_RX if the double-buffered bulk endpoint is enabled for
reception, STAT_TX if the double-buffered bulk endpoint is enabled for transmission. In
case it is required to have double-buffered bulk endpoints enabled both for reception and
transmission, two USB_EPnR registers must be used.
To exploit the double-buffering feature and reach the highest possible transfer rate, the
endpoint flow control structure, described in previous chapters, has to be modified, in order
to switch the endpoint status to NAK only when a buffer conflict occurs between the USB
peripheral and application software, instead of doing it at the end of each successful
transaction. The memory buffer which is currently being used by the USB peripheral is
defined by the DTOG bit related to the endpoint direction: DTOG_RX (bit 14 of USB_EPnR
register) for ‘reception’ double-buffered bulk endpoints or DTOG_TX (bit 6 of USB_EPnR
register) for ‘transmission’ double-buffered bulk endpoints. To implement the new flow
control scheme, the USB peripheral should know which packet buffer is currently in use by
the application software, so to be aware of any conflict. Since in the USB_EPnR register,
there are two DTOG bits but only one is used by USB peripheral for data and buffer
sequencing (due to the unidirectional constraint required by double-buffering feature) the
other one can be used by the application software to show which buffer it is currently using.
This new buffer flag is called SW_BUF. In the following table the correspondence between
USB_EPnR register bits and DTOG/SW_BUF definition is explained, for the cases of
‘transmission’ and ‘reception’ double-buffered bulk endpoints.

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Table 99. Double-buffering buffer flag definition

Buffer flag ‘Transmission’ endpoint ‘Reception’ endpoint

DTOG DTOG_TX (USB_EPnR bit 6) DTOG_RX (USB_EPnR bit 14)

SW_BUF USB_EPnR bit 14 USB_EPnR bit 6

The memory buffer which is currently being used by the USB peripheral is defined by DTOG
buffer flag, while the buffer currently in use by application software is identified by SW_BUF
buffer flag. The relationship between the buffer flag value and the used packet buffer is the
same in both cases, and it is listed in the following table.

Table 100. Bulk double-buffering memory buffers usage

Endpoint Packet buffer used by Packet buffer used by
DTOG SW_BUF
type USB peripheral Application Software

ADDRn_TX_0 / COUNTn_TX_0 ADDRn_TX_1 / COUNTn_TX_1

0 1
Buffer description table locations. Buffer description table locations.
ADDRn_TX_1 / COUNTn_TX_1 ADDRn_TX_0 / COUNTn_TX_0
1 0
Buffer description table locations Buffer description table locations.
IN
ADDRn_TX_0 / COUNTn_TX_0
0 0 None (1)
Buffer description table locations.
ADDRn_TX_1 / COUNTn_TX_1
1 1 None (1)
Buffer description table locations.
ADDRn_RX_0 / COUNTn_RX_0 ADDRn_RX_1 / COUNTn_RX_1
0 1
Buffer description table locations. Buffer description table locations.
ADDRn_RX_1 / COUNTn_RX_1 ADDRn_RX_0 / COUNTn_RX_0
1 0
Buffer description table locations. Buffer description table locations.
OUT
ADDRn_RX_0 / COUNTn_RX_0
0 0 None (1)
Buffer description table locations.
ADDRn_RX_1 / COUNTn_RX_1
1 1 None (1)
Buffer description table locations.
1. Endpoint in NAK Status.

Double-buffering feature for a bulk endpoint is activated by:

• Writing EP_TYPE bit field at ‘00 in its USB_EPnR register, to define the endpoint as a
bulk, and
• Setting EP_KIND bit at ‘1 (DBL_BUF), in the same register.
The application software is responsible for DTOG and SW_BUF bits initialization according
to the first buffer to be used; this has to be done considering the special toggle-only property
that these two bits have. The end of the first transaction occurring after having set
DBL_BUF, triggers the special flow control of double-buffered bulk endpoints, which is used
for all other transactions addressed to this endpoint until DBL_BUF remain set. At the end of
each transaction the CTR_RX or CTR_TX bit of the addressed endpoint USB_EPnR
register is set, depending on the enabled direction. At the same time, the affected DTOG bit
in the USB_EPnR register is hardware toggled making the USB peripheral buffer swapping
completely software independent. Unlike common transactions, and the first one after

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DBL_BUF setting, STAT bit pair is not affected by the transaction termination and its value
remains ‘11 (Valid). However, as the token packet of a new transaction is received, the
actual endpoint status is masked as ‘10 (NAK) when a buffer conflict between the USB
peripheral and the application software is detected (this condition is identified by DTOG and
SW_BUF having the same value, see Table 100 on page 682). The application software
responds to the CTR event notification by clearing the interrupt flag and starting any
required handling of the completed transaction. When the application packet buffer usage is
over, the software toggles the SW_BUF bit, writing ‘1 to it, to notify the USB peripheral about
the availability of that buffer. In this way, the number of NAKed transactions is limited only by
the application elaboration time of a transaction data: if the elaboration time is shorter than
the time required to complete a transaction on the USB bus, no re-transmissions due to flow
control will take place and the actual transfer rate is limited only by the host PC.
The application software can always override the special flow control implemented for
double-buffered bulk endpoints, writing an explicit status different from ‘11 (Valid) into the
STAT bit pair of the related USB_EPnR register. In this case, the USB peripheral will always
use the programmed endpoint status, regardless of the buffer usage condition.

25.5.4 Isochronous transfers

The USB standard supports full speed peripherals requiring a fixed and accurate data
production/consume frequency, defining this kind of traffic as ‘Isochronous’. Typical
examples of this data are: audio samples, compressed video streams, and in general any
sort of sampled data having strict requirements for the accuracy of delivered frequency.
When an endpoint is defined to be ‘isochronous’ during the enumeration phase, the host
allocates in the frame the required bandwidth and delivers exactly one IN or OUT packet
each frame, depending on endpoint direction. To limit the bandwidth requirements, no re-
transmission of failed transactions is possible for Isochronous traffic; this leads to the fact
that an isochronous transaction does not have a handshake phase and no ACK packet is
expected or sent after the data packet. For the same reason, Isochronous transfers do not
support data toggle sequencing and always use DATA0 PID to start any data packet.
The Isochronous behavior for an endpoint is selected by setting the EP_TYPE bits at ‘10 in
its USB_EPnR register; since there is no handshake phase the only legal values for the
STAT_RX/STAT_TX bit pairs are ‘00 (Disabled) and ‘11 (Valid), any other value will produce
results not compliant to USB standard. Isochronous endpoints implement double-buffering
to ease application software development, using both ‘transmission’ and ‘reception’ packet
memory areas to manage buffer swapping on each successful transaction in order to have
always a complete buffer to be used by the application, while the USB peripheral fills the
other.
The memory buffer which is currently used by the USB peripheral is defined by the DTOG
bit related to the endpoint direction (DTOG_RX for ‘reception’ isochronous endpoints,
DTOG_TX for ‘transmission’ isochronous endpoints, both in the related USB_EPnR
register) according to Table 101.

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Table 101. Isochronous memory buffers usage

Endpoint DTOG bit Packet buffer used by the Packet buffer used by the
Type value USB peripheral application software

ADDRn_TX_0 / COUNTn_TX_0 ADDRn_TX_1 / COUNTn_TX_1

0 buffer description table buffer description table
locations. locations.
IN
ADDRn_TX_1 / COUNTn_TX_1 ADDRn_TX_0 / COUNTn_TX_0
1 buffer description table buffer description table
locations. locations.
ADDRn_RX_0 / COUNTn_RX_0 ADDRn_RX_1 / COUNTn_RX_1
0 buffer description table buffer description table
locations. locations.
OUT
ADDRn_RX_1 / COUNTn_RX_1 ADDRn_RX_0 / COUNTn_RX_0
1 buffer description table buffer description table
locations. locations.

As it happens with double-buffered bulk endpoints, the USB_EPnR registers used to

implement Isochronous endpoints are forced to be used as unidirectional ones. In case it is
required to have Isochronous endpoints enabled both for reception and transmission, two
USB_EPnR registers must be used.
The application software is responsible for the DTOG bit initialization according to the first
buffer to be used; this has to be done considering the special toggle-only property that these
two bits have. At the end of each transaction, the CTR_RX or CTR_TX bit of the addressed
endpoint USB_EPnR register is set, depending on the enabled direction. At the same time,
the affected DTOG bit in the USB_EPnR register is hardware toggled making buffer
swapping completely software independent. STAT bit pair is not affected by transaction
completion; since no flow control is possible for Isochronous transfers due to the lack of
handshake phase, the endpoint remains always ‘11 (Valid). CRC errors or buffer-overrun
conditions occurring during Isochronous OUT transfers are anyway considered as correct
transactions and they always trigger an CTR_RX event. However, CRC errors will anyway
set the ERR bit in the USB_ISTR register to notify the software of the possible data
corruption.

25.5.5 Suspend/Resume events

The USB standard defines a special peripheral state, called SUSPEND, in which the
average current drawn from the USB bus must not be greater than 2.5 mA. This
requirement is of fundamental importance for bus-powered devices, while self-powered
devices are not required to comply to this strict power consumption constraint. In suspend
mode, the host PC sends the notification by not sending any traffic on the USB bus for more
than 3 ms: since a SOF packet must be sent every 1 ms during normal operations, the USB
peripheral detects the lack of 3 consecutive SOF packets as a suspend request from the
host PC and set the SUSP bit to ‘1 in USB_ISTR register, causing an interrupt if enabled.
Once the device is suspended, its normal operation can be restored by a so called
RESUME sequence, which can be started from the host PC or directly from the peripheral
itself, but it is always terminated by the host PC. The suspended USB peripheral must be
anyway able to detect a RESET sequence, reacting to this event as a normal USB reset
event.

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The actual procedure used to suspend the USB peripheral is device dependent since
according to the device composition, different actions may be required to reduce the total
consumption.
A brief description of a typical suspend procedure is provided below, focused on the USB-
related aspects of the application software routine responding to the SUSP notification of
the USB peripheral:
1. Set the FSUSP bit in the USB_CNTR register to 1. This action activates the suspend
mode within the USB peripheral. As soon as the suspend mode is activated, the check
on SOF reception is disabled to avoid any further SUSP interrupts being issued while
the USB is suspended.
2. Remove or reduce any static power consumption in blocks different from the USB
peripheral.
3. Set LP_MODE bit in USB_CNTR register to 1 to remove static power consumption in
the analog USB transceivers but keeping them able to detect resume activity.
4. Optionally turn off external oscillator and device PLL to stop any activity inside the
device.
When an USB event occurs while the device is in SUSPEND mode, the RESUME
procedure must be invoked to restore nominal clocks and regain normal USB behavior.
Particular care must be taken to insure that this process does not take more than 10 ms
when the wakening event is an USB reset sequence (See “Universal Serial Bus
Specification” for more details). The start of a resume or reset sequence, while the USB
peripheral is suspended, clears the LP_MODE bit in USB_CNTR register asynchronously.
Even if this event can trigger an WKUP interrupt if enabled, the use of an interrupt response
routine must be carefully evaluated because of the long latency due to system clock restart;
to have the shorter latency before re-activating the nominal clock it is suggested to put the
resume procedure just after the end of the suspend one, so its code is immediately
executed as soon as the system clock restarts. To prevent ESD discharges or any other kind
of noise from waking-up the system (the exit from suspend mode is an asynchronous
event), a suitable analog filter on data line status is activated during suspend; the filter width
is about 70 ns.
The following is a list of actions a resume procedure should address:
1. Optionally turn on external oscillator and/or device PLL.
2. Clear FSUSP bit of USB_CNTR register.
3. If the resume triggering event has to be identified, bits RXDP and RXDM in the
USB_FNR register can be used according to Table 102, which also lists the intended
software action in all the cases. If required, the end of resume or reset sequence can
be detected monitoring the status of the above mentioned bits by checking when they
reach the “10” configuration, which represent the Idle bus state; moreover at the end of
a reset sequence the RESET bit in USB_ISTR register is set to 1, issuing an interrupt if
enabled, which should be handled as usual.

Table 102. Resume event detection

[RXDP,RXDM] status Wake-up event Required resume software action

“00” Root reset None

“10” None (noise on bus) Go back in Suspend mode

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Table 102. Resume event detection (continued)

[RXDP,RXDM] status Wake-up event Required resume software action

“01” Root resume None

“11” Not allowed (noise on bus) Go back in Suspend mode

A device may require to exit from suspend mode as an answer to particular events not
directly related to the USB protocol (e.g. a mouse movement wakes up the whole system).
In this case, the resume sequence can be started by setting the RESUME bit in the
USB_CNTR register to ‘1 and resetting it to 0 after an interval between 1 ms and 15 ms (this
interval can be timed using ESOF interrupts, occurring with a 1 ms period when the system
clock is running at nominal frequency). Once the RESUME bit is clear, the resume
sequence is completed by the host PC and its end can be monitored again using the RXDP
and RXDM bits in the USB_FNR register.
Note: The RESUME bit must be anyway used only after the USB peripheral has been put in
suspend mode, setting the FSUSP bit in USB_CNTR register to 1.

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25.6 USB and USB SRAM registers

The USB peripheral registers can be divided into the following groups:
• Common Registers: Interrupt and Control registers
• Endpoint Registers: Endpoint configuration and status
The USB SRAM registers cover:
• Buffer Descriptor Table: Location of packet memory used to locate data buffers (see
Section 2.2: Memory organization to find USB SRAM base address).
All register addresses are expressed as offsets with respect to the USB peripheral registers
base address, except the buffer descriptor table locations, which starts at the USB SRAM
base address offset by the value specified in the USB_BTABLE register.
Refer to Section 1.2 on page 33 for a list of abbreviations used in register descriptions.
The peripheral registers can be accessed by half-words (16-bit) or words (32-bit).

25.6.1 Common registers

These registers affect the general behavior of the USB peripheral defining operating mode,
interrupt handling, device address and giving access to the current frame number updated
by the host PC.

USB control register (USB_CNTR)

Address offset: 0x40
Reset value: 0x0003

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTR PMAOVR ERR WKUP SUSP RESET SOF ESOF L1REQ Res L1RESU RE F LP_ PDW F
M M M M M M M M M . ME SUME SUSP MODE N RES
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bit 15 CTRM: Correct transfer interrupt mask

0: Correct Transfer (CTR) Interrupt disabled.
1: CTR Interrupt enabled, an interrupt request is generated when the corresponding bit in the
USB_ISTR register is set.
Bit 14 PMAOVRM: Packet memory area over / underrun interrupt mask
0: PMAOVR Interrupt disabled.
1: PMAOVR Interrupt enabled, an interrupt request is generated when the corresponding bit
in the USB_ISTR register is set.
Bit 13 ERRM: Error interrupt mask
0: ERR Interrupt disabled.
1: ERR Interrupt enabled, an interrupt request is generated when the corresponding bit in
the USB_ISTR register is set.
Bit 12 WKUPM: Wake-up interrupt mask
0: WKUP Interrupt disabled.
1: WKUP Interrupt enabled, an interrupt request is generated when the corresponding bit in
the USB_ISTR register is set.

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Bit 11 SUSPM: Suspend mode interrupt mask

0: Suspend Mode Request (SUSP) Interrupt disabled.
1: SUSP Interrupt enabled, an interrupt request is generated when the corresponding bit in
the USB_ISTR register is set.
Bit 10 RESETM: USB reset interrupt mask
0: RESET Interrupt disabled.
1: RESET Interrupt enabled, an interrupt request is generated when the corresponding bit in
the USB_ISTR register is set.
Bit 9 SOFM: Start of frame interrupt mask
0: SOF Interrupt disabled.
1: SOF Interrupt enabled, an interrupt request is generated when the corresponding bit in the
USB_ISTR register is set.
Bit 8 ESOFM: Expected start of frame interrupt mask
0: Expected Start of Frame (ESOF) Interrupt disabled.
1: ESOF Interrupt enabled, an interrupt request is generated when the corresponding bit in
the USB_ISTR register is set.
Bit 7 L1REQM: LPM L1 state request interrupt mask
0: LPM L1 state request (L1REQ) Interrupt disabled.
1: L1REQ Interrupt enabled, an interrupt request is generated when the corresponding bit in
the USB_ISTR register is set.
Bit 6 Reserved, must be kept at reset value.
Bit 5 L1RESUME: LPM L1 Resume request
The microcontroller can set this bit to send a LPM L1 Resume signal to the host. After the
signaling ends, this bit is cleared by hardware.
Bit 4 RESUME: Resume request
The microcontroller can set this bit to send a Resume signal to the host. It must be activated,
according to USB specifications, for no less than 1 ms and no more than 15 ms after which
the Host PC is ready to drive the resume sequence up to its end.
Bit 3 FSUSP: Force suspend
Software must set this bit when the SUSP interrupt is received, which is issued when no
traffic is received by the USB peripheral for 3 ms.
0: No effect.
1: Enter suspend mode. Clocks and static power dissipation in the analog transceiver are left
unaffected. If suspend power consumption is a requirement (bus-powered device), the
application software should set the LP_MODE bit after FSUSP as explained below.
Bit 2 LP_MODE: Low-power mode
This mode is used when the suspend-mode power constraints require that all static power
dissipation is avoided, except the one required to supply the external pull-up resistor. This
condition should be entered when the application is ready to stop all system clocks, or
reduce their frequency in order to meet the power consumption requirements of the USB
suspend condition. The USB activity during the suspend mode (WKUP event)
asynchronously resets this bit (it can also be reset by software).
0: No Low-power mode.
1: Enter Low-power mode.

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Bit 1 PDWN: Power down

This bit is used to completely switch off all USB-related analog parts if it is required to
completely disable the USB peripheral for any reason. When this bit is set, the USB
peripheral is disconnected from the transceivers and it cannot be used.
0: Exit Power Down.
1: Enter Power down mode.
Bit 0 FRES: Force USB Reset
0: Clear USB reset.
1: Force a reset of the USB peripheral, exactly like a RESET signaling on the USB. The USB
peripheral is held in RESET state until software clears this bit. A “USB-RESET” interrupt is
generated, if enabled.

USB interrupt status register (USB_ISTR)

Address offset: 0x44
Reset value: 0x0000 0000

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

PMA
CTR ERR WKUP SUSP RESET SOF ESOF L1REQ Res. Res. DIR EP_ID[3:0]
OVR

r rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 r r r r r

This register contains the status of all the interrupt sources allowing application software to
determine, which events caused an interrupt request.
The upper part of this register contains single bits, each of them representing a specific
event. These bits are set by the hardware when the related event occurs; if the
corresponding bit in the USB_CNTR register is set, a generic interrupt request is generated.
The interrupt routine, examining each bit, will perform all necessary actions, and finally it will
clear the serviced bits. If any of them is not cleared, the interrupt is considered to be still
pending, and the interrupt line is kept high again. If several bits are set simultaneously, only
a single interrupt is generated.
Endpoint transaction completion can be handled in a different way to reduce interrupt
response latency. The CTR bit is set by the hardware as soon as an endpoint successfully
completes a transaction, generating a generic interrupt request if the corresponding bit in
USB_CNTR is set. An endpoint dedicated interrupt condition is activated independently
from the CTRM bit in the USB_CNTR register. Both interrupt conditions remain active until
software clears the pending bit in the corresponding USB_EPnR register (the CTR bit is
actually a read only bit). For endpoint-related interrupts, the software can use the Direction
of Transaction (DIR) and EP_ID read-only bits to identify, which endpoint made the last
interrupt request and called the corresponding interrupt service routine.
The user can choose the relative priority of simultaneously pending USB_ISTR events by
specifying the order in which software checks USB_ISTR bits in an interrupt service routine.
Only the bits related to events, which are serviced, are cleared. At the end of the service
routine, another interrupt is requested, to service the remaining conditions.
To avoid spurious clearing of some bits, it is recommended to clear them with a load
instruction where all bits which must not be altered are written with 1, and all bits to be
cleared are written with ‘0 (these bits can only be cleared by software). Read-modify-write
cycles should be avoided because between the read and the write operations another bit

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could be set by the hardware and the next write will clear it before the microprocessor has
the time to serve the event.
The following describes each bit in detail:

Bit 15 CTR: Correct transfer

This bit is set by the hardware to indicate that an endpoint has successfully completed a
transaction; using DIR and EP_ID bits software can determine which endpoint requested the
interrupt. This bit is read-only.
Bit 14 PMAOVR: Packet memory area over / underrun
This bit is set if the microcontroller has not been able to respond in time to an USB memory
request. The USB peripheral handles this event in the following way: During reception an
ACK handshake packet is not sent, during transmission a bit-stuff error is forced on the
transmitted stream; in both cases the host will retry the transaction. The PMAOVR interrupt
should never occur during normal operations. Since the failed transaction is retried by the
host, the application software has the chance to speed-up device operations during this
interrupt handling, to be ready for the next transaction retry; however this does not happen
during Isochronous transfers (no isochronous transaction is anyway retried) leading to a loss
of data in this case. This bit is read/write but only ‘0 can be written and writing ‘1 has no
effect.
Bit 13 ERR: Error
This flag is set whenever one of the errors listed below has occurred:
NANS: No ANSwer. The timeout for a host response has expired.
CRC: Cyclic Redundancy Check error. One of the received CRCs, either in the token or in
the data, was wrong.
BST: Bit Stuffing error. A bit stuffing error was detected anywhere in the PID, data, and/or
CRC.
FVIO: Framing format Violation. A non-standard frame was received (EOP not in the right
place, wrong token sequence, etc.).
The USB software can usually ignore errors, since the USB peripheral and the PC host
manage retransmission in case of errors in a fully transparent way. This interrupt can be
useful during the software development phase, or to monitor the quality of transmission over
the USB bus, to flag possible problems to the user (e.g. loose connector, too noisy
environment, broken conductor in the USB cable and so on). This bit is read/write but only ‘0
can be written and writing ‘1 has no effect.
Bit 12 WKUP: Wake-up
This bit is set to 1 by the hardware when, during suspend mode, activity is detected that
wakes up the USB peripheral. This event asynchronously clears the LP_MODE bit in the
CTLR register and activates the USB_WAKEUP line, which can be used to notify the rest of
the device (e.g. wake-up unit) about the start of the resume process. This bit is read/write but
only ‘0 can be written and writing ‘1 has no effect.
Bit 11 SUSP: Suspend mode request
This bit is set by the hardware when no traffic has been received for 3 ms, indicating a
suspend mode request from the USB bus. The suspend condition check is enabled
immediately after any USB reset and it is disabled by the hardware when the suspend mode
is active (FSUSP=1) until the end of resume sequence. This bit is read/write but only ‘0 can
be written and writing ‘1 has no effect.

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Bit 10 RESET: USB reset request

Set when the USB peripheral detects an active USB RESET signal at its inputs. The USB
peripheral, in response to a RESET, just resets its internal protocol state machine, generating
an interrupt if RESETM enable bit in the USB_CNTR register is set. Reception and
transmission are disabled until the RESET bit is cleared. All configuration registers do not
reset: the microcontroller must explicitly clear these registers (this is to ensure that the
RESET interrupt can be safely delivered, and any transaction immediately followed by a
RESET can be completed). The function address and endpoint registers are reset by an USB
reset event.
This bit is read/write but only ‘0 can be written and writing ‘1 has no effect.
Bit 9 SOF: Start of frame
This bit signals the beginning of a new USB frame and it is set when a SOF packet arrives
through the USB bus. The interrupt service routine may monitor the SOF events to have a
1 ms synchronization event to the USB host and to safely read the USB_FNR register which
is updated at the SOF packet reception (this could be useful for isochronous applications).
This bit is read/write but only ‘0 can be written and writing ‘1 has no effect.
Bit 8 ESOF: Expected start of frame
This bit is set by the hardware when an SOF packet is expected but not received. The host
sends an SOF packet each 1 ms, but if the device does not receive it properly, the Suspend
Timer issues this interrupt. If three consecutive ESOF interrupts are generated (i.e. three
SOF packets are lost) without any traffic occurring in between, a SUSP interrupt is
generated. This bit is set even when the missing SOF packets occur while the Suspend
Timer is not yet locked. This bit is read/write but only ‘0 can be written and writing ‘1 has no
effect.
Bit 7 L1REQ: LPM L1 state request
This bit is set by the hardware when LPM command to enter the L1 state is successfully
received and acknowledged. This bit is read/write but only ‘0 can be written and writing ‘1 has
no effect.
Bits 6:5 Reserved, must be kept at reset value.
Bit 4 DIR: Direction of transaction
This bit is written by the hardware according to the direction of the successful transaction,
which generated the interrupt request.
If DIR bit=0, CTR_TX bit is set in the USB_EPnR register related to the interrupting endpoint.
The interrupting transaction is of IN type (data transmitted by the USB peripheral to the host
PC).
If DIR bit=1, CTR_RX bit or both CTR_TX/CTR_RX are set in the USB_EPnR register
related to the interrupting endpoint. The interrupting transaction is of OUT type (data
received by the USB peripheral from the host PC) or two pending transactions are waiting to
be processed.
This information can be used by the application software to access the USB_EPnR bits
related to the triggering transaction since it represents the direction having the interrupt
pending. This bit is read-only.

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Bits 3:0 EP_ID[3:0]: Endpoint Identifier

These bits are written by the hardware according to the endpoint number, which generated
the interrupt request. If several endpoint transactions are pending, the hardware writes the
endpoint identifier related to the endpoint having the highest priority defined in the following
way: Two endpoint sets are defined, in order of priority: Isochronous and double-buffered
bulk endpoints are considered first and then the other endpoints are examined. If more than
one endpoint from the same set is requesting an interrupt, the EP_ID bits in USB_ISTR
register are assigned according to the lowest requesting endpoint register, EP0R having the
highest priority followed by EP1R and so on. The application software can assign a register
to each endpoint according to this priority scheme, so as to order the concurring endpoint
requests in a suitable way. These bits are read only.

USB frame number register (USB_FNR)

Address offset: 0x48
Reset value: 0x0XXX where X is undefined

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RXDP RXDM LCK LSOF[1:0] FN[10:0]

r r r r r r r r r r r r r r r r

Bit 15 RXDP: Receive data + line status

This bit can be used to observe the status of received data plus upstream port data line. It
can be used during end-of-suspend routines to help determining the wake-up event.
Bit 14 RXDM: Receive data - line status
This bit can be used to observe the status of received data minus upstream port data line. It
can be used during end-of-suspend routines to help determining the wake-up event.
Bit 13 LCK: Locked
This bit is set by the hardware when at least two consecutive SOF packets have been
received after the end of an USB reset condition or after the end of an USB resume
sequence. Once locked, the frame timer remains in this state until an USB reset or USB
suspend event occurs.
Bits 12:11 LSOF[1:0]: Lost SOF
These bits are written by the hardware when an ESOF interrupt is generated, counting the
number of consecutive SOF packets lost. At the reception of an SOF packet, these bits are
cleared.
Bits 10:0 FN[10:0]: Frame number
This bit field contains the 11-bits frame number contained in the last received SOF packet.
The frame number is incremented for every frame sent by the host and it is useful for
Isochronous transfers. This bit field is updated on the generation of an SOF interrupt.

USB device address (USB_DADDR)

Address offset: 0x4C
Reset value: 0x0000

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15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res. Res. Res. Res. Res. Res. Res. Res. EF ADD6 ADD5 ADD4 ADD3 ADD2 ADD1 ADD0

rw rw rw rw rw rw rw rw

Bits 15:8 Reserved

Bit 7 EF: Enable function
This bit is set by the software to enable the USB device. The address of this device is
contained in the following ADD[6:0] bits. If this bit is at ‘0 no transactions are handled,
irrespective of the settings of USB_EPnR registers.
Bits 6:0 ADD[6:0]: Device address
These bits contain the USB function address assigned by the host PC during the
enumeration process. Both this field and the Endpoint Address (EA) field in the associated
USB_EPnR register must match with the information contained in a USB token in order to
handle a transaction to the required endpoint.

Buffer table address (USB_BTABLE)

Address offset: 0x50
Reset value: 0x0000

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

BTABLE[15:3] Res. Res. Res.

rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 15:3 BTABLE[15:3]: Buffer table

These bits contain the start address of the buffer allocation table inside the dedicated packet
memory. This table describes each endpoint buffer location and size and it must be aligned
to an 8 byte boundary (the 3 least significant bits are always ‘0). At the beginning of every
transaction addressed to this device, the USB peripheral reads the element of this table
related to the addressed endpoint, to get its buffer start location and the buffer size (Refer to
Structure and usage of packet buffers on page 676).
Bits 2:0 Reserved, forced by hardware to 0.

LPM control and status register (USB_LPMCSR)

Address offset: 0x54
Reset value: 0x0000

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

REM LPM LPM

Res. Res. Res. Res. Res. Res. Res. Res. BESL[3:0] Res.
WAKE ACK EN

r r r r r rw rw

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Bits 15:8 Reserved, must be kept at reset value.

Bits 7:4 BESL[3:0]: BESL value
These bits contain the BESL value received with last ACKed LPM Token
Bit 3 REMWAKE: bRemoteWake value
This bit contains the bRemoteWake value received with last ACKed LPM Token
Bit 2 Reserved
Bit 1 LPMACK: LPM Token acknowledge enable
0: the valid LPM Token is NYET.
1: the valid LPM Token is ACK.
The NYET/ACK is returned only on a successful LPM transaction:
No errors in both the EXT token and the LPM token (else ERROR)
A valid bLinkState = 0001B (L1) is received (else STALL)
Bit 0 LPMEN: LPM support enable
This bit is set by the software to enable the LPM support within the USB device. If this bit is
at ‘0 no LPM transactions are handled.

Battery charging detector (USB_BCDR)

Address offset: 0x58
Reset value: 0x0000

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

PS2 DC DCD BCD

DPPU Res. Res. Res. Res. Res. Res. Res. SDET PDET SDEN PDEN
DET DET EN EN

rw r r r r rw rw rw rw

Bit 15 DPPU: DP pull-up control

This bit is set by software to enable the embedded pull-up on the DP line. Clearing it to ‘0’
can be used to signalize disconnect to the host when needed by the user software.
Bits 14:8 Reserved, must be kept at reset value.
Bit 7 PS2DET: DM pull-up detection status
This bit is active only during PD and gives the result of comparison between DM voltage
level and VLGC threshold. In normal situation, the DM level should be below this threshold. If
it is above, it means that the DM is externally pulled high. This can be caused by connection
to a PS2 port (which pulls-up both DP and DM lines) or to some proprietary charger not
following the BCD specification.
0: Normal port detected (connected to SDP, ACA, CDP or DCP).
1: PS2 port or proprietary charger detected.
Bit 6 SDET: Secondary detection (SD) status
This bit gives the result of SD.
0: CDP detected.
1: DCP detected.
Bit 5 PDET: Primary detection (PD) status
This bit gives the result of PD.
0: no BCD support detected (connected to SDP or proprietary device).
1: BCD support detected (connected to ACA, CDP or DCP).

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Bit 4 DCDET: Data contact detection (DCD) status

This bit gives the result of DCD.
0: data lines contact not detected.
1: data lines contact detected.
Bit 3 SDEN: Secondary detection (SD) mode enable
This bit is set by the software to put the BCD into SD mode. Only one detection mode (DCD,
PD, SD or OFF) should be selected to work correctly.
Bit 2 PDEN: Primary detection (PD) mode enable
This bit is set by the software to put the BCD into PD mode. Only one detection mode (DCD,
PD, SD or OFF) should be selected to work correctly.
Bit 1 DCDEN: Data contact detection (DCD) mode enable
This bit is set by the software to put the BCD into DCD mode. Only one detection mode
(DCD, PD, SD or OFF) should be selected to work correctly.
Bit 0 BCDEN: Battery charging detector (BCD) enable
This bit is set by the software to enable the BCD support within the USB device. When
enabled, the USB PHY is fully controlled by BCD and cannot be used for normal
communication. Once the BCD discovery is finished, the BCD should be placed in OFF
mode by clearing this bit to ‘0 in order to allow the normal USB operation.

Endpoint-specific registers
The number of these registers varies according to the number of endpoints that the USB
peripheral is designed to handle. The USB peripheral supports up to 8 bidirectional
endpoints. Each USB device must support a control endpoint whose address (EA bits) must
be set to 0. The USB peripheral behaves in an undefined way if multiple endpoints are
enabled having the same endpoint number value. For each endpoint, an USB_EPnR
register is available to store the endpoint specific information.

USB endpoint n register (USB_EPnR), n=[0..7]

Address offset: 0x00 to 0x1C
Reset value: 0x0000

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

CTR_ DTOG EP EP_ CTR_ DTOG_

STAT_RX[1:0] SETUP STAT_TX[1:0] EA[3:0]
RX _RX TYPE[1:0] KIND TX TX

rc_w0 t t t r rw rw rw rc_w0 t t t rw rw rw rw

They are also reset when an USB reset is received from the USB bus or forced through bit
FRES in the CTLR register, except the CTR_RX and CTR_TX bits, which are kept
unchanged to avoid missing a correct packet notification immediately followed by an USB
reset event. Each endpoint has its USB_EPnR register where n is the endpoint identifier.
Read-modify-write cycles on these registers should be avoided because between the read
and the write operations some bits could be set by the hardware and the next write would
modify them before the CPU has the time to detect the change. For this purpose, all bits
affected by this problem have an ‘invariant’ value that must be used whenever their
modification is not required. It is recommended to modify these registers with a load
instruction where all the bits, which can be modified only by the hardware, are written with
their ‘invariant’ value.

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Bit 15 CTR_RX: Correct transfer for reception

This bit is set by the hardware when an OUT/SETUP transaction is successfully completed
on this endpoint; the software can only clear this bit. If the CTRM bit in USB_CNTR register
is set accordingly, a generic interrupt condition is generated together with the endpoint
related interrupt condition, which is always activated. The type of occurred transaction, OUT
or SETUP, can be determined from the SETUP bit described below.
A transaction ended with a NAK or STALL handshake does not set this bit, since no data is
actually transferred, as in the case of protocol errors or data toggle mismatches.
This bit is read/write but only ‘0 can be written, writing 1 has no effect.
Bit 14 DTOG_RX: Data toggle, for reception transfers
If the endpoint is not Isochronous, this bit contains the expected value of the data toggle bit
(0=DATA0, 1=DATA1) for the next data packet to be received. Hardware toggles this bit,
when the ACK handshake is sent to the USB host, following a data packet reception having
a matching data PID value; if the endpoint is defined as a control one, hardware clears this
bit at the reception of a SETUP PID addressed to this endpoint.
If the endpoint is using the double-buffering feature this bit is used to support packet buffer
swapping too (Refer to Section 25.5.3: Double-buffered endpoints).
If the endpoint is Isochronous, this bit is used only to support packet buffer swapping since
no data toggling is used for this sort of endpoints and only DATA0 packet are transmitted
(Refer to Section 25.5.4: Isochronous transfers). Hardware toggles this bit just after the end
of data packet reception, since no handshake is used for isochronous transfers.
This bit can also be toggled by the software to initialize its value (mandatory when the
endpoint is not a control one) or to force specific data toggle/packet buffer usage. When the
application software writes ‘0, the value of DTOG_RX remains unchanged, while writing ‘1
makes the bit value toggle. This bit is read/write but it can be only toggled by writing 1.
Bits 13:12 STAT_RX [1:0]: Status bits, for reception transfers
These bits contain information about the endpoint status, which are listed in Table 103:
Reception status encoding on page 698.These bits can be toggled by software to initialize
their value. When the application software writes ‘0, the value remains unchanged, while
writing ‘1 makes the bit value toggle. Hardware sets the STAT_RX bits to NAK when a
correct transfer has occurred (CTR_RX=1) corresponding to a OUT or SETUP (control only)
transaction addressed to this endpoint, so the software has the time to elaborate the
received data before it acknowledge a new transaction
Double-buffered bulk endpoints implement a special transaction flow control, which control
the status based upon buffer availability condition (Refer to Section 25.5.3: Double-buffered
endpoints).
If the endpoint is defined as Isochronous, its status can be only “VALID” or “DISABLED”, so
that the hardware cannot change the status of the endpoint after a successful transaction. If
the software sets the STAT_RX bits to ‘STALL’ or ‘NAK’ for an Isochronous endpoint, the
USB peripheral behavior is not defined. These bits are read/write but they can be only
toggled by writing ‘1.
Bit 11 SETUP: Setup transaction completed
This bit is read-only and it is set by the hardware when the last completed transaction is a
SETUP. This bit changes its value only for control endpoints. It must be examined, in the
case of a successful receive transaction (CTR_RX event), to determine the type of
transaction occurred. To protect the interrupt service routine from the changes in SETUP
bits due to next incoming tokens, this bit is kept frozen while CTR_RX bit is at 1; its state
changes when CTR_RX is at 0. This bit is read-only.

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Bits 10:9 EP_TYPE[1:0]: Endpoint type

These bits configure the behavior of this endpoint as described in Table 104: Endpoint type
encoding on page 698. Endpoint 0 must always be a control endpoint and each USB
function must have at least one control endpoint which has address 0, but there may be
other control endpoints if required. Only control endpoints handle SETUP transactions,
which are ignored by endpoints of other kinds. SETUP transactions cannot be answered
with NAK or STALL. If a control endpoint is defined as NAK, the USB peripheral will not
answer, simulating a receive error, in the receive direction when a SETUP transaction is
received. If the control endpoint is defined as STALL in the receive direction, then the
SETUP packet is accepted anyway, transferring data and issuing the CTR interrupt. The
reception of OUT transactions is handled in the normal way, even if the endpoint is a control
one.
Bulk and interrupt endpoints have very similar behavior and they differ only in the special
feature available using the EP_KIND configuration bit.
The usage of Isochronous endpoints is explained in Section 25.5.4: Isochronous transfers
Bit 8 EP_KIND: Endpoint kind
The meaning of this bit depends on the endpoint type configured by the EP_TYPE bits.
Table 105 summarizes the different meanings.
DBL_BUF: This bit is set by the software to enable the double-buffering feature for this bulk
endpoint. The usage of double-buffered bulk endpoints is explained in Section 25.5.3:
Double-buffered endpoints.
STATUS_OUT: This bit is set by the software to indicate that a status out transaction is
expected: in this case all OUT transactions containing more than zero data bytes are
answered ‘STALL’ instead of ‘ACK’. This bit may be used to improve the robustness of the
application to protocol errors during control transfers and its usage is intended for control
endpoints only. When STATUS_OUT is reset, OUT transactions can have any number of
bytes, as required.
Bit 7 CTR_TX: Correct Transfer for transmission
This bit is set by the hardware when an IN transaction is successfully completed on this
endpoint; the software can only clear this bit. If the CTRM bit in the USB_CNTR register is
set accordingly, a generic interrupt condition is generated together with the endpoint related
interrupt condition, which is always activated.
A transaction ended with a NAK or STALL handshake does not set this bit, since no data is
actually transferred, as in the case of protocol errors or data toggle mismatches.
This bit is read/write but only ‘0 can be written.
Bit 6 DTOG_TX: Data Toggle, for transmission transfers
If the endpoint is non-isochronous, this bit contains the required value of the data toggle bit
(0=DATA0, 1=DATA1) for the next data packet to be transmitted. Hardware toggles this bit
when the ACK handshake is received from the USB host, following a data packet
transmission. If the endpoint is defined as a control one, hardware sets this bit to 1 at the
reception of a SETUP PID addressed to this endpoint.
If the endpoint is using the double buffer feature, this bit is used to support packet buffer
swapping too (Refer to Section 25.5.3: Double-buffered endpoints)
If the endpoint is Isochronous, this bit is used to support packet buffer swapping since no
data toggling is used for this sort of endpoints and only DATA0 packet are transmitted (Refer
to Section 25.5.4: Isochronous transfers). Hardware toggles this bit just after the end of data
packet transmission, since no handshake is used for Isochronous transfers.
This bit can also be toggled by the software to initialize its value (mandatory when the
endpoint is not a control one) or to force a specific data toggle/packet buffer usage. When
the application software writes ‘0, the value of DTOG_TX remains unchanged, while writing
‘1 makes the bit value toggle. This bit is read/write but it can only be toggled by writing 1.

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Bits 5:4 STAT_TX [1:0]: Status bits, for transmission transfers

These bits contain the information about the endpoint status, listed in Table 106. These bits
can be toggled by the software to initialize their value. When the application software writes
‘0, the value remains unchanged, while writing ‘1 makes the bit value toggle. Hardware sets
the STAT_TX bits to NAK, when a correct transfer has occurred (CTR_TX=1) corresponding
to a IN or SETUP (control only) transaction addressed to this endpoint. It then waits for the
software to prepare the next set of data to be transmitted.
Double-buffered bulk endpoints implement a special transaction flow control, which controls
the status based on buffer availability condition (Refer to Section 25.5.3: Double-buffered
endpoints).
If the endpoint is defined as Isochronous, its status can only be “VALID” or “DISABLED”.
Therefore, the hardware cannot change the status of the endpoint after a successful
transaction. If the software sets the STAT_TX bits to ‘STALL’ or ‘NAK’ for an Isochronous
endpoint, the USB peripheral behavior is not defined. These bits are read/write but they can
be only toggled by writing ‘1.
Bits 3:0 EA[3:0]: Endpoint address
Software must write in this field the 4-bit address used to identify the transactions directed to
this endpoint. A value must be written before enabling the corresponding endpoint.

Table 103. Reception status encoding

STAT_RX[1:0] Meaning

00 DISABLED: all reception requests addressed to this endpoint are ignored.

STALL: the endpoint is stalled and all reception requests result in a STALL
01
handshake.
10 NAK: the endpoint is naked and all reception requests result in a NAK handshake.
11 VALID: this endpoint is enabled for reception.

Table 104. Endpoint type encoding

EP_TYPE[1:0] Meaning

00 BULK
01 CONTROL
10 ISO
11 INTERRUPT

Table 105. Endpoint kind meaning

EP_TYPE[1:0] EP_KIND meaning

00 BULK DBL_BUF
01 CONTROL STATUS_OUT
10 ISO Not used
11 INTERRUPT Not used

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RM0360 Universal serial bus full-speed device interface (USB)

Table 106. Transmission status encoding

STAT_TX[1:0] Meaning

00 DISABLED: all transmission requests addressed to this endpoint are ignored.

STALL: the endpoint is stalled and all transmission requests result in a STALL
01
handshake.
NAK: the endpoint is naked and all transmission requests result in a NAK
10
handshake.
11 VALID: this endpoint is enabled for transmission.

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Universal serial bus full-speed device interface (USB) RM0360

25.6.2 Buffer descriptor table

Note: The buffer descriptor table is located inside the packet buffer memory in the separate "USB
SRAM" address space.
Although the buffer descriptor table is located inside the packet buffer memory ("USB
SRAM" area), its entries can be considered as additional registers used to configure the
location and size of the packet buffers used to exchange data between the USB macro cell
and the device.
The first packet memory location is located at USB SRAM base address. The buffer
descriptor table entry associated with the USB_EPnR registers is described below. The
packet memory should be accessed only by byte (8-bit) or half-word (16-bit) accesses.
Word (32-bit) accesses are not allowed.
A thorough explanation of packet buffers and the buffer descriptor table usage can be found
in Structure and usage of packet buffers on page 676.

Transmission buffer address n (USB_ADDRn_TX)

Address offset: [USB_BTABLE] + n*8
Note: In case of double-buffered or isochronous endpoints in the IN direction, this address location
is referred to as USB_ADDRn_TX_0.
In case of double-buffered or isochronous endpoints in the OUT direction, this address
location is used for USB_ADDRn_RX_0.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

ADDRn_TX[15:1] -

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw -

Bits 15:1 ADDRn_TX[15:1]: Transmission buffer address

These bits point to the starting address of the packet buffer containing data to be transmitted
by the endpoint associated with the USB_EPnR register at the next IN token addressed to it.
Bit 0 Must always be written as ‘0 since packet memory is half-word wide and all packet buffers
must be half-word aligned.

Transmission byte count n (USB_COUNTn_TX)

Address offset: [USB_BTABLE] + n*8 + 2
Note: In case of double-buffered or isochronous endpoints in the IN direction, this address location
is referred to as USB_COUNTn_TX_0.
In case of double-buffered or isochronous endpoints in the OUT direction, this address
location is used for USB_COUNTn_RX_0.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res. Res. Res. Res. Res. Res. COUNTn_TX[9:0]

rw rw rw rw rw rw rw rw rw rw

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Bits 15:10 These bits are not used since packet size is limited by USB specifications to 1023 bytes. Their
value is not considered by the USB peripheral.
Bits 9:0 COUNTn_TX[9:0]: Transmission byte count
These bits contain the number of bytes to be transmitted by the endpoint associated with the
USB_EPnR register at the next IN token addressed to it.

Reception buffer address n (USB_ADDRn_RX)

Address offset: [USB_BTABLE] + n*8 + 4
Note: In case of double-buffered or isochronous endpoints in the OUT direction, this address
location is referred to as USB_ADDRn_RX_1.
In case of double-buffered or isochronous endpoints in the IN direction, this address location
is used for USB_ADDRn_TX_1.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

ADDRn_RX[15:1] -

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw -

Bits 15:1 ADDRn_RX[15:1]: Reception buffer address

These bits point to the starting address of the packet buffer, which will contain the data
received by the endpoint associated with the USB_EPnR register at the next OUT/SETUP
token addressed to it.
Bit 0 This bit must always be written as ‘0 since packet memory is half-word wide and all packet
buffers must be half-word aligned.

Reception byte count n (USB_COUNTn_RX)

Address offset: [USB_BTABLE] + n*8 + 6
Note: In case of double-buffered or isochronous endpoints in the OUT direction, this address
location is referred to as USB_COUNTn_RX_1.
In case of double-buffered or isochronous endpoints in the IN direction, this address location
is used for USB_COUNTn_TX_1.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

BLSIZE NUM_BLOCK[4:0] COUNTn_RX[9:0]

rw rw rw rw rw rw r r r r r r r r r r

This table location is used to store two different values, both required during packet
reception. The most significant bits contains the definition of allocated buffer size, to allow
buffer overflow detection, while the least significant part of this location is written back by the
USB peripheral at the end of reception to give the actual number of received bytes. Due to
the restrictions on the number of available bits, buffer size is represented using the number
of allocated memory blocks, where block size can be selected to choose the trade-off
between fine-granularity/small-buffer and coarse-granularity/large-buffer. The size of
allocated buffer is a part of the endpoint descriptor and it is normally defined during the

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Universal serial bus full-speed device interface (USB) RM0360

enumeration process according to its maxPacketSize parameter value (See “Universal

Serial Bus Specification”).

Bit 15 BL_SIZE: Block size

This bit selects the size of memory block used to define the allocated buffer area.
– If BL_SIZE=0, the memory block is 2-byte large, which is the minimum block
allowed in a half-word wide memory. With this block size the allocated buffer size
ranges from 2 to 62 bytes.
– If BL_SIZE=1, the memory block is 32-byte large, which allows to reach the
maximum packet length defined by USB specifications. With this block size the
allocated buffer size theoretically ranges from 32 to 1024 bytes, which is the longest
packet size allowed by USB standard specifications. However, the applicable size is
limited by the available buffer memory.
Bits 14:10 NUM_BLOCK[4:0]: Number of blocks
These bits define the number of memory blocks allocated to this packet buffer. The actual
amount of allocated memory depends on the BL_SIZE value as illustrated in Table 107.
Bits 9:0 COUNTn_RX[9:0]: Reception byte count
These bits contain the number of bytes received by the endpoint associated with the
USB_EPnR register during the last OUT/SETUP transaction addressed to it.

Table 107. Definition of allocated buffer memory

Value of Memory allocated Memory allocated
NUM_BLOCK[4:0] when BL_SIZE=0 when BL_SIZE=1

0 (‘00000) Not allowed 32 bytes

1 (‘00001) 2 bytes 64 bytes
2 (‘00010) 4 bytes 96 bytes
3 (‘00011) 6 bytes 128 bytes
... ... ...
14 (‘01110) 28 bytes 480 bytes
15 (‘01111) 30 bytes 512 bytes
16 (‘10000) 32 bytes 544 bytes
... ... ...
29 (‘11101) 58 bytes 960 bytes
30 (‘11110) 60 bytes 992 bytes
31 (‘11111) 62 bytes N/A

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 0x48
0x44
0x40
0x18
0x14
0x10
0x08
0x04
0x00

0x3F

0x4C
0x1C
0x0C

0x20-
Offset
25.6.3
RM0360

USB_FNR
Register

USB_ISTR

Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value

USB_EP7R
USB_EP6R
USB_EP5R
USB_EP4R
USB_EP3R
USB_EP2R
USB_EP1R
USB_EP0R

USB_CNTR

USB_DADDR
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 31
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 30
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 29
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 28
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 27
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
USB register map

26
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 25
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 24
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 23
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 22
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 21
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 20
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 19
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 18
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

Reserved

RM0360 Rev 5
17
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 16

0
0
0
0
0
0
0
0
0
0
0

Res. RXDP CTR CTRM CTR_RX CTR_RX CTR_RX CTR_RX CTR_RX CTR_RX CTR_RX CTR_RX 15

0
0
0
0
0
0
0
0
0
0
0

Res. RXDM PMAOVR PMAOVRM DTOG_RX DTOG_RX DTOG_RX DTOG_RX DTOG_RX DTOG_RX DTOG_RX DTOG_RX 14

0
0
0
0
0
0
0
0
0
0
0

Res. LCK ERR ERRM 13

RX
RX
RX
RX
RX
RX
RX
RX

[1:0]
[1:0]
[1:0]
[1:0]
[1:0]
[1:0]
[1:0]
[1:0]

0
0
0
0
0
0
0
0
0
0
0

Res. WKUP WKUPM

STAT_
STAT_
STAT_
STAT_
STAT_
STAT_
STAT_
STAT_

12

[1:0]
0
0
0
0
0
0
0
0
0
0
0

Res. SUSP SUSPM SETUP SETUP SETUP SETUP SETUP SETUP SETUP SETUP

LSOF
11
Table 108. USB register map and reset values

x
0
0
0
0
0
0
0
0
0
0

Res. RESET RESETM 10

The table below provides the USB register map and reset values.

EP
EP
EP
EP
EP
EP
EP
EP

[1:0]
[1:0]
[1:0]
[1:0]
[1:0]
[1:0]
[1:0]
[1:0]

x
0
0
0
0
0
0
0
0
0
0

Res. SOF SOFM

TYPE
TYPE
TYPE
TYPE
TYPE
TYPE
TYPE
TYPE

x
0
0
0
0
0
0
0
0
0
0

Res. ESOF ESOFM EP_KIND EP_KIND EP_KIND EP_KIND EP_KIND EP_KIND EP_KIND EP_KIND 8

x
0
0
0
0
0
0
0
0
0
0

0
L1REQ L1REQM CTR_TX CTR_TX CTR_TX CTR_TX CTR_TX CTR_TX CTR_TX CTR_TX

EF
7

x
0
0
0
0
0
0
0
0

0
Res. Res. DTOG_TX DTOG_TX DTOG_TX DTOG_TX DTOG_TX DTOG_TX DTOG_TX DTOG_TX 6

x
0
0
0
0
0
0
0
0
0

0
Res. L1RESUME 5

TX
TX
TX
TX
TX
TX
TX
TX

[1:0]
[1:0]
[1:0]
[1:0]
[1:0]
[1:0]
[1:0]
[1:0]

x
FN[10:0]
0
0
0
0
0
0
0
0
0
0

0
DIR RESUME

STAT_
STAT_
STAT_
STAT_
STAT_
STAT_
STAT_
STAT_

x
0
0
0
0
0
0
0
0
0
0

0
FSUSP 3

x
0
0
0
0
0
0
0
0
0
0

0
ADD[6:0]
LP_MODE 2

x
0
1
0
0
0
0
0
0
0
0

0
PDWN EA[3:0] 1
EA[3:0]
EA[3:0]
EA[3:0]
EA[3:0]
EA[3:0]
EA[3:0]
EA[3:0]

EP_ID[3:0]

x
0
1
0
0
0
0
0
0
0
0

0
FRES
Universal serial bus full-speed device interface (USB)

703/775
0

704
 0x58
0x54
0x50
Offset

704/775
Register

Reset value

Reset value
Reset value

USB_BCDR
USB_BTABLE

USB_LPMCSR
Res. Res. Res. 31
Res. Res. Res. 30
Res. Res. Res. 29
Res. Res. Res. 28
Res. Res. Res. 27
Res. Res. Res. 26
Res. Res. Res. 25
Res. Res. Res. 24
Res. Res. Res. 23
Res. Res. Res. 22
Res. Res. Res. 21
Res. Res. Res. 20
Res. Res. Res. 19
Res. Res. Res. 18
Universal serial bus full-speed device interface (USB)

Res. Res. Res.

RM0360 Rev 5
17
Res. Res. Res. 16
0
0

DPPU Res. 15
0

Res. Res. 14
0

Res. Res. 13
0

Res. Res. 12
0

Res. Res. 11
0

Res. Res. 10
0

Res. Res. 9
Refer to Section 2.2 on page 37 for the register boundary addresses.
0

Res. Res.
Table 108. USB register map and reset values (continued)

8
BTABLE[15:3]

0
0

PS2DET 7
0
0

SDET 6
0
0

PDET 5
BESL[3:0]

0
0

DCDET 4
0
0

SDEN REMWAKE 3
0

PDEN Res. Res. 2

0
0

DCDEN LPMACK Res. 1

0
0

BCDEN LPMEN Res.

RM0360

0
RM0360 Debug support (DBG)

26 Debug support (DBG)

26.1 Overview
The STM32F0x0 devices are built around a Arm® Cortex®-M0 core, which contains
hardware extensions for advanced debugging features. The debug extensions allow the
core to be stopped either on a given instruction fetch (breakpoint) or data access
(watchpoint). When stopped, the core’s internal state and the system’s external state may
be examined. Once examination is complete, the core and the system may be restored and
program execution resumed.
The debug features are used by the debugger host when connecting to and debugging the
STM32F0x0 MCUs.
One interface for debug is available:
• Serial wire

Figure 267. Block diagram of STM32F0x0 MCU and Arm® Cortex®-M0-level debug
support

STM32 MCU debug support

Cortex-M0 debug support

Bus matrix System

interface
Cortex-M0
Core

Debug AP

Bridge DBGMCU
SWDIO SW-DP
SWCLK Debug AP
NVIC

DWT

BPU

MS19240V2

1. The debug features embedded in the Arm® Cortex®-M0 core are a subset of the Arm CoreSight Design Kit.

RM0360 Rev 5 705/775

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The Arm Arm® Cortex®-M0 core provides integrated on-chip debug support. It is comprised
of:
• SW-DP: Serial wire
• BPU: Break point unit
• DWT: Data watchpoint trigger
It also includes debug features dedicated to the STM32F0x0:
• Flexible debug pinout assignment
• MCU debug box (support for low-power modes, control over peripheral clocks, etc.)
Note: For further information on debug functionality supported by the Arm Arm® Cortex®-M0 core,
refer to the Arm® Cortex®-M0 Technical Reference Manual (see Section 26.2: Reference
Arm documentation).

26.2 Reference Arm documentation

• Arm® Cortex®-M0 Technical Reference Manual (TRM)
It is available from:
http://infocenter.arm.com
• Arm Debug Interface V5
• Arm CoreSight Design Kit revision r1p1 Technical Reference Manual

26.3 Pinout and debug port pins

The STM32F0x0 MCUs are available in various packages with different numbers of
available pins.

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26.3.1 SWD port pins

Two pins are used as outputs for the SW-DP as alternate functions of general purpose I/Os.
These pins are available on all packages.

Table 109. SW debug port pins

SW debug port
Pin
SW-DP pin name
assignment
Type Debug assignment

SWDIO IO Serial Wire Data Input/Output PA13

SWCLK I Serial Wire Clock PA14

26.3.2 SW-DP pin assignment

After reset (SYSRESETn or PORESETn), the pins used for the SW-DP are assigned as
dedicated pins, immediately usable by the debugger host.
However, the MCU offers the possibility to disable the SWD port and can then release the
associated pins for general-purpose I/O (GPIO) usage. For more details on how to disable
SW-DP port pins, refer to Section 8.3.2: I/O pin alternate function multiplexer and mapping
on page 127.

26.3.3 Internal pull-up and pull-down on SWD pins

Once the SW I/O is released by the user software, the GPIO controller takes control of these
pins. The reset states of the GPIO control registers put the I/Os in the equivalent states:
• SWDIO: input pull-up
• SWCLK: input pull-down
Having embedded pull-up and pull-down resistors removes the need to add external
resistors.

26.4 ID codes and locking mechanism

There are several ID codes inside the MCU. ST strongly recommends the tool
manufacturers (for example Keil, IAR, Raisonance) to lock their debugger using the MCU
device ID located at address 0x40015800.
Only the DEV_ID[15:0] should be used for identification by the debugger/programmer tools
(the revision ID must not be taken into account).

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26.4.1 MCU device ID code

The STM32F0xx products integrate an MCU ID code. This ID identifies the ST MCU part
number and the die revision.
This code is accessible by the software debug port (two pins) or by the user software.
For code example refer to the Appendix section A.10.1: DBG read device ID.

DBGMCU_IDCODE
Address: 0x40015800
Only 32-bit access supported. Read-only

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REV_ID
r r r r r r r r r r r r r r r r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. DEV_ID
r r r r r r r r r r r r

Bits 31:16 REV_ID[15:0] Revision identifier

This field indicates the revision of the device. Refer to Table 115.
Bits 15:12 Reserved: read 0b0110.
Bits 11:0 DEV_ID[11:0]: Device identifier
This field indicates the device ID. Refer to Table 115.

Table 110. DEV_ID and REV_ID field values

Device DEV_ID Revision code Revision number REV_ID

STM32F030x4
0x444 A or 1 1.0 0x1000
STM32F030x6
STM32F070x6 0x445 A 1.0 0x1000
B or 1 1.1 0x1001
STM32F030x8 0x440
Z 1.2 0x1003
Y or 1 2.1 0x2001
STM32F070xB 0x448
W 2.2 0x2003
STM32F030xC 0x442 A 1.0 0x1000

26.5 SWD port

26.5.1 SWD protocol introduction

This synchronous serial protocol uses two pins:
• SWCLK: clock from host to target
• SWDIO: bidirectional

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RM0360 Debug support (DBG)

The protocol allows two banks of registers (DPACC registers and APACC registers) to be
read and written to.
Bits are transferred LSB-first on the wire.
For SWDIO bidirectional management, the line must be pulled-up on the board (100 kΩ
recommended by Arm).
Each time the direction of SWDIO changes in the protocol, a turnaround time is inserted
where the line is not driven by the host nor the target. By default, this turnaround time is one
bit time, however this can be adjusted by configuring the SWCLK frequency.

26.5.2 SWD protocol sequence

Each sequence consist of three phases:
1. Packet request (8 bits) transmitted by the host
2. Acknowledge response (3 bits) transmitted by the target
3. Data transfer phase (33 bits) transmitted by the host or the target

Table 111. Packet request (8-bits)

Bit Name Description

0 Start Must be “1”

0: DP Access
1 APnDP
1: AP Access
0: Write Request
2 RnW
1: Read Request
Address field of the DP or AP registers (refer to Table 115 on
4:3 A[3:2]
page 712)
5 Parity Single bit parity of preceding bits
6 Stop 0
Not driven by the host. Must be read as “1” by the target
7 Park
because of the pull-up

Refer to the Arm® Cortex®-M0 TRM for a detailed description of DPACC and APACC
registers.
The packet request is always followed by the turnaround time (default 1 bit) where neither
the host nor target drive the line.

Table 112. ACK response (3 bits)

Bit Name Description

001: FAULT
0..2 ACK 010: WAIT
100: OK

The ACK Response must be followed by a turnaround time only if it is a READ transaction
or if a WAIT or FAULT acknowledge has been received.

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Table 113. DATA transfer (33 bits)

Bit Name Description

WDATA or
0..31 Write or Read data
RDATA
32 Parity Single parity of the 32 data bits

The DATA transfer must be followed by a turnaround time only if it is a READ transaction.

26.5.3 SW-DP state machine (reset, idle states, ID code)

The State Machine of the SW-DP has an internal ID code which identifies the SW-DP. It
follows the JEP-106 standard. This ID code is the default Arm one and is set to
0x0BB11477 (corresponding to Arm® Cortex®-M0).
Note: Note that the SW-DP state machine is inactive until the target reads this ID code.
• The SW-DP state machine is in RESET STATE either after power-on reset, or after the
line is high for more than 50 cycles
• The SW-DP state machine is in IDLE STATE if the line is low for at least two cycles
after RESET state.
• After RESET state, it is mandatory to first enter into an IDLE state AND to perform a
READ access of the DP-SW ID CODE register. Otherwise, the target will issue a
FAULT acknowledge response on another transactions.
Further details of the SW-DP state machine can be found in the Arm® Cortex®-M0 TRM and
the CoreSight Design Kit r1p0 TRM.

26.5.4 DP and AP read/write accesses

• Read accesses to the DP are not posted: the target response can be immediate (if
ACK=OK) or can be delayed (if ACK=WAIT).
• Read accesses to the AP are posted. This means that the result of the access is
returned on the next transfer. If the next access to be done is NOT an AP access, then
the DP-RDBUFF register must be read to obtain the result.
The READOK flag of the DP-CTRL/STAT register is updated on every AP read access
or RDBUFF read request to know if the AP read access was successful.
• The SW-DP implements a write buffer (for both DP or AP writes), that enables it to
accept a write operation even when other transactions are still outstanding. If the write
buffer is full, the target acknowledge response is “WAIT”. With the exception of
IDCODE read or CTRL/STAT read or ABORT write which are accepted even if the write
buffer is full.
• Because of the asynchronous clock domains SWCLK and HCLK, two extra SWCLK
cycles are needed after a write transaction (after the parity bit) to make the write
effective internally. These cycles should be applied while driving the line low (IDLE
state)
This is particularly important when writing the CTRL/STAT for a power-up request. If the
next transaction (requiring a power-up) occurs immediately, it will fail.

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RM0360 Debug support (DBG)

26.5.5 SW-DP registers

Access to these registers are initiated when APnDP=0

Table 114. SW-DP registers

CTRLSEL bit
A[3:2] R/W of SELECT Register Notes
register

The manufacturer code is set to the default

00 Read IDCODE Arm code for Cortex-M0:
0x0BB11477 (identifies the SW-DP)
00 Write ABORT
Purpose is to:
– request a system or debug power-up
– configure the transfer operation for AP
accesses
01 Read/Write 0 DP-CTRL/STAT
– control the pushed compare and pushed
verify operations.
– read some status flags (overrun, power-up
acknowledges)
Purpose is to configure the physical serial
WIRE
01 Read/Write 1 port protocol (like the duration of the
CONTROL
turnaround time)
Enables recovery of the read data from a
READ
10 Read corrupted debugger transfer, without
RESEND
repeating the original AP transfer.
The purpose is to select the current access
10 Write SELECT
port and the active 4-words register window
This read buffer is useful because AP
accesses are posted (the result of a read AP
request is available on the next AP
11 Read/Write READ BUFFER transaction).
This read buffer captures data from the AP,
presented as the result of a previous read,
without initiating a new transaction

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26.5.6 SW-AP registers

Access to these registers are initiated when APnDP=1
There are many AP Registers addressed as the combination of:
• The shifted value A[3:2]
• The current value of the DP SELECT register.

Table 115. 32-bit debug port registers addressed through the shifted value A[3:2]
Address A[3:2] value Description

0x0 00 Reserved, must be kept at reset value.

DP CTRL/STAT register. Used to:
– Request a system or debug power-up
0x4 01 – Configure the transfer operation for AP accesses
– Control the pushed compare and pushed verify operations.
– Read some status flags (overrun, power-up acknowledges)
DP SELECT register: Used to select the current access port and the
active 4-words register window.
– Bits 31:24: APSEL: select the current AP
0x8 10 – Bits 23:8: reserved
– Bits 7:4: APBANKSEL: select the active 4-words register window on the
current AP
– Bits 3:0: reserved
DP RDBUFF register: Used to allow the debugger to get the final result
0xC 11 after a sequence of operations (without requesting new JTAG-DP
operation)

26.6 Core debug

Core debug is accessed through the core debug registers. Debug access to these registers
is by means of the debug access port. It consists of four registers:

Table 116. Core debug registers

Register Description

The 32-bit Debug Halting Control and Status Register

DHCSR This provides status information about the state of the processor enable core debug
halt and step the processor
The 17-bit Debug Core Register Selector Register:
DCRSR
This selects the processor register to transfer data to or from.
The 32-bit Debug Core Register Data Register:
DCRDR This holds data for reading and writing registers to and from the processor selected
by the DCRSR (Selector) register.
The 32-bit Debug Exception and Monitor Control Register:
DEMCR
This provides Vector Catching and Debug Monitor Control.

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These registers are not reset by a system reset. They are only reset by a power-on reset.
Refer to the Arm® Cortex®-M0 TRM for further details.
To Halt on reset, it is necessary to:
• enable the bit0 (VC_CORRESET) of the Debug and Exception Monitor Control
Register
• enable the bit0 (C_DEBUGEN) of the Debug Halting Control and Status Register

26.7 BPU (Break Point Unit)

The Cortex-M0 BPU implementation provides four breakpoint registers. The BPU is a
subset of the Flash Patch and Breakpoint (FPB) block available in Armv7-M (Cortex-M3 &
Cortex-M4).

26.7.1 BPU functionality

The processor breakpoints implement PC based breakpoint functionality.
Refer to the Armv6-M Arm and the Arm CoreSight Components Technical Reference
Manual for more information about the BPU CoreSight identification registers, and their
addresses and access types.

26.8 DWT (Data Watchpoint)

The Cortex-M0 DWT implementation provides two watchpoint register sets.

26.8.1 DWT functionality

The processor watchpoints implement both data address and PC based watchpoint
functionality, a PC sampling register, and support comparator address masking, as
described in the Armv6-M Arm.

26.8.2 DWT Program Counter Sample Register

A processor that implements the data watchpoint unit also implements the Armv6-M
optional DWT Program Counter Sample Register (DWT_PCSR). This register permits a
debugger to periodically sample the PC without halting the processor. This provides coarse
grained profiling. See the ARMv6-M Arm for more information.
The Cortex-M0 DWT_PCSR records both instructions that pass their condition codes and
those that fail.

26.9 MCU debug component (DBGMCU)

The MCU debug component helps the debugger provide support for:
• Low-power modes
• Clock control for timers, watchdog and I2C during a breakpoint

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26.9.1 Debug support for low-power modes

To enter low-power mode, the instruction WFI or WFE must be executed.
The MCU implements several low-power modes which can either deactivate the CPU clock
or reduce the power of the CPU.
The core does not allow FCLK or HCLK to be turned off during a debug session. As these
are required for the debugger connection, during a debug, they must remain active. The
MCU integrates special means to allow the user to debug software in low-power modes.
For this, the debugger host must first set some debug configuration registers to change the
low-power mode behavior:
• In Sleep mode: FCLK and HCLK are still active. Consequently, this mode does not
impose any restrictions on the standard debug features.
• In Stop/Standby mode, the DBG_STOP bit must be previously set by the debugger.
This enables the internal RC oscillator clock to feed FCLK and HCLK in Stop mode.
For code example refer to the Appendix section A.10.2: DBG debug in Low-power mode.

26.9.2 Debug support for timers, watchdog and I2C

During a breakpoint, it is necessary to choose how the counter of timers and watchdog
should behave:
• They can continue to count inside a breakpoint. This is usually required when a PWM is
controlling a motor, for example.
• They can stop to count inside a breakpoint. This is required for watchdog purposes.
For the I2C, the user can choose to block the SMBUS timeout during a breakpoint.

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26.9.3 Debug MCU configuration register (DBGMCU_CR)

This register allows the configuration of the MCU under DEBUG. This concerns:
• Low-power mode support
This DBGMCU_CR is mapped at address 0x4001 5804.
It is asynchronously reset by the PORESET (and not the system reset). It can be written by
the debugger under system reset.
If the debugger host does not support these features, it is still possible for the user software
to write to these registers.
Address: 0x40015804
Only 32-bit access supported
POR Reset: 0x0000 0000 (not reset by system reset)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBG_
DBG_
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. STAND Res.
STOP
BY
rw rw

Bits 31:3 Reserved, must be kept at reset value.

Bit 2 DBG_STANDBY: Debug Standby mode
0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered.
From software point of view, exiting from Standby is identical than fetching reset vector
(except a few status bit indicated that the MCU is resuming from Standby)
1: (FCLK=On, HCLK=On) In this case, the digital part is not unpowered and FCLK and
HCLK are provided by the internal RC oscillator which remains active. In addition, the MCU
generate a system reset during Standby mode so that exiting from Standby is identical than
fetching from reset
Bit 1 DBG_STOP: Debug Stop mode
0: (FCLK=Off, HCLK=Off) In STOP mode, the clock controller disables all clocks (including
HCLK and FCLK). When exiting from STOP mode, the clock configuration is identical to the
one after RESET (CPU clocked by the 8 MHz internal RC oscillator (HSI)). Consequently,
the software must reprogram the clock controller to enable the PLL, the Xtal, etc.
1: (FCLK=On, HCLK=On) In this case, when entering STOP mode, FCLK and HCLK are
provided by the internal RC oscillator which remains active in STOP mode. When exiting
STOP mode, the software must reprogram the clock controller to enable the PLL, the Xtal,
etc. (in the same way it would do in case of DBG_STOP=0)

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26.9.4 Debug MCU APB1 freeze register (DBGMCU_APB1_FZ)

The DBGMCU_APB1_FZ register is used to configure the MCU under DEBUG. It concerns
some APB peripherals:
• Timer clock counter freeze
• I2C SMBUS timeout freeze
• System window watchdog and independent watchdog counter freeze support
This DBGMCU_APB1_FZ is mapped at address 0x4001 5808.
The register is asynchronously reset by the POR (and not the system reset). It can be
written by the debugger under system reset.
Address offset: 0x08
Only 32-bit access are supported.
Power on reset (POR): 0x0000 0000 (not reset by system reset)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

DBG_I2C1_SMBUS_TIMEOUT
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBG_WWDG_STOP

DBG_TIM14_STOP
DBG_IWDG_STOP

DBG_TIM7_STOP

DBG_TIM6_STOP

DBG_TIM3_STOP
DBG_RTC_STOP

Res. Res. Res. Res. Res. Res. Res. Res. Res.

rw rw rw rw rw rw rw

Bits 31:22 Reserved, must be kept at reset value.

Bit 21 DBG_I2C1_SMBUS_TIMEOUT: SMBUS timeout mode stopped when core is halted
0: Same behavior as in normal mode
1: The SMBUS timeout is frozen
Bits 20:13 Reserved, must be kept at reset value.
Bit 12 DBG_IWDG_STOP: Debug independent watchdog stopped when core is halted
0: The independent watchdog counter clock continues even if the core is halted
1: The independent watchdog counter clock is stopped when the core is halted
Bit 11 DBG_WWDG_STOP: Debug window watchdog stopped when core is halted
0: The window watchdog counter clock continues even if the core is halted
1: The window watchdog counter clock is stopped when the core is halted

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Bit 10 DBG_RTC_STOP: Debug RTC stopped when core is halted

0: The clock of the RTC counter is fed even if the core is halted
1: The clock of the RTC counter is stopped when the core is halted
Bit 9 Reserved, must be kept at reset value.
Bit 8 DBG_TIM14_STOP: TIM14 counter stopped when core is halted
0: The counter clock of TIM14 is fed even if the core is halted
1: The counter clock of TIM14 is stopped when the core is halted
Bits 7:6 Reserved, must be kept at reset value.
Bit 5 DBG_TIM7_STOP: TIM7 counter stopped when core is halted.
0: The counter clock of TIM7 is fed even if the core is halted
1: The counter clock of TIM7 is stopped when the core is halted
Bit 4 DBG_TIM6_STOP: TIM6 counter stopped when core is halted
0: The counter clock of TIM6 is fed even if the core is halted
1: The counter clock of TIM6 is stopped when the core is halted
Bits 3:2 Reserved, must be kept at reset value.
Bit 1 DBG_TIM3_STOP: TIM3 counter stopped when core is halted
0: The counter clock of TIM3 is fed even if the core is halted
1: The counter clock of TIM3 is stopped when the core is halted
Bit 0 Reserved, must be kept at reset value.

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26.9.5 Debug MCU APB2 freeze register (DBGMCU_APB2_FZ)

The DBGMCU_APB2_FZ register is used to configure the MCU under DEBUG. It concerns
some APB peripherals:
• Timer clock counter freeze
This register is mapped at address 0x4001580C.
It is asynchronously reset by the POR (and not the system reset). It can be written by the
debugger under system reset.
Address offset: 0x0C
Only 32-bit access is supported.
POR: 0x0000 0000 (not reset by system reset)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

DBG_TIM17_STOP

DBG_TIM16_STOP

DBG_TIM15_STOP
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBG_TIM1_STOP

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

rw

Bits 31:19 Reserved, must be kept at reset value.

Bit 18 DBG_TIM17_STOP: TIM17 counter stopped when core is halted
0: The counter clock of TIM17 is fed even if the core is halted
1: The counter clock of TIM17 is stopped when the core is halted
Bit 17 DBG_TIM16_STOP: TIM16 counter stopped when core is halted
0: The counter clock of TIM16 is fed even if the core is halted
1: The counter clock of TIM16 is stopped when the core is halted
Bit 16 DBG_TIM15_STOP: TIM15 counter stopped when core is halted
0: The counter clock of TIM15 is fed even if the core is halted
1: The counter clock of TIM15 is stopped when the core is halted
Bits 15:12 Reserved, must be kept at reset value.
Bit 11 DBG_TIM1_STOP: TIM1 counter stopped when core is halted
0: The counter clock of TIM 1 is fed even if the core is halted
1: The counter clock of TIM 1 is stopped when the core is halted
Bits 0:10 Reserved, must be kept at reset value.

26.9.6 DBG register map

The following table summarizes the Debug registers.

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 0x4001580C 0x40015808 0x40015804 0x40015800

Addr.
RM0360

IDCODE

APB2_FZ
APB1_FZ

DBGMCU_
DBGMCU_
DBGMCU_
Register

Reset value
Reset value
Reset value
Reset value(1)

DBGMCU_CR
X
Res. Res. Res. 31

X
Res. Res. Res. 30

X
Res. Res. Res. 29
Res. Res. Res. X
X 28
Res. Res. Res. 27
X

Res. Res. Res. 26

X

Res. Res. Res. 25

Res. Res. Res. 24
Res. Res. Res. 23
REV_ID

Res. Res. Res. 22

0
X X X X

Res. DBG_I2C1_SMBUS_TIMEOUT Res. 21

X

Res. Res. Res. 20

X

Res. Res. Res. 19

0
X

DBG_TIM17_STOP Res. Res. 18

0
X

DBG_TIM16_STOP Res. Res.

RM0360 Rev 5
17

0
X

DBG_TIM15_STOP Res. Res. 16

Res. Res. Res. Res. 15
Res. Res. Res. Res. 14
Res. Res. Res. Res. 13
0
Res. DBG_IWDG_STOP Res. Res. 12

0
0
X

DBG_TIM1_STOP DBG_WWDG_STOP Res. 11

Table 117. DBG register map and reset values

0
X

Res. DBG_RTC_STOP Res. 10

X

Res. Res. Res. 9

0
X

Res. DBG_TIM14_STOP Res. 8

X

Res. Res. Res. 7

X

Res. Res. Res.

1. The reset value is product dependent. For more information, refer to Section 26.4.1: MCU device ID code.
6
0
X

Res. DBG_TIM7_STOP Res. 5

DEV_ID

0
X

Res. DBG_TIM6_STOP Res. 4

X

Res. Res. Res. 3

0
X

Res. Res. DBG_STANDBY 2

0
0
X

Res. DBG_TIM3_STOP DBG_STOP 1

0
X

Res. Res. Res. 0

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27 Device electronic signature

The device electronic signature is stored in the System memory area of the Flash memory
module, and can be read using the debug interface or by the CPU. It contains factory-
programmed identification and calibration data that allow the user firmware or other external
devices to automatically match to the characteristics of the STM32F0x0 microcontroller.

27.1 Flash memory size data register

Base address: 0x1FFF
Address offset: 0x00
Read only = 0xXXXX where X is factory-programmed

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FLASH_SIZE
r r r r r r r r r r r r r r r r

Bits 15:0 FLASH_SIZE[15:0]: Flash memory size

This bitfield indicates the size of the device Flash memory expressed in Kbytes.
As an example, 0x040 corresponds to 64 Kbytes.

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Appendix A Code examples

A.1 Introduction
This appendix shows the code examples of the sequences described in this document.
These code examples are extracted from the STM32F0xx Snippet firmware package
STM32SnippetsF0 available on www.st.com.
These code examples use the peripheral bit and register description from the CMSIS
header file (stm32f0xx.h).
Code lines starting with // should be uncommented if the given register has been modified
before.

A.2 FLASH operation code examples

A.2.1 Flash memory unlocking sequence

/* (1) Wait till no operation is on going */
/* (2) Check that the flash memory is unlocked */
/* (3) Perform unlock sequence */
while ((FLASH->SR & FLASH_SR_BSY) != 0) /* (1) */
{
/* For robust implementation, add here time-out management */
}
if ((FLASH->CR & FLASH_CR_LOCK) != 0) /* (2) */
{
FLASH->KEYR = FLASH_FKEY1; /* (3) */
FLASH->KEYR = FLASH_FKEY2;
}

A.2.2 Main flash memory programming sequence

/* (1) Set the PG bit in the FLASH_CR register to enable programming */
/* (2) Perform the data write (half-word) at the desired address */
/* (3) Wait until the BSY bit is reset in the FLASH_SR register */
/* (4) Check the EOP flag in the FLASH_SR register */
/* (5) clear it by software by writing it at 1 */
/* (6) Reset the PG Bit to disable programming */
FLASH->CR |= FLASH_CR_PG; /* (1) */
*(__IO uint16_t*)(flash_addr) = data; /* (2) */
while ((FLASH->SR & FLASH_SR_BSY) != 0) /* (3) */
{
/* For robust implementation, add here time-out management */
}

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if ((FLASH->SR & FLASH_SR_EOP) != 0) /* (4) */

{
FLASH->SR = FLASH_SR_EOP; /* (5) */
}
else
{
/* Manage the error cases */
}
FLASH->CR &= ~FLASH_CR_PG; /* (6) */

A.2.3 Page erase sequence

/* (1) Set the PER bit in the FLASH_CR register to enable page erasing */
/* (2) Program the FLASH_AR register to select a page to erase */
/* (3) Set the STRT bit in the FLASH_CR register to start the erasing */
/* (4) Wait until the BSY bit is reset in the FLASH_SR register */
/* (5) Check the EOP flag in the FLASH_SR register */
/* (6) Clear EOP flag by software by writing EOP at 1 */
/* (7) Reset the PER Bit to disable the page erase */
FLASH->CR |= FLASH_CR_PER; /* (1) */
FLASH->AR = page_addr; /* (2) */
FLASH->CR |= FLASH_CR_STRT; /* (3) */
while ((FLASH->SR & FLASH_SR_BSY) != 0) /* (4) */
{
/* For robust implementation, add here time-out management */
}
if ((FLASH->SR & FLASH_SR_EOP) != 0) /* (5) */
{
FLASH->SR = FLASH_SR_EOP; /* (6)*/
}
else
{
/* Manage the error cases */
}
FLASH->CR &= ~FLASH_CR_PER; /* (7) */

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A.2.4 Mass erase sequence

/* (1) Set the MER bit in the FLASH_CR register to enable mass erasing */
/* (2) Set the STRT bit in the FLASH_CR register to start the erasing */
/* (3) Wait until the BSY bit is reset in the FLASH_SR register */
/* (4) Check the EOP flag in the FLASH_SR register */
/* (5) Clear EOP flag by software by writing EOP at 1 */
/* (6) Reset the PER Bit to disable the mass erase */
FLASH->CR |= FLASH_CR_MER; /* (1) */
FLASH->CR |= FLASH_CR_STRT; /* (2) */
while ((FLASH->SR & FLASH_SR_BSY) != 0) /* (3) */
{
/* For robust implementation, add here time-out management */
}

if ((FLASH->SR & FLASH_SR_EOP) != 0) /* (4)*/

{
FLASH->SR = FLASH_SR_EOP; /* (5) */
}
else
{
/* Manage the error cases */
}
FLASH->CR &= ~FLASH_CR_MER; /* (6) */

A.2.5 Option byte unlocking sequence

/* (1) Wait till no operation is on going */

/* (2) Check that the flash memory is unlocked */
/* (3) Perform unlock sequence for flash memory */
/* (4) Check that the Option Bytes are unlocked */
/* (5) Perform unlock sequence for Option Bytes */
while ((FLASH->SR & FLASH_SR_BSY) != 0) /* (1) */
{
/* For robust implementation, add here time-out management */
}
if ((FLASH->CR & FLASH_CR_LOCK) != 0) /* (2) */
{
FLASH->KEYR = FLASH_FKEY1; /* (3) */
FLASH->KEYR = FLASH_FKEY2;
}
if ((FLASH->CR & FLASH_CR_OPTWRE) == 0) /* (4) */
{
FLASH->OPTKEYR = FLASH_OPTKEY1; /* (5) */
FLASH->OPTKEYR = FLASH_OPTKEY2;
}

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A.2.6 Option byte programming sequence

/* (1) Set the PG bit in the FLASH_CR register to enable programming */

/* (2) Perform the data write */
/* (3) Wait until the BSY bit is reset in the FLASH_SR register */
/* (4) Check the EOP flag in the FLASH_SR register */
/* (5) Clear the EOP flag by software by writing it at 1 */
/* (6) Reset the PG Bit to disable programming */
FLASH->CR |= FLASH_CR_OPTPG; /* (1) */
*opt_addr = data; /* (2) */
while ((FLASH->SR & FLASH_SR_BSY) != 0) /* (3) */
{
/* For robust implementation, add here time-out management */
}
if ((FLASH->SR & FLASH_SR_EOP) != 0) /* (4) */
{
FLASH->SR = FLASH_SR_EOP; /* (5) */
}
else
{
/* Manage the error cases */
}
FLASH->CR &= ~FLASH_CR_OPTPG; /* (6) */

A.2.7 Option byte erasing sequence

/* (1) Set the OPTER bit in the FLASH_CR register to enable option byte
erasing */
/* (2) Set the STRT bit in the FLASH_CR register to start the erasing */
/* (3) Wait until the BSY bit is reset in the FLASH_SR register */
/* (4) Check the EOP flag in the FLASH_SR register */
/* (5) Clear EOP flag by software by writing EOP at 1 */
/* (6) Reset the PER Bit to disable the page erase */
FLASH->CR |= FLASH_CR_OPTER; /* (1) */
FLASH->CR |= FLASH_CR_STRT; /* (2) */
while ((FLASH->SR & FLASH_SR_BSY) != 0) /* (3) */
{
/* For robust implementation, add here time-out management */
}
if ((FLASH->SR & FLASH_SR_EOP) != 0) /* (4) */
{
FLASH->SR = FLASH_SR_EOP; /* (5)*/
}
else
{
/* Manage the error cases */
}
FLASH->CR &= ~FLASH_CR_OPTER; /* (6) */

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A.3 Clock controller code examples

A.3.1 HSE start sequence

/**
* Description: This function enables the interrupt on HSE ready,
* and start the HSE as external clock.
*/
__INLINE void StartHSE(void)
{
/* Configure NVIC for RCC */
/* (1) Enable Interrupt on RCC */
/* (2) Set priority for RCC */
NVIC_EnableIRQ(RCC_CRS_IRQn); /* (1)*/
NVIC_SetPriority(RCC_CRS_IRQn,0); /* (2) */

/* (1) Enable interrupt on HSE ready */

/* (2) Enable the CSS
Enable the HSE and set HSEBYP to use the external clock
instead of an oscillator
Enable HSE */
/* Note : the clock is switched to HSE in the RCC_CRS_IRQHandler ISR */
RCC->CIR |= RCC_CIR_HSERDYIE; /* (1) */
RCC->CR |= RCC_CR_CSSON | RCC_CR_HSEBYP | RCC_CR_HSEON; /* (2) */
}

/**
* Description: This function handles RCC interrupt request
* and switch the system clock to HSE.
*/
void RCC_CRS_IRQHandler(void)
{
/* (1) Check the flag HSE ready */
/* (2) Clear the flag HSE ready */
/* (3) Switch the system clock to HSE */

if ((RCC->CIR & RCC_CIR_HSERDYF) != 0) /* (1) */

{
RCC->CIR |= RCC_CIR_HSERDYC; /* (2) */
RCC->CFGR = ((RCC->CFGR & (~RCC_CFGR_SW)) | RCC_CFGR_SW_0); /* (3) */
}
else
{
/* Report an error */
}
}

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A.3.2 PLL configuration modification

/* (1) Test if PLL is used as System clock */

/* (2) Select HSI as system clock */
/* (3) Wait for HSI switched */
/* (4) Disable the PLL */
/* (5) Wait until PLLRDY is cleared */
/* (6) Set the PLL multiplier to 6 */
/* (7) Enable the PLL */
/* (8) Wait until PLLRDY is set */
/* (9) Select PLL as system clock */
/* (10) Wait until the PLL is switched on */
if ((RCC->CFGR & RCC_CFGR_SWS) == RCC_CFGR_SWS_PLL) /* (1) */
{
RCC->CFGR &= (uint32_t) (~RCC_CFGR_SW); /* (2) */
while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_HSI) /* (3) */
{
/* For robust implementation, add here time-out management */
}
}
RCC->CR &= (uint32_t)(~RCC_CR_PLLON);/* (4) */
while((RCC->CR & RCC_CR_PLLRDY) != 0) /* (5) */
{
/* For robust implementation, add here time-out management */
}
RCC->CFGR = RCC->CFGR & (~RCC_CFGR_PLLMUL) | (RCC_CFGR_PLLMUL6); /* (6) */
RCC->CR |= RCC_CR_PLLON; /* (7) */
while((RCC->CR & RCC_CR_PLLRDY) == 0) /* (8) */
{
/* For robust implementation, add here time-out management */
}
RCC->CFGR |= (uint32_t) (RCC_CFGR_SW_PLL); /* (9) */
while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_PLL) /* (10) */
{
/* For robust implementation, add here time-out management */
}

A.3.3 MCO selection

/* Select system clock to be output on the MCO without prescaler */

RCC->CFGR |= RCC_CFGR_MCO_SYSCLK;

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A.3.4 Clock measurement configuration with TIM14

/**
* Description: This function configures the TIM14 as input capture
* and enables the interrupt on TIM14
*/
__INLINE void ConfigureTIM14asInputCapture(void)
{
/* (1) Enable the peripheral clock of Timer 14 */
/* (2) Select the active input TI1,Program the input filter, and prescaler
*/
/* (3) Enable interrupt on Capture/Compare */
RCC->APB1ENR |= RCC_APB1ENR_TIM14EN; /* (1) */
TIM14->CCMR1 |= TIM_CCMR1_IC1F_0 | TIM_CCMR1_IC1F_1 \
| TIM_CCMR1_CC1S_0 | TIM_CCMR1_IC1PSC_1; /* (2)*/
TIM14->DIER |= TIM_DIER_CC1IE; /* (3) */

/* Configure NVIC for TIM14 */

/* (4) Enable Interrupt on TIM14 */
/* (5) Set priority for TIM14 */
NVIC_EnableIRQ(TIM14_IRQn); /* (4) */
NVIC_SetPriority(TIM14_IRQn,0); /* (5) */

/* (6) Select HSE/32 as input on TI1 */

/* (7) Enable counter */
/* (8) Enable capture */
TIM14->OR |= TIM14_OR_TI1_RMP_1; /* (6) */
TIM14->CR1 |= TIM_CR1_CEN; /* (7) */
TIM14->CCER |= TIM_CCER_CC1E; /* (8) */
}
Note: The measurement is done in the TIM14 interrupt subroutine.

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A.4 GPIO code examples

A.4.1 Lock sequence

/**
* Description: This function locks the targeted pins of Port A
configuration
This function can be easily modified to lock Port B
* Parameter: lock contains the port pin mask to be locked
*/
void LockGPIOA(uint16_t lock)
{
/* (1) Write LCKK bit to 1 and set the pin bits to lock */
/* (2) Write LCKK bit to 0 and set the pin bits to lock */
/* (3) Write LCKK bit to 1 and set the pin bits to lock */
/* (4) Read the Lock register */
/* (5) Check the Lock register (optionnal) */
GPIOA->LCKR = GPIO_LCKR_LCKK + lock; /* (1) */
GPIOA->LCKR = lock; /* (2) */
GPIOA->LCKR = GPIO_LCKR_LCKK + lock; /* (3) */
GPIOA->LCKR; /* (4) */
if ((GPIOA->LCKR & GPIO_LCKR_LCKK) == 0) /* (5) */
{
/* Manage an error */
}
}

A.4.2 Alternate function selection sequence

/* This sequence select AF2 for GPIOA4, 8 and 9. This can be easily adapted
with another port by changing all GPIOA references by another GPIO port,
and the alternate function number can be changed by replacing 0x04 or
0x02 for
each pin by the targeted alternate function in the 2 last code lines. */
/* (1) Enable the peripheral clock of GPIOA */
/* (2) Select alternate function mode on GPIOA pin 4, 8 and 9 */
/* (3) Select AF4 on PA4 in AFRL for TIM14_CH1 */
/* (4) Select AF2 on PA8 and PA9 in AFRH for TIM1_CH1 and TIM1_CH2 */
RCC->AHBENR |= RCC_AHBENR_GPIOAEN; /* (1) */
GPIOA->MODER = (GPIOA->MODER & ~(GPIO_MODER_MODER4 | GPIO_MODER_MODER8
| GPIO_MODER_MODER9)) | GPIO_MODER_MODER4_1
| GPIO_MODER_MODER8_1 | GPIO_MODER_MODER9_1; /* (2) */
GPIOA->AFR[0] |= 0x04 << GPIO_AFRL_AFRL4_Pos; /* (3) */
GPIOA->AFR[1] |= (0x02 << GPIO_AFRL_AFRH8_Pos) | (0x02 <<
GPIO_AFRL_AFRH9_Pos); /* (4) */

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A.4.3 Analog GPIO configuration

/* (1) Enable the peripheral clock of GPIOA, GPIOB and GPIOC */

/* (2) Select analog mode for PA1 */
/* (3) Select analog mode for PB1 */
/* (4) Select analog mode for PC0 */
RCC->AHBENR |= RCC_AHBENR_GPIOAEN | RCC_AHBENR_GPIOBEN
| RCC_AHBENR_GPIOCEN; /* (1) */
GPIOA->MODER |= GPIO_MODER_MODER1; /* (2) */
GPIOB->MODER |= GPIO_MODER_MODER1; /* (3) */
GPIOC->MODER |= GPIO_MODER_MODER0; /* (4) */

A.5 DMA code examples

A.5.1 DMA channel configuration sequence

/* The following example is given for the ADC. It can be easily ported on
any peripheral supporting DMA transfer taking of the associated channel
to the peripheral, this must check in the datasheet. */
/* (1) Enable the peripheral clock on DMA */
/* (2) Enable DMA transfer on ADC */
/* (3) Configure the peripheral data register address */
/* (4) Configure the memory address */
/* (5) Configure the number of DMA transfer to be performs on channel 1 */
/* (6) Configure increment, size and interrupts */
/* (7) Enable DMA Channel 1 */
RCC->AHBENR |= RCC_AHBENR_DMA1EN; /* (1) */
ADC1->CFGR1 |= ADC_CFGR1_DMAEN; /* (2) */
DMA1_Channel1->CPAR = (uint32_t) (&(ADC1->DR)); /* (3) */
DMA1_Channel1->CMAR = (uint32_t)(ADC_array); /* (4) */
DMA1_Channel1->CNDTR = 3; /* (5) */
DMA1_Channel1->CCR |= DMA_CCR_MINC | DMA_CCR_MSIZE_0 | DMA_CCR_PSIZE_0
| DMA_CCR_TEIE | DMA_CCR_TCIE ; /* (6) */
DMA1_Channel1->CCR |= DMA_CCR_EN; /* (7) */
/* Configure NVIC for DMA */
/* (1) Enable Interrupt on DMA Channel 1 */
/* (2) Set priority for DMA Channel 1 */
NVIC_EnableIRQ(DMA1_Channel1_IRQn); /* (1) */
NVIC_SetPriority(DMA1_Channel1_IRQn,0); /* (2) */

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A.6 Interrupts and event code examples

A.6.1 NVIC initialization

/* (1) Enable Interrupt on ADC */

/* (2) Set priority for ADC to 2*/
NVIC_EnableIRQ(ADC1_IRQn); /* (1) */
NVIC_SetPriority(ADC1_IRQn,2); /* (2) */

A.6.2 External interrupt selection

/* (1) Enable the peripheral clock of GPIOA */

/* (2) Select Port A for pin 0 external interrupt by writing 0000 in
EXTI0 (reset value)*/
/* (3) Configure the corresponding mask bit in the EXTI_IMR register */
/* (4) Configure the Trigger Selection bits of the Interrupt line on
rising edge*/
/* (5) Configure the Trigger Selection bits of the Interrupt line on
falling edge*/
RCC->AHBENR |= RCC_AHBENR_GPIOAEN; /* (1) */
//SYSCFG->EXTICR[1] &= (uint16_t)~SYSCFG_EXTICR1_EXTI0_PA; /* (2) */
EXTI->IMR = 0x0001; /* (3) */
EXTI->RTSR = 0x0001; /* (4) */
EXTI->FTSR = 0x0001; /* (5) */
/* Configure NVIC for External Interrupt */
/* (1) Enable Interrupt on EXTI0_1 */
/* (2) Set priority for EXTI0_1 */
NVIC_EnableIRQ(EXTI0_1_IRQn); /* (1) */
NVIC_SetPriority(EXTI0_1_IRQn,0); /* (2) */

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A.7 ADC code examples

A.7.1 ADC calibration

/* (1) Ensure that ADEN = 0 */

/* (2) Clear ADEN by setting ADDIS*/
/* (3) Clear DMAEN */
/* (4) Launch the calibration by setting ADCAL */
/* (5) Wait until ADCAL=0 */
if ((ADC1->CR & ADC_CR_ADEN) != 0) /* (1) */
{
ADC1->CR |= ADC_CR_ADDIS; /* (2) */
}
while ((ADC1->CR & ADC_CR_ADEN) != 0)
{
/* For robust implementation, add here time-out management */
}
ADC1->CFGR1 &= ~ADC_CFGR1_DMAEN; /* (3) */
ADC1->CR |= ADC_CR_ADCAL; /* (4) */
while ((ADC1->CR & ADC_CR_ADCAL) != 0) /* (5) */
{
/* For robust implementation, add here time-out management */
}

A.7.2 ADC enable sequence

/* (1) Ensure that ADRDY = 0 */

/* (2) Clear ADRDY */
/* (3) Enable the ADC */
/* (4) Wait until ADC ready */
if ((ADC1->ISR & ADC_ISR_ADRDY) != 0) /* (1) */
{
ADC1->ISR |= ADC_CR_ADRDY; /* (2) */
}
ADC1->CR |= ADC_CR_ADEN; /* (3) */
while ((ADC1->ISR & ADC_ISR_ADRDY) == 0) /* (4) */
{
/* For robust implementation, add here time-out management */
}

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A.7.3 ADC disable sequence

/* (1) Stop any ongoing conversion */

/* (2) Wait until ADSTP is reset by hardware i.e. conversion is stopped */
/* (3) Disable the ADC */
/* (4) Wait until the ADC is fully disabled */
ADC1->CR |= ADC_CR_ADSTP; /* (1) */
while ((ADC1->CR & ADC_CR_ADSTP) != 0) /* (2) */
{
/* For robust implementation, add here time-out management */
}
ADC1->CR |= ADC_CR_ADDIS; /* (3) */
while ((ADC1->CR & ADC_CR_ADEN) != 0) /* (4) */
{
/* For robust implementation, add here time-out management */
}

A.7.4 ADC clock selection

/* This code selects the HSI14 as clock source. */

/* (1) Enable the peripheral clock of the ADC */
/* (2) Start HSI14 RC oscillator */
/* (3) Wait HSI14 is ready */
/* (4) Select HSI14 by writing 00 in CKMODE (reset value) */
RCC->APB2ENR |= RCC_APB2ENR_ADC1EN; /* (1) */
RCC->CR2 |= RCC_CR2_HSI14ON; /* (2) */
while ((RCC->CR2 & RCC_CR2_HSI14RDY) == 0) /* (3) */
{
/* For robust implementation, add here time-out management */
}
//ADC1->CFGR2 &= (~ADC_CFGR2_CKMODE); /* (4) */

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A.7.5 Single conversion sequence - software trigger

/* (1) Select HSI14 by writing 00 in CKMODE (reset value) */

/* (2) Select CHSEL0, CHSEL9, CHSEL10 andCHSEL17 for VRefInt */
/* (3) Select a sampling mode of 111 i.e. 239.5 ADC clk to be greater
than 17.1us */
/* (4) Wake-up the VREFINT (only for VBAT, Temp sensor and VRefInt) */
//ADC1->CFGR2 &= ~ADC_CFGR2_CKMODE; /* (1) */
ADC1->CHSELR = ADC_CHSELR_CHSEL0 | ADC_CHSELR_CHSEL9
| ADC_CHSELR_CHSEL10 | ADC_CHSELR_CHSEL17; /* (2) */
ADC1->SMPR |= ADC_SMPR_SMP_0 | ADC_SMPR_SMP_1 | ADC_SMPR_SMP_2; /* (3) */
ADC->CCR |= ADC_CCR_VREFEN; /* (4) */
while (1)
{
/* Performs the AD conversion */
ADC1->CR |= ADC_CR_ADSTART; /* Start the ADC conversion */
for (i=0; i < 4; i++)
{
while ((ADC1->ISR & ADC_ISR_EOC) == 0) /* Wait end of conversion */
{
/* For robust implementation, add here time-out management */
}
ADC_Result[i] = ADC1->DR; /* Store the ADC conversion result */
}
ADC1->CFGR1 ^= ADC_CFGR1_SCANDIR; /* Toggle the scan direction */
}

A.7.6 Continuous conversion sequence - software trigger

/* This code example configures the AD conversion in continuous mode and in

backward scan. It also enable the interrupts. */
/* (1) Select HSI14 by writing 00 in CKMODE (reset value) */
/* (2) Select the continuous mode and scanning direction */
/* (3) Select CHSEL1, CHSEL9, CHSEL10 and CHSEL17 */
/* (4) Select a sampling mode of 111 i.e. 239.5 ADC clk to be greater than
17.1us */
/* (5) Enable interrupts on EOC, EOSEQ and overrun */
/* (6) Wake-up the VREFINT (only for VBAT, Temp sensor and VRefInt) */
//ADC1->CFGR2 &= ~ADC_CFGR2_CKMODE; /* (1) */
ADC1->CFGR1 |= ADC_CFGR1_CONT | ADC_CFGR1_SCANDIR; /* (2) */
ADC1->CHSELR = ADC_CHSELR_CHSEL1 | ADC_CHSELR_CHSEL9
| ADC_CHSELR_CHSEL10 | ADC_CHSELR_CHSEL17; /* (3) */
ADC1->SMPR |= ADC_SMPR_SMP_0 | ADC_SMPR_SMP_1 | ADC_SMPR_SMP_2; /* (4) */
ADC1->IER = ADC_IER_EOCIE | ADC_IER_EOSEQIE | ADC_IER_OVRIE; /* (5) */
ADC->CCR |= ADC_CCR_VREFEN; /* (6) */

/* Configure NVIC for ADC */

/* (7) Enable Interrupt on ADC */
/* (8) Set priority for ADC */
NVIC_EnableIRQ(ADC1_IRQn); /* (7) */
NVIC_SetPriority(ADC1_IRQn,0); /* (8) */

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A.7.7 Single conversion sequence - hardware trigger

/* Configure the ADC, the ADC and its clock having previously been
enabled. */
/* (1) Select HSI14 by writing 00 in CKMODE (reset value) */
/* (2) Select the external trigger on falling edge and external trigger on
TIM15_TRGO */
/* (3) Select CHSEL0, 1, 2 and 3 */
//ADC1->CFGR2 &= ~ADC_CFGR2_CKMODE; /* (1) */
ADC1->CFGR1 |= ADC_CFGR1_EXTEN_0 | ADC_CFGR1_EXTSEL_2; /* (2) */
ADC1->CHSELR = ADC_CHSELR_CHSEL0 | ADC_CHSELR_CHSEL1
| ADC_CHSELR_CHSEL2 | ADC_CHSELR_CHSEL3; /* (3) */

A.7.8 Continuous conversion sequence - hardware trigger

/* (1) Select HSI14 by writing 00 in CKMODE (reset value) */

/* (2) Select the external trigger on TIM15_TRGO (EXTSEL = 100),falling
edge (EXTEN = 10), the continuous mode (CONT = 1)*/
/* (3) Select CHSEL0/1/2/3 */
/* (4) Enable interrupts on EOC, EOSEQ and overrun */
//ADC1->CFGR2 &= ~ADC_CFGR2_CKMODE; /* (1) */
ADC1->CFGR1 |= ADC_CFGR1_EXTEN_1 | ADC_CFGR1_EXTSEL_2
| ADC_CFGR1_CONT; /* (2) */
ADC1->CHSELR = ADC_CHSELR_CHSEL0 | ADC_CHSELR_CHSEL1
| ADC_CHSELR_CHSEL2 | ADC_CHSELR_CHSEL3; /* (3)*/
ADC1->IER = ADC_IER_EOCIE | ADC_IER_EOSEQIE | ADC_IER_OVRIE; /* (4) */

/* Configure NVIC for ADC */

/* (1) Enable Interrupt on ADC */
/* (2) Set priority for ADC */
NVIC_EnableIRQ(ADC1_IRQn); /* (1) */
NVIC_SetPriority(ADC1_IRQn,0); /* (2) */

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A.7.9 DMA one shot mode sequence

/* (1) Enable the peripheral clock on DMA */

/* (2) Enable DMA transfer on ADC - DMACFG is kept at 0
for one shot mode */
/* (3) Configure the peripheral data register address */
/* (4) Configure the memory address */
/* (5) Configure the number of DMA transfer to be performs
on DMA channel 1 */
/* (6) Configure increment, size and interrupts */
/* (7) Enable DMA Channel 1 */
RCC->AHBENR |= RCC_AHBENR_DMA1EN; /* (1) */
ADC1->CFGR1 |= ADC_CFGR1_DMAEN; /* (2) */
DMA1_Channel1->CPAR = (uint32_t) (&(ADC1->DR)); /* (3) */
DMA1_Channel1->CMAR = (uint32_t)(ADC_array); /* (4) */
DMA1_Channel1->CNDTR = NUMBER_OF_ADC_CHANNEL; /* (5) */
DMA1_Channel1->CCR |= DMA_CCR_MINC | DMA_CCR_MSIZE_0 | DMA_CCR_PSIZE_0
| DMA_CCR_TEIE | DMA_CCR_TCIE ; /* (6) */
DMA1_Channel1->CCR |= DMA_CCR_EN; /* (7) */

A.7.10 DMA circular mode sequence

/* (1)
Enable the peripheral clock on DMA */
/* (2)
Enable DMA transfer on ADC and circular mode */
/* (3)
Configure the peripheral data register address */
/* (4)
Configure the memory address */
/* (5)
Configure the number of DMA transfer to be performs
on DMA channel 1 */
/* (6) Configure increment, size, interrupts and circular mode */
/* (7) Enable DMA Channel 1 */
RCC->AHBENR |= RCC_AHBENR_DMA1EN; /* (1) */
ADC1->CFGR1 |= ADC_CFGR1_DMAEN | ADC_CFGR1_DMACFG; /* (2) */
DMA1_Channel1->CPAR = (uint32_t) (&(ADC1->DR)); /* (3) */
DMA1_Channel1->CMAR = (uint32_t)(ADC_array); /* (4) */
DMA1_Channel1->CNDTR = NUMBER_OF_ADC_CHANNEL; /* (5) */
DMA1_Channel1->CCR |= DMA_CCR_MINC | DMA_CCR_MSIZE_0 | DMA_CCR_PSIZE_0
| DMA_CCR_TEIE | DMA_CCR_CIRC; /* (6) */
DMA1_Channel1->CCR |= DMA_CCR_EN; /* (7) */

A.7.11 Wait mode sequence

/* (1) Select HSI14 by writing 00 in CKMODE (reset value) */

/* (2) Select the continuous mode and the wait mode */
/* (3) Select CHSEL1/2/3 */
ADC1->CFGR2 &= ~ADC_CFGR2_CKMODE; /* (1) */
ADC1->CFGR1 |= ADC_CFGR1_CONT | ADC_CFGR1_WAIT; /* (2) */
ADC1->CHSELR = ADC_CHSELR_CHSEL1 | ADC_CHSELR_CHSEL2
| ADC_CHSELR_CHSEL3; /* (3)*/
ADC1->CR |= ADC_CR_ADSTART; /* start the ADC conversions */

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A.7.12 Auto Off and no wait mode sequence

/* (1) Select HSI14 by writing 00 in CKMODE (reset value) */

/* (2) Select the external trigger on TIM15_TRGO and rising edge
and auto off */
/* (3) Select CHSEL1/2/3/4 */
/* (4) Enable interrupts on EOC, EOSEQ and overrun */
ADC1->CFGR2 &= ~ADC_CFGR2_CKMODE; /* (1) */
ADC1->CFGR1 |= ADC_CFGR1_EXTEN_1 | ADC_CFGR1_EXTSEL_2
| ADC_CFGR1_AUTOFF; /* (2) */
ADC1->CHSELR = ADC_CHSELR_CHSEL1 | ADC_CHSELR_CHSEL2
| ADC_CHSELR_CHSEL3 | ADC_CHSELR_CHSEL4; /* (3) */
ADC1->IER = ADC_IER_EOCIE | ADC_IER_EOSEQIE | ADC_IER_OVRIE; /* (4) */

A.7.13 Auto Off and wait mode sequence

/* (1) Select HSI14 by writing 00 in CKMODE (reset value) */

/* (2) Select the external trigger on TIM15_TRGO and falling edge,
the continuous mode, scanning direction and auto off */
/* (3) Select CHSEL1, CHSEL9, CHSEL10 and CHSEL17 */
/* (4) Enable interrupts on EOC, EOSEQ and overrun */
ADC1->CFGR2 &= ~ADC_CFGR2_CKMODE; /* (1) */
ADC1->CFGR1 |= ADC_CFGR1_EXTEN_0 | ADC_CFGR1_EXTSEL_2
| ADC_CFGR1_SCANDIR | ADC_CFGR1_AUTOFF; /* (2) */
ADC1->CHSELR = ADC_CHSELR_CHSEL1 | ADC_CHSELR_CHSEL2
| ADC_CHSELR_CHSEL3 | ADC_CHSELR_CHSEL4; /* (3) */
ADC1->IER = ADC_IER_EOCIE | ADC_IER_EOSEQIE | ADC_IER_OVRIE; /* (4) */

A.7.14 Analog watchdog

/* (1) Select the continuous mode

and configure the Analog watchdog to monitor only CH17 */
/* (2) Define analog watchdog range : 16b-MSW is the high limit
and 16b-LSW is the low limit */
/* (3) Enable interrupt on Analog Watchdog */
ADC1->CFGR1 |= ADC_CFGR1_CONT
| (17 << 26) | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL; /* (1) */
ADC1->TR = (vrefint_high << 16) + vrefint_low; /* (2)*/
ADC1->IER = ADC_IER_AWDIE; /* (3) */

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A.7.15 Temperature configuration

/* (1) Select CHSEL16 for temperature sensor */

/* (2) Select a sampling mode of 111 i.e. 239.5 ADC clk to be greater than
17.1us */
/* (3) Wake-up the Temperature sensor (only for VBAT, Temp sensor and
VRefInt) */
ADC1->CHSELR = ADC_CHSELR_CHSEL16; /* (1) */
ADC1->SMPR |= ADC_SMPR_SMP_0 | ADC_SMPR_SMP_1 | ADC_SMPR_SMP_2; /* (2) */
ADC->CCR |= ADC_CCR_TSEN; /* (3) */

A.7.16 Temperature computation

/* Temperature sensor calibration value address */

#define TEMP30_CAL_ADDR ((uint16_t*) ((uint32_t) 0x1FFFF7B8))
#define VDD_CALIB ((uint32_t) (3300))
#define VDD_APPLI ((uint32_t) (3000))
#define AVG_SLOPE ((uint32_t) (5336)) //AVG_SLOPE in ADC conversion step
(@3.3V)/°C multiplied by 1000 for precision on the division
int32_t temperature; /* will contain the temperature in degrees Celsius */
temperature = ((uint32_t) ADC1->DR * VDD_APPLI / VDD_CALIB)) * 1000
- ((uint32_t) *TEMP30_CAL_ADDR;
temperature = (temperature / AVG_SLOPE) + 30;

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A.8 Timers

A.8.1 Upcounter on TI2 rising edge

/* (1)
Enable the peripheral clock of Timer 1 */
/* (2)
Enable the peripheral clock of GPIOA */
/* (3)
Select Alternate function mode (10) on GPIOA pin 9 */
/* (4)
Select TIM1_CH2 on PA9 by enabling AF2 for pin 9 in GPIOA AFRH
register */
RCC->APB2ENR |= RCC_APB2ENR_TIM1EN; /* (1) */
RCC->AHBENR |= RCC_AHBENR_GPIOAEN; /* (2) */
GPIOA->MODER = (GPIOA->MODER & ~(GPIO_MODER_MODER9))
| (GPIO_MODER_MODER9_1); /* (3) */
GPIOA->AFR[1] |= 0x2 << ((9-8)*4); /* (4) */
/* (1) Configure channel 2 to detect rising edges on the TI2 input by
writing CC2S = ‘01’, and configure the input filter duration by
writing the IC2F[3:0] bits in the TIMx_CCMR1 register (if no filter
is needed, keep IC2F=0000).*/
/* (2) Select rising edge polarity by writing CC2P=0 in the TIMx_CCER
register (reset value). */
/* (3) Configure the timer in external clock mode 1 by writing SMS=111
Select TI2 as the trigger input source by writing TS=110
in the TIMx_SMCR register.*/
/* (4) Enable the counter by writing CEN=1 in the TIMx_CR1 register. */
TIMx->CCMR1 |= TIM_CCMR1_IC2F_0 | TIM_CCMR1_IC2F_1
| TIM_CCMR1_CC2S_0; /* (1) */
TIMx->CCER &= (uint16_t)(~TIM_CCER_CC2P); /* (2) */
TIMx->SMCR |= TIM_SMCR_SMS | TIM_SMCR_TS_2 | TIM_SMCR_TS_1; /* (3) */
TIMx->CR1 |= TIM_CR1_CEN; /* (4) */

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A.8.2 Up counter on each 2 ETR rising edges

/* (1)
Enable the peripheral clock of Timer 1 */
/* (2)
Enable the peripheral clock of GPIOA */
/* (3)
Select Alternate function mode (10) on GPIOA pin 12 */
/* (4)
Select TIM1_ETR on PA12 by enabling AF2 for pin 12 in GPIOA AFRH
register */
RCC->APB2ENR |= RCC_APB2ENR_TIM1EN; /* (1) */
RCC->AHBENR |= RCC_AHBENR_GPIOAEN; /* (2) */
GPIOA->MODER = (GPIOA->MODER & ~(GPIO_MODER_MODER12))
| (GPIO_MODER_MODER12_1); /* (3) */
GPIOA->AFR[1] |= 0x2 << ((12-8)*4); /* (4) */
/* (1) As no filter is needed in this example, write ETF[3:0]=0000
in the TIMx_SMCR register. Keep the reset value.
Set the prescaler by writing ETPS[1:0]=01 in the TIMx_SMCR
register.
Select rising edge detection on the ETR pin by writing ETP=0
in the TIMx_SMCR register. Keep the reset value.
Enable external clock mode 2 by writing ECE=1 in the TIMx_SMCR
register. */
/* (2) Enable the counter by writing CEN=1 in the TIMx_CR1 register. */
TIMx->SMCR |= TIM_SMCR_ETPS_0 | TIM_SMCR_ECE; /* (1) */
TIMx->CR1 |= TIM_CR1_CEN; /* (2) */

A.8.3 Input capture configuration

/* (1) Select the active input TI1 (CC1S = 01),

program the input filter for 8 clock cycles (IC1F = 0011),
select the rising edge on CC1 (CC1P = 0, reset value)
and prescaler at each valid transition (IC1PS = 00, reset value) */
/* (2) Enable capture by setting CC1E */
/* (3) Enable interrupt on Capture/Compare */
/* (4) Enable counter */
TIMx->CCMR1 |= TIM_CCMR1_CC1S_0
| TIM_CCMR1_IC1F_0 | TIM_CCMR1_IC1F_1; /* (1)*/
TIMx->CCER |= TIM_CCER_CC1E; /* (2) */
TIMx->DIER |= TIM_DIER_CC1IE; /* (3) */
TIMx->CR1 |= TIM_CR1_CEN; /* (4) */

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A.8.4 Input capture data management

This code must be inserted in the Timer interrupt subroutine.

if ((TIMx->SR & TIM_SR_CC1IF) != 0)
{
if ((TIMx->SR & TIM_SR_CC1OF) != 0) /* Check the overflow */
{
/* Overflow error management */
gap = 0; /* Reinitialize the laps computing */
TIMx->SR &= ~(TIM_SR_CC1OF | TIM_SR_CC1IF); /* Clear the flags */
return;
}
if (gap == 0) /* Test if it is the first rising edge */
{
counter0 = TIMx->CCR1; /* Read the capture counter which clears the
CC1ICF */
gap = 1; /* Indicate that the first rising edge has yet been detected */
}
else
{
counter1 = TIMx->CCR1; /* Read the capture counter which clears the
CC1ICF */
if (counter1 > counter0) /* Check capture counter overflow */
{
Counter = counter1 - counter0;
}
else
{
Counter = counter1 + 0xFFFF - counter0 + 1;
}
counter0 = counter1;
}
}
else
{
/* Unexpected Interrupt */
/* Manage an error for robust application */
}
Note: This code manages only a single counter overflow. To manage many counter overflows the
update interrupt must be enabled (UIE = 1) and properly managed.

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A.8.5 PWM input configuration

/* (1) Select the active input TI1 for TIMx_CCR1 (CC1S = 01),
select the active input TI1 for TIMx_CCR2 (CC2S = 10) */
/* (2) Select TI1FP1 as valid trigger input (TS = 101)
configure the slave mode in reset mode (SMS = 100) */
/* (3) Enable capture by setting CC1E and CC2E
select the rising edge on CC1 and CC1N (CC1P = 0 and CC1NP = 0, reset
value),
select the falling edge on CC2 (CC2P = 1). */
/* (4) Enable interrupt on Capture/Compare 1 */
/* (5) Enable counter */
TIMx->CCMR1 |= TIM_CCMR1_CC1S_0 | TIM_CCMR1_CC2S_1; /* (1)*/
TIMx->SMCR |= TIM_SMCR_TS_2 | TIM_SMCR_TS_0
| TIM_SMCR_SMS_2; /* (2) */
TIMx->CCER |= TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC2P; /* (3) */
TIMx->DIER |= TIM_DIER_CC1IE; /* (4) */
TIMx->CR1 |= TIM_CR1_CEN; /* (5) */

A.8.6 PWM input with DMA configuration

/* (1)
Enable the peripheral clock on DMA */
/* (2)
Configure the peripheral data register address for DMA channel x */
/* (3)
Configure the memory address for DMA channel x */
/* (4)
Configure the number of DMA transfers to be performed
on DMA channel x */
/* (5) Configure no increment (reset value), size (16-bits), interrupts,
transfer from peripheral to memory and circular mode
for DMA channel x */
/* (6) Enable DMA Channel x */
RCC->AHBENR |= RCC_AHBENR_DMA1EN; /* (1) */
DMA1_Channel2->CPAR = (uint32_t) (&(TIM1->CCR1)); /* (2) */
DMA1_Channel2->CMAR = (uint32_t)(&Period); /* (3) */
DMA1_Channel2->CNDTR = 1; /* (4) */
DMA1_Channel2->CCR |= DMA_CCR_MSIZE_0 | DMA_CCR_PSIZE_0
| DMA_CCR_TEIE | DMA_CCR_CIRC; /* (5) */
DMA1_Channel2->CCR |= DMA_CCR_EN; /* (6) */
/* repeat (2) to (6) for channel 3 */
DMA1_Channel3->CPAR = (uint32_t) (&(TIM1->CCR2)); /* (2) */
DMA1_Channel3->CMAR = (uint32_t)(&DutyCycle); /* (3) */
DMA1_Channel3->CNDTR = 1; /* (4) */
DMA1_Channel3->CCR |= DMA_CCR_MSIZE_0 | DMA_CCR_PSIZE_0
| DMA_CCR_TEIE | DMA_CCR_CIRC; /* (5) */
DMA1_Channel3->CCR |= DMA_CCR_EN; /* (6) */

/* Configure NVIC for DMA */

/* (7) Enable Interrupt on DMA Channels x */
/* (8) Set priority for DMA Channels x */
NVIC_EnableIRQ(DMA1_Channel2_3_IRQn); /* (7) */
NVIC_SetPriority(DMA1_Channel2_3_IRQn,3); /* (8) */

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A.8.7 Output compare configuration

/* (1)
Set prescaler to 3, so APBCLK/4 i.e 12MHz */
/* (2)
Set ARR = 12000 -1 */
/* (3)
Set CCRx = ARR, as timer clock is 12MHz, an event occurs each 1 ms */
/* (4)
Select toggle mode on OC1 (OC1M = 011),
disable preload register on OC1 (OC1PE = 0, reset value) */
/* (5) Select active high polarity on OC1 (CC1P = 0, reset value),
enable the output on OC1 (CC1E = 1)*/
/* (6) Enable output (MOE = 1)*/
/* (7) Enable counter */
TIMx->PSC |= 3; /* (1) */
TIMx->ARR = 12000 - 1; /* (2) */
TIMx->CCR1 = 12000 - 1; /* (3) */
TIMx->CCMR1 |= TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_1; /* (4) */
TIMx->CCER |= TIM_CCER_CC1E; /* (5)*/
TIMx->BDTR |= TIM_BDTR_MOE; /* (6) */
TIMx->CR1 |= TIM_CR1_CEN; /* (7) */

A.8.8 Edge-aligned PWM configuration example

/* (1)
Set prescaler to 47, so APBCLK/48 i.e 1MHz */
/* (2)
Set ARR = 8, as timer clock is 1MHz the period is 9 us */
/* (3)
Set CCRx = 4, , the signal will be high during 4 us */
/* (4)
Select PWM mode 1 on OC1 (OC1M = 110),
enable preload register on OC1 (OC1PE = 1) */
/* (5) Select active high polarity on OC1 (CC1P = 0, reset value),
enable the output on OC1 (CC1E = 1)*/
/* (6) Enable output (MOE = 1)*/
/* (7) Enable counter (CEN = 1)
select edge aligned mode (CMS = 00, reset value)
select direction as upcounter (DIR = 0, reset value) */
/* (8) Force update generation (UG = 1) */
TIMx->PSC = 47; /* (1) */
TIMx->ARR = 8; /* (2) */
TIMx->CCR1 = 4; /* (3) */
TIMx->CCMR1 |= TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1
| TIM_CCMR1_OC1PE; /* (4) */
TIMx->CCER |= TIM_CCER_CC1E; /* (5) */
TIMx->BDTR |= TIM_BDTR_MOE; /* (6) */
TIMx->CR1 |= TIM_CR1_CEN; /* (7) */
TIMx->EGR |= TIM_EGR_UG; /* (8) */

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A.8.9 Center-aligned PWM configuration example

/* (1) Set prescaler to 47, so APBCLK/48 i.e 1MHz */

/* (2) Set ARR = 8, as timer clock is 1MHz and center-aligned counting,
the period is 16 us */
/* (3) Set CCRx = 7, the signal will be high during 14 us */
/* (4) Select PWM mode 1 on OC1 (OC1M = 110),
enable preload register on OC1 (OC1PE = 1, reset value) */
/* (5) Select active high polarity on OC1 (CC1P = 0, reset value),
enable the output on OC1 (CC1E = 1)*/
/* (6) Enable output (MOE = 1)*/
/* (7) Enable counter (CEN = 1)
select center-aligned mode 1 (CMS = 01) */
/* (8) Force update generation (UG = 1) */
TIMx->PSC = 47; /* (1) */
TIMx->ARR = 8; /* (2) */
TIMx->CCR1 = 7; /* (3) */
TIMx->CCMR1 |= TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1
| TIM_CCMR1_OC1PE; /* (4) */
TIMx->CCER |= TIM_CCER_CC1E; /* (5) */
TIMx->BDTR |= TIM_BDTR_MOE; /* (6) */
TIMx->CR1 |= TIM_CR1_CMS_0 | TIM_CR1_CEN; /* (7) */
TIMx->EGR |= TIM_EGR_UG; /* (8) */

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A.8.10 ETR configuration to clear OCxREF

/* This code is similar to the edge-aligned PWM configuration but it enables

the clearing on OC1 for ETRclearing (OC1CE = 1) in CCMR1 (5) and ETR is
configured in SMCR (7).*/
/* (1) Set prescaler to 47, so APBCLK/48 i.e 1MHz */
/* (2) Set ARR = 8, as timer clock is 1MHz the period is 9 us */
/* (3) Set CCRx = 4, , the signal will be high during 4 us */
/* (4) Select PWM mode 1 on OC1 (OC1M = 110),
enable preload register on OC1 (OC1PE = 1),
enable clearing on OC1 for ETR clearing (OC1CE = 1) */
/* (5) Select active high polarity on OC1 (CC1P = 0, reset value),
enable the output on OC1 (CC1E = 1) */
/* (6) Enable output (MOE = 1) */
/* (7) Select ETR as OCREF clear source (OCCS = 1),
select External Trigger Prescaler off (ETPS = 00, reset value),
disable external clock mode 2 (ECE = 0, reset value),
select active at high level (ETP = 0, reset value) */
/* (8) Enable counter (CEN = 1),
select edge aligned mode (CMS = 00, reset value),
select direction as upcounter (DIR = 0, reset value) */
/* (9) Force update generation (UG = 1) */
TIMx->PSC = 47; /* (1) */
TIMx->ARR = 8; /* (2) */
TIMx->CCR1 = 4; /* (3) */
TIMx->CCMR1 |= TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1PE
| TIM_CCMR1_OC1CE; /* (4) */
TIMx->CCER |= TIM_CCER_CC1E; /* (5) */
TIMx->BDTR |= TIM_BDTR_MOE; /* (6) */
TIMx->SMCR |= TIM_SMCR_OCCS; /* (7) */
TIMx->CR1 |= TIM_CR1_CEN; /* (8) */
TIMx->EGR |= TIM_EGR_UG; /* (9) */

A.8.11 Encoder interface

/* (1) Configure TI1FP1 on TI1 (CC1S = 01),

configure TI1FP2 on TI2 (CC2S = 01) */
/* (2) Configure TI1FP1 and TI1FP2 non inverted (CC1P = CC2P = 0, reset
value) */
/* (3) Configure both inputs are active on both rising and falling edges
(SMS = 011) */
/* (4) Enable the counter by writing CEN=1 in the TIMx_CR1 register. */
TIMx->CCMR1 |= TIM_CCMR1_CC1S_0 | TIM_CCMR1_CC2S_0; /* (1)*/
TIMx->CCER &= (uint16_t)(~(TIM_CCER_CC21 | TIM_CCER_CC2P); /* (2) */
TIMx->SMCR |= TIM_SMCR_SMS_0 | TIM_SMCR_SMS_1; /* (3) */
TIMx->CR1 |= TIM_CR1_CEN; /* (4) */

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A.8.12 Reset mode

/* (1) Configure channel 1 to detect rising edges on the TI1 input

by writing CC1S = ‘01’,
and configure the input filter duration by writing the IC1F[3:0]
bits in the TIMx_CCMR1 register (if no filter is needed, keep
IC1F=0000).*/
/* (2) Select rising edge polarity by writing CC1P=0 in the TIMx_CCER
register
Not necessary as it keeps the reset value. */
/* (3) Configure the timer in reset mode by writing SMS=100
Select TI1 as the trigger input source by writing TS=101
in the TIMx_SMCR register.*/
/* (4) Set prescaler to 48000-1 in order to get an increment each 1ms */
/* (5) Enable the counter by writing CEN=1 in the TIMx_CR1 register. */
TIMx->CCMR1 |= TIM_CCMR1_CC1S_0; /* (1)*/
TIMx->CCER &= (uint16_t)(~TIM_CCER_CC1P); /* (2) */
TIMx->SMCR |= TIM_SMCR_SMS_2 | TIM_SMCR_TS_2 | TIM_SMCR_TS_0; /* (3) */
TIM1->PSC = 47999; /* (4) */
TIMx->CR1 |= TIM_CR1_CEN; /* (5) */

A.8.13 Gated mode

/* (1) Configure channel 1 to detect low level on the TI1 input

by writing CC1S = ‘01’,
and configure the input filter duration by writing the IC1F[3:0]
bits in the TIMx_CCMR1 register (if no filter is needed,
keep IC1F=0000). */
/* (2) Select polarity by writing CC1P=1 in the TIMx_CCER register */
/* (3) Configure the timer in gated mode by writing SMS=101
Select TI1 as the trigger input source by writing TS=101
in the TIMx_SMCR register. */
/* (4) Set prescaler to 12000-1 in order to get an increment each 250us */
/* (5) Enable the counter by writing CEN=1 in the TIMx_CR1 register. */
TIMx->CCMR1 |= TIM_CCMR1_CC1S_0; /* (1)*/
TIMx->CCER |= TIM_CCER_CC1P; /* (2) */
TIMx->SMCR |= TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0
| TIM_SMCR_TS_2 | TIM_SMCR_TS_0; /* (3) */
TIMx->PSC = 11999; /* (4) */
TIMx->CR1 |= TIM_CR1_CEN; /* (5) */

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A.8.14 Trigger mode

/* (1) Configure channel 2 to detect rising edge on the TI2 input

by writing CC2S = ‘01’,
and configure the input filter duration by writing the IC1F[3:0]
bits in the TIMx_CCMR1 register (if no filter is needed,
keep IC1F=0000). */
/* (2) Select polarity by writing CC2P=0 (reset value) in the TIMx_CCER
register */
/* (3) Configure the timer in trigger mode by writing SMS=110
Select TI2 as the trigger input source by writing TS=110
in the TIMx_SMCR register. */
/* (4) Set prescaler to 12000-1 in order to get an increment each 250us */
TIMx->CCMR1 |= TIM_CCMR1_CC2S_0; /* (1)*/
TIMx->CCER &= ~TIM_CCER_CC2P; /* (2) */
TIMx->SMCR |= TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1
| TIM_SMCR_TS_2 | TIM_SMCR_TS_1; /* (3) */
TIM1->PSC = 11999; /* (4) */

A.8.15 External clock mode 2 + trigger mode

/* (1) Configure no input filter (ETF=0000, reset value)

configure prescaler disabled (ETPS = 0, reset value)
select detection on rising edge on ETR (ETP = 0, reset value)
enable external clock mode 2 (ECE = 1) */
/* (2) Configure no input filter (IC1F=0000, reset value)
select input capture source on TI1 (CC1S = 01) */
/* (3) Select polarity by writing CC1P=0 (reset value) in the TIMx_CCER
register */
/* (4) Configure the timer in trigger mode by writing SMS=110
Select TI1 as the trigger input source by writing TS=101
in the TIMx_SMCR register. */
TIMx->SMCR |= TIM_SMCR_ECE; /* (1) */
TIMx->CCMR1 |= TIM_CCMR1_CC1S_0; /* (2)*/
TIMx->CCER &= ~TIM_CCER_CC1P; /* (3) */
TIMx->SMCR |= TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1
| TIM_SMCR_TS_2 | TIM_SMCR_TS_0; /* (4) */
/* Use TI2FP2 as trigger 1 */
/* (1) Map TI2FP2 on TI2 by writing CC2S=01 in the TIMx_CCMR1 register */
/* (2) TI2FP2 must detect a rising edge, write CC2P=0 and CC2NP=0
in the TIMx_CCER register (keep the reset value) */
/* (3) Configure TI2FP2 as trigger for the slave mode controller (TRGI)
by writing TS=110 in the TIMx_SMCR register,
TI2FP2 is used to start the counter by writing SMS to ‘110'
in the TIMx_SMCR register (trigger mode) */
TIMx->CCMR1 |= TIM_CCMR1_CC2S_0; /* (1) */
//TIMx->CCER &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP); /* (2) */
TIMx->SMCR |= TIM_SMCR_TS_2 | TIM_SMCR_TS_1
| TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1; /* (3) */

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A.8.16 One-Pulse mode

/* The
OPM waveform is defined by writing the compare registers */
/* (1)
Set prescaler to 47, so APBCLK/48 i.e 1MHz */
/* (2)
Set ARR = 7, as timer clock is 1MHz the period is 8 us */
/* (3)
Set CCRx = 5, the burst will be delayed for 5 us (must be > 0) */
/* (4)
Select PWM mode 2 on OC1 (OC1M = 111),
enable preload register on OC1 (OC1PE = 1, reset value)
enable fast enable (no delay) if PULSE_WITHOUT_DELAY is set */
/* (5) Select active high polarity on OC1 (CC1P = 0, reset value),
enable the output on OC1 (CC1E = 1) */
/* (6) Enable output (MOE = 1) */
/* (7) Write '1 in the OPM bit in the TIMx_CR1 register to stop the counter
at the next update event (OPM = 1),
enable auto-reload register(ARPE = 1) */
TIMx->PSC = 47; /* (1) */
TIMx->ARR = 7; /* (2) */
TIMx->CCR1 = 5; /* (3) */
TIMx->CCMR1 |= TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0
| TIM_CCMR1_OC1PE
#if PULSE_WITHOUT_DELAY > 0
| TIM_CCMR1_OC1FE
#endif
; /* (4) */
TIMx->CCER |= TIM_CCER_CC1E; /* (5) */
TIMx->BDTR |= TIM_BDTR_MOE; /* (6) */
TIMx->CR1 |= TIM_CR1_OPM | TIM_CR1_ARPE; /* (7) */

A.8.17 Timer prescaling another timer

/* TIMy is slave of TIMx */

/* (1) Select Update Event as Trigger output (TRG0) by writing MMS = 010
in TIMx_CR2. */
/* (2) Configure TIMy in slave mode using ITR1 as internal trigger
by writing TS = 000 in TIMy_SMCR (reset value)
Configure TIMy in external clock mode 1, by writing SMS=111 in the
TIMy_SMCR register. */
/* (3) Set TIMx prescaler to 47999 in order to get an increment each 1ms */
/* (4) Set TIMx Autoreload to 999 in order to get an overflow (so an UEV)
each second */
/* (5) Set TIMx Autoreload to 24*3600-1 in order to get an overflow each 24-
hour */
/* (6) Enable the counter by writing CEN=1 in the TIMx_CR1 register. */
/* (7) Enable the counter by writing CEN=1 in the TIMy_CR1 register. */
TIMx->CR2 |= TIM_CR2_MMS_1; /* (1) */
TIMy->SMCR |= TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0; /* (2) */
TIMx->PSC = 47999; /* (3) */
TIMx->ARR = 999; /* (4) */
TIMy->ARR = (24 * 3600) - 1; /* (5) */
TIMx->CR1 |= TIM_CR1_CEN; /* (6) */
TIMy->CR1 |= TIM_CR1_CEN; /* (7) */

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A.8.18 Timer enabling another timer

/* TIMy is slave of TIMx */

/* (1) Configure Timer x master mode to send its Output Compare 1 Reference
(OC1REF) signal as trigger output
(MMS=100 in the TIM1_CR2 register). */
/* (2) Configure the Timer x OC1REF waveform (TIM1_CCMR1 register)
Channel 1 is in PWM mode 1 when the counter is less than the
capture/compare register (write OC1M = 110) */
/* (3) Configure TIMy in slave mode using ITR1 as internal trigger
by writing TS = 000 in TIMy_SMCR (reset value)
Configure TIMy in gated mode, by writing SMS=101 in the
TIMy_SMCR register. */
/* (4) Set TIMx prescaler to 2 */
/* (5) Set TIMy prescaler to 2 */
/* (6) Set TIMx Autoreload to 999 in order to get an overflow (so an UEV)
each 100ms */
/* (7) Set capture compare register to a value between 0 and 999 */
TIMx->CR2 |= TIM_CR2_MMS_2; /* (1) */
TIMx->CCMR1 |= TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1; /* (2) */
TIMy->SMCR |= TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0; /* (3) */
TIMx->PSC = 2; /* (4) */
TIMy->PSC = 2; /* (5) */
TIMx->ARR = 999; /* (6) */
TIMx-> CCR1 = 700; /* (7) */
/* Configure the slave timer to generate toggling on each count */
/* (1) Configure the TIMy in PWM mode 1 (write OC1M = 110) */
/* (2) Set TIMy Autoreload to 1 */
/* (3) Set capture compare register to 1 */
TIMy->CCMR1 |= TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1; /* (1) */
TIMy->ARR = 1; /* (2) */
TIMy-> CCR1 = 1; /* (3) */
/* Enable the output of TIMx OC1 */
/* (1) Select active high polarity on OC1 (CC1P = 0, reset value),
enable the output on OC1 (CC1E = 1) */
/* (2) Enable output (MOE = 1) */
TIMx->CCER |= TIM_CCER_CC1E; /* (1) */
TIMx->BDTR |= TIM_BDTR_MOE; /* (2) */
/* Enable the output of TIMy OC1 */
/* (1) Select active high polarity on OC1 (CC1P = 0, reset value),
enable the output on OC1 (CC1E = 1) */
/* (2) Enable output (MOE = 1) */
TIMy->CCER |= TIM_CCER_CC1E; /* (1) */
TIMy->BDTR |= TIM_BDTR_MOE; /* (2) */
/* (1) Enable the slave counter first by writing CEN=1
in the TIMy_CR1 register. */
/* (2) Enable the master counter by writing CEN=1
in the TIMx_CR1 register. */
TIMy->CR1 |= TIM_CR1_CEN; /* (1) */
TIMx->CR1 |= TIM_CR1_CEN; /* (2) */

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A.8.19 Master and slave synchronization

/* (1) Configure Timer x master mode to send its enable signal

as trigger output (MMS=001 in the TIM1_CR2 register). */
/* (2) Configure the Timer x Channel 1 waveform (TIM1_CCMR1 register)
is in PWM mode 1 (write OC1M = 110) */
/* (3) Configure TIMy in slave mode using ITR1 as internal trigger
by writing TS = 000 in TIMy_SMCR (reset value)
Configure TIMy in gated mode, by writing SMS=101 in the
TIMy_SMCR register. */
/* (4) Set TIMx prescaler to 2 */
/* (5) Set TIMy prescaler to 2 */
/* (6) Set TIMx Autoreload to 99 in order to get an overflow (so an UEV)
each 10ms */
/* (7) Set capture compare register to a value between 0 and 99 */
TIMx->CR2 |= TIM_CR2_MMS_0; /* (1) */
TIMx->CCMR1 |= TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1; /* (2) */
TIMy->SMCR |= TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0; /* (3) */
TIMx->PSC = 2; /* (4) */
TIMy->PSC = 2; /* (5) */
TIMx->ARR = 99; /* (6) */
TIMx-> CCR1 = 25; /* (7) */
/* Configure the slave timer Channel 1 as PWM as Timer
to show synchronicity */
/* (1) Configure the TIMy in PWM mode 1 (write OC1M = 110) */
/* (2) Set TIMy Autoreload to 99 */
/* (3) Set capture compare register to 25 */
TIMy->CCMR1 |= TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1; /* (1) */
TIMy->ARR = 99; /* (2) */
TIMy-> CCR1 = 25; /* (3) */
/* Enable the output of TIMx OC1 */
/* (1) Select active high polarity on OC1 (CC1P = 0, reset value),
enable the output on OC1 (CC1E = 1)*/
/* (2) Enable output (MOE = 1) */
TIMx->CCER |= TIM_CCER_CC1E; /* (1) */
TIMx->BDTR |= TIM_BDTR_MOE; /* (2) */
/* Enable the output of TIMy OC1 */
/* (1) Select active high polarity on OC1 (CC1P = 0, reset value),
enable the output on OC1 (CC1E = 1) */
/* (2) Enable output (MOE = 1) */
TIMy->CCER |= TIM_CCER_CC1E; /* (1) */
TIMy->BDTR |= TIM_BDTR_MOE; /* (2) */
/* (1) Reset Timer x by writing ‘1 in UG bit (TIMx_EGR register) */
/* (2) Reset Timer y by writing ‘1 in UG bit (TIMy_EGR register) */
TIMx->EGR |= TIM_EGR_UG; /* (1) */
TIMy->EGR |= TIM_EGR_UG; /* (2) */
/* (1) Enable the slave counter first by writing CEN=1 in the TIMy_CR1
register.
TIMy will start synchronously with the master timer */
/* (2) Start the master counter by writing CEN=1
in the TIMx_CR1 register. */
TIMy->CR1 |= TIM_CR1_CEN; /* (1) */
TIMx->CR1 |= TIM_CR1_CEN; /* (2) */

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A.8.20 Two timers synchronized by an external trigger

/* (1) Configure TIMx master mode to send its enable signal

as trigger output (MMS=001 in the TIM1_CR2 register). */
/* (2) Configure TIMx in slave mode to get the input trigger from TI1
by writing TS = 100 in TIMx_SMCR
Configure TIMx in trigger mode, by writing SMS=110 in the
TIMx_SMCR register.
Configure TIMx in Master/Slave mode by writing MSM = 1
in TIMx_SMCR */
/* (3) Configure TIMy in slave mode to get the input trigger from Timer1
by writing TS = 000 in TIMy_SMCR (reset value)
Configure TIMy in trigger mode, by writing SMS=110 in the
TIMy_SMCR register. */
/* (4) Reset Timer x counter by writing ‘1 in UG bit (TIMx_EGR register) */
/* (5) Reset Timer y counter by writing ‘1 in UG bit (TIMy_EGR register) */
TIMx->CR2 |= TIM_CR2_MMS_0; /* (1)*/
TIMx->SMCR |= TIM_SMCR_TS_2 | TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1
| TIM_SMCR_MSM; /* (2) */
TIMy->SMCR |= TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1; /* (3) */
TIMx->EGR |= TIM_EGR_UG; /* (4) */
TIMy->EGR |= TIM_EGR_UG; /* (5) */
/* Configure the Timer Channel 2 as PWM */
/* (1) Configure the Timer x Channel 2 waveform (TIM1_CCMR1 register)
is in PWM mode 1 (write OC2M = 110) */
/* (2) Set TIMx prescaler to 2 */
/* (3) Set TIMx Autoreload to 99 in order to get an overflow (so an UEV)
each 10ms */
/* (4) Set capture compare register to a value between 0 and 99 */
TIMx->CCMR1 |= TIM_CCMR1_OC2M_2 | TIM_CCMR1_OC2M_1; /* (1) */
TIMx->PSC = 2; /* (2) */
TIMx->ARR = 99; /* (3) */
TIMx->CCR2 = 25; /* (4) */
/* Configure the slave timer Channel 1 as PWM as Timer
to show synchronicity */
/* (1) Configure the TIMy in PWM mode 1 (write OC1M = 110) */
/* (2) Set TIMy prescaler to 2 */
/* (3) Set TIMx Autoreload to 99 */
/* (4) Set capture compare register to 25 */
TIMy->CCMR1 |= TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1; /* (1) */
TIMy->PSC = 2; /* (2) */
TIMy->ARR = 99; /* (3) */
TIMy-> CCR1 = 25; /* (4) */
/* Enable the output of TIMx OC1 */
/* (1) Select active high polarity on OC1 (CC1P = 0, reset value),
enable the output on OC1 (CC1E = 1)*/
/* (2) Enable output (MOE = 1)*/
TIMx->CCER |= TIM_CCER_CC2E; /* (1) */
TIMx->BDTR |= TIM_BDTR_MOE; /* (2) */
/* Enable the output of TIMy OC1 */
/* (1) Select active high polarity on OC1 (CC1P = 0, reset value),
enable the output on OC1 (CC1E = 1)*/
/* (2) Enable output (MOE = 1)*/
TIMy->CCER |= TIM_CCER_CC1E; /* (1) */
TIMy->BDTR |= TIM_BDTR_MOE; /* (2) */

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A.8.21 DMA burst feature

/* In this example TIMx has been previously configured

in PWM center-aligned */
/* Configure DMA Burst Feature */
/* Configure the corresponding DMA channel */
/* (1) Set DMA channel peripheral address is the DMAR register address */
/* (2) Set DMA channel memory address is the address of the buffer
in the RAM containing the data to be transferred by DMA
into CCRx registers */
/* (3) Set the number of data transfer to sizeof(Duty_Cycle_Table) */
/* (4) Configure DMA transfer in CCR register,
enable the circular mode by setting CIRC bit (optional),
set memory size to 16_bits MSIZE = 01,
set peripheral size to 32_bits PSIZE = 10,
enable memory increment mode by setting MINC,
set data transfer direction read from memory by setting DIR. */
/* (5) Configure TIMx_DCR register with DBL = 3 transfers
and DBA = (@TIMx->CCR2 - @TIMx->CR1) >> 2 = 0xE */
/* (6) Enable the TIMx update DMA request by setting UDE bit in DIER
register */
/* (7) Enable TIMx */
/* (8) Enable DMA channel */
DMA1_Channel2->CPAR = (uint32_t)(&(TIMx->DMAR)); /* (1) */
DMA1_Channel2->CMAR = (uint32_t)(Duty_Cycle_Table); /* (2) */
DMA1_Channel2->CNDTR = 10*3; /* (3) */
DMA1_Channel2->CCR |= DMA_CCR_CIRC | DMA_CCR_MSIZE_0 | DMA_CCR_PSIZE_1
| DMA_CCR_MINC | DMA_CCR_DIR; /* (4) */
TIMx->DCR = (3 << 8)
+ ((((uint32_t)(&TIMx->CCR2))
- ((uint32_t)(&TIMx->CR1))) >> 2); /* (5) */
TIMx->DIER |= TIM_DIER_UDE; /* (6) */
TIMx->CR1 |= TIM_CR1_CEN; /* (7) */
DMA1_Channel2->CCR |= DMA_CCR_EN; /* (8) */

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A.9 IRTIM code examples

A.9.1 TIM16 and TIM17 configuration

/* The following configuration is for RC5 standard */

/* TIM16 is used for the enveloppe while TIM17 is used for the carrier */
#define TIM_ENV TIM16
#define TIM_CAR TIM17
/* (1) Enable the peripheral clocks of Timer 16 and 17 and SYSCFG */
/* (2) Enable the peripheral clock of GPIOB */
/* (3) Select alternate function mode on GPIOB pin 9 */
/* (4) Select AF0 on PB9 in AFRH for IR_OUT (reset value) */
/* (5) Enable the high sink driver capability by setting I2C_PB9_FM+ bit
in SYSCFG_CFGR1 */
RCC->APB2ENR |= RCC_APB2ENR_TIM16EN | RCC_APB2ENR_TIM17EN
| RCC_APB2ENR_SYSCFGCOMPEN; /* (1) */
RCC->AHBENR |= RCC_AHBENR_GPIOBEN; /* (2) */
GPIOB->MODER = (GPIOB->MODER & ~GPIO_MODER_MODER9)
| GPIO_MODER_MODER9_1; /* (3) */
GPIOB->AFR[1] &= ~(0x0F << ((9 - 8) * 4)); /* (4) */
SYSCFG->CFGR1 |= SYSCFG_CFGR1_I2C_FMP_PB9; /* (5) */
/* Configure TIM_CAR as carrier signal */
/* (1) Set prescaler to 1, so APBCLK i.e 48MHz */
/* (2) Set ARR = 1333, as timer clock is 48MHz the frequency is 36kHz */
/* (3) Set CCRx = 1333/4, , the signal will bhave a 25% duty cycle */
/* (4) Select PWM mode 1 on OC1 (OC1M = 110),
enable preload register on OC1 (OC1PE = 1) */
/* (5) Select active high polarity on OC1 (CC1P = 0, reset value),
enable the output on OC1 (CC1E = 1)*/
/* (6) Enable output (MOE = 1)*/
TIM_CAR->PSC = v; /* (1) */
TIM_CAR->ARR = 1333; /* (2) */
TIM_CAR->CCR1 = (uint16_t)(1333 / 4); /* (3) */
TIM_CAR->CCMR1 |= TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1
| TIM_CCMR1_OC1PE; /* (4) */
TIM_CAR->CCER |= TIM_CCER_CC1E; /* (5) */
TIM_CAR->BDTR |= TIM_BDTR_MOE; /* (6) */
/* Configure TIM_ENV is the modulation enveloppe */
/* (1) Set prescaler to 1, so APBCLK i.e 48MHz */
/* (2) Set ARR = 42627, as timer clock is 48MHz the period is 888 us */
/* (3) Select Forced inactive on OC1 (OC1M = 100) */
/* (4) Select active high polarity on OC1 (CC1P = 0, reset value),
enable the output on OC1 (CC1E = 1) */
/* (5) Enable output (MOE = 1) */
/* (6) Enable Update interrupt (UIE = 1) */
TIM_ENV->PSC = 0; /* (1) */
TIM_ENV->ARR = 42627; /* (2) */
TIM_ENV->CCMR1 |= TIM_CCMR1_OC1M_2; /* (3) */
TIM_ENV->CCER |= TIM_CCER_CC1E; /* (4) */
TIM_ENV->BDTR |= TIM_BDTR_MOE; /* (5) */
TIM_ENV->DIER |= TIM_DIER_UIE; /* (6) */
/* Enable and reset TIM_CAR only */
/* (1) Enable counter (CEN = 1),
select edge aligned mode (CMS = 00, reset value),
select direction as upcounter (DIR = 0, reset value) */

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/* (2) Force update generation (UG = 1) */

TIM_CAR->CR1 |= TIM_CR1_CEN; /* (1) */
TIM_CAR->EGR |= TIM_EGR_UG; /* (2) */
/* Configure TIM_ENV interrupt */
/* (1) Enable Interrupt on TIM_ENV */
/* (2) Set priority for TIM_ENV */
NVIC_EnableIRQ(TIM_ENV_IRQn); /* (1) */
NVIC_SetPriority(TIM_ENV_IRQn,0); /* (2) */

A.9.2 IRQHandler for IRTIM

/**
* Description: This function handles TIM_16 interrupt request.
* This interrupt subroutine computes the laps between 2
* rising edges on T1IC.
* This laps is stored in the "Counter" variable.
*/
void TIM16_IRQHandler(void)
{
uint8_t bit_msg = 0;

if ((SendOperationReady == 1)
&& (BitsSentCounter < (RC5_GlobalFrameLength * 2)))
{
if (BitsSentCounter < 32)
{
SendOperationCompleted = 0x00;
bit_msg = (uint8_t)((ManchesterCodedMsg >> BitsSentCounter)& 1);

if (bit_msg== 1)
{
/* Force active level - OC1REF is forced high */
TIM_ENV->CCMR1 |= TIM_CCMR1_OC1M_0;
}
else
{
/* Force inactive level - OC1REF is forced low */
TIM_ENV->CCMR1 &= (uint16_t)(~TIM_CCMR1_OC1M_0);
}
}
BitsSentCounter++;
}
else
{
SendOperationCompleted = 0x01;
SendOperationReady = 0;
BitsSentCounter = 0;
}
/* Clear TIM_ENV update interrupt */
TIM_ENV->SR &= (uint16_t)(~TIM_SR_UIF);
}

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A.10 DBG code examples

A.10.1 DBG read device ID

/* Read MCU Id, 32-bit access */

MCU_Id = DBGMCU->IDCODE;

A.10.2 DBG debug in Low-power mode

/* To be able to debug in stop mode */

DBGMCU->CR |= DBGMCU_CR_DBG_STOP;

A.11 I2C code examples

A.11.1 I2C configured in master mode to receive

/* (1) Timing register value is computed with the AN4235 xls file,
fast Mode @400kHz with I2CCLK = 48MHz, rise time = 140ns,
fall time = 40ns */
/* (2) Periph enable, receive interrupt enable */
/* (3) Slave address = 0x5A, read transfer, 1 byte to receive, autoend */
I2C2->TIMINGR = (uint32_t)0x00B01A4B; /* (1) */
I2C2->CR1 = I2C_CR1_PE | I2C_CR1_RXIE; /* (2) */
I2C2->CR2 = I2C_CR2_AUTOEND | (1<<16) | I2C_CR2_RD_WRN
| (I2C1_OWN_ADDRESS << 1); /* (3) */

A.11.2 I2C configured in master mode to transmit

/* (1) Timing register value is computed with the AN4235 xls file,
fast Mode @400kHz with I2CCLK = 48MHz, rise time = 140ns,
fall time = 40ns */
/* (2) Periph enable */
/* (3) Slave address = 0x5A, write transfer, 1 byte to transmit, autoend */
I2C2->TIMINGR = (uint32_t)0x00B01A4B; /* (1) */
I2C2->CR1 = I2C_CR1_PE; /* (2) */
I2C2->CR2 = I2C_CR2_AUTOEND | (1 << 16) | (I2C1_OWN_ADDRESS << 1); /* (3) */

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A.11.3 I2C configured in slave mode

/* (1) Timing register value is computed with the AN4235 xls file,
fast Mode @400kHz with I2CCLK = 48MHz, rise time = 140ns,
fall time = 40ns */
/* (2) Periph enable, address match interrupt enable */
/* (3) 7-bit address = 0x5A */
/* (4) Enable own address 1 */
I2C1->TIMINGR = (uint32_t)0x00B00000; /* (1) */
I2C1->CR1 = I2C_CR1_PE | I2C_CR1_ADDRIE; /* (2) */
I2C1->OAR1 |= (uint32_t)(I2C1_OWN_ADDRESS << 1); /* (3) */
I2C1->OAR1 |= I2C_OAR1_OA1EN; /* (4) */

A.11.4 I2C master transmitter

/* Check Tx empty */
if ((I2C2->ISR & I2C_ISR_TXE) == I2C_ISR_TXE)
{
I2C2->TXDR = I2C_BYTE_TO_SEND; /* Byte to send */
I2C2->CR2 |= I2C_CR2_START; /* Go */
}

A.11.5 I2C master receiver

if ((I2C2->ISR & I2C_ISR_RXNE) == I2C_ISR_RXNE)

{
/* Read receive register, will clear RXNE flag */
if (I2C2->RXDR == I2C_BYTE_TO_SEND)
{
/* Process */
}
}

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A.11.6 I2C slave transmitter

uint32_t I2C_InterruptStatus = I2C1->ISR; /* Get interrupt status */

/* Check address match */
if ((I2C_InterruptStatus & I2C_ISR_ADDR) == I2C_ISR_ADDR)
{
I2C1->ICR |= I2C_ICR_ADDRCF; /* Clear address match flag */
/* Check if transfer direction is read (slave transmitter) */
if ((I2C1->ISR & I2C_ISR_DIR) == I2C_ISR_DIR)
{
I2C1->CR1 |= I2C_CR1_TXIE; /* Set transmit IT */
}
}
else if ((I2C_InterruptStatus & I2C_ISR_TXIS) == I2C_ISR_TXIS)
{
I2C1->CR1 &=~ I2C_CR1_TXIE; /* Disable transmit IT */
I2C1->TXDR = I2C_BYTE_TO_SEND; /* Byte to send */
}

A.11.7 I2C slave receiver

uint32_t I2C_InterruptStatus = I2C1->ISR; /* Get interrupt status */

if ((I2C_InterruptStatus & I2C_ISR_ADDR) == I2C_ISR_ADDR)
{
I2C1->ICR |= I2C_ICR_ADDRCF; /* Address match event */
}
else if ((I2C_InterruptStatus & I2C_ISR_RXNE) == I2C_ISR_RXNE)
{
/* Read receive register, will clear RXNE flag */
if (I2C1->RXDR == I2C_BYTE_TO_SEND)
{
/* Process */
}
}

A.11.8 I2C configured in master mode to transmit with DMA

/* (1) Timing register value is computed with the AN4235 xls file,
fast Mode @400kHz with I2CCLK = 48MHz, rise time = 140ns,
fall time = 40ns */
/* (2) Periph enable */
/* (3) Slave address = 0x5A, write transfer, 2 bytes to transmit,
autoend */
I2C2->TIMINGR = (uint32_t)0x00B01A4B; /* (1) */
I2C2->CR1 = I2C_CR1_PE | I2C_CR1_TXDMAEN; /* (2) */
I2C2->CR2 = I2C_CR2_AUTOEND | (SIZE_OF_DATA << 16)
| (I2C1_OWN_ADDRESS << 1); /* (3) */

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A.11.9 I2C configured in slave mode to receive with DMA

/* (1) Timing register value is computed with the AN4235 xls file,
fast Mode @400kHz with I2CCLK = 48MHz, rise time = 140ns,
fall time = 40ns */
/* (2) Periph enable, receive DMA enable */
/* (3) 7-bit address = 0x5A */
/* (4) Enable own address 1 */
I2C1->TIMINGR = (uint32_t)0x00B00000; /* (1) */
I2C1->CR1 = I2C_CR1_PE | I2C_CR1_RXDMAEN | I2C_CR1_ADDRIE; /* (2) */
I2C1->OAR1 |= (uint32_t)(I2C1_OWN_ADDRESS << 1); /* (3) */
I2C1->OAR1 |= I2C_OAR1_OA1EN; /* (4) */

A.12 IWDG code examples

A.12.1 IWDG configuration

/* (1) Activate IWDG (not needed if done in option bytes) */

/* (2) Enable write access to IWDG registers */
/* (3) Set prescaler by 8 */
/* (4) Set reload value to have a rollover each 100ms */
/* (5) Check if flags are reset */
/* (6) Refresh counter */
IWDG->KR = IWDG_START; /* (1) */
IWDG->KR = IWDG_WRITE_ACCESS; /* (2) */
IWDG->PR = IWDG_PR_PR_0; /* (3) */
IWDG->RLR = IWDG_RELOAD; /* (4) */
while (IWDG->SR) /* (5) */
{
/* add time out here for a robust application */
}
IWDG->KR = IWDG_REFRESH; /* (6) */

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A.12.2 IWDG configuration with window

/* (1) Activate IWDG (not needed if done in option bytes) */

/* (2) Enable write access to IWDG registers */
/* (3) Set prescaler by 8 */
/* (4) Set reload value to have a rollover each 100ms */
/* (5) Check if flags are reset */
/* (6) Set a 50ms window, this will refresh the IWDG */
IWDG->KR = IWDG_START; /* (1) */
IWDG->KR = IWDG_WRITE_ACCESS; /* (2) */
IWDG->PR = IWDG_PR_PR_0; /* (3) */
IWDG->RLR = IWDG_RELOAD; /* (4) */
while (IWDG->SR) /* (5) */
{
/* add time out here for a robust application */
}
IWDG->WINR = IWDG_RELOAD >> 1; /* (6) */

A.13 RTC code examples

A.13.1 RTC calendar configuration

/* (1) Write access for RTC registers */

/* (2) Enable init phase */
/* (3) Wait until it is allow to modify RTC register values */
/* (4) set prescaler, 40kHz/128 => 312 Hz, 312Hz/312 => 1Hz */
/* (5) New time in TR */
/* (6) Disable init phase */
/* (7) Disable write access for RTC registers */
RTC->WPR = 0xCA; /* (1) */
RTC->WPR = 0x53; /* (1) */
RTC->ISR |= RTC_ISR_INIT; /* (2) */
while ((RTC->ISR & RTC_ISR_INITF) != RTC_ISR_INITF) /* (3) */
{
/* add time out here for a robust application */
}
RTC->PRER = 0x007F0137; /* (4) */
RTC->TR = RTC_TR_PM | Time; /* (5) */
RTC->ISR &=~ RTC_ISR_INIT; /* (6) */
RTC->WPR = 0xFE; /* (7) */
RTC->WPR = 0x64; /* (7) */

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A.13.2 RTC alarm configuration

/* (1) Write access for RTC registers */

/* (2) Disable alarm A to modify it */
/* (3) Wait until it is allow to modify alarm A value */
/* (4) Modify alarm A mask to have an interrupt each 1Hz */
/* (5) Enable alarm A and alarm A interrupt */
/* (6) Disable write access */
RTC->WPR = 0xCA; /* (1) */
RTC->WPR = 0x53; /* (1) */
RTC->CR &=~ RTC_CR_ALRAE; /* (2) */
while ((RTC->ISR & RTC_ISR_ALRAWF) != RTC_ISR_ALRAWF) /* (3) */
{
/* add time out here for a robust application */
}
RTC->ALRMAR = RTC_ALRMAR_MSK4 | RTC_ALRMAR_MSK3
| RTC_ALRMAR_MSK2 | RTC_ALRMAR_MSK1; /* (4) */
RTC->CR = RTC_CR_ALRAIE | RTC_CR_ALRAE; /* (5) */
RTC->WPR = 0xFE; /* (6) */
RTC->WPR = 0x64; /* (6) */

A.13.3 RTC WUT configuration

/* (1) Write access for RTC registers */

/* (2) Disable wake up timerto modify it */
/* (3) Wait until it is allow to modify wake up reload value */
/* (4) Modify wake upvalue reload counter to have a wake up each 1Hz */
/* (5) Enable wake up counter and wake up interrupt */
/* (6) Disable write access */
RTC->WPR = 0xCA; /* (1) */
RTC->WPR = 0x53; /* (1) */
RTC->CR &= ~RTC_CR_WUTE; /* (2) */
while ((RTC->ISR & RTC_ISR_WUTWF) != RTC_ISR_WUTWF) /* (3) */
{
/* add time out here for a robust application */
}
RTC->WUTR = 0x9C0; /* (4) */
RTC->CR = RTC_CR_WUTE | RTC_CR_WUTIE; /* (5) */
RTC->WPR = 0xFE; /* (6) */
RTC->WPR = 0x64; /* (6) */

A.13.4 RTC read calendar

if((RTC->ISR & RTC_ISR_RSF) == RTC_ISR_RSF)

{
TimeToCompute = RTC->TR; /* get time */
DateToCompute = RTC->DR; /* need to read date also */
}

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A.13.5 RTC calibration

/* (1) Write access for RTC registers */

/* (2) Enable init phase */
/* (3) Wait until it is allow to modify RTC register values */
/* (4) set prescaler, 40kHz/125 => 320 Hz, 320Hz/320 => 1Hz */
/* (5) New time in TR */
/* (6) Disable init phase */
/* (7) Wait until it's allow to modify calibartion register */
/* (8) Set calibration to around +20ppm, which is a standard value @25°C */
/* Note: the calibration is relevant when LSE is selected for RTC clock */
/* (9) Disable write access for RTC registers */
RTC->WPR = 0xCA; /* (1) */
RTC->WPR = 0x53; /* (1) */
RTC->ISR |= RTC_ISR_INIT; /* (2) */
while ((RTC->ISR & RTC_ISR_INITF) != RTC_ISR_INITF) /* (3) */
{
/* add time out here for a robust application */
}
RTC->PRER = (124<<16) | 319; /* (4) */
RTC->TR = RTC_TR_PM | Time; /* (5) */
RTC->ISR &=~ RTC_ISR_INIT; /* (6) */
while((RTC->ISR & RTC_ISR_RECALPF) == RTC_ISR_RECALPF) /* (7) */
{
/* add time out here for a robust application */
}
RTC->CALR = RTC_CALR_CALP | 482; /* (8) */
RTC->WPR = 0xFE; /* (9) */
RTC->WPR = 0x64; /* (9) */

A.13.6 RTC tamper and time stamp configuration

/* Tamper configuration:
- Disable precharge (PU)
- RTCCLK/256 tamper sampling frequency
- Activate time stamp on tamper detection
- input rising edge trigger detection on RTC_TAMP2 (PA0)
- Tamper interrupt enable */
RTC->TAFCR = RTC_TAFCR_TAMPPUDIS | RTC_TAFCR_TAMPFREQ | RTC_TAFCR_TAMPTS
| RTC_TAFCR_TAMP2E | RTC_TAFCR_TAMPIE;

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A.13.7 RTC tamper and time stamp

/* Check tamper and timestamp flag */

if (((RTC->ISR & (RTC_ISR_TAMP2F)) == (RTC_ISR_TAMP2F))
&& ((RTC->ISR & (RTC_ISR_TSF)) == (RTC_ISR_TSF)))
{
RTC->ISR &= ~RTC_ISR_TAMP2F; /* clear tamper flag */
EXTI->PR = EXTI_PR_PR19; /* clear exti line 19 flag */
TimeToCompute = RTC->TSTR; /* get tamper time in timestamp register */
RTC->ISR &= ~RTC_ISR_TSF; /* clear timestamp flag */
}

A.13.8 RTC clock output

/* (1)
Write access for RTC registers */
/* (2)
Disable alarm A to modify it */
/* (3)
Wait until it is allow to modify alarm A value */
/* (4)
Modify alarm A mask to have an interrupt each 1Hz */
/* (5)
Enable alarm A and alarm A interrupt,
enable calibration output (1Hz) */
/* (6) Disable write access */
RTC->WPR = 0xCA; /* (1) */
RTC->WPR = 0x53; /* (1) */
RTC->CR &=~ RTC_CR_ALRAE; /* (2) */
while ((RTC->ISR & RTC_ISR_ALRAWF) != RTC_ISR_ALRAWF) /* (3) */
{
/* add time out here for a robust application */
}
RTC->ALRMAR = RTC_ALRMAR_MSK4 | RTC_ALRMAR_MSK3
| RTC_ALRMAR_MSK2 | RTC_ALRMAR_MSK1; /* (4) */
RTC->CR = RTC_CR_ALRAIE | RTC_CR_ALRAE | RTC_CR_COE
| RTC_CR_COSEL; /* (5) */
RTC->WPR = 0xFE; /* (6) */
RTC->WPR = 0x64; /* (6) */

A.14 SPI code examples

A.14.1 SPI master configuration

/* (1) Master selection, BR: Fpclk/256 (due to C27 on the board, SPI_CLK is
set to the minimum) CPOL and CPHA at zero (rising first edge) */
/* (2) Slave select output enabled, RXNE IT, 8-bit Rx fifo */
/* (3) Enable SPI1 */
SPI1->CR1 = SPI_CR1_MSTR | SPI_CR1_BR; /* (1) */
SPI1->CR2 = SPI_CR2_SSOE | SPI_CR2_RXNEIE | SPI_CR2_FRXTH
| SPI_CR2_DS_2 | SPI_CR2_DS_1 | SPI_CR2_DS_0; /* (2) */
SPI1->CR1 |= SPI_CR1_SPE; /* (3) */

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A.14.2 SPI slave configuration

/* nSS hard, slave, CPOL and CPHA at zero (rising first edge) */
/* (1) RXNE IT, 8-bit Rx fifo */
/* (2) Enable SPI2 */
SPI2->CR2 = SPI_CR2_RXNEIE | SPI_CR2_FRXTH
| SPI_CR2_DS_2 | SPI_CR2_DS_1 | SPI_CR2_DS_0; /* (1) */
SPI2->CR1 |= SPI_CR1_SPE; /* (2) */

A.14.3 SPI full duplex communication

if ((SPI1->SR & SPI_SR_TXE) == SPI_SR_TXE) /* Test Tx empty */

{
/* Will inititiate 8-bit transmission if TXE */
*(__IO uint8_t *)&(SPI1->DR) = SPI1_DATA;
}

A.14.4 SPI interrupt

if ((SPI1->SR & SPI_SR_RXNE) == SPI_SR_RXNE)

{
SPI1_Data = (uint8_t)SPI1->DR; /* receive data, clear flag */
/* Process */
}

A.14.5 SPI master configuration with DMA

/* (1) Master selection, BR: Fpclk/256 (due to C27 on the board, SPI_CLK is
set to the minimum)
CPOL and CPHA at zero (rising first edge) */
/* (2) TX and RX with DMA,
enable slave select output,
enable RXNE interrupt,
select 8-bit Rx fifo */
/* (3) Enable SPI1 */
SPI1->CR1 = SPI_CR1_MSTR | SPI_CR1_BR; /* (1) */
SPI1->CR2 = SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN | SPI_CR2_SSOE
| SPI_CR2_RXNEIE | SPI_CR2_FRXTH
| SPI_CR2_DS_2 | SPI_CR2_DS_1 | SPI_CR2_DS_0; /* (2) */
SPI1->CR1 |= SPI_CR1_SPE; /* (3) */

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A.14.6 SPI slave configuration with DMA

/* nSS hard, slave, CPOL and CPHA at zero (rising first edge) */
/* (1) Select TX and RX with DMA,
enable RXNE interrupt,
select 8-bit Rx fifo */
/* (2) Enable SPI2 */
SPI2->CR2 = SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN
| SPI_CR2_RXNEIE | SPI_CR2_FRXTH
| SPI_CR2_DS_2 | SPI_CR2_DS_1 | SPI_CR2_DS_0; /* (1) */
SPI2->CR1 |= SPI_CR1_SPE; /* (2) */

A.15 USART code examples

A.15.1 USART transmitter configuration

/* (1) Oversampling by 16, 9600 baud */

/* (2) 8 data bit, 1 start bit, 1 stop bit, no parity */
USART1->BRR = 480000 / 96; /* (1) */
USART1->CR1 = USART_CR1_TE | USART_CR1_UE; /* (2) */

A.15.2 USART transmit byte

/* Start USART transmission */

USART1->TDR = stringtosend[send++]; /* Will inititiate TC if TXE is set*/

A.15.3 USART transfer complete

if ((USART1->ISR & USART_ISR_TC) == USART_ISR_TC)

{
if (send == sizeof(stringtosend))
{
send=0;
USART1->ICR |= USART_ICR_TCCF; /* Clear transfer complete flag */
}
else
{
/* clear transfer complete flag and fill TDR with a new char */
USART1->TDR = stringtosend[send++];
}
}

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Code examples RM0360

A.15.4 USART receiver configuration

/* (1) oversampling by 16, 9600 baud */

/* (2) 8 data bit, 1 start bit, 1 stop bit, no parity, reception mode */
USART1->BRR = 480000 / 96; /* (1) */
USART1->CR1 = USART_CR1_RXNEIE | USART_CR1_RE | USART_CR1_UE; /* (2) */

A.15.5 USART receive byte

if ((USART1->ISR & USART_ISR_RXNE) == USART_ISR_RXNE)

{
chartoreceive = (uint8_t)(USART1->RDR); /* Receive data, clear flag */
}

A.15.6 USART synchronous mode

/* (1) Oversampling by 16, 9600 baud */

/* (2) Synchronous mode
CPOL and CPHA = 0 => rising first edge
Last bit clock pulse
Most significant bit first in transmit/receive */
/* (3) 8 data bit, 1 start bit, 1 stop bit, no parity
Transmission enabled, reception enabled */
USART1->BRR = 480000 / 96; /* (1) */
USART1->CR2 = USART_CR2_MSBFIRST | USART_CR2_CLKEN
| USART_CR2_LBCL; /* (2) */
USART1->CR1 = USART_CR1_TE | USART_CR1_RXNEIE
| USART_CR1_RE | USART_CR1_UE; /* (3) */
/* Polling idle frame Transmission w/o clock */
while ((USART1->ISR & USART_ISR_TC) != USART_ISR_TC)
{
/* add time out here for a robust application */
}
USART1->ICR |= USART_ICR_TCCF; /* Clear TC flag */
USART1->CR1 |= USART_CR1_TCIE; /* Enable TC interrupt */

764/775 RM0360 Rev 5

RM0360 Code examples

A.15.7 USART DMA

/* (1) Oversampling by 16, 9600 baud */

/* (2) Enable DMA in reception and transmission */
/* (3) 8 data bit, 1 start bit, 1 stop bit, no parity, reception and
transmission enabled */
USART1->BRR = 480000 / 96; /* (1) */
USART1->CR3 = USART_CR3_DMAT | USART_CR3_DMAR; /* (2) */
USART1->CR1 = USART_CR1_TE | USART_CR1_RE | USART_CR1_UE; /* (3) */
/* Polling idle frame Transmission */
while ((USART1->ISR & USART_ISR_TC) != USART_ISR_TC)
{
/* add time out here for a robust application */
}
USART1->ICR |= USART_ICR_TCCF; /* Clear TC flag */
USART1->CR1 |= USART_CR1_TCIE; /* Enable TC interrupt */

A.15.8 USART hardware flow control

/* (1) oversampling by 16, 9600 baud */

/* (2) RTS and CTS enabled */
/* (3) 8 data bit, 1 start bit, 1 stop bit, no parity, reception and
transmission enabled */
USART1->BRR = 480000 / 96; /* (1) */
USART1->CR3 = USART_CR3_RTSE | USART_CR3_CTSE; /* (2) */
USART1->CR1 = USART_CR1_TE | USART_CR1_RXNEIE
| USART_CR1_RE | USART_CR1_UE; /* (3) */
/* Polling idle frame Transmission */
while ((USART1->ISR & USART_ISR_TC) != USART_ISR_TC)
{
/* add time out here for a robust application */
}
USART1->ICR |= USART_ICR_TCCF; /* Clear TC flag */
USART1->CR1 |= USART_CR1_TCIE; /* Enable TC interrupt */

A.16 WWDG code examples

A.16.1 WWDG configuration

/* (1) Set prescaler to have a roll-over each about 5.5ms,

set window value (about 2.25ms) */
/* (2) Refresh WWDG before activate it */
/* (3) Activate WWDG */
WWDG->CFR = 0x60; /* (1) */
WWDG->CR = WWDG_REFRESH; /* (2) */
WWDG->CR |= WWDG_CR_WDGA; /* (3) */

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765
Important security notice RM0360

Important security notice

The STMicroelectronics group of companies (ST) places a high value on product security,
which is why the ST product(s) identified in this documentation may be certified by various
security certification bodies and/or may implement our own security measures as set forth
herein. However, no level of security certification and/or built-in security measures can
guarantee that ST products are resistant to all forms of attacks. As such, it is the
responsibility of each of ST's customers to determine if the level of security provided in an
ST product meets the customer needs both in relation to the ST product alone, as well as
when combined with other components and/or software for the customer end product or
application. In particular, take note that:
• ST products may have been certified by one or more security certification bodies, such
as Platform Security Architecture (www.psacertified.org) and/or Security Evaluation
standard for IoT Platforms (www.trustcb.com). For details concerning whether the ST
product(s) referenced herein have received security certification along with the level
and current status of such certification, either visit the relevant certification standards
website or go to the relevant product page on www.st.com for the most up to date
information. As the status and/or level of security certification for an ST product can
change from time to time, customers should re-check security certification status/level
as needed. If an ST product is not shown to be certified under a particular security
standard, customers should not assume it is certified.
• Certification bodies have the right to evaluate, grant and revoke security certification in
relation to ST products. These certification bodies are therefore independently
responsible for granting or revoking security certification for an ST product, and ST
does not take any responsibility for mistakes, evaluations, assessments, testing, or
other activity carried out by the certification body with respect to any ST product.
• Industry-based cryptographic algorithms (such as AES, DES, or MD5) and other open
standard technologies which may be used in conjunction with an ST product are based
on standards which were not developed by ST. ST does not take responsibility for any
flaws in such cryptographic algorithms or open technologies or for any methods which
have been or may be developed to bypass, decrypt or crack such algorithms or
technologies.
• While robust security testing may be done, no level of certification can absolutely
guarantee protections against all attacks, including, for example, against advanced
attacks which have not been tested for, against new or unidentified forms of attack, or
against any form of attack when using an ST product outside of its specification or
intended use, or in conjunction with other components or software which are used by
customer to create their end product or application. ST is not responsible for resistance
against such attacks. As such, regardless of the incorporated security features and/or
any information or support that may be provided by ST, each customer is solely
responsible for determining if the level of attacks tested for meets their needs, both in
relation to the ST product alone and when incorporated into a customer end product or
application.
• All security features of ST products (inclusive of any hardware, software,
documentation, and the like), including but not limited to any enhanced security
features added by ST, are provided on an "AS IS" BASIS. AS SUCH, TO THE EXTENT
PERMITTED BY APPLICABLE LAW, ST DISCLAIMS ALL WARRANTIES, EXPRESS
OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, unless the
applicable written and signed contract terms specifically provide otherwise.

766/775 RM0360 Rev 5

RM0360 Revision history

Revision history

Table 118. Document revision history

Date Revision Changes

23-Sep-2013 1 Initial release

Extended the applicability to STM32F070x6/xB and
STM32F030x4/x6/x8/xC.
13-Jan-2015 2 Added Chapter 30: Universal serial bus full-speed
device interface (USB) and reviewed the content of most
chapters.
Renamed TIM16 and TIM17 in the table TIMx internal
trigger connection in the section General purpose timer
(TIM15/16/17).
Updated Table 85: STM32F0x0 USART implementation
for STM32F070xB.
Added Section Appendix A: Code examples.
Updated:
– Bit 8 (DBP) description of PWR_CR register in
Section 6.4.1: Power control register (PWR_CR),
– TIM1_ARR reset value in Section 16.4.12: TIM1 auto-
reload register (TIM1_ARR),
– Bit 3 (TE) description of USART_ISR and Bit 21
description of USARTx_ISR in Section 26.8.8:
Interrupt and status register (USART_ISR).
– Bit SMS description for encoder mode 1 and encoder
19-May-2015 3
mode 2 and added the last note in SMS bit description
in Section 16.4.3: TIM1 slave mode control register
(TIM1_SMCR), Section 17.4.3: TIM2 and TIM3 slave
mode control register (TIM2_SMCR and
TIM3_SMCR) and Section 19.5.3: TIM15 slave mode
control register (TIM15_SMCR)
– the description of ETF bits in Section 16.4.3: TIM1
slave mode control register (TIM1_SMCR) and
Section 17.4.3: TIM2 and TIM3 slave mode control
register (TIM2_SMCR and TIM3_SMCR).
– the description of IC1F[3:0] bits in Section 16.4.7:
TIM1 capture/compare mode register 1
(TIM1_CCMR1), Section 17.4.7: TIM2 and TIM3
capture/compare mode register 1 (TIM2_CCMR1 and
TIM3_CCMR1) and Section 19.5.7: TIM15
capture/compare mode register 1 (TIM15_CCMR1).

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771
Revision history RM0360

Table 118. Document revision history

Date Revision Changes

– Section: Option bytes - note and description

CRC
– Feature list
RCC
– Section: RTC domain control register (RCC_BDCR) -
bit field LSEDRV
GPIO
– Section: GPIO alternate function low register
(GPIOx_AFRL) (x = A to D, ) and other AF registers -
AFR renamed to AFSEL
DMA
Section: DMA interrupt flag clear register (DMA_IFCR) -
bit description
Interrupt
– Table: Vector table - removed “(combined with EXTI
line 28)” from row position 29
– Section: External and internal interrupt/event line
mapping - line 23 reserved
– Section: Interrupt mask register (EXTI_IMR) - MRx
bits renamed to IMx
– Section: Event mask register (EXTI_EMR) - MRx bits
renamed to EMx
– Section: Rising trigger selection register
24-Apr-2017 4 (EXTI_RTSR) - TRx renamed to RTx and FTx; RT31
added
– Section: Software interrupt event register
(EXTI_SWIER) - SWIERx renamed to SWIx; SWI31
added
– Section: Pending register (EXTI_PR) - PRx renamed
to PIFx; PIF31 added
ADC
– Section: ADC voltage regulator (ADVREGEN) -
calibration software procedure
– Section: ADC on-off control (ADEN, ADDIS, ADRDY)
- modified
– Section: Starting conversions (ADSTART) and
corresponding bit description
– Section Temperature sensor and VREFINT channel
block diagram - added paragraphs
TIM1
– Section: Using the break function
TIM3
– removed redundant table before Table: TIM3 internal
trigger connection
– Section: TIM3 auto-reload register (TIM3_ARR) reset
value
– corrected Table: TIM3 register map and reset values

768/775 RM0360 Rev 5

RM0360 Revision history

Table 118. Document revision history

Date Revision Changes

TIM6/TIM7
– Section: TIM6/TIM7 auto-reload register (TIMx_ARR)
reset value
TIM15/16/17
– Section: Using the break function - break function
– corrected Section: TIMx auto-reload register
(TIMx_ARR)(x = 16 to 17)
IWDG
– added Section: Behavior in Stop and Standby modes
– Section: IWDG status register (IWDG_SR)
RTC
– Section: RTC block diagram - figures
– Section Programming the wakeup timer
– Section: Resetting the RTC
– Section: Calibration clock output
– Section: RTC interrupts - EXTI replaced with NVIC
– Section: RTC control register (RTC_CR) bits SUB1H
and ADD1H; added caution at the end
– Section: RTC initialization and status register
(RTC_ISR) bit WUTWF
I2C
24-Apr-2017 4 – Table: STM32F0x0 I2C implementation
– Table: Comparison of analog vs. digital filters
– Figure: Slave initialization flow
– Section: I2C timings - multiple additions
– Section: I2C master mode - information on
STM32CubeMX
– Section: Master communication initialization (address
phase) - information on 10-bit addressing mode
– Section: Control register 2 (I2C_CR2) - bit START -
information on 10-bit addressing mode, and bit fields
SADD and ADDRCF
USART
– Table: STM32F0x0 USART features
– Section: USART functional description - removed 1.5
stop bits
– Table: Effect of low-power modes on the USART
– Table: USART interrupt requests
– Figure: USART interrupt mapping diagram
– Section: USART control register 1 (USART_CR1)
– Section: USART control register 2 (USART_CR2)
– Section: USART control register 3 (USART_CR3)

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771
Revision history RM0360

Table 118. Document revision history

Date Revision Changes

– Section: USART interrupt and status register

(USART_ISR)
– Section “Guard time and prescale register” removed
– Table: USART register map and reset values
Section “USART smartcard code example” removed
SPI
– Table: STM32F0x0 SPI implementation
– Section: Communications between one master and
one slave - NSS pin
– Section: Half-duplex communication
– Section Simplex communications
– Section: Multimaster communication
– Section: Configuration of SPI - point 1b
– Section: CRC calculation
– Section: SPI control register 1 (SPIx_CR1) bit MSTR
24-Apr-2017 4 – Section: SPI Rx CRC register (SPIx_RXCRCR) and
Section: SPI Tx CRC register (SPIx_TXCRCR) - bits
15:0
Debug
– Table: DEV_ID and REV_ID field values added
Appendix
– Section: Alternate function selection sequence code
example
– Section: ADC calibration code example
– Section: ADC enable sequence code example
– Section: ADC disable sequence code example
– Section: Analog watchdog code example
– Section: Temperature computation code example
– Section: DMA burst feature code example
– Sections “USART smartcard mode code example”
and “USART IrDA mode code example” removed

770/775 RM0360 Rev 5

RM0360 Revision history

Table 118. Document revision history

Date Revision Changes

Cover page
– Introduction
Document conventions
– Section 1.1: General information added
– Section 1.2: List of abbreviations for registers
System and memory overview
– Section 2.3: Embedded SRAM
– Section 2.5: Boot configuration
RCC
– Figure 10: Clock tree (STM32F030x4, STM32F030x6
and STM32F030x8 devices) and Figure 11: Clock tree
(STM32F070x6, STM32F070xB and STM32F030xC)
– Section 7.4.2: Clock configuration register
(RCC_CFGR)
SYSCFG
– Section 9.1.1: SYSCFG configuration register 1
(SYSCFG_CFGR1)
ADC
– Section 12.3.5: Configuring the ADC
– Section 12.8: Temperature sensor and internal
reference voltage
09-May-2023 5 TIM
– Section 17: General-purpose timers (TIM15/16/17)
RTC
– Section 21.4: RTC functional description
I2C
– section Enabling and disabling the peripheral
USART
– Table 86: STM32F0x0 USART features
– section How to derive USARTDIV from USART_BRR
register values
– section Transmission using DMA
– Section 23.7.7: USART interrupt and status register
(USART_ISR) bits ORE and FE
Code examples
– Section A.4.2: Alternate function selection sequence
– Section A.6.1: NVIC initialization
– Section A.7.6: Continuous conversion sequence -
software trigger
– Section A.7.8: Continuous conversion sequence -
hardware trigger
Other
– section Important security notice added

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Index RM0360

Index

A G
ADC_CCR . . . . . . . . . . . . . . . . . . . . . . . . . . .223 GPIOx_AFRH . . . . . . . . . . . . . . . . . . . . . . . . 139
ADC_CFGR1 . . . . . . . . . . . . . . . . . . . . . . . . .216 GPIOx_AFRL . . . . . . . . . . . . . . . . . . . . . . . . 138
ADC_CFGR2 . . . . . . . . . . . . . . . . . . . . . . . . .220 GPIOx_BRR . . . . . . . . . . . . . . . . . . . . . . . . . 139
ADC_CHSELR . . . . . . . . . . . . . . . . . . . . . . . .221 GPIOx_BSRR . . . . . . . . . . . . . . . . . . . . . . . . 137
ADC_CR . . . . . . . . . . . . . . . . . . . . . . . . . . . .214 GPIOx_IDR . . . . . . . . . . . . . . . . . . . . . . . . . . 136
ADC_DR . . . . . . . . . . . . . . . . . . . . . . . . . . . .222 GPIOx_LCKR . . . . . . . . . . . . . . . . . . . . . . . . 137
ADC_IER . . . . . . . . . . . . . . . . . . . . . . . . . . . .212 GPIOx_MODER . . . . . . . . . . . . . . . . . . . . . . 134
ADC_ISR . . . . . . . . . . . . . . . . . . . . . . . . . . . .211 GPIOx_ODR . . . . . . . . . . . . . . . . . . . . . . . . . 136
ADC_SMPR . . . . . . . . . . . . . . . . . . . . . . . . . .220 GPIOx_OSPEEDR . . . . . . . . . . . . . . . . . . . . 135
ADC_TR . . . . . . . . . . . . . . . . . . . . . . . . . . . . .221 GPIOx_OTYPER . . . . . . . . . . . . . . . . . . . . . . 134
GPIOx_PUPDR . . . . . . . . . . . . . . . . . . . . . . . 135
C
CRC_CR . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 I
CRC_DR . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72 I2C_CR1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 575
CRC_IDR . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 I2C_CR2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 577
CRC_INIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74 I2C_ICR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 585
I2C_ISR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 583
I2C_OAR1 . . . . . . . . . . . . . . . . . . . . . . . . . . . 579
D
I2C_OAR2 . . . . . . . . . . . . . . . . . . . . . . . . . . . 580
DBGMCU_APB1_FZ . . . . . . . . . . . . . . . . . . .716 I2C_PECR . . . . . . . . . . . . . . . . . . . . . . . . . . . 586
DBGMCU_APB2_FZ . . . . . . . . . . . . . . . . . . .718 I2C_RXDR . . . . . . . . . . . . . . . . . . . . . . . . . . . 587
DBGMCU_CR . . . . . . . . . . . . . . . . . . . . . . . .715 I2C_TIMEOUTR . . . . . . . . . . . . . . . . . . . . . . 582
DBGMCU_IDCODE . . . . . . . . . . . . . . . . . . . .708 I2C_TIMINGR . . . . . . . . . . . . . . . . . . . . . . . . 581
DMA_CCRx . . . . . . . . . . . . . . . . . . . . . . . . . .164 I2C_TXDR . . . . . . . . . . . . . . . . . . . . . . . . . . . 587
DMA_CMARx . . . . . . . . . . . . . . . . . . . . . . . . .168 IWDG_KR . . . . . . . . . . . . . . . . . . . . . . . . . . . 472
DMA_CNDTRx . . . . . . . . . . . . . . . . . . . . . . . .166 IWDG_PR . . . . . . . . . . . . . . . . . . . . . . . . . . . 473
DMA_CPARx . . . . . . . . . . . . . . . . . . . . . . . . .167 IWDG_RLR . . . . . . . . . . . . . . . . . . . . . . . . . . 474
DMA_IFCR . . . . . . . . . . . . . . . . . . . . . . . . . . .163 IWDG_SR . . . . . . . . . . . . . . . . . . . . . . . . . . . 475
DMA_ISR . . . . . . . . . . . . . . . . . . . . . . . . . . . .161 IWDG_WINR . . . . . . . . . . . . . . . . . . . . . . . . . 476
DMA1_CSELR . . . . . . . . . . . . . . . . . . . . . . . .168
P
E
PWR_CR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
EXTI_EMR . . . . . . . . . . . . . . . . . . . . . . . . . . .177 PWR_CSR . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
EXTI_FTSR . . . . . . . . . . . . . . . . . . . . . . . . . .178
EXTI_IMR . . . . . . . . . . . . . . . . . . . . . . . . . . . .177
EXTI_PR . . . . . . . . . . . . . . . . . . . . . . . . . . . .179 R
EXTI_RTSR . . . . . . . . . . . . . . . . . . . . . . . . . .177 RCC_AHBENR . . . . . . . . . . . . . . . . . . . . . . . 110
EXTI_SWIER . . . . . . . . . . . . . . . . . . . . . . . . .179 RCC_AHBRSTR . . . . . . . . . . . . . . . . . . . . . . 118
RCC_APB1ENR . . . . . . . . . . . . . . . . . . . . . . 113
RCC_APB1RSTR . . . . . . . . . . . . . . . . . . . . . 108
F
RCC_APB2ENR . . . . . . . . . . . . . . . . . . . . . . 111
FLASH_ACR . . . . . . . . . . . . . . . . . . . . . . . . . .59 RCC_APB2RSTR . . . . . . . . . . . . . . . . . . . . . 107
FLASH_CR . . . . . . . . . . . . . . . . . . . . . . . . . . .61 RCC_BDCR . . . . . . . . . . . . . . . . . . . . . . . . . 115
FLASH_KEYR . . . . . . . . . . . . . . . . . . . . . . . . .59 RCC_CFGR . . . . . . . . . . . . . . . . . . . . . . . . . 101
FLASH_OPTKEYR . . . . . . . . . . . . . . . . . . . . .60 RCC_CFGR2 . . . . . . . . . . . . . . . . . . . . . . . . 119
FLASH_SR . . . . . . . . . . . . . . . . . . . . . . . . . . . .61

772/775 RM0360 Rev 5

RM0360 Index

RCC_CFGR3 . . . . . . . . . . . . . . . . . . . . . . . . .120 TIM1_EGR . . . . . . . . . . . . . . . . . . . . . . . . . . 281

RCC_CIR . . . . . . . . . . . . . . . . . . . . . . . . . . . .104 TIM1_PSC . . . . . . . . . . . . . . . . . . . . . . . . . . . 292
RCC_CR . . . . . . . . . . . . . . . . . . . . . . . . . . . .100 TIM1_RCR . . . . . . . . . . . . . . . . . . . . . . . . . . 292
RCC_CR2 . . . . . . . . . . . . . . . . . . . . . . . . . . .121 TIM1_SMCR . . . . . . . . . . . . . . . . . . . . . . . . . 275
RCC_CSR . . . . . . . . . . . . . . . . . . . . . . . . . . .116 TIM1_SR . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280
RTC_ALRMAR . . . . . . . . . . . . . . . . . . . . . . . .511 TIM14_ARR . . . . . . . . . . . . . . . . . . . . . . . . . . 398
RTC_ALRMASSR . . . . . . . . . . . . . . . . . . . . .521 TIM14_CCER . . . . . . . . . . . . . . . . . . . . . . . . 396
RTC_CALR . . . . . . . . . . . . . . . . . . . . . . . . . .517 TIM14_CCMR1 . . . . . . . . . . . . . . . . . . . 394-395
RTC_CR . . . . . . . . . . . . . . . . . . . . . . . . . . . . .504 TIM14_CCR1 . . . . . . . . . . . . . . . . . . . . . . . . 398
RTC_DR . . . . . . . . . . . . . . . . . . . . . . . . . . . . .502 TIM14_CNT . . . . . . . . . . . . . . . . . . . . . . . . . . 397
RTC_ISR . . . . . . . . . . . . . . . . . . . . . . . . . . . .507 TIM14_CR1 . . . . . . . . . . . . . . . . . . . . . . . . . . 391
RTC_PRER . . . . . . . . . . . . . . . . . . . . . . . . . .509 TIM14_DIER . . . . . . . . . . . . . . . . . . . . . . . . . 392
RTC_SHIFTR . . . . . . . . . . . . . . . . . . . . . . . . .513 TIM14_EGR . . . . . . . . . . . . . . . . . . . . . . . . . 393
RTC_SSR . . . . . . . . . . . . . . . . . . . . . . . . . . .512 TIM14_OR . . . . . . . . . . . . . . . . . . . . . . . . . . . 399
RTC_TAFCR . . . . . . . . . . . . . . . . . . . . . . . . .518 TIM14_PSC . . . . . . . . . . . . . . . . . . . . . . . . . . 398
RTC_TR . . . . . . . . . . . . . . . . . . . . . . . . . . . . .501 TIM14_SR . . . . . . . . . . . . . . . . . . . . . . . . . . . 393
RTC_TSDR . . . . . . . . . . . . . . . . . . . . . . . . . .515 TIM15_ARR . . . . . . . . . . . . . . . . . . . . . . . . . . 444
RTC_TSSSR . . . . . . . . . . . . . . . . . . . . . . . . .516 TIM15_BDTR . . . . . . . . . . . . . . . . . . . . . . . . 446
RTC_TSTR . . . . . . . . . . . . . . . . . . . . . . . . . .514 TIM15_CCER . . . . . . . . . . . . . . . . . . . . . . . . 441
RTC_WPR . . . . . . . . . . . . . . . . . . . . . . . . . . .512 TIM15_CCMR1 . . . . . . . . . . . . . . . . . . . 438-439
RTC_WUTR . . . . . . . . . . . . . . . . . . . . . . . . . .510 TIM15_CCR1 . . . . . . . . . . . . . . . . . . . . . . . . 445
TIM15_CCR2 . . . . . . . . . . . . . . . . . . . . . . . . 445
TIM15_CNT . . . . . . . . . . . . . . . . . . . . . . . . . . 444
S
TIM15_CR1 . . . . . . . . . . . . . . . . . . . . . . . . . . 430
SPIx_CR1 . . . . . . . . . . . . . . . . . . . . . . . . . . .663 TIM15_CR2 . . . . . . . . . . . . . . . . . . . . . . . . . . 431
SPIx_CR2 . . . . . . . . . . . . . . . . . . . . . . . . . . .665 TIM15_DCR . . . . . . . . . . . . . . . . . . . . . . . . . 448
SPIx_CRCPR . . . . . . . . . . . . . . . . . . . . . . . . .669 TIM15_DIER . . . . . . . . . . . . . . . . . . . . . . . . . 434
SPIx_DR . . . . . . . . . . . . . . . . . . . . . . . . . . . .668 TIM15_DMAR . . . . . . . . . . . . . . . . . . . . . . . . 449
SPIx_RXCRCR . . . . . . . . . . . . . . . . . . . . . . .669 TIM15_EGR . . . . . . . . . . . . . . . . . . . . . . . . . 437
SPIx_SR . . . . . . . . . . . . . . . . . . . . . . . . . . . . .667 TIM15_PSC . . . . . . . . . . . . . . . . . . . . . . . . . . 444
SPIx_TXCRCR . . . . . . . . . . . . . . . . . . . . . . . .669 TIM15_RCR . . . . . . . . . . . . . . . . . . . . . . . . . 445
SYSCFG_CFGR1 . . . . . . . . . . . . . . . . . . . . .142 TIM15_SMCR . . . . . . . . . . . . . . . . . . . . . . . . 432
SYSCFG_CFGR2 . . . . . . . . . . . . . . . . . . . . .147 TIM15_SR . . . . . . . . . . . . . . . . . . . . . . . . . . . 435
SYSCFG_EXTICR1 . . . . . . . . . . . . . . . . . . . .144 TIMx_ARR . . . . . . . . . . . . . . . . . . . 359, 378, 461
SYSCFG_EXTICR2 . . . . . . . . . . . . . . . . . . . .145 TIMx_BDTR . . . . . . . . . . . . . . . . . . . . . . . . . . 462
SYSCFG_EXTICR3 . . . . . . . . . . . . . . . . . . . .145 TIMx_CCER . . . . . . . . . . . . . . . . . . . . . 357, 458
SYSCFG_EXTICR4 . . . . . . . . . . . . . . . . . . . .146 TIMx_CCMR1 . . . . . . . . . . . . 283, 353, 455-456
TIMx_CCMR2 . . . . . . . . . . . . . . . . . . . . 286, 356
T TIMx_CCR1 . . . . . . . . . . . . . . . . . . . . . . 360, 462
TIMx_CCR2 . . . . . . . . . . . . . . . . . . . . . . . . . . 360
TIM1_ARR . . . . . . . . . . . . . . . . . . . . . . . . . . .292 TIMx_CCR3 . . . . . . . . . . . . . . . . . . . . . . . . . . 360
TIM1_BDTR . . . . . . . . . . . . . . . . . . . . . . . . . .295 TIMx_CCR4 . . . . . . . . . . . . . . . . . . . . . . . . . . 362
TIM1_CCER . . . . . . . . . . . . . . . . . . . . . . . . . .288 TIMx_CNT . . . . . . . . . . . . . . . . . . . 359, 377, 461
TIM1_CCR1 . . . . . . . . . . . . . . . . . . . . . . . . . .293 TIMx_CR1 . . . . . . . . . . . . . . . . . . . 343, 375, 450
TIM1_CCR2 . . . . . . . . . . . . . . . . . . . . . . . . . .293 TIMx_CR2 . . . . . . . . . . . . . . . . . . . . . . . 345, 452
TIM1_CCR3 . . . . . . . . . . . . . . . . . . . . . . . . . .294 TIMx_DCR . . . . . . . . . . . . . . . . . . . . . . . 362, 464
TIM1_CCR4 . . . . . . . . . . . . . . . . . . . . . . . . . .295 TIMx_DIER . . . . . . . . . . . . . . . . . . 348, 376, 452
TIM1_CNT . . . . . . . . . . . . . . . . . . . . . . . . . . .291 TIMx_DMAR . . . . . . . . . . . . . . . . . . . . . 363, 465
TIM1_CR1 . . . . . . . . . . . . . . . . . . . . . . . . . . .272 TIMx_EGR . . . . . . . . . . . . . . . . . . . 352, 377, 454
TIM1_CR2 . . . . . . . . . . . . . . . . . . . . . . . . . . .273 TIMx_PSC . . . . . . . . . . . . . . . . . . . 359, 378, 461
TIM1_DCR . . . . . . . . . . . . . . . . . . . . . . . . . . .297 TIMx_RCR . . . . . . . . . . . . . . . . . . . . . . . . . . . 462
TIM1_DIER . . . . . . . . . . . . . . . . . . . . . . . . . .278 TIMx_SMCR . . . . . . . . . . . . . . . . . . . . . . . . . 346
TIM1_DMAR . . . . . . . . . . . . . . . . . . . . . . . . .298

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Index RM0360

TIMx_SR . . . . . . . . . . . . . . . . . . . 349, 377, 453

U
USART_BRR . . . . . . . . . . . . . . . . . . . . . . . . .628
USART_CR1 . . . . . . . . . . . . . . . . . . . . . . . . .620
USART_CR2 . . . . . . . . . . . . . . . . . . . . . . . . .623
USART_CR3 . . . . . . . . . . . . . . . . . . . . . . . . .626
USART_ICR . . . . . . . . . . . . . . . . . . . . . . . . . .633
USART_ISR . . . . . . . . . . . . . . . . . . . . . . . . . .630
USART_RDR . . . . . . . . . . . . . . . . . . . . . . . . .634
USART_RQR . . . . . . . . . . . . . . . . . . . . . . . . .629
USART_RTOR . . . . . . . . . . . . . . . . . . . . . . . .628
USART_TDR . . . . . . . . . . . . . . . . . . . . . . . . .635
USB_ADDRn_RX . . . . . . . . . . . . . . . . . . . . . .701
USB_ADDRn_TX . . . . . . . . . . . . . . . . . . . . . .700
USB_BCDR . . . . . . . . . . . . . . . . . . . . . . . . . .694
USB_BTABLE . . . . . . . . . . . . . . . . . . . . . . . .693
USB_CNTR . . . . . . . . . . . . . . . . . . . . . . . . . .687
USB_COUNTn_RX . . . . . . . . . . . . . . . . . . . .701
USB_COUNTn_TX . . . . . . . . . . . . . . . . . . . .700
USB_DADDR . . . . . . . . . . . . . . . . . . . . . . . . .692
USB_EPnR . . . . . . . . . . . . . . . . . . . . . . . . . .695
USB_FNR . . . . . . . . . . . . . . . . . . . . . . . . . . .692
USB_ISTR . . . . . . . . . . . . . . . . . . . . . . . . . . .689
USB_LPMCSR . . . . . . . . . . . . . . . . . . . . . . . .693

W
WWDG_CFR . . . . . . . . . . . . . . . . . . . . . . . . .482
WWDG_CR . . . . . . . . . . . . . . . . . . . . . . . . . .481
WWDG_SR . . . . . . . . . . . . . . . . . . . . . . . . . .482

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RM0360

IMPORTANT NOTICE – READ CAREFULLY

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Information in this document supersedes and replaces information previously supplied in any prior versions of this document.

© 2023 STMicroelectronics – All rights reserved

RM0360 Rev 5 775/775

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