Scribd
Upload
21 views

CS102401 - Computer System Architecture and Microprocessor

Uploaded by

manglamdubey2011
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
21 views

CS102401 - Computer System Architecture and Microprocessor

Uploaded by

manglamdubey2011
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 2

CS102401

th
B.Tech.-4 Semester Examination Apr-May 2022
Branch: [CSE, CSE (AI), CSE (AIML), CSE (DS), CSE (IOT),
CSE (IOT&CSBCT), CSE (GT), CSE (BDA)]
Course: Computer System Architecture and Microprocessor

Maximum Marks: 100


Time Allowed: 3 Hours Minimum Marks: 35

_____________________________________________
Note: (i) Attempt all questions. Part (a) from each question is compulsory and carries 4 marks; attempt any two parts from part
(b), (c) and (d) carrying 8 marks each.
Q. No Questions Marks CO BL PI
Q.1 a) Discuss Data, address and Control bus. 4 CO1 L3 1.1.1

b) An instruction is stored at location 300 with its address


field at location 301. The address field has value 400, a
processor register RI contain the number 200. Evaluate
effective address if the addressing modes of the 8 CO1 L3 1.1.1
instruction are -
(i) direct (ii) immediate (iii) relative (iv) register
indirect.
c) Evaluate the arithmetic statement: X = (A+B)*(T+Q)
Using three address instruction and two address 8 CO1 L3 1.1.1
instruction.
d) Differentiate between hardwired and micro
8 CO1 L3 1.1.1
programmed control unit.
Q.2 a) Discuss guard bits and rounding. 4 CO2 L3 1.1.1

b) Divide 8 by 3 using non restoring division method. 8 CO2 L3 1.1.1

c) Multiply each of the following pairs of signed 2's


complement numbers using the Booth algorithm. In
each case, assume that A is the multiplicand and B is 8 CO2 L6 1.4.1
the multiplier.
A=(-8) and B (-14)
d) Design and implement Fast Adder. 8 CO2 L6 1.1.2

Q.3 a) (i) Which of the following required least access time?


a) back storage b) disk c) main memory d) cache

(ii) Which of the following have largest space?


a) back storage b) disk c) main memory d) cache

(iii) Memory interleaving is related to-


a) Consecutive words in a module 4 CO3 L4 1.1.2

b) Consecutive words in consecutive modules

(iv) Full form of ABR & DBR are-


a)address byte register and data buffer resistor
b) address buffer register and buffer resistor
c) address buffer register and buffer register
d) address buffer register and data buffer register
b) Define interrupts. Explain poling in details. 8 CO3 L3 1.3.1
c) What is direct memory access technique? Explain the
8 CO3 L3 1.3.1
rate of DMA controller with diagram.
d) Explain virtual memory in details. 8 CO3 L3 1.3.1

Q.4 a) Discuss various types of parallel architecture in brief. 4 CO4 L3 1.3.1

b) Consider the execution of the program of 15000


instructions a linear pipeline processor with a clock rate
of 25 MHz Assume that the instruction pipeline has 5
8 CO4 L4 1.1.2
stages and that one instruction is issued per clock cycle.
Calculate-
(i) speed up factor (ii) efficiency (iii) throughput
c) Draw and explain flow chart and timing diagram for
8 CO4 L3 1.3.1
the four-segment instruction pipeline.
d) Write short notes on-
(i) Vector Processor 8 CO4 L3 1.3.1
(ii) Array Processor
Q.5 a) Explain the flag register of 8085 microprocessor with
4 CO5 L3 1.3.1
neat diagram.
b) Explain read and write cycle timing diagram of 8086.
8 CO5 L3 1.3.1
Also draw proper diagram.
c) Explain 80386 processor using its registers, memory
8 CO5 L3 1.3.1
system and signal description.
d) Give comparison among core i3, core i5 and core i7
8 CO5 L3 1.3.1
processor.
CO- Course Outcomes, BL– Bloom’s Taxonomy Levels, PI– Performance Indicator

**********************

You might also like