IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS-I1 ANALOG AND DIGITAL SIGNAL PROCESSING, VOL. 43, NO.

OL. 43, NO. 12, DECEMBER 1996 785

High Performance CMOS Current

Comparator Design
Giuseppe Palmisano and Gaetano Palumbo, Member, ZEEE

Abstruct- The paper describes some design aspects in the [30]. In order to achieve a fast time response the current
implementation of CMOS current comparators. More specifi- comparator using a nonlinear positive feedback was proposed
cally, techniques for offset and charge-injection compensations [21], [22]. Unfortunately, positive feedback applied at the input
are discussed in detail, and some basic topologies for compensated
current comparators are presented and compared by SPICE intrinsically leads to a lower sensitivity which, in turn, means
simulations. Moreover, a novel compensated fully differential a low speed with low input levels. This approach also has
current comparator is proposed which achieves a very high other drawbacks which reduce the comparator performance.
performance. It provides a sensitivity as low as 20 nA and a The input resistance is heavily dependent on the input signal
switching time better than 30 ns with a 0.5 pA input step current and no control exists on the bias current, whose effect can
while dissipating 45 pW.
greatly increase power dissipation, especially in some process
conditions. Moreover, speed and sensitivity are drastically
I. INTRODUCTION reduced if input signal generators with a relatively low internal

C URRENT-MODE signal processing in CMOS technol- resistance are used. An improved nonlinear positive feedback
ogy has received great interest in recent years [1]-[5]. solution was proposed in [23]. However, its performance is
Adopting this approach, small area and low power dissipation still strongly dependent on process tolerances. Other solutions
analog circuits have been designed which seem particularly to increase speed in comparators were proposed in [24].
interesting because they can be implemented with digital An alternative solution to increase sp
processes and reduced power supply voltages. Moreover, many parators adopts the prebiasing' technique [25]. Prebiasing was
signal sources in temperature sensors, photo-sensors, etc., also adopted in the switched-current comparator reported in
provide current signals and current Schmitt Triggers have often [24], but the authors' solution in [25] uses only one switch
been designed to detect them [6]-[9]. In these applications and is more efficient since it initially sets the output at half
and in other current-mode circuits such as AID converters, the supply voltage rather than the supply voltage. Comparators
oscillators, current to frequency converters, neural networks, can be further improved in terms of speed and sensitivity by
etc. [lo]-[ 191 the current comparator is a fundamental building using the double folded-cascode configuration [29], which is
block. based on common-gate stages instead of current-mirror stages.
The original CMOS current comparator has been proposed Another important parameter of a comparator is accuracy,
in [20]. It is based on the simple current mirror and can be which is principally affected by offset. It is usually due
improved by using cascoded structures. The main limitation of to matching tolerances of current mirrors. The first offset-
this circuit lies in the absence of an appropriate input branch. compensated current comparator was proposed in [26], but its
Due to this, parameters such as input resistance and input bias implementation is quite complicated. A general technique for
voltage, which greatly determine the comparator performance, offset compensation was presented in [27] and requires only
are not controlled unless an additional bias current is used. a switched transconductance stage (for example a simple in-
A solution to achieve a controlled design is that of using an verter). This approach has, however, the drawback of reducing
appropriate input stage. At present, the best solution seems the gain of the whole comparator. Moreover, since it uses a
to be the class AB source-coupled stage proposed in [25] clocked switch, the accuracy is limited by a residual offset due
and [29]. This stage provides an accurate input-current and to the charge-injection error. A less general offset technique
input-resistance control and a good input bias voltage control. which does not reduce the comparator gain was presented in
One of the most important requirements of comparators is [28]. It can easily include a charge-injection compensation to
fast time response. The main limitation to the time response increase accuracy even further [29].
in most current comparators comes from the output branch In this paper design strategies for high-performance current
which is unbalanced at the beginning of the comparation phase. comparators are discussed. More specifically, basic offset
For example, in the original current-mirror comparator one of compensation techniques are reviewed and further improved
the two output transistors is often in the triode region before in order to increase accuracy. Moreover, according to the
comparation due to the high impedance of the output node suggested design strategies a novel fully differential current
Manuscript received July 31, 1995; revised February 14, 1996. This paper
comparator is presented. It achieves a high speed and is well
was recommended by Associate Editor C. Toumazou.
The authors are with the Dipartimento Elettrico Elettronico e Sistemistico, Prebiasing means setting the operating point properly before comparation
Universit6 di Catania, 1-95125 Catania, Italy. in order to put the circuit in the best working condition at the beginning of
Publisher Item Identifier S 1057-7130(96)07636-7. the transient response.

1057-7130/96$05.00 0 1996 IEEE

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186 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS-I1 ANALOG AND DIGITAL SIGNAL PROCESSING, VOL 43, NO 12, DECEMBER 1996

controlled in terms of input resistance, input bias voltage, and

input and output bias current.
11. OFFSETCOMPENSATION
The first offset-compensated current comparator was pro-
posed in [26],but the approach is quite complicated and cannot
easily be extended to other topologies. Subsequently, two more
general offset-compensation techniques were proposed which
can easily be applied to different comparator architectures. I
They use an addtional compensation circuit which is embed-
ded in parallel or in series in the uncompensated comparator. In
the following these two compensation techniques are discussed
together with the circuit arrangements needed to achieve uncompensated ’I
compensation for the charge-injection error as well. compensation circuit
comparator

A. First Approach: Parallel-Connected Compensation Circuit

A first solution for offset compensation is schematically
illustrated in Fig. l(a). It uses a compensation circuit based on I
I
a hold capacitor, C H ,a switch, SA, and a transconductance I

stage whose output is connected in parallel to the uncompen-

sated comparator, In order to discuss the circuit behavior, the
uncompensated comparator has been represented by a unity-
gain current amplifier with an output resistance r,1 and an
input offset current Iosl. The transconductance stage in the
compensation circuit is characterized by a transconductance
gain gm an output resistance r02 and an input offset voltage
Vasa.Assuming as an initial condition switch S A to be open
and capacitor CH to be discharged, the output offset voltage
V,, of the overall circuit is uncompensated I compensation circuit
comparator
K s +
= T J , , ~gmroKs2 (1)
(b)
where r, is the equivalent output resistance
VDD
ro = ~ o l / l r , p . (2)
The equivalent offset current to the comparator input is

When switch SA is closed, the transconductance stage is

connected in a unity-gain configuration and the output offset
voltage Vas,becomes

(4) I I
VSS
where term g m r o is the loop-gain of the feedback transconduc-
(c)
tance stage. When switch S A turns off. voltage V,,,is stored
in capacitor CH thus maintaining its value in the output node. Fig 1 Current comparator using the parallel-connected offset compensation
circuit (a) Block diagram without charge-injection compensatlon. (b) Block
The equivalent offset current I,,, to the comparator input is diagram with charge-injection compensation (c) Circuit implementation with
now given by charge-injection compensation.

vo,,
Io,, = - N - - Io,
(5) course, cascode transconductance stages have to be used with
TO gmro
cascode-mirror or folded-cascoded comparators.
Therefore, despite the additional offset component due to
the compensation circuit, a very low input offset current is
achieved. Actually, the overall offset current before compen- B. Charge-tnjection Compensation
sation Io, is reduced by a stage gain. It is apparent that the The offset compensation topology in Fig. l(a) is affected by
input signal has to be fed after switch S A is opened. a charge-injection error. Indeed, when switch S A is opened a
In order to preserve the simplicity of the original compara- portion AQ of its channel charge is pushed into CH,giving
tor, an inverter can be used as the transconductance stage rise to an uncompensated residual offset. The charge-injection
whose input capacitance provides the storage element. Of offset can be included in the input offset current by simply
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PALMISANO AND PALUMBO: CMOS CURRENT COMPARATOR DESIGN 787

modifying ( 5 ) into

where AV,,, which is given by

is the offset voltage at the input of the transconductance stage

due to the charge injection.
The charge AQ injected into CH depends on the total
amount of the switch channel charge, the shape of the clock
edges, and the ratio between the capacitances at the switch
terminals [31], [32]. In order to reduce it, common remedies
are the use of a CMOS switch, a larger capacitance C H ,and/or
the use of a dummy switch. T I E in Secs

A more efficient charge-injection compensation technique is Fig. 2. Charge-injection simulation for the circuit in Fig. 1. 1) Without
to adopt a differential-input transconductance stage as shown compensation 2) With compensation.
in Fig. l(b) [33]. Indeed, since switches SA1 and SA2 have
equal voltages at their terminals, if we assume a clock phase comparator would be needed. However, such a requirement is
with very sharp edges, the charges injected into C H I and c H 2 hard to satisfy especially when cascode comparators are used.
are approximately equal, regardless of the impedance at the An alternative but less general approach to offset compen-
switch terminals. Therefore, if capacitors CHI and C H are ~ sation which does not affect the comparator gain is shown in
equal, the injected charges do not affect the comparator output, Fig. 3(a). It was first introduced in [28] and then optimized
since they give rise to a common mode signal which is rejected in [29] for both offset and charge-injection compensation. The
by the differential transconductance stage. technique is based on a feedback loop which includes a switch
A circuit implementation of the compensation circuit in SA, a voltage gain stage block A, and a current generator
Fig. l(b) for the current-mirror comparator is illustrated in transistor M A , which belongs to the output branch of the
Fig. l(c). In order to validate the charge-injection compen- uncompensated comparator. This approach is quite similar to
sation, the circuit was simulated by means of SPICE using the parallel solution in Fig. l(a), but here the transconductance
minimum area CMOS switches. The simulation results are element, which is performed by transistor M A , is in series
illustrated in Fig. 2. They were obtained without an input with the output branch. Thus, unlike the parallel solution, the
signal and considering only an input offset current of 0.4 ,LLA output impedance of the original comparator is now preserved.
and the charge-injection error. Looking at Fig. 2, curve 1 refers As far as offset performance is concerned, the analysis of
to the circuit without charge-injection compensation (i.e., the circuit in Fig. l(a) can easily be extended to the series-
without c H 2 and SA2, and with the gate of M 6 to ground), connected compensation circuit provided that the transconduc-
while curve 2 refers to the circuit with charge-injection com- tance g m in (3) and (5) is replaced by the transconductance
pensation. In the first 20 ns the circuit is uncompensated and A, . gmA ( A , is the voltage gain of block A). Therefore, the
shows an output offset voltage which is forced by the input uncompensated and compensated equivalent offset currents to
offset current. During the time interval from 20 to 60 ns, the the comparator input are, respectively,
switches are closed and the offset is compensated. After 60 ns,
the switches are open and the charge-injection error occurs.
The simulation shows that this error is greatly reduced by the
Iosc (9)
compensation circuit. AogmAro
where Vos2is the input offset voltage of block A , and r, is the
C. Second Approach: Series-Connected Compensation Circuit equivalent output resistance of the uncompensated comparator.
Both the solutions in Fig. 1 can easily be arranged for Of course, the output branch of the uncompensated comparator
most current comparators, since the compensation circuit is in the series solution affects the loop performance when switch
connected in parallel to the output branch. This means that no S A is closed.
constraints have to be imposed on the frequency response of Block A can be implemented with a source follower since
the uncompensated comparator in order to guarantee stability, the gain gmATo is usually high enough to provide accurate
provided that the compensation circuit is stable. Unfortunately, offset compensation. Presently, the best implementation of the
using these solutions the overall comparator gain, and hence solution in Fig. 3(a) is the one based on the double folded-
the sensitivity, are reduced due to the reduction in the output cascode current comparator, as for example that shown in
resistance which is caused by the compensation circuit. In Fig. 3(b).
order to overcome this drawback, compensation circuits with The natural evolution of the series-connected compensation
an output resistance higher than that of the uncompensated circuit to achieve charge-injection compensation is shown in

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788 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS-I1 ANALOG AND DIGITAL SIGNAL PROCESSING, VOL 43, NO 12, DECEMBER 1996

vss Fig. 4. (a) Block diagram of a current comparator using the series-connected
(b) offset and charge-injection compensation cncuit (b) The double
folded-cascode current comparator using the series-connected offset
Fig. 3. (a) Block diagram of a current comparator using the series-connected and charge-injection compensation circuit.
offset compensation circuit (b) The double folded-cascode current comparator
using the series-connected offset compensation ciicuit.
capacitors C H I , and C N and~ the switches SA1 and SA2.
Thanks to the perfect symmetry of the circuit, the diode-
Fig. 4(a). Similarly to the solution in Fig. l(b) block A in
connected transistors MlOA,MlOB set the bias current in
Fig. 4(a) has been replaced by a differential stage. A circuit M 8 A and M8B to I ~ s / 2Moreover,. the gate-source voltage
implementation based on the double folded-cascode current
of M9 together with the gate-source voltage of M7 provide
comparator is shown in Fig. 4(b).
the output bias voltage.
When switches SA1 and SA2 are closed, the uncompen-
111. A HIGH-PERFORMANCE FULLY sated comparator and the compensation circuit are connected
DIFFERENTIAL COMPARATOR through two different loops, one for the differential signal,
A fully differential topology has the intrinsic advantages the other for the common-mode signal. When switches S A 1
of accuracy and power supply noise rejection. Moreover, the and SA2 are opened, the two loops are disconnected and the
availability of a differential input could be very useful in common-mode output level and the output offset voltage are
applications where the input is a floating source. In this section, both frozen in the hold capacitors. As far as the differential
a new high-performance fully differential current comparator loop is concerned, the circuit can be represented with a block
is presented which adopts most of the design arrangements diagram which is a differential version of the one in Fig. 3(a).
discussed in the previous sections. Hence, the charge injection is intrinsically compensated since
it appears as a common mode signal. The input offset current
A. Circuit Description after compensation is given by (9) provided that the transcon-
ductance gmA is substituted with that of transistors M8 and
The proposed comparator is shown in Fig. 5. It is based gain A, is defined as the differential gain of the compensation
on the double folded-cascode structure and includes a com- circuit (i.e., gmg/gmlo). Thus, the input offset current is given
pensation circuit which provides offset and charge-injection
by
compensation as well as common-mode output voltage control.
gm10
The uncompensated comparator is made up of transis- I,,,,Gi ___ -. I o s (10)
tors M3-M6 and current source transistors M 7 , M8. Diode- Sm9 g m 8 r o

connected transistors A41 and M 2 , and current sources I B ~ Setting bias currents I,, and I B to~ 1 p A and using a 5 V
and I B Z ,set the input bias current and the input bias voltage. power supply, the overall power dissipation is around 45 p W .
The offset compensation circuit is provided by the differ- A sensitivity simulation with a slowly varying triangular input
ential stage M9-Ml0, the current generator 1 ~ 3 the , storage current is shown in Fig. 6, where curve 1 is the input current
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PALMISANO AND PALUMBO: CMOS CURRENT COMPARATOR DESIGN 789

I
VDD I
I
I 1 I

M8B

vOl

M7B
I I I I
I
vss I
I
I
I
uncompensated
I compensation circuit
comparator
Fig. 5. Fully differential current comparator.

TABLE I

M1, M3A, M3B, M6A, M6B 312

M2, M4A, M4B, M5A, MSB, M8A, M8B, MlOA, MlOB 812
M7A, M7B, M9A, M9B 214 Y
CHI, CH? 1 pF
i
IBlr IRZ IpA
IR? 4pA
voo-vss 5v

secs

Fig. 6. Sensitivity simulation of the circuit in Fig. 5: 1) input current i r l ,

2) output response z1,1 - w,z.

Actually, we have also to consider the time required for the

offset compensation (or prebiasing), but this time is less than
8 ns as shown in Fig. 7.

IV. CONCLUSION
In this paper design strategies for improving the perfor-
mance of current comparators have been discussed which
mainly concern off set and charge injection compensation.
Moreover, a novel high-performance fully differential current
comparator has been presented which implements most of the
arrangements discussed.

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790 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS-11. ANALOG AND DIGITAL SIGNAL PROCESSING, VOL. 43, NO. 12, DECEMBER 1996

/I91 K. Current and J. Current, “CMOS current-mode circuits for neural

network,” in Proc. ISCAS 90, 1990.
4.80 4“
[20] D Freitas and K Current, “CMOS current comparator circuit,” Electron
Lett, vol 19, no 17, pp 695-697, Ang 1983
[21] H Traff, “Novel approach to high speed CMOS current comparators,”
Electron Lett, vol 28, no 3, pp 310-312, Jan 1992
-
c
0
2
2108
” ff [22] R Dominguez-Castro, A Rodriguez-Vazquez, F Medeiro, and J Huer-
tas, ‘Wgh resolution CMOS current comparators,” in Proc ESSCIRC
92, 1992
e A Tang and C Toumazou, “High performance CMOS current compara-
tor,” Electron Lett., vol 30, no 1, pp 5-6, Jan 1994
J Cmeira and J Franca, “High-speed CMOS current comparators,” in
-2.88 -2” Proc IEEE ISCAS’94, May 1994
G Palmsano, G Palumbo, and S Pennisi, “A high-accuracy, high-speed
CMOC cnrrent comparator,” in Proc IEEE ISCAS’94, 1994
C Wu, C Chen, M Tsa, and C Cho, “A 0 5 mA offset-free current
-4 .eo -4WN
comparator for high precision current-mode signal processing,” in Proc
ISCAS’91, 1991
40.W 129N 28oN 36W
G. Palmisano and G Palumbo, “An offset compensation technique
TINE in Secs
for CMOS current comparators,” Electron. Lett, vol 30, no 11, pp
Fig. 7. Time response of the circuit in Fig. 5. 1) Input step current 852-854, May 1994
Output response w,1 - v,q. G Di Cataldo, G Palmisano, G Palumbo, and S Penmsi, “An accurate
offset-compensated current comparator,” in Proc IEEE MDWST’94,
1994
1291 G Palmisano and G Palumbo, “Offset-compensated low power current
The proposed design need one or comparator,” Electron Lett, vol 30, no 20, pp 1637-1639, Sept 1994
switches. This, however, does not give rise to a real limitation, 1301 G palumbo. “CMOS Current comoarator slmohfied of the
since clock signals are usually needed by applications which delay-time,” Int J Circuit Theory Applicat , vol 22, no 2, pp 157-162,
Apr 1994
comparators [31] J Shieh, M Patil and R Shen “Measurement and analysis of charge
injection in MOS analog switches,” IEEE J Solid-State Circuits, vol
REFERENCES SC 22, pp 277-281, Apr 1987
1321 G Wegmann, E Vittoz, and F Rahali, ‘Charge injection in analog MOS
C Tomazou, F Lidgey, and D Hagh, Analogue IC Design The switches,” IEEE J Solid-State Circuits, vol SC-22, pp 1091-1 1097,
Current-Mode Approach U K IEE, 1990 Dec 1987
C Torndmu, J Hughes, and N Battersby, Snitched-Currents An Ana- [33] F Maloberti, G Palmisano, and G lorelli, “A novel approach for high-
logue Technique For Digital Technology U K IEE, 1993 frequency gain-compensated sample-and-hold circuits,” In Proc IEEE
Z Wang, “Current-mode CMOS integrated circuits for analog computa- ISCAS’94, May 1991
tion and signal processing A tutorial,” Int J Analog Integrated Circuits
Signal Processing, no 1, pp 287-295, 1991
__ , Current Mode Analog Integrated Cirruitr and Linmrization
Techniques in CMOS Technology Hartung-Gone Verlag Konstanz,
1990
M Ismal and T Fiesz, Analog VLSI Signal and Information Processing Giuseppe Palmisano was bom in Lampedusa, Italy,
New York McGraw-Hill, 1994 in 1956 He graduated in 1982 with a Laurea degree
Z Wang and W Guggenbthl, “Novel CMOS current schmitt tngger,” in electronics engineenng at the University of Pavia,
Electron Lett, vol 24, no 24, pp 15161516, Nov 1988 Italy
-, “CMOS current Schmitt trigger with fully adjustable hysteresis,” From 1983 to 1991 he conducted research with
Electron Lett, vol 25, no 6, pp 397-398, Mar 1989 the Department of Electronics, University of Pavia
G Di Cataldo and G Palumbo, “New CMOS current schmitt tngger,” in the field of CMOS and BiCMOS analog mte-
in Proc IEEE ISCAS’92, May 1992 grated circuits In 1992, he was a visiting professor
G Di Cataldo, G Palmisano, and G Palumbo “Low area accurate at UAM (Universidad Autonoma Metropolitana) in
CMOS current Schmitt tngger,” in Proc ECCTD’93, Sept 1993 Mexico City where he taught a course on mcro-
P Crolla, “A fast latching current comparator for 12-bit AID apphca- electronics for the doctoral students In 1993, he
hons,” IEEE J Solid State Circuits, vol SC-17, pp 1088-1093, Dec joined the Faculty of Enginccring of the University of Catania as Associate
1982 Professor He has contributed to the design of vanous integrated circuits for
J Robert, P Deval, and G Wegmann, “Novel CMOS pipelined A/D mobile radio communicahons systems in collaboration with Italtel and of
convertor architecture using- current mirrors. ’ Electron Lett, vol 25, several analog building blocks for A/D and D/A converters His research
pp. 691-692, May 1989. interests include current-mode analog circuits, low-voltage power amplifiers
D. Nairn and C. Salama, “Current-mode algorithmic analog-to-digital and, recently, bipolar RF circuits
converters,” IEEE J Solid-State Circuits, voi 25, pp 997-1004, i u g
1990
C P. Chong, “A technique for improving the accuracy and the speed
of CMOS current-cell DAC,” IEEE Trans Circuits Syst , vol. 37, pp
1325-1327, Oct 1990.
D. Nairn and C Salama, “A ratio-independent algorithmic analog-to- Gaetano Palumbo (M’91) was born in Catania,
digital converter combining current mode and dynamic techniques,” Italy, on September 11, 1964 He received the
IEEE Trans. Circuits Syst., vol 37, pp. 1325-1327, Oct 1990 laurea degree in electrical engineenng and the Ph D.
2 Wang, “Design methodology of CMOS algorithmic current A/D degree from the University of Catania in 1988 and
converters in view of transistor nusmatches,” IEEE Trans Circuits Syst , 1993, respectively In 1993, he conducted couses
vol 38, pp 660-667, June 1991 on electronic devices for the diploma degree in
S.-W. EOm and S -W. E m , “Current-mode cyclic ADC for low power electronics engineenng
and high speed applications,” Electron. Lett , vol 27, pp 818-820, May In 1994, be joined the Department of Electncal
1991 Electronics and System (DEES) of the University
C Wey, “Concurrent error detection in current-mode A/D convertors,” of Catania as a researcher His primary research
Electron Lett., vol. 27, no 25, pp 2370-2372, Dec. 1991 interest is analog circuit with particular emphasis
M Yamamoto, A Kobayashi, and Y Horio, “Switched current F/I and on compensation techniques, current-mode approach, low-voltage circ&.
I/F converters,” in Proc ECCTD-91, Sept 1991 Dr. Palumbo is a member of AEI.

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