Week 4: Course Material

Test Generation
Lecture 17

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 Test
Generation
D Introduction
D Random Test Generation
D Theoretical Foundations
D Deterministic Combinational ATPG
D Untestable Fault Identification
D Simulation-based ATPG
D ATPG for Delay and Bridge Faults
D Other Topics in Test Generation
D Concluding Remarks
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 Introducti
on
D Test generation is the bread-and-butter in VLSI
Testing
• Efficient and p
powerful ATPG can alleviate highg costs of DFT
• Goal: generation of a small set of effective vectors at a low
computational cost
D ATPG is a veryy challenging
g g task
• Exponential complexity
• Circuit sizes continue to increase (Moore’s Law)
– Aggravate
gg the complexity
p ypproblem further
• Higher clock frequencies
– Need to test for both structural and delay defects

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 Conceptual View of ATPG
D Generate an input vector that can distinguish
the defect-free circuit from the hypothetically
defective one

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 Fault
Models
D Instead of targeting specific defects,
fault models are used to capture the
logical effect of the underlying defect
D Fault models considered in this chapter:
• Stuck-at fault
• Bridging fault
• Transition fault
• Path-delay fault

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 Simple illustration of
ATPG
D Consider the fault d/1 in the defective circuit
D Need to distinguish the output of the defective
circuit from the defect-free circuit
D Need: set d=0
d 0 in the defect
defect-free
free circuit
D Need: propagate effect of fault to output
D Vector: abc=001 (output = 0/1)

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 A Typical ATPG System
D Given a circuit and a fault model
• Repeat
• Generate a test for each undetected fault
• Drop all other faults detected by the test using
a fault simulator
• Until all faults have been considered
D Note 1: a fault may be untestable, in which no
test would be generated
D Note 2: an ATPG mayy abort on a fault if the
resources needed exceed a preset limit

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 Random Test
Generation
D Simplest form of test generation
• N tests are randomly generated
D L
Level
l off confidence
fid on random
d ttestt sett T
• The probability that T can detect all stuck-at
faults in the g
given circuit
• Quality of a random test set highly depends on
the underlying circuit
• Some circuits have many random-resistant
random resistant faults

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 Weighted Random Test
Generation
D Bias input probabilities to target random
resistant faults
D Consider an 8-input AND gate
• Without biasing input probabilities, the prob of generating a
logic 1 at the gate output = (0.5)8 = 0.004
• If we bias the inputs to 0.75, then the prob of generating a
logic 1 at the gate output = (0.75)
(0 75)8 = 0.100
0 100
D Obtaining an optimal set of input probabilities
a difficult task
D Goal: increase the signal probabilities of hard-to-
test regions

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 Probability of Fault
Detection
D Given a circuit with n inputs
D Let Tf be the set of vectors that can
detect fault f
D Then is the prob that f can be
detected by a random vector
D Let be the prob that a random
vector cannot detect f

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 Prob of Fault Detection
(Cont.)
D Then, is the prob that N
random vectors do not detect f
D Thus, the prob that at least one out ofN
random vectors can detect f is

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 Minimum Detection
D
Probability
The min detection p
prob of anyy detectable fault actuallyy does not
depend on n, the num of PIs
D Instead, it depends on the largest primary-output cone that it is
in
D This is because anyy detectable fault must be excited and
sensitized to a primary output

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 Lemma
1
D In a combinational circuit with multiple
outputs, let nmax be the number of
primary inputs that can lead to a primary
output. Then, the detection probability
for the most difficult detectable fault,
fault
dmin, is:

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 Exhaustive Test
Generation
D Exhaustive Testing
• Apply 2n patterns to an n-input combinational circuit under
test (CUT)
• Guarantees all detectable faults in the combinational circuits
are detected
• Test time maybe be prohibitively long if the number of inputs
is large
• Feasible only for small circuits
D Pseudo-exhaustive Testing
• Partition circuit into respective cones
• Apply exhaustive testing only to each cone
• Still guarantees to detect every detectable fault based on
Lemma 1

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Week 4: Course Material

Test Generation (Contd

(Contd.))
Lecture 18
Theoretical Foundations: Boolean
Difference
D The function for the circuit is
D Let the target fault be y/0, then the function for the faulty circuit
is f’ = f(y=0)
D Goal of test generation: find a vector that makes f XOR ff’ = 1

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 Boolean Difference
Continued
D f XOR f’ = 1 iff f and f’ result in opposing
logic values
D Thus, any vector that can set f XOR f’=
1 is able to produce opposing values at
the outputs of the fault-free and faulty
circuits respectively
D Definition:

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 Boolean Difference
Example
D To excite the fault y/0,y=1
D Thus,

xyz= 110 or 011 can

detect the fault

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 Another
Example
D Let target fault bew/0

xyz=001, 101
can detect w/0

But:

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 A Third
Example
D Fault:z/0

This fault is untestable!

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 Wrap Up on Boolean
Difference
D Given a circuit with output f and fault
D The set of vectors that can detect this
fault includes all vectors that satisfy

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 Deterministic
ATPG
D In general, we don’t need an entire set of vectors
that can detect the target fault
D Instead, we just want to compute one vector quickly
D Rather than using Boolean Difference that can
obtain all vectors
• Simply use a branch-and-bound search to find one vector
quickly
i kl
D Deterministic ATPG has two main goals
• Excite the target fault
• Propagate
P t the
th corresponding
di ffaultlt effect
ff t to
t an output
t t

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 5‐valued
5 valued Algebra for
Comb. Circuits
D Instead of using two circuits (fault-free and
the faulty)
• We will solve the ATPG problem on one single
circuit
D To do so, every signal value must be able to
capture fault-free
fault free and faulty values
simultaneously
D 5-Value Algebra: 0, 1, X, D, D-bar
• D: 1/0
• D-bar: 0/1

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Boolean Operators on 5‐Valued
Algebra

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 Decision Tree for Branch-and-Bound
Search
D The ATPG systematically and implicitly searches the
entire search space

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 Backtrackin
g
D The ATPG searches one branch at a time
D Whenever a conflict (e.g., all D’s disappeared)
arises,
i mustt backtrack
b kt k on previousi d i i
decisions

If d=1
d 1 also
l causes a conflict,
fli b backtrack
k k
to c=0

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 Basic ATPG for Fanout‐Free
Fanout Free
Circuits

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 The Justify
Routine

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 Exampl
e
Fault: g/0

The recursive calls to JustifyFanoutFree():

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 The Propagate
Routine

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Week 4: Course Material

Test Generation
Lecture 19
 Example
Continued
Propagate fault-effect
from g to z

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 D
Algorithm
D Can handle arbitrary combinational
circuits, with internal fanout structures
D Main
M i idea:
id always
l maintain
i t i a non-empty t
D-frontier and try to propagate at least a
fault effect to a primary output
D Initially, all circuit nodes are X, except
for the fault cite,, where a fault effect ((D
or D-bar) is placed.

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 D‐Frontier
D Frontier and J‐
J
Frontier
D D-Frontier: All gates whose outputs are
X but has at least one D or D-bar at the
input of the gates
• Initially, the D-frontier consists of only 1
gate (output of the fault-site)
fault site)
D J-Frontier: All gates whose outputs are
specified by are not justified by the input
assignments
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 D-Frontier Example
D The D-frontier contains 2 gates

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 J-Frontier Example
D The J-Frontier contains 2 gates

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 Idea Behind D Algorithm
D To advance the fault-effects in the D-frontier,,
add nodes to the J-frontier to justify

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 D
Algorithm

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 D Algorithm
g Example
p

Target f stuck‐at‐0

Initialize all gates to X

Places D on line f
Propagate fault effect to z
Places a=1 in J‐frontier, followed by
h 0
h=0
Fault effect has reached primary output
Try to justify entries in J‐frontier
a is alreadyy jjustified as it is p
primaryy input
p
For f=D, d = 0, making c=0
For h=0, either e=0 or b=0 is sufficient
Test found.
 D Algorithm
Example

D Target fault: g/1

D Initially, D-Frontier: {h}, J-Frontier={g=D-bar}
D T advance
To d D
D-frontier,
f ti add dd f=1
f 1 and
d c=1
1 tto J-
J
frontier

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 D Algorithm Example
(Cont.)

D Now justify
N j tif every value
l iin J-Frontier
J F ti via i
branch-and-bound search
• Must not make D-frontier empty or conflict
with other JJ-frontier
frontier values
• Otherwise backtrack
D Result: g/1 is untestable
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 PODE
M
D Also a branch-and-bound search
D Decisions only on PIs
• No J-Frontier
J Frontier needed
• No internal conflicts
D D-frontier may still become empty
• Backtrack whenever D-frontier becomes
empty
• Backtrack also when no X-path exists from
any D/D-bar
D/D bar to a PO
D Decisions selected based on a backtrace
from the current objective
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 X‐
Path
D The D in the circuit has no path of X’s to any
PO
• i.e.,
i e the D is blocked by every path to any PO

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 Getting the
Objective

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 Multiple
Objectives

D Objectives: {k=0, m=1}

D Backtrace from k=0 may favor b=0,
b=0 but
simulate(b=0) would violate the second
objective m=1!
D Makes backtrace more intelligent to avoid
future conflicts

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 FIRE Example

D Impl[b=1] = {b=1, b1=1, b2=1, d=1, x=0, z=0}

D Faults unexcitable when b=1: {b/1,
{b/1 b1/1,
b1/1 b2/1,
b2/1
d/1, x/0, z/0}
D Faults unobservable when b=1: {a/0, a/1, e1/0,
e1/1,, yy/0,, y/1,
y , e2/0,, e2/1}}
D Faults undetectable when b=1: {a/0, a/1, b/1,
b1/1, b2/1, d/1,e1/0, e1/1, e2/0, e2/1, x/0, y/0,
y/1, z/0}
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 Pseudo Code for
GA

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 The Selection
Operator
D Roulette WheelSelection

D TournamentSelection

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 The Crossover
Operator
D One-pointcrossover

D Two-pointcrossover

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 Uniform Crossover
D The crossover is performed whenevera
mask bit is set

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 The Mutation
Operator
D Random flip of a bit position
D Need to keep p mutation rate small, so
that the search will not seem
randomized

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 GA Population
Size
D Should be a function of the individual size
D Larger individuals require larger populations
to allow for reasonable diversity
D Individual size depends on the number of PIs
in the circuit
• In sequential circuits, an individual may be
a sequence of vectors
D Generation Gap: p some individuals mayy be
carried over from one generation to the next

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 Number of GA
Generations
D Related to the populationsize
• Larger populations usually demand more
generations
• Generation gap also will affect the number
of generations needed to reach a
satisfactory solution

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 The Fitness
Function
D Measures the quality of the individual
D Essential for a GA to converge on a solution
D Example fitness functions:
• Number of faults detected by the individual
• Number of faults excited by the individual
• Number of flip-flops set to a specified value (in
seq ckts)
• A weighted sum of various factors

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