A CMOS image sensor for low light applications

Honghao Ji, Pamela A. Abshire

Department of Electrical and Computer Engineering, Institute for Systems Research
University of Maryland, College Park, Maryland 20742, USA
Email: {jhonghao, [email protected]}

Abstract- We describe and analyze a novel CMOS pixel for 3 V to near 0 V. However, since photocurrent is integrated
high speed, low light imaging applications. The new pixel achieves at the column level for each selected row, the frame rate is
lower dark current and noise and increased gain in comparison reduced by a factor of Nrow, the number of rows, compared
with conventional three-transistor, one-photodiode active pixel to that of a conventional APS given the same integration time.
sensors without sacrificing speed and scalability to large arrays.
It accomplishes this by biasing the photodiode of each pixel near In addition, the scalability of the pixel array is limited because
zero volts and by separating the photodiode from the floating all unselected pixels in each column contribute leakage current
diffusion integration node. An image sensor with a 256 x 256 to the column-level integration capacitor as well.
array of these pixels was designed for a commercially available
0.18 ,im CMOS technology. The pixel size is 5,im x 5,im with Vdd
a fill factor of 31%. The chip area is 3000,im x 3000,im. 1.8 :
V and 3.3 V power supplies are used for logic and sensor array,
respectively. Differential output and chip level correlated-double
sampling are used to suppress fixed pattern noise. Transmission Reset
gates with dummy transistors are incorporated into the readout
chain to reduce both clock feedthrough and charge injection. Nin
I. INTRODUCTION
The main challenges for CMOS imagers in industrial and
scientific applications are their relatively large dark current and
random noise, especially at low light. To increase both signal Row t
to noise ratio (SNR) and dynamic range (DR) of a CMOS V
image sensor, prior efforts focused on reduction of reset noise, Fig. 1. A conventional three transistor one photodiode pixel.
the dominant temporal noise component of an active pixel In this paper, a new CMOS image sensor structure is
sensor (APS), with significant improvement of performance proposed to achieve low dark current and low noise by biasing
[1]-[3]. Reduction of dark current mainly relies on specialized all photodiodes near zero volts. One additional transistor
CMOS imaging processes. Though dark currents less than is added to a conventional APS pixel, and photocurrent is
0.5nA/cm2 have been reported [4], the spatial distribution integrated in the pixel. Thus, it enables low dark current,
was non-uniform and not well-behaved. Pain et al. [5] suggest low noise, and good linearity while retaining the speed and
that dark current may set the ultimate noise limit in CMOS scalability of a conventional APS. Column level differential
imagers. sampling and chip level correlated double sampling (CDS)
Dark current of a CMOS APS pixel is mainly generated are performed to eliminate fixed pattern noise (FPN) due to
as leakage current from the reverse biased photodiode and threshold mismatches of transistors along the readout chain.
parasitic junctions. Previous work has shown that dark current The rest of this paper is organized as follows: section
increases significantly with increasing reverse bias voltage II briefly analyzes dark current related artifacts; section III
across the photodiode [6], [7]. Several techniques have been discusses the design and performance of the proposed pixel,
proposed for reducing dark current induced temporal and column and chip level readout; section IV shows simulation
spatial noise. In [8], a shielded dummy phototransistor was results to demonstrate the feasibility of the proposed structure;
added to compensate dark current of the phototransistor in and section V summarizes this work.
neighboring pixels. Since the bias conditions for the dummy
pixel and neighboring pixels differ, dark current can not be I ARTIFACTS INTRODUCED BY DARK CURRENT
sufficiently removed. The extra dummy pixel also degrades The schematic of a conventional three transistor one photo-
the imager's resolution. Wu et al. proposed a "pseudo-active- diode APS is shown in Figure 1. During the integration period,
pixel-sensor" structure, where each pixel includes only one the nplus/psub photodiode is usually reverse biased and the
switch transistor and one photodiode [9], like the passive pixel bias voltage decreases at a rate of ('ph + Idk) X tnCh
sensor first introduced by Weckler [10]. They demonstrated where Iph is the photocurrent, 'dkC is the dark current, tin
that the ratio of photo current to dark current increased by is the integration time, and Cph is the total capacitance at
nearly 40dB when the reverse bias voltage was reduced from the integration node Nin An artifact introduced by 'dk is

0-7803-9390-2/06/$20.00 ©2006 IEEE 1651 ISCAS 2006

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 Row sel

:Rst LM....lI
FD

------- F!

Vdd
I IR 1 I-,

+ '~~PDm 0

H IAMCM RIT

Fig. 2. Low dark current pixel along with chip-level circuits for generating
the common gate voltage for the entire pixel array.
the reduction of signal dynamic range. The temporal noise is
increased due to shot noise of the dark current, which has a
power spectral density of qldk. In addition, dark current intro-
duces spatial noise due to different reverse-bias voltages seen
by photodiodes in different pixels. Another artifact resulting Fig. 3. The layout of two neighboring pixels in one column.
from dark current is nonlinearity since the dark current varies and fill factor, a separate photodiode PDCM is used to
with bias voltage across the photodiode. The linearity is further generate a global bias voltage V,,,t for the gate of M2.
degraded since both 'ph and Cph change with the reverse bias The positive terminal of PDCM is connected to both ground
voltage across the photodiode as well. Dark current ldk mainly and the positive input of the feedback amplifier. The negative
arises from the surface and bulk leakage current of the reverse terminal of PDCM is connected to the source of common gate
biased nplus/psub diffusion area of the photodiode. By biasing transistor MCM and the negative input of the feedback ampli-
the photodiode near zero volts, all artifacts discussed above fier. The feedback loop is closed through MCM by connecting
can be significantly improved. the feedback amplifier's output to the gate of MCM. The drain
of MCM is directly connected to a 3.3V power supply. The
feedback amplifier has a single-stage folded-cascode structure
A. Pixel circuit and operation with p-type input transistors in order to operate at a common
Figure 2 shows the schematic of a low-dark-current pixel mode input voltage near OV. It has output swing from 0.3V
along with the chip level feedback amplifier that generates the to 2.5V, gain of 740 with common mode input as low as 0 V,
gate voltage for in-pixel common gate transistor M2. Similar and unity gain bandwidth of 440MHz.
pixel structures were previously reported. M2 is used as a The gate source voltage Vgs_CM of transistor MCM is
shutter switch in [11], so photocurrent integration occurs at determined by its drain current Ids_CM Since IdsOCM is
the same time in all pixels. Gonzalez et al. [12] used M2 as a normally on the order of pA or less, MCM operates in the
transfer gate, similar to the one used in a photogate pixel, so saturated subthreshold region. Therefore, its drain current can
that the reset signal can be sampled before the photovoltage in be expressed as: Ids_CM = 1o x (W/L) x exp (IVgS_CM/VT),
order to perform a true CDS. Kyomasu used M2 as a transfer where 1o is the characteristic current, W/L is the geometry
gate during integration to achieve high conversion gain and factor, K is the subthreshold slope factor, and VT is the thermal
good linearity, with the gate voltage of M2 generated off- voltage. VgS_M is equal to VOt- VSOM_ -(A +1) VScM,
chip. Kyomasu's pixel comprises more than seven transistors where A is the gain of the feedback amplifier. Thus, the source
and occupies an area of 35,um X 240,um [13]. voltage of MOM is given by
While the proposed pixel can be operated as mentioned in lm( Id C )VT
[11]-[13], the intention of this work is to bias the photodiode VSO (AI 1o/)(I
+
near 0 V in order to significantly reduce dark current andK
improve related artifacts. To achieve a reasonable pixel size Assuming IdsOCM =1PA, IO= 9.5aA, W/L =1.5,

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K = 2/3, and VT = 26mV, VSCM is about -0.59mV and operation without data interruption, an additional analog buffer
VC,,t, the output of feedback amplifier, is approximately equal stage is added to the column level sampling circuit. Therefore,
to 435mV. At this output level, the amplifier gain A actually while the data of one row stored in the second buffer are being
drops to around 220. However, VC,,t remains approximately read out column-wise, the signal and reset levels of pixels in
the same given that Vc,nt = -AVS_CM, where VS_CM is the next row are sampled and stored in the first buffer. When
around -2mV. the first column is selected again, signals for the next row are
If an in-pixel photodiode has a photocurrent greater than that transferred to the second buffer. MOS capacitors of 150fF
of PDCM, this photodiode will be forward biased because are used for both buffer stages. The signal swing range of
of the greater V9, of M2 in the same pixel. The photo 3.3V - Vth is maintained by alternately using n-type and p-
current will thus be partially cancelled by current flowing type source followers. The input transistor of the n-type source
from ground to the source of M2. In order to reduce the follower is implemented in a pwell isolated from the p-type
likelihood that the in-pixel photodiodes might become forward substrate using a deep nwell layer (DNW) and its source is
biased, PDMC is designed to have twice the area of an in- connected to the pwell body. Therefore, the n-type source
pixel photodiode. PDCM can also be implemented by several follower achieves good linearity as well. To reduce channel
photodiodes distributed around the pixel array in order to resistance and charge injection over the entire signal range,
faithfully represent the background illumination. transmission gates with dummy transistors for both NMOS
Since Vc,nt is a constant voltage for a given background and PMOS are used for sample and hold switches connected
illumination, the voltage across an in-pixel photodiode Vpd to storage capacitors.
will also be slightly influenced by the the voltage VFD
at the floating diffusion node (FD). As VFD decreases to IV. SIMULATION RESULTS AND CHIP LAYOUT
3VT from its reset level, the drain current of M2 can be Simulations confirm that the photodiode bias voltage will
expressed as Ids M2 = lo x (W/L) x eCp (KVgS-M2/VT) x (1- not vary significantly with the signal level at FD node. Figure
exp[-(VFD -Vpd)/VT]). For VFD - Vpd = VT, Vgs-M2 must 4 illustrates the source voltage of a common gate transistor
be increased by about 18mV relative to its original value when as a function of its drain voltage while the gate voltage and
VFD is at the reset level in order to maintain the same drain drain current are held constant. The bias voltage across the
current. Thus the bias across the photodiode will be decreased photodiode changes less than 20mV for a signal swing of
by the same amount. Under uniform background illumination, 1.8V. In a pixel, the drain current is the sum of photocurrent
the photocurrent of PDCM is twice the photocurrent of an and dark current, so it is expected to change slightly with the
in-pixel photodiode, so the reverse bias voltage of an in- source voltage of the common gate transistor M2; however,
pixel photodiode is about 27mV greater than that of PDCM. this simple model represents the predominant effects.
This helps to reduce the chance of any in-pixel photodiode The linearity of the analog signal chain including the in-
becoming forward biased. pixel source follower is also confirmed by simulation. In order
In addition to largely removing dark current and related to quantify nonlinear effects in the readout chain, the output
artifacts, input referred noise arising from the readout circuits of the analog readout is subtracted from the ideal output
is reduced due to the large conversion gain resulting from with unity gain (i.e. the input value) and normalized by the
the small capacitance CFD of the floating diffusion region. amplitude of the input signal. A linearity better than 98% is
The reset noise can be estimated from XkTCFD/2. A low achieved for input signals ranging from 0.3 V to 2.1 V as
reset noise of 7e- can be achieved with the CFD of 0.58fF shown in Figure 5.
extracted from the layout. Sampling errors due to charge injection and clock feed
In order to achieve good linearity, p-type transistors with through were also simulated. The offset between input and
separate nwells are used for the source follower input transistor sampled signal is shown in Figure 6 as a function of signal
Msf and row select transistor Mrse. The p-type source level from O.4V to 2.9V. A loading capacitor of 200fF is used
follower further increases the dynamic range by one Vth to account for the 150fF gate capacitance of MOS capacitor
in comparison with conventional APS. The layout of two and parasitic capacitances introduced by the subsequent source
neighboring pixels is shown in Figure 3, where row select follower and the switch itself. The offset for a transmission
transistors in the two neighboring pixels share the same nwell. gate and single channel switch with dummy transistor are also
The pixel has an area of 5,um x 5,um, with a fill factor of 31%. shown for comparison.
A chip level reset-assist circuit, similar to the one described in To save chip area, 1.8V minimum size transistors are used
[14], can be used to achieve the lower reset noise of soft reset for digital control blocks. A simple level shifter composed
without suffering the image lag associated with soft reset. of a source follower and an inverter is used as the interface
between control blocks and sensor array including pixel array
B. Column and chip level readout and column-wise readout. All 1.8V digital components are
A modified double delta sampling circuit (DDS) [15] is built in deep nwells and aseparate 3.3V power line is used for
adopted for the readout. The column level circuits comprise all level shifters. Thus, digital power and ground are separate
one p-type loading transistor and two branches for sampling from the analog power and ground in order to reduce coupling
and storing the signal and reset levels. To enable video mode noise from the digital components.

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 V. SUMMARY
A new pixel structure for CMOS imagers has been described
0.206
~~~~~~~~~~and
analyzed. By adding one common gate transistor between
0.204- the photodiode and integration
node in a conventional three
0.202 -transistor one photodiode APS, a very large conversion gain
5~ 0.2 -can be achieved regardless of the photodiode area. As a result,
both reset noise and input-referred read noise are significantly
0 ~~~~~~~~~~~~~~reduced.The gate voltage for all in-pixel common gate tran-
> 0.196 ~~~~~~~~~~sistors is generated on chip to bias all photodiodes near zero
0.194 ~~~~~~~~~~volts.Dark current and its relevant artifacts are expected to be
0.192 ~~~~~~~~~greatly improved. A modified DDS circuit is used to remove
the FPN due to mismatch in column drivers. Switches in
0.19~~~~~~~ ~~~the column readout circuits are carefully designed so that
0.38 05 07 09 11 13 15 17 19 21 charge injection and clock feedthrough noise are effectively
Vdrain (V) suppressed over the entire signal swing range. With reduced
noise and low dark current and good linearity, the image sensor
Fig. 4. Change in source voltage of a common gate transistor as a function is expected to be suitable for low-light applications.
of the drain voltage, where Id, lpA and Vg 0.5V.
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