THE VLSI DESIGN PROBLEM IC Design Hierarchy and Abstraction

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HIERARCHY AND ABSTRACTION

DESIGN HIERARCHY

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Y-Chart showing Design Domain Hierarchy DESIGN DOMAIN

Synthesis is defined as the transformation between different design abstraction levels.

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TopTop-Down Structural Design

Architectural synthesis Logic synthesis

Design views
Algorithm
Architectural synthesis
For i = 0 ; i = 15 sum = sum + data[I] i Data[0] Data[0] Data[15]

Architecture

Data[15] Sum Sum

Register level
Logic synthesis

Clear address Clock

MEM

Clear sum

Gate level

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Cell development (Analog/digital)

Schematic entry (transistor symbols) Analog simulation (SPICE models) Layout (layer definitions) Design Rule Checking, DRC ( design rules) Extraction (extraction rules and parameters) Electrical Rule Checking, ERC (ERC rules) Layout Versus Schematic, LVS Characterization: delay, setup, hold, loading sensitivity,etc. Generation of digital simulation model with back annotation.

Simulation
Simulates behavior of designed circuit Input: Models (transistor, gates) Textual netlist (schematic, extracted layout, behavioral) User defined stimulus Output: Circuit response (waveforms, patterns) Transistor level simulation using analog simulator (SPICE) Time domain Frequency domain Noise Gate level simulation using digital simulator Logic functionality Normally Timing: Operating frequency, delay, setup & hold violations same Timing calculator needed to calculate delays from extracted simulator parameters Functional simulation

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Gate level models

Border between transistor domain (analog) and digital domain Digital gate level models introduced to speed up digital simulation. Gate level model contains: Logic behavior Delays depending on: operating conditions, process, loading, signal slew rates Setup and hold timing violation checks Gate level model parameters extracted from transistor level simulations and characterization of real gates.
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Design Flow of ASIC

Design Specification Design Partition Verilog Behavioral Functional simulation Design Integration and Verification Presynthesis Sign-Off Gate level netlist
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Postsynthesis validation Timing verification Cell placement and routing DRC and ERC Extract Parasitics Design Sign-Off

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Postsynthesis Design Validation

Synthesis Behavioral description Gate level description Design Iteration

Design Flow of ASIC

Design Capture HDL Pre-Layout Simulation Logic Synthesis Structural or Gate level Behavioral

Testbench for postsynthesis design validation

Floorplanning Post-Layout Simulation Circuit Extraction Placement Routing Physical

Response Comparator Check Signal

Tape-out
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A High Level View of an Industry Standard Design Flow

HDL Entry good?

A More Accurate Picture of the Standard Flow

Architecture 10 months
Architecture: Partition the chip into functional units and generate bit-true test vectors to specify the behavior of each unit TOOLS: Matlab, C, SPW Front-End: Enter HDL code which matches the test vectors TOOLS: HDL Simulators, Design Compiler

Front Front-End

Synthesis good? Floor-plan Place & Route good? Physical Verification DRC & LVS good? done 15

Back-End

Front-End 10 months

Back-End: Create a floor-plan and tweak the tools until a successful mask layout is created TOOLS: Design Compiler, Floor-planners, Placers,
Routers, Clock-tree generators, Physical Verification

Back-End 2 months Fabrication 2 months

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A Uniprocessor implementation of a Generic function

IN
fsample

A Pipelined implementation of a generic function

IN
Nfsample

IN
f sample
Nfsample Nfsample

CLK Logic Function F(IN) IN OUT IN0 X IN1 OUT0 IN2 OUT1 IN3 OUT2 IN4 IN5
Logic Function F(IN)
fsample

. . .

Tsample

Nfsample Nfsample Nfsample

OUT3 OU

Tcritical-path=Tsample/N

fsample

High fsample can be achieved by either using a faster technology or by reducing the delay of the functional block by some transformations.

OUT

OUT

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A multi-processor implementation of a generic function

IN
Capacitance overhead REGN-2 Logic Function F(INN-2 ) MUX REGN-1 Logic Function F(INN-1 )

Implementation approaches
Digital Circuit Implementation Approaches

fsample

REG0 Logic Function Function F(IN0 )

REG1 Logic Function F(IN1 )

fsample

Full Custom
SEL

Semi-custom

Nfsample
Tsample/N
OUT

Capacitance overhead

Cell-based

Array-based

IN CLK 0 CLK 1 CLK N-1

IN0

IN1

INN-2

INN-1

INN

Pre-diffused (Gate Arrays)

Pre-wired (FPGA's)

Tsample

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OUT 0

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Impact of Implementation Choices

100-1000 Domain-specific processor (e.g. DSP) Energy Efficiency (in MOPS/mW) Embedded microprocessor

Hardware describing languages (HDL)

Describe behavior not implementation Make model independent of technology Model complete systems Speed up simulation of large systems High level Design is carried out at a level higher than the Gate level CAE tool independent

10-100

Configurable/Parameterizable

Hardwired custom

1-10

0.1-1

None

Somewhat flexible

Fully flexible

Flexibility (or application scope) 21 22 21

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Verilog HDL
Verilog Developed by Phil Moorby at Gateway Design Automation in 1984-85
Initailly Verilog was used for functional simulation using Verilog-XL Synopsys Design Compiler pushes HDL to the forefront of digital design In 1995, Verilog became an IEEE standard IEEE 1364-2001 is the latest standard

Verilog/VHDL
First real commercial HDL language from gateway automation (now Cadence) Default standard among chip designers for many years Initially proprietary language of Cadence. Now also an IEEE standard because of severe competition from VHDL. Result: multiple vendors

VHDL
Very High speed integrated circuit Description Language Initiated by American department of defense as a specification language. Standardized by IEEE
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Design Methodologies
Top level

Levels of Design abstraction

Verilog is both a behavioral and a structural language. Each Verilog module can be defined at four levels of abstraction depending upon the need of the design.

Block 1 Top-down Top-

Block 2

Block 3

Block 4 BottomBottom-up

Behavioral or algorithmic level Dataflow level Gate level Switch level The RTL description uses a combination of behavioral and dataflow constructs that is acceptable to the synthesis tool.
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Leaf cell

Leaf cell

Leaf cell

Leaf cell

Leaf cell

Leaf cell

Leaf cell

Leaf cell

In Verilog, the basic building block is the module.

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Components of a Verilog Module

Module Name, Port list, Port Declarations, Parameters Declarations of wires and regs e.g. wire w1, w2; reg k; Instantiation of lower level modules COMP U1 (w1,w2); or
COMP U2 (.P1(w1), .P2(w2));

module M (a,b,c,d); input c,d; output b; inout a; parameter x = 2; Dataflow statements (assign) always and initial blocks containing behavioral statements

Tasks and Functions endmodule

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Port Declarations for DFF

I
module DFF (q, d, clk, reset); output q; reg q; input d, clk, reset; // Comments endmodule endmodule

Port connection rules

net net input reg or net net inout output reg or net net

II
module DFF (output reg q, input d, clk, reset);

Fulladd fa(SUM, , A,B, C_IN);

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Connecting Ports to External Signals

Ordered list
module Top; reg [3:0] A,B; reg C_IN; wire [3:0] SUM; wire C_OUT; fulladd4 fa_ordered(SUM, C_OUT, A, B, C_IN); stimulus endmodule module fulladd4(sum,c_out, a, b, c_in); output [3:0] sum; output c_out; input [3:0] a, b; input c_in; module internals endmodule
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Hierarchical Names
module SR(Q, Qbar, Sbar, Rbar); output Q, Qbar; input Sbar, Rbar; nand n1(Q, Sbar, Qbar); nand n2(Qbar, Rbar, Q); endmodule module stimulus; wire q, qbar; reg set, reset; SR uut(.Q(q), .Qbar(qbar), .Sbar(~set), .Rbar(~reset)); ---------endmodule Hierarchical names : stimulus.q, stimulus.qbar, stimulus.set, stimulus.reset stimulus.uut.Q, stimulus.uut.Qbar, stimulus.uut.Sbar, stimulus.uut.Rbar,stimulus.uut.n1, stimulus.uut.n2

By name
module Top; reg [3:0] A,B; reg C_IN; wire [3:0] SUM; wire C_OUT; fulladd4 fa_name(.c_out(C_OUT), .sum(SUM), .a(A), .b(B), .c_in(C_IN)); stimulus endmodule module fulladd4(sum,c_out, a, b, c_in); output [3:0] sum; output c_out; input [3:0] a, b; input c_in; module internals endmodule 31 31

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Design Hierarchy
Stimulus (Root level)
Hierarchical names :

Gate level Modeling

A digital system is described in terms of gates
One-to-one correspondence between the logic circuit diagram and the Verilog description Verilog supports basic logic gates as predefined primitives(and, or, xor, nand, nor, xnor) These primitives are instantiated like modules except that they are predefined in Verilog Gates have one scalar output and multiple scalar inputs. The first terminal in the list of gates is always an output.
Basic gate instantiation:
and a1(OUT, IN1, IN2);

uut (SR)

stimulus.q, stimulus.qbar, stimulus.set, stimulus.reset stimulus.uut.Q, stimulus.uut.Qbar, stimulus.uut.Sbar, stimulus.uut.Rbar,stimulus.uut.n1, stimulus.uut.n2

n1 (nand)

n2 (nand)

There is a dot(.) for each level of hierarchy.

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Instantiation without instance name: and (OUT, IN1, IN2); Instantiation with more than two inputs: nand n1(OUT, IN1, IN2, IN3);
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Array of gate instances

wire [2:0] OUT, IN1,IN2; nand array_gate[2:0] (OUT, IN1, IN2); is equivalent to nand array_gate0 (OUT[0], IN1[0], IN2[0]); nand array_gate1 (OUT[1], IN1[1], IN2[1]); nand array_gate2 (OUT[2], IN1[2], IN2[2]);

Buf/Not gates
One scalar input and one or more scalar outputs. The last terminal in the port list is connected to the input.

buf b1(OUT1, IN1); not n1(OUT1, IN1); or not (OUT1, IN1);

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Bufif/notif
Additional control on buf and not gates
in ctrl bufif1 in ctrl bufif0 out in ctrl notif0 out in ctrl notif1 out out

4-bit Ripple Carry adder example

Sum= a xor b xor cin, cout = a.b + cin. (a xor b) 1-bit adder 4-bit adder
module fulladd(sum, cout, a, b, cin); output sum, cout; input a, b, cin; wire s1, c1, c2; xor (s1,a,b); and(c1,a,b); xor (sum, s1,cin); and(c2,s1,cin); xor(cout,c2,c1); endmodule module fulladd4(sum, cout, a ,b, cin); output [3:0]sum; output cout; input [3:0] a, b; input cin; wire c1,c2,c3; fulladd fa0(sum[0], c1, a[0],b[0], cin); fulladd fa1(sum[1], c2, a[1],b[1], c1); fulladd fa2(sum[2], c3, a[2],b[2], c2); fulladd fa3(sum[3], cout, a[3],b[3], c3); endmodule

module stimulus; reg[3:0] A, B; reg C_IN; wire [3:0] SUM; wire C_OUT; fulladd4 FA1(SUM, C_OUT, A, B, C_IN); initial begin $monitor($time, SUM= %b, SUM);end Initial begin A=0; B=0, C_IN=0; #10 A=3; B=4, C_IN=0; #5 $finish; end endmodule
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Gate Delays
There are three types of gates from the inputs to the output of a primitive gate: Rise Delay (w.r.t. the output) Fall Delay Turn-off delay (output transition to the high impedance state from another value) For each type of delay, three different values (min., typ., max.) can also be specified

and #(delay_time) a1 (out, i1, i2); and #(rise_time, fall_time) a1(out, i1, i2); and #(rise_time, fall_time, turnoff_val) a1 (out, i1, i2); bufif0 #(1,2,1) br (out, in, control);
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Delay example
module X(out, a, b, c); output out; input a, b, c; wire e; and #(5) a1(e, a, b); or #(4) o1(out, e, c); endmodule

Dataflow Modeling
Circuit is defined in terms of Dataflow between registers (in terms of expressions rather than gate connectivity)

Continuous assignments is the basic statement in dataflow modeling. It is used to drive a value onto a net.
syntax : assign [delay] = expression; LHS must be a scalar or vector net or their concatenation Continuous assignments are always active RHS operands can be registers or nets or function calls. Delay values can be specified on operands.

assign out = i1 & i2; assign addr[15:0] = addr1[15:0] ^addr2[15:0]; assign {c_out, sum[3:0]} = a[3:0] + b[3:0] +c_in;
(Concatenation)
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Implicit continuous assignment: wire out = in1 & in2; Only 42 one declaration assignment per net. 42

Delay incorporation
assign #delay out = i1 & i2; The output out will change after delay in response to the input signals rather than instantaneously. The expression is recomputed after delay for proper assignment.

Basic constituents of the RHS

1. Expressions: Constructs that combine operators and operands to produce results. ( a + b), in1 | in2 2. Operands: Can be constants, integers, real, nets, registers, times, bit-select, memories or function calls e.g. real a, b, c; integer count; count = count + 1; 3. Operators: acts on operands to produce results

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Operator types
1. Arithmetic: *, /, +, -, %(modulus),**(exponent) 2. Logical: !, &&, || 3. Relational: >, <, >=, <= 4. Equality: ==, !=, ===(case equality including x and z) , !== 5. Bitwise operators: ~, &, |, ^, ^~ or ~^ 6. Reduction: &, ~&, |, ~|, ^, ^~ or ~^ 7. Shift: >>, <<, >>> (Arithmetic right shift), <<< 8. Concatenation: { } 9. Replication: { { } } 10. Conditional: ?:

4-bit Full adder and Mux example

Gatelevel (structural)
module fulladd4(sum, cout, a ,b, cin); output [3:0]sum; output cout; input [3:0] a, b; input cin; wire c1,c2,c3; fulladd fa0(sum[0], c1, a[0],b[0], cin); fulladd fa1(sum[1], c2, a[1],b[1], c1); fulladd fa2(sum[2], c3, a[2],b[2], c2); fulladd fa3(sum[3], cout, a[3],b[3], c3); endmodule

Dataflow adder
module fulladd4(sum, cout, a ,b, cin); output [3:0]sum; output cout; input [3:0] a, b; input cin; assign {c_out, sum } = a + b + c_in; endmodule

Dataflow 2:1 MUX

module mux2(out, i0, i1, sel); output out; input i0, i1,sel; assign out = (sel & i1) | (~sel & i0); Or assign out = sel ? i1 : i0; endmodule

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Behavioral Modeling
Decisions early in the project w.r.t. the architecture for a given
algorithm. Design functionality can be described in an algorithmic manner (behavior) always and initial are the two structured procedure statements. All other behavioral statements can appear only inside these statements. always and initial are concurrent statements but the statements inside these two are sequential. Verilog is a concurrent language unlike C always and initial statements cannot be nested. Each statement starts at simulation time 0 and represents an activity flow.
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Initial statement
All statements inside an initial statement constitute an initial block. An initial block starts at time 0, executes exactly once during a simulation and then does not execute again. All initial blocks start executing concurrently at time 0. Each block finishes execution independent of other blocks. Multiple behavioral statements must be grouped using the keywords begin and end Initial blocks are used for initialisation, monitoring, waveform generation that must be executed only once during the simulation.

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Example
module stimulus; reg x, y, a, b, m; initial m = 1b0; initial begin #5 a = 1b1 ; #25 b = 1b0 ; end initial begin #10 x = 1b0; #25 y = 1b1; end initial #50 $finish; endmodule
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always statement
All behavioral statements inside an always statement constitute an always block. Starts at time 0 and executes the statements in the always block continuously in a looping fashion. Models a block of activity that is repeated continuously in a digital circuit.
Clock generator: module clock1(clock); output clock; reg clock; initial clock = 0; always #10 clock = ~clock; initial #1000 $finish; endmodule
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Time 0 5 10 30 35 50 m = 1b0; a = 1b1; x=1b0; b=1b0; y=1b1; $finish;

Combined Variable declaration and Initialisation: reg clock; initial clock = 0; Or reg clock = 0;

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Assignments
Continuous assignments assign values to nets (vector and scalar) They are triggered whenever simulation causes the value of the right-hand side to change Keyword assign e.g. assign out = in1 & in2; Procedural assignments drive values onto registers (vector and scalar)
They Occur within procedures such as always and initial They are triggered when the flow of execution reaches them (like in C) Blocking and Non-Blocking procedural assignments
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Procedural Assignments
For updating values of reg, integer, real, time variables The value placed on a variable will remain unchanged until another procedural assignment updates it to a different value. variable = [delay] expression LHS can be reg, integer, real, time variables RHS can be an expression that evaluated to a value.

Assignments (cont.)
Procedural Assignments
Blocking assignment statement (= operator) acts much like in traditional programming languages. The whole statement is done before control passes on to the next statement Nonblocking assignment statement (<= operator) evaluates all the right-hand sides for the current time unit and assigns the left-hand sides at the end of the time unit

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Assignments (cont.)
Assignments Example: reg [7:0] A, B; Initial

Ouput: begin Blocking: A=4 B=5 A = 3; #1 A = A + 1; Non-blocking: A=4 B=4 B = A + 1; $display(Blocking: A=%d B=%d:, A, B); A = 3; #1 A <= A + 1; B <= A + 1; end #1 $display(Non-blocking: A=%d B=%d, A, B);

endmodule

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More Examples
reg x, y, z; reg [15:0] reg_a, reg_b; integer count; Initial
begin x=0; y=1; z =1; count = 0; reg_a = 16b0; reg_b = reg_a; #15 reg_a[2] = 1b1; or reg_a[2] <= #15 1b1; #10 reg_b[15:13] = {x, y, z} ; or reg_b[15:13] <= #10 {x, y, z} ; count = count +1; end

Timing Control
Verilog is a discrete event time simulator. If there is no timing control, simulation time does not advance. Simulated time can only progress by one of the following:
a delay control, introduced by the # symbol. an event control, introduced by the @ symbol. the wait statement.

The order of execution of events in the same clock time may not be predictable.

endmodule
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Delay based Timing Control

Delay Control (#)
Expression specifies the time duration between initially encountering the statement and when the statement actually executes. Delay in Procedural Assignments
Inter-Statement Delay Intra-Statement Delay

EventEvent-Based Timing Control (cont.)

Events (@)
Change in the value of a register or net Used to trigger execution of a statement or block (reactive behavior/reactivity)

Types of Event-based timing control

Defer the entire execution till current time + 10 Evaluate the RHS at the current time and only the assignment is deferred by 63 10 time 63

For example:
Inter-Statement Delay

#10 A = A + 1;
Intra-Statement Delay

A = #10 A + 1;
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Regular event control Named event control Event OR control Level-sensitive timing control (wait statement)
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EventEvent-Based Timing Control (cont.)

Regular event control
Symbol: @(<event>) Events to specify:
posedge sig:
Change of sig from any value to 1 or from 0 to any value

EventEvent-Based Timing Control (cont.)

Regular event control Examples:
@reg_a begin A = B&C; end @(posedge clock1) A = B&C; @(negedge clock2) A = B&C; Forever @(negedge clock3) begin A = B&C; end
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negedge sig:
Change of sig from any value to 0 or from 1 to any value

sig: Any change in sig value

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EventEvent-Based Timing Control (cont.)

Named event control event x; always @(posedge clock) If(a) -> x always @(x)

EventEvent-Based Timing Control (cont.)

Event OR control
Used when need to trigger a block upon occurrence of any of a set of events. The list of the events: sensitivity list Verilog keyword: or

Event OR control Example:

always @ ( reset or clock )
begin if ( reset ) q= 1b0; else q= d; end

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Timing Control (cont.)

wait Statement
The wait statement allows a procedural statement or a block to be delayed until a condition becomes true. The difference between the behavior of a wait statement and an event is that the wait statement is level sensitive whereas @(posedge clock); is triggered by a signal transition or is edge sensitive. For Example:
wait (A == 3)
begin A = B&C; End
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Conditional statements
1. if(expression) true_statement; 2. if(expression) true_statement; else false_statement; 3. if(expression1) true_statement1; else if(expression2) true_statement2; else if(expression3) true_statement3; else default_statement;

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Shift Register

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Multiway branching
case (expression) alternative1: statement1; alternative2: statement2; default: default_statement; endcase
always @ (s1 or s0 or i0 or i1 or i2 or i3) case ({s1,s0}) 2d0 : out = i0; 2d1 : out = i1; 2d2 : out = i2; 2d3 : out = i3; default: $display(invalid); endcase
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Four Channel Multiplexer

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Loops
There are four types of looping constructs: 1. While while (count < 8) count = count + 1; 2. For for (count = 0; count < 8; count = count + 1; 3. Repeat repeat (8) count = count + 1; 4. Forever (infinite loop) forever #10 clock = ~clock;
8b 1111_0011

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8b 1111_0011

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Find_first_one

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Tasks and Functions

Used to break up large behavioral designs into smaller pieces Used when same functionality is required to be used at many places. Both must contain only behavioral statements. They are called from always or initial blocks or other tasks and functions. Tasks are used for the code that contains timing constructs or multiple outputs. Functions are used when the code is purely combinational, executes in 0 simulation time and has only one output.
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Tasks and Functions (cont.)

Functions always execute in zero simulation time Functions must not contain any delay, even or timing control statements Functions must have at least 1 input argument. They can have more than 1 input Functions always return a single value. They can not have output or inout arguments Tasks may execute in non zero simulation time. Tasks may contain delay, event or timing control statements Tasks may have 0 or more arguments of type input, output , inout Tasks dont return with a value but can pass multiple values through output & inout arguments

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Tasks and Functions (cont.)

task <task name>; <argument ports> <declarations> <statements> endtask To invoke a task: <name of task> (<port list>);
Complex RTL are structured using many always Use instead one always that enables several tasks
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Tasks and Functions (cont.)

module tasks task comp; // task definition input a, b; // two input argument ports output c; // one output argument port begin if (a == b) c = 1; else c = 0; end endtask

initial begin: init1 reg p; comp(1, 0, p); // invocation of task with 3 arguments $display("p= %b", p); end

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endmodule

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Tasks and Functions (cont.)

function <range or type> <function name>; <argument ports> <declarations> <statements> endfunction <range or type> is the type of results passed back to the expression where the function was called.

Tasks and Functions (cont.)

Module functions
function [1:1] comp; input a, b; // two input argument ports begin if (a == b) comp = 1; else comp = 0; end endfunction

initial begin: init1 reg p; p = comp(1, 0); // invocation of function with 2 arguments $display("p= %b", p); end

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endmodule
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System tasks (for routine operations)

$display : $display(Bus value is %b, bus); $time : Current simulation time $finish : To terminate the simulation $monitor : Records after every event in the signal list $stop : To suspend the simulation

System tasks (cont.)

Standard tasks to do routine operations; appear in form $<keyword> $display, $monitor (similar to printf in C programming) Format strings: %d, %b, %h, %e etc. $monitor is used to continuously monitors the values of variables and displays all parameters in list whenever value of any variable changes
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System tasks (cont.)

$stop is used to stop during simulation (suspend simulation) $finish is used to terminate simulation Compiler Directives: All are defined by using <keyword> e.g. define word_size 16, include, timescale 100ns/1ps (1,10,100 reference time unit/time precision)
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Useful system tasks

file output
integer handle1, handle2; initial begin handle1 = $fopen(file1.out); write to the file $fdisplay(handle1, x=%b, x); $fclose(handle1); end
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Initialising memory from file

reg [7:0] memory [0: 7]; $readmemb(file.dat, memory); $readmemb(file.dat, memory, start address, finish address); $readmemh(file1.dat, memory); initial $readmemb(file.dat, memory); for(i=0; i < 8; i=i +1) $display(Memory [%0d] = %b, memory[i]); @002 11110000 01010000 10000110 00000000
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Important points:

@006 1111zzzz 000101111

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Register files are not used for mass storage because they occupy significantly more Si area than Compiled memory
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Design verification
Traditional method:
Simulation is predominant verification method
Gate level or register transfer level (RTL)

Test cases

UP-DOWN COUNTER

manually defined, or randomly generated

Steps involved:
1. Partition the chip into functional units and generate bit-true test vectors to specify the behavior of each unit 2. Verify the RTL level through simulation 3. Verify the gate level netlist through simulation 4. Verify the post layout gate level (physical) netlist through simulation
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Analysis
The design is analysed to check the following items: 1. Data received equal to the expected data 2. Correct data according to the interface protocol Data correctness is checked by viewing the waveform or log files that contain traces of simulation and compare it with the standard output. This method is tedious and time consuming for large design. Test environment is made self checking by using Data and Protocol checkers.

Coverage
Coverage helps the designer to determine when the verification is complete. Types of coverage:
1. Structural 2. Functional

Structural:
1. Code coverage (Unexercised code bears bugs) 2. Toggle coverage (If a bit is not toggling, it has not been verified) 3. Branch coverage (If all possible branches in a control flow are taken)

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Coverage Contd.
Functional Coverage It ensures that all possible legal values of input stimuli are exercised in all possible combinations at all possible times. It may be enhanced by inserting assertions in the RTL code.

Advanced Verification Technique

Verilog was heavily used for simulation of test-benches for smaller designs and simpler test environment Design verification started taking 50-70% of the total design time To overcome the problem, assertion-based verification methodology was adopted for complex designs These new developments enhance the productivity of verifying Verilog HDL based design

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Assertion Checking
Traditional verification assumes the Design under test as a black box i.e. verifies only the input-output functionality. Assertion checking is a white box verification approach. It requires knowledge of internal structure of the design. Assertions are statements about a designs intended behaviour. 1. Temporal assertions: Describe timing relationships between signals. (Request and acknowledge signals) 2. Static assertions: Describe a property of a signal that is always true or false.(Full and empty flags cant be 1 simultaneously)
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Design Flow
Behavioral view
Logic synthesis Equivalence

Structural (Gate) view

Physical synthesis Equivalence

Physical (layout) view

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Equivalence Checking
It ensures that the gate level netlist or the physical netlist has the same functionality as the RTL that was simulated. Equivalence checkers build a logical model of both the RTL and gate level representations of the design and mathematically prove that they are functionally equivalent. Thus functional verification can focus entirely on RTL and there is little need of gate level simulation.

RAM with Bidirectional Bus

module (data, cs,we,oe); data inout; input cs, oe, we; wire latch_out; assign latch_out = (cs==0) && (we==0) && (oe==1) ? data: latch_out; assign data = (cs==0) && (we==1) && (oe==0) ? latch_out : 1bz; endmodule

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Synthesis Coding standards

Contd.

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