Logic Design - CMOS devices

by:
Anand S Moghe
Goal of this topic

• Present intuitive understanding of MOS device

operation

• Introduction of basic device equations.

• Concept of perfect transmission and imperfect

transmission of a logic level ( 0 or 1)(gnd or Vdd).
The MOS Transistor

Polysilicon Aluminu
m

L
 The NMOS Transistor

Polysilic Alumin
on um

NMOS device

1. Source and Drain are interchangeable due to MOS

construction.
2. How to identify source and drain ?
3. In a MOS device, the majority carriers always flow from
source (S) to drain (D).
 The NMOS Transistor

Polysilic Alumin
on um

NMOS device

1. In a MOS device, the majority carriers always flow from

source (S) to drain (D).
NMOS device – current flows from Drain to Source (electrons flow from
source to drain; Drain is at higher potential than Source)
PMOS device – current flows from Source to Drain (holes flow from
source to drain; Drain is at lower potential than the Source)
MOS Transistors - Types and Symbols

D D

+ve
G G

S S
NMOS Enhancement NMOS Depletion
D D

G G B

S S

PMOS Enhancement NMOS with

Bulk Contact
Threshold Voltage (Vt): Concept
Transistor in Linear (active) region
Vds < (Vgs –Vt )- effective voltage
Transistor in Saturation region

Pinch-off
Current-Voltage Relations
Long-Channel NMOS Device

Resistive or Active region: Vds < (Vgs – Vt ) (effective voltage)

Ids = (µn.εrεo)(W)[(Vgs–Vt)–Vds].Vds
tox L 2

Saturation region: Vds > Vgs - Vt

Ids = (µn.εrεo)(W)(Vgs–Vt)2(1+λ.Vds)
tox 2L
MOS Transistors - Types and Symbols

D
D

G=0 OFF G

S
S
NMOS Enhancement NMOS Depletion
D
S

G=1 OFF G B

D
S

PMOS Enhancement NMOS with

Bulk Contact
MOS Transistors - Types and Symbols

In=0 volts In=1 D

On -> kohms OFF -> megaohms

G

Out=0 Out S

NMOS Enhancement NMOS Depletion

D

in in
G B

On -> low R OFF -> HIGH R

S
NMOS with
out out Bulk Contact
PMOS Enhancement
 Threshold Drops
VD (input)
NMOS (o/p) VDD →
D
D 0
VDD D C
G VD G
S L
VGS (o/p) 0 → VDD-VTn D
VGS S (input)
C
L

PMOS VD (input)
(o/p) VDD →|VTp|
VSG SD VGS
S C
G G
L
D (o/p) 0→ D (input)
V
C DD
L
 Threshold Drops

NMOS device is perfect for 0 but imperfect for 1 transmission

(o/p) 0 → VDD-VTn Gnd(0V) (o/p) VDD-VTn → 0v
VD S D
D S
D C C
G VGS VGS G
L L
VD (input=1) VD (input=1)
D D

PMOS device is perfect for 1 but imperfect for 0 transmission

VD (o/p) 0 → VDD gnd (o/p) VDD → VTp
S D D S
D C C
VSG G G VSG
L L
VD (input=1) VD (input=1)
D D
ID versus VDS

-4 -4
6 x 10 2. x 10
VGS= 2.5 V 5
VGS= 2.5 V
5
2
Resistive/ Saturation
4 active VGS= 2.0 V
VGS= 2.0 V 1.

ID (A)
5
ID (A)

3
VDS = VGS - VT
VGS= 1.5 V
1
2 VGS= 1.5 V

0. VGS= 1.0 V
1 5
VGS= 1.0 V

0 0
0 0.5 1 1.5 2 2.5 0 0. 1 1. 2 2.
V (V) 5 VDS(V)5 5
DS

Long Channel Short Channel

Current-Voltage Relations
NMOS / PMOS Device
NMOS
Linear or Active region: Vdsn < (Vgsn – Vt ) (effective voltage)

Idsn = (µn.εrεo)(Wn)[(Vgsn–Vt)–Vdsn].Vdsn
tox Ln 2
PMOS (W)p = (2.8)(W)n

Linear or Active region: Vsdp < (Vsgp – Vt ) (effective voltage)

Isdp = (µp.εrεo)(Wp)[(Vsgp–Vt)–Vsdp].Vsdp
tox Lp 2
Current-Voltage Relations
NMOS / PMOS Device
NMOS
Saturation region: Vdsn > (Vgsn – Vt ) (effective voltage)

Idsn = (µn.εrεo)(Wn)[(Vgsn–Vt)2]
tox Ln 2

PMOS
Saturation region: Vsdp > (Vsgp – Vt ) (effective voltage)

Isdp = (µp.εrεo)(Wp)[(Vsgp–Vt)2]
tox Lp 2
The CMOS Inverter: A First Glance

VD
D CL .Rp = charging time constant
Vsgp = 0 s
Rp CL .Rn = discharging time constant

d
V in Vout =VDD - Vt
Vin = VDD
d
CL
pmos nmos
Rn
Vgs = VDD
s
The CMOS Inverter: ..When NMOS and
PMOS devices are interchanged
Pull up
VD Pull down
D d
Vsgp = 0
g CL . Rp
Rn

s
Vout =VDD - Vt
Vin = 0
s
CL
pmos nmos
g Rp Vout = Vt
Vsg = 0
pmos is ON d
Voltage swing = VDD – 2Vt
CMOS Inverter
First-Order DC Analysis

V DD V DD

Rp
VOL = 0
VOH = VDD
V out=1
V out =0 VM = f(Rn, Rp)

Rn

V in 5 V DD V in 5 0
 CMOS Inverter: Transient Response

V DD V DD

tpLH = f(R p .CL) tpHL = f(R n .CL)

Rp
= 0.69 Rp C L = 0.69 Rn C L

V out V out
CL CL
Rn

V in = 0 V in = V DD
(a) Low-to-high (b) High-to-low
R-C circuits – a revision
R

vi C vo Low Pass Filter (l p f)

v
Vi

Vo = Vi.[1- e-t/RC]

i = [Vi / R] [e-t/RC]

t
R-C circuits – a revision
C

High Pass Filter (h p f)

v R vo
i

v,i
Vi

i = [Vi / R][e-t/RC]

Vo = Vi .[e-t/RC]
 The CMOS Inverter: A First Glance

V DD The following equations hold:

Idsn = Isdp
s
g Vsdp + Vdsn = Vdd => Vsdp = Vdd - Vdsn
P
Vin = Vgsn
d
V in V out Vsgp = Vdd – Vgsn = Vdd – Vin

d CL
g
N
s
CMOS Inverter Load Characteristics
 CMOS Inverter VTC

Vout
NMOS off
PMOS act
NMOS sat Voh(min)
2.5

PMOS act
3 NMH
4 5 Vih(min)
2

1 2
NMOS sat
1.5

PMOS sat
Vil(max)
1

NMOS act Vol(max) NML

0.5

PMOS sat NMOS act

PMOS off

0.5 1 1.5 2 2.5 V in

Noise Margin - definition