VERILOG – Structural and Memory Modeling

Anand S Moghe

* ANAND S MOGHE 1
 Aims and Topics
* Aims
- Learn about the capabilities of Verilog for structural
modeling and memory modeling.

* Topics
- Built in primitives (and, or, xor, nand, bufif0, bufif1, not)
- Modeling memories

* ANAND S MOGHE 2
 Structural Modeling
* Pure structural model only contains instantiated modules or
instantiated primitives and wire connections
* Used for block diagrams, schematics, post synthesis netlist
and ASIC/FPGA
nsela = a.nsel
a nsel
selb = b.sel
out = a.nsel + b.sel
a
se ou
l nse
l t module mux (a, sel, b, out);
input a, sel, b;
b sel output out;
b wire nsela, selb, nsel;
or U32(.A(nsela), .B(selb), .Z(out) );
• (Gate level) structural modeling not U33 (.A(sel), .Z(nsel) );
and U34 (.A(a), .B(nsel), .Z(nsela) );
and U35 (.A(b), .B(sel), .z(selb) );
* endmodule
ANAND S MOGHE 3
 Structural Modeling
a3 b3 a2 b2 a1 b1 a0 b0

a b
w3 w2 w1
co FA3 cin FA2 FA1 HA1
s

cout sout[3] sout[2] sout[1] sout[0]

module adder_4bit (a, b, s, sout, cout);

• (Module level) structural modeling
input [3:0] a, b;
• No Logic or logic expressions
output [3:0] sout;
• Only connections through wires
output cout;
half_adder HA1 (.a(a0), .b(b0), .s(sout[0]), .co(w1) );
full_adder FA1 (.a(a1), .b(b1), .s(sout[1]), .cin(w1), .co(w2) );
full_adder FA2 (.a(a2), .b(b2), .s(sout[2]), .cin(w2), .co(w3) );
full_adder FA3 (.a(a3), .b(b3), .s(sout[3]), .cin(w3), .co(cout) );

endmodule
* ANAND S MOGHE 4
 Conditional Primitives
* Four different types of conditional primitives
* Conditional primitives only have three pins: output, input and enable
* Enabled / disabled by the enable pin
- When disabled, outputs are at high impedance

Primitive Name Functionality

bufif1 Conditional buffer with logic 1 as enabling input
bufif0 Conditional buffer with logic 0 as enabling input
notif1 Conditional inverter with logic 1 as enabling input
notif0 Conditional inverter with logic 0 as enabling input

* ANAND S MOGHE 5
 Conditional Buffers
bufif1 bufif0

data out data out

enable
enable
bufif1(out, data, enable) bufif0(out, data, enable)

enable enable
bufif1
0 1 x z bufif0
0 1 x z
0 z 0 L L 0 0 z L L
1 z 1 H H 1 1 z H H
data x z x x x x x z x x
z z x x x z x z x x

Note : Verilog uses the symbols L and H to represent partially unknown

* logic values ANAND S MOGHE 6
 Modeling a Memory Device
A memory device must do two things :

* Declare a memory of appropriate size(ex: 128 x 8 bits)

* Provide some level of access to its contents, such as :

- Read only (ROM)
- Read and Write (RAM)
- Write and Simultaneous read
- Multiple reads , simultaneous to a single write
- Multiple simultaneous reads and writes, with
some method of ensuring consistency

* ANAND S MOGHE 7
 Simple ROM Model
my_rom_data
`timescale 1ns / 10ps 0000
module myrom (read_data, addr, read_en_); 0101
input read_en_; 1100
input [3:0] addr; 0011
output [3:0] read_data; 1101
reg [3:0] read_data; 0010
reg [3:0] mem [0:15]; 0011
1111
initial $readmemb (“my_rom_data”, mem); 1000
1001
always @ (addr or read_en_) 1000
if (! read_en_) 0001
read_data = mem[addr]; 1101
endmodule 1010
0001
ROM data is stored in a separate file 1101

* ANAND S MOGHE 8
 Simple RAM Model – asynchronous write
module myRAM (data, addr, read, write);
inout [3:0] data; // bi-directional port
input [3:0] addr;
input read, write;
reg [3:0] memory [0:15]; 4 bit , 16 word array for
// read memory contents
assign data = (read ? memory [addr] : 4’bz);
// asynchronous write
always @ (posedge write)
memory[addr] <= data; tri- state controller
endmodule enabled by read
rising edge triggered
RAM write
Note: Simultaneous models for internal RAM/ROM usually
*
supplied by technology ANAND
vendorS MOGHE 9
 Simple RAM Model – synchronous write
module myRAM (data, addr, read, write, clk);
inout [3:0] data; // bi-directional port
input [3:0] addr;
input read, write, clk;
reg [3:0] memory [0:15]; 4 bit , 16 word array for
// read memory contents
assign data = (read ? memory [addr] : 4’bz);
// synchronous write. . .
always @ (posedge clk)
if (write) tri- state controller
memory[addr] <= data; enabled by read
endmodule
Clock edge triggered
RAM write
Note: Simultaneous models for internal RAM/ROM usually
*
supplied by technology ANAND
vendorS MOGHE 10
 Scalable Memory device
* Parameters can be used to scale memory models
module scalable_ROM (mem_word, address);
parameter addr_bits = 8; size of address bus
parameter wordsize = 8; width of memory word
parameter words = (1 << addr_bits); size of memory

output [wordsize-1 : 0] mem_word; output word

input [addr_bits-1 : 0] address; address bus
memory
reg [wordsize-1 : 0] mem [0 : words - 1];
declaration
// output one word of memory
assign mem_word = mem[address]; continuous
assignment
endmodule to output

* ANAND S MOGHE 11
 Loading a Memory
* ROM will need to be loaded with data
* RAM may need to be initialized (with some data)
* Memory can be pre-loaded via loops or from an external file
// initialize memory via loop
for (i = 0 ; i< memsize ; i = i+1)
mema[i] = {wordsize {1’b0}};

// load memory from a file

$ readmemb (“mem_file.txt”, mema);

* ANAND S MOGHE 12
 Using inout Ports
module mymem (data , addr , read , write);
inout [3 : 0] data;
input [3 : 0] addr;
input read, write;
.............

assign data = (read ? memory[addr] : 4’ bz);

...................

* Bi - directional ports are declared with the inout keyword

* You can not directly connect an inout port to a register
* Your design should drive an inout port from only one direction at
a time
- To avoid bus contention
- You must design logic around the inout port to ensure
* proper operation ANAND S MOGHE 13
 Bidirectional (inout) Ports Using Primitives
en_a2
b
b
1
bus_ bus_
a b
b en_b2
2 a
module bus_xcvr (bus_a , bus_b, en_a2b, en_b2a);
inout bus_a, bus_b;
When en_a2b = 1,
input en_a2b , en_b2a;
primitive b1 is enabled
bufif1 b1 (bus_b , bus_a , en_a2b);
and the value on bus_a
bufif1 b2 (bus_a , bus_b , en_b2a);
is transferred to bus_b
//structural module logic
endmodule When en_b2a = 1,
primitive b2 is enabled
and the value on bus_b
* ANAND S MOGHE is transferred to bus_a
14
Bidirectional Ports Using Continuous Assignment
en_a2
b
b
1
bus_ bus_
a b
b en_b2
2
module bus_xcvr(bus_a , bus_b, en_a2b, en_b2a);a
inout bus_a, bus_b;
When en_a2b = 1,
input en_a_b , en_b_a;
this assignment drives
assign bus_b = en_a2b ? bus_a : ’bz;
the value of bus_a
assign bus_a = en_b2a ? bus_b : ’bz;
on to bus_b
//structural module logic…
.... When en_b2a = 1,
.... this assignment drives
endmodule the value of bus_b
* ANAND S MOGHE on to bus_a 15
 Modeling Memory Ports
Test RAM
Bench r cell
d
dat
a dat
bus a
w
r reg
module ram_cell (databus, rd, wr); when rd = 1 the value
input databus; of datareg is assigned
input rd, wr; to databus
reg datareg;

assign databus = rd ? datareg : ‘bz; When wr asserts (-ve)

always @ (negedge wr); the value of databus
is written to datareg
datareg <= databus;
endmodule
* ANAND S MOGHE 16