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2024 CSET105 Digital Design Lab1 Thursday

The document provides information about a digital design lab course including the course code, semester, objectives, and 5 questions related to logic gates and Verilog HDL. The questions ask students to draw logic gate symbols, write truth tables, Boolean expressions, and Verilog code for logic gates like NOT, AND, and OR gates.

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Jude Law
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12 views

2024 CSET105 Digital Design Lab1 Thursday

The document provides information about a digital design lab course including the course code, semester, objectives, and 5 questions related to logic gates and Verilog HDL. The questions ask students to draw logic gate symbols, write truth tables, Boolean expressions, and Verilog code for logic gates like NOT, AND, and OR gates.

Uploaded by

Jude Law
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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School of Computer Science Engineering and Technology

Course-B. Tech. Type- Core


Course Code- CSET105 Course Name- Digital Design (Lab)

Year- 2024 Semester- ODD


Date- 23/03/2023 Batch- 2022-2025

CO-Mapping
CO1 CO2 CO3
Q1 √
Q2 √
Q3 √
Q4 √
Q5 √

Objectives
1. Students will be able to learn basic Logic Gates.
2. Students will be able to learn Verilog Hardware Description Language.

Questions:

1. Draw the Symbol along with their truth tables and Boolean expressions of
fundamental building gates used for digital design.

Hint: NOT, AND, and OR Gates

2. Draw the Symbol along with their truth tables and Boolean expressions of Universal
gates used for digital design.

3. Write a Verilog code to implement NOT gate. Write the corresponding Testbench code for the
verification of your Verilog code.
Hint: Truth Table of NOT Gate:

.
4. Write a Verilog code to implement the Boolean Expression Y = A B. Write the corresponding
Testbench code for the verification of your Verilog code. Identify the gate that matches to this
operation.
School of Computer Science Engineering and Technology

.
5. Write a Verilog code to implement the Boolean Expression Y = (A B)'. Write the corresponding
Testbench code for the verification of your Verilog code. Identify the gate that matches to this
operation.

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