Introduction to

Microelectronic Fabrication
by
Richard C. Jaeger
Distinguished University Professor
ECE Department

Auburn University

Chapter 7
Interconnections and Contacts

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Interconnections and Contacts
MOS Logic Circuit
• 3 Basic Interconnection Levels
– n+ diffusion
– Polysilicon
– Aluminum Metallization
• Contacts
– Al-n+
– Al-Polysilicon
– Al-p
• Substrate Contact Not Shown

Figure 7.1 Portion of MOS integrated circuit

(a) Top view (b) Cross section

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Interconnections
Resistivity of Metals
Commonly Used Metals
Aluminum
Titanium
Tungsten
Copper

Less Frequently Utilized

Nickel
Platinum
Paladium

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Contacts
Ohmic Contact Formation

(a) Ideal Ohmic Contact

(b) Rectifying Contact (similar to diode)
(c) Practical Nonlinear “Ohmic” Contact

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Contacts
Ohmic Contact Formation

Figure 7.2
Figure 7.3
• Aluminum to p-type silicon forms an ohmic contact similar
to Fig. 7.2(a) [Remember Al is p-type dopant]
• Aluminum to n-type silicon can form a rectifying contact
(Schottky barrier diode) similar to Fig. 7.3(b)
• Aluminum to n+ silicon yields a contact similar to Fig. 7.3c
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Contacts
Aluminum-Silicon Phase Diagram
Aluminum-Silicon
Eutectic Point 577o C

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Contacts
Aluminum Spiking and Junction Penetration

• Silicon absorption into the aluminum results in aluminum

spikes
• Spikes can short junctions or cause excess leakage
• Barrier metal deposited prior to metallization
• Sputter deposition of Al - 1% Si
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Contacts
Alloying of Contacts
Alloy to Obtain Very Low Contact Resistivity

Specific Contact Resistivity

r c = 1.2x10-6 W - cm 2

Contact Resistance RC

rc
RC = A = contact area
A

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Contacts
Contact Resistance
Example for r C = 1 mW - cm 2

A = 10 mm x 10 mm = 10 -6 cm 2
rC
RC = =1 W
A

A = 1 mm x 1 mm = 10 -8 cm 2
RC = 100 W

A = 0.1 mm x 0.1 mm = 10 -10 cm 2

RC = 10 kW Unacceptable!

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Interconnections
Electromigration
High current density
causes voids to form in
interconnections

“Electron wind” causes

movement of metal
atoms

(a) (b)
1A 10mA
J= 2 = 2 = 1 MA /cm 2
(1mm) (10-4 cm)

High Current Densities

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Interconnections
Electromigration
• Copper added to aluminum to
improve lifetime (95%Al, 4%
Cu, 1% Si) EA for Al ~0.4-0.5eV
1 æ EA ö
MTF µ 2 expç ÷
J è kT ø
TiN clad Cu J = current density
E A = activation energy
MTF = mean time to failure

• Heavier metals (e. g. Cu)

� have lower activation energy

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Interconnections
Diffused Interconnections
• n- and p-type diffusions can be
used for local interconnections
• pn-junction diode must be kept in
its reverse-biased (non-
conducting) state
• All interconnections have a series
resistance R and shunt
capacitance C per unit length
• The RC time constant limits
Figure 7.9 operating frequency
Lumped RC model for a small • n+ and polysilicon lines RS ≥ 30
section of an n+ diffusion
W/square

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material is protected under all copyright laws as they currently exist. No portion of this Introduction to Microelectronic Fabrication, Second
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Interconnections
Diffused Interconnection
• Diffused interconnection
in NMOS OR gate.
• Merged source and drain
regions used to
interconnect devices
• Multiple contacts used
to reduce overall contact
resistance
Figure 7.10

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 Interconnections
Buried and Butted Contacts
Techniques for
interconnecting polysilicon
Intervening space
Wasteful area and n+ diffusion
(a) Standard metal level link
(b) Buried contact with
polysilicon in contact with
diffusion (requires
Save area additional mask step to
place n+ under polysilicon
(c) Butted contact with
aluminum overlap
Figure 7.11
More Conserving area
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material is protected under all copyright laws as they currently exist. No portion of this Introduction to Microelectronic Fabrication, Second
material may be reproduced, in any form or by any means, without permission in writing Edition by Richard C. Jaeger. ISBN0-201-44494-1.
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 Poly Si/shallow diffusion:
Interconnections Not possible: RS < 10~20 W/�

Silicides/Polycides/Salicides

Figure 7.12

• Silicides of noble and refractory metals can be used to

reduce sheet resistance of polisilicon and diffused
interconnections
• Provide shunting layer in parallel with original
inteconnection
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material is protected under all copyright laws as they currently exist. No portion of this Introduction to Microelectronic Fabrication, Second
material may be reproduced, in any form or by any means, without permission in writing Edition by Richard C. Jaeger. ISBN0-201-44494-1.
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Interconnections
Properties of Various Silicides

Stable below

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Interconnections
Salicide
• Self-Aligned Silicide on
silicon and polysilicon
• Often termed “Salicide”

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material is protected under all copyright laws as they currently exist. No portion of this Introduction to Microelectronic Fabrication, Second
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Contacts
Silicide Contacts in Devices

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Interconnections
Liftoff Process

(a) Subtractive etching

process
(b) Additive metal liftoff
process

Figure 7.15

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Interconnections
Multilevel Metallization

• Two level metal processes

• Silicon dioxide, polyimide
or silicon nitride
dielectrics
• Vias formed to connect
between metal levels
• Vias can be filled (b)to
improve planarization
Figure 7.16

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Interconnections
Multilevel Metallization

• Example of multilevel
Al aluminum
metallization with
tungsten via plugs
• Planarity achieved
through Chemical
Mechanical Polishing
Figure 7.17
Multilevel aluminum metallization with (CMP)
tungsten plugs. Copyright 1998 IEEE.
Reprinted with permission from Ref. [7].

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Interconnections
Plated Copper
• Copper deposited using
“standard” plating
processes adapted to
microelectronics
• Seed layer deposited
• Mask layer deposited and
patterned
• Copper plated up
• Mask layer removed
• Seed layer etched away
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Interconnections
Copper Damascene Process

• Damascene process used

to obtain highly planar
surfaces
• Dielectric layer (insulator)
deposited and patterned
• Seed layer deposited
• Copper plated
• Surface polished
mechanical & chemical
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Interconnections
Dual Damascene Process

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Interconnections
Dual Damascene Process (cont.)

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Multilevel Metallization
Examples

(b)

Figure 7.20
(a) Dual Damascene copper combined with aluminum-
copper and tungsten plugs on the lower levels. Copyright
1997 IEEE. Reprinted with permission from Ref. [6]. (b)
(a) Dual Damsascene Copper. Courtesy of Motorola Inc.
Note planarity of both structures.

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Interconnections and Contacts
References

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material may be reproduced, in any form or by any means, without permission in writing Edition by Richard C. Jaeger. ISBN0-201-44494-1.
from the publisher.
 End of Chapter 7

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This material is protected under all copyright laws as they currently exist. No Introduction to Microelectronic Fabrication,
portion of this material may be reproduced, in any form or by any means, Second Edition by Richard C. Jaeger. ISBN0-201-
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Copyright Notice

• © 2002 Pearson Education, Inc., Upper Saddle River, NJ. All

rights reserved. This material is protected under all copyright
laws as they currently exist. No portion of this material may be
reproduced, in any form or by any means, without permission in
writing from the publisher.

• For the exclusive use of adopters of the book Introduction to

Microelectronic Fabrication, Second Edition by Richard C.
Jaeger. ISBN0-201-44494-1.

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material is protected under all copyright laws as they currently exist. No portion of this Introduction to Microelectronic Fabrication, Second
material may be reproduced, in any form or by any means, without permission in writing Edition by Richard C. Jaeger. ISBN0-201-44494-1.
from the publisher.