A PROJECT REPORT ON

HVDC LINE FAULT ANALYSIS

Submitted by:

ABHISHEK GOYAL (10BEE1008)

NITIN SAINI (10BEE1056)

SUJAI SUDEVAN (10BEE1089)

BHAVYA KATARIA (10BEE1044)

BACHELOR OF TECHNOLOGY

in

ELECTRICAL AND ELECTRONICS ENGINEERING

JULY-DEC, 2012

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 BONAFIDE CERTIFICATE

Certified that this project report on “HVDC LINE FAULT ANALYSIS”, is the bonafide work
of “Abhishek Goyal (10BEE1008), Nitin Saini (10BEE1056) and Sujai Sudevan
(10BEE1089), Bhavya Kataria (10BEE1044)” who carried out this PBL work.

School of Electrical Engineering

VIT University, Chennai Campus

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 TABLE OF CONTENTS

S,No Title Page No

1 Abstract 4
2 Introduction 5
3 DC fault location method 6
4 Simulation model 8
5 Matlab Simulation 9
6 Working 10
7 Conclusion 13
8 References 14

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 ABSTRACT

In this paper, fault location accuracies in a 2400 km long overhead HVDC line and 300km
long underground cable HVDC line using the two-terminal travelling wave method is
investigated. The paper proposes to use continuous wavelet transform for detecting the
arrival time of travelling waves, and shows that it provides better accuracy when
compared with the commonly used discrete wavelet transform based technique.

Furthermore, the results show that the continuous wavelet transform based wave front
detection can provide adequate accuracy in the fault location in extra-long overhead
lines and long underground cables. The influence of noise on the fault location accuracy
is discussed. The results also show that either dc terminal voltages or the surge capacitor
currents can be used in dc line fault location.

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 INTRODUCTION

With the rapid development of HVDC technology, HVDC transmission systems with extra-
long overhead (OH) lines such as the 2500 km long Porto Velho-São Paulo HVDC system
[1] and HVDC systems with extra-long underground (UG) cables such as the 295km long
Bass link HVDC system are under consideration. Accurate fault location in such extra-long
dc lines is a challenging task. Fault location in extra-long HVDC systems is currently
achieved with the help of repeater stations. Installation of extra hardware at the
repeater stations, which are required to locate line faults using the existing technology,
increases the cost of these transmission projects. This paper investigates whether the
faults can be located accurately only using the terminal measurements, thereby
eliminating the cost of extra hardware required in the repeater stations. Travelling-wave-
based line fault location principle has been successfully applied to transmission line fault
location in the conventional HVDC systems with two terminals. The key requirement to
improve the accuracy of fault location long lines is precise detection of wave front arrival
times. In most of the recently published research, surge arrival times have been detected
using discrete-wavelet transform (DWT) coefficients of the measured signal. Wavelet
transform works well for analyzing transient in signals because of its simultaneous time
and frequency localization capabilities. Availability of software tools and lower
computational burden have made discrete version of the wavelet transform, DWT, is the
common choice for implementation of these improved fault location algorithms.
Compared to the DWT, the continuous-wavelet transform (CWT) provides more detailed
and continuous analysis of a fault transient. In CWT, the analyzing wavelet is shifted
smoothly along the time axis of the input signal. Therefore, CWT coefficients have better
time resolution which is very important to have high accuracy in travelling wave based dc

line fault location. Hence, as shown in this paper, the CWT approach allows obtaining
default location accuracy better than that obtained with the DWT coefficients.
All studies were carried out with detailed models of HVDC converters and transmission
lines simulated in PSCAD/EMTDC and the fault location algorithm was implemented in
MATLAB. The appropriate type and scale of continuous wavelet transform coefficients at
a given sampling rate was found through the simulation studies. The importance of
calibrating the travelling wave speed, which is depended on the scale of the wavelet
coefficients used, is highlighted. Furthermore, the accuracy of the fault location of the
proposed method was studied under noisy input signals.
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 DC LINE FAULT LOCATION METHOD

The proposed simplified fault location algorithm which is an offline calculation is

illustrated.

This calculation can be initiated once the primary protection scheme identifies the dc line
fault. The fault location scheme maintains a runtime input data buffer, which will be
saved when a fault is detected. The size of this buffer depends on factors such as the
primary protection time delay, sampling time and the transmission line length of the
specific HVDC scheme. The largest time delay in the system is used to estimate the
buffer size. For example, consider that the primary protection scheme has 1 ms time
delay and the data acquisition rate is 2MHz for a HVDC scheme with a transmission line
length of 2400km. The worst case travel time of the surge is approximately equal to 8ms
(assuming 3*105 km/s propagation velocity) when the fault is closer to one end of the
line. In this case, the primary protection time delay (1ms) is smaller than the worst case
travelling wave time delay. Therefore the buffer size is determined by the travel time and

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the required value is 16000 samples at 2 MHz With a safety margin the buffer size can be
taken as double of this value (32000 samples). Data acquisition boards with sufficient on
board memory meet such requirements are commercially available.

n this research, both terminal voltage and surge capacitor current measurements were
tested as potential input signals. Sampling is assumed synchronized and time tagged
using GPS clock signals. Wavelet transform either DWT or CWT is applied to the input
signal and the magnitude values of the wavelet coefficients are extracted.
A threshold to identify the surge arrival point is set about 15% above the maximum value
of the wavelet coefficient of the corresponding input signal under the normal conditions
The safety margins are required to allow for the noise. Different threshold values are
found for each coefficient scale considered in the algorithm. The time when the
magnitude of the considered coefficient rises above the threshold is recognized as the
time of arrival of a surge at the terminal. From the measurements at the other end of the
transmission line, the time of arrival of the surge in that terminal is received via
telecommunication channel. Fault location is calculated by using the travelling wave
principle according to. As different coefficient scales or levels represent different
frequency bands in the signal, the velocity of propagation at each of these frequency
bands could slightly differ. These velocities can be found and the algorithm can be
calibrated by using test data for a known fault. The algorithm attempts to find an arrival
of surge in the current data buffer, and if it did not find an edge, then the buffer window
is shifted and the procedure is repeated. Note that if the signal processing can be done in
real time, the occurrence of a fault can be detected by continuously observing the
wavelet coefficients, without depending on an external initiation signal. With fast digital
signal processors (DSPs), this is also a practically viable approach.

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 SIMULATION MODELS

Simulations were done using two HVDC transmission networks, one with OH
transmission line and the other with UG cable line. All the test networks are based on the
modified
version of the first Cigré benchmark HVDC scheme. This test network has 500kV as the
nominal dc voltage and it is designed to deliver 1000MW of active power. Furthermore, a
bipolar HVDC configuration is used since most of the present day HVDC systems are built
in bipolar configuration, instead of the mono-polar arrangement in the original
reference. The simplified PI model representing a cable dc line scheme in the original
Cigré model was replaced with a frequency dependent distributed parameter model of a
2400km long overhead transmission line in one of the test network and in the other test
network, it was replaced with a frequency dependent distributed parameter model of a
300 km long underground cable line. Schematic diagram of the test networks are shown

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MATLAB REPRESENTATION

This demonstration illustrates steady-state and transient performance of a simple 500

MW (250 kV-2kA) HVDC transmission system. This demonstration helps to determine the
fault in the transmission if there is any. Fault detection circuit is present at various points
to catch the fault. A 500 MW (250 kV, 2 kA) DC is used to transmit power from a 315 kV,
5000 MVA AC network. The network is simulated by a LLR damped equivalent
(impedance angle of 80 degrees at 60 Hz and 3rd harmonic).

The converter transformer and the rectifier are modeled respectively with the Universal
Transformer and Universal Bridge blocks The converter is a 6-pulse rectifier. It is
connected to a 300 km distributed parameter line through a 0.5 H smoothing reactor
LsR.

The inverter is simulated by a simple DC voltage source in series with a diode (to force
unidirectional conduction) and smoothing reactor LsI. The reactive power required by

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the converter is provided by a set of filters (C bank plus 5th, 7th and high pass filters;
total 320 Mvar). Open the AC filter subsystem to see the filter topology. A circuit breaker
allows to apply a DC line fault on the rectifier side.

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 WORKING

The system is programmed to start and reach a steady state. Then, a step is applied on
the reference current to observe the dynamic response of the regulator. Finally a DC
fault is applied on the line. The system is programmed to start and reach a steady state.
Then, a step is applied on the reference current to observe the dynamic response of the
regulator. Finally a DC fault is applied on the line.

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 SIMULATION STEPS

The system is programmed to start and reach a steady state. Then steps are applied on
the reference current of the rectifier and on the inverter reference voltage in order to
observe the dynamic response of the regulators. Finally, a stop sequence is initiated to
bring the DC power down before blocking the converters.

Start the simulation, open the RECTIFIER and INVERTER scopes (in the Data Acquisition
subsystem) and observe the DC line voltage on trace 1 (1pu = 500 kV) and the DC line
current (reference and measured values) on trace 2 (1pu = 2 kA).

Start-up and Stop

In the Master Control, the converters are unblocked and started by ramping the rectifier
and inverter reference current.

At t = 0.02 s (i.e. when the converters at unblocked), the reference current is ramped to
reach the minimum value of 0.1 pu in 0.3 s (0.33 pu/s). At the end of this first ramp (t =
0.32 s) the DC line is charged at its nominal voltage and DC voltage reaches steady-state.

At t= 0.4 s, the reference current is ramped from 0.1 pu to 1 pu (2kA) in 0.18 s (5 pu/s).
At the end of this starting sequence (t=0.58 s), the DC current reaches steady state. The
RECTIFIER then controls the current and the INVERTER controls the voltage.

In steady-state, the alpha firing angles (trace 3) are 17.7 degrees and 144.5 degrees
respectively on the RECTIFIER and INVERTER sides. Note that in the detailed model these
traces (16.5° for the rectifier and 143° for the inverter) are not the measured firing delay
angles but the corresponding orders from the control regulators. In the detailed model,
the firing angles are smaller because the regulators must advance the firing orders by
two time steps in order to compensate for the delays introduced by interfacing of input
AC voltages and output firing pulses of the 12-pulse Firing Control block. The extinction
angle gamma value is an output of the average model. It is used at the INVERTER and
shown in trace 5. In steady-state, its value is 23 degrees.

The control mode of operation (an integer between 0 to 6) is shown in trace 4 (0=
blocked; 1=Current control; 2=Voltage control; 3=Alpha minimum limitation; 4=Alpha
maximum limitation; 5=Forced or constant alpha; 6=Gamma control).

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At t = 1.4 s the Stop sequence is initiated by ramping down the current to 0.1 pu.

At t = 1.6 s a Forced-alpha at the Rectifier extinguishes the current and at the Inverter
the Forced-alpha brings down the DC voltage.

At t = 1.7 s the pulses are blocked in both converters.

CONCLUSION

For high-speed HVDC line protection based on travelling wave, the methods regarding
transient signal analysis are necessary; the edge detection and identification from the
similar transients are decisive. The wavelet transform technique provides new possibility
for this. The proposed protection criterions based on wavelet modulus maxima can make
a definite HVDC line fault detection and the identification from the similar faults such as
commutation failure and AC single phase fault. The simulation results has shown that the
application of wavelet technique leads to a faster, easier and more reliable solution for
the fault detection and protection of HVDC lines.

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REFERENCE

1. Arrilaga, J., High Voltage Direct Current Transmission, IEEE® Power Engineering
Series 6, Peter Peregrinus, Ltd., 1983.
2. Lidong Zhang, Lars Dofnas, "A Novel Method to Mitigate Commutation Failures in
HVDC Systems, “Proceedings PowerCon 2002. International Conference
on, Volume: 1, 13–17 Oct. 2002, pp. 51–56.
3. T.W. Radford, “HVDC line fault locator upgrade”, in Proc. HVDC operating conf.,
1987, pp. 189-200.
4. www.wikipedia.com/hvdc
5. Green Power Superhighways: Building a Path to America's Clean Energy Future,
February 2009

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