6 Transistor Amplifiers

[20 minutes] 7.1 (b) If the gate width is doubled but the value of [5 points]
[17 points] VOV is maintained, what do the values of ID , gm ,
+1.5 V
and ro become?

iD RD
6.3 [35 minutes]
A 0.18-µm CMOS technology is specified to have [35 points]
+ μn = 450 cm2 /V·s, μp = 100 cm2 /V·s, Cox =
8.6 fF/µm2 , Vtn = −Vtp = 0.5 V, and dc power
+ vD
supply of 1.8 V.
vGS (a) Find the transconductance parameters kn and [4 points]
– – kp expressed in µA/V2 .
(b) Find the W/L ratios of matched NMOS [6 points]
Figure 61.1 and PMOS transistors that exhibit resistance rDS
of 250  when operated in the triode region
The NMOS transistor in the circuit in Fig. 6.1.1 with an overdrive voltage of 0.3 V. If twice-the-
has μn Cox = 0.4 mA/V2 , W/L = 25, and Vt = minimum channel length is used, specify the
0.4 V.
width of the NMOS transistor and the PMOS
[3 points] (a) Find the value of VGS that results in saturation- transistor.
mode operation with a dc current of 0.1 mA. (c) If the devices in (b) are operated in saturation [8 points]
Neglect the Early effect. with |VOV | = 0.2 V, what drain current results?
[2 points] (b) Find the value of RD that results in a dc drain If for each transistor the source is connected to
voltage of 0.5 V. ground, what should the gate voltages be? In
[4 points] (c) Find gm and ro at the dc operating point each case, specify the range of voltages permit-
specified above. Assume VA = 5 V. ted at the drain for saturation-mode operation to
[3 points] (d) Find the open-circuit voltage gain Avo . be maintained.
[5 points] (e) If a sinusoidal signal with peak amplitude Vi (d) If the drain currents in (c) are to be reduced [5 points]
is superimposed on the dc voltage VGS , find the by a factor of 4, what should the overdrive voltage
maximum allowable value of Vi for which the be? If instead of changing |VOV |, the IC designer
transistor operates in saturation. redesigns the widths of the transistors, what W
values would be required?
[15 minutes] 6.2 (e) If the devices described in (b) above are oper- [2 points]
[12 points] An NMOS transistor fabricated in a 0.18-µm ated in saturation with |VOV | = 0.2 V, find the
CMOS technology has L = 0.54 µm and W = resulting value of gm .
10.8 µm. The technology is specified to have (f) If an NMOS transistor as in (e) above is con- [5 points]
μn Cox = 400 µA/V2 , Vtn = 0.5 V, and VA = nected as a common-source amplifier with RD =
5 V/µm. 5 k and VDD = 1.8 V, what dc voltage would
[7 points] (a) If the device is operated in saturation with an appear at the drain? What small-signal voltage
overdrive voltage of 0.2 V, find the required values gain Av would be obtained?
of ID and VGS , along with the resulting values of (g) Recalculate the voltage gain in (f) taking into [5 points]
gm and ro . account channel-length modulation. Assume the

6-1
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 6-2

Early voltage for the process technology is spec- (f) For Rsig = 1 M and RL = 40 k, find the [5 points]
ified as 10 V/µm. value of the overall voltage gain vo /vsig .
(g) What does the voltage gain become if CS is [2 points]
removed?
[20 minutes] 6.4
[17 points] VDD = +5 V

6.5 [35 minutes]

RD
Figure 6.5.1 (refer to Figure below) shows a [28 points]
` capacitively coupled amplifier. In the following,
vo assume operation at midband frequencies where
Rsig `
the coupling and bypass capacitors behave as short
circuits. The BJT has β = 99 and the Early effect
RL
` can be neglected.
(a) If the dc voltage at the base is to be 5 V and [2 points]
CS the emitter current 1 mA, find the required value
+ vsig RG
– I of (RE1 + RE2 ). Assume VBE = 0.7 V.
(b) If the input resistance at the base, Rib , is to be [5 points]
10 k, find the required value of RE1 and hence
Rin –VSS the value of RE2 .
(c) If the dc current in RB2 is to be 0.1 mA, find [3 points]
Figure 6.4.1 the values of RB1 and RB2 .
(d) Find the value of RC that results in a dc voltage [3 points]
The MOSFET in the circuit of Fig. 6.4.1 has of +6 V at the collector.
μn Cox (W/L) = 4 mA/V2 . (e) Find the input resistance Rin and the value of [4 points]
[2 points] (a) Find the value of I that causes the MOSFET to vb /vsig .
operate in saturation with an overdrive voltage of (f) Find the value of vo /vb . [4 points]
0.25 V. (g) Find the value of the overall voltage gain [2 points]
[2 points] (b) What value of RD results in VD = 0 V? vo /vsig .
[2 points] (c) Find the value of gm . (h) If the peak amplitude of the signal between [5 points]
[2 points] (d) Find the value of ro given that VA = 25 V. base and emitter (vπ ) is to be limited to 5 mV,
[2 points] (e) If Rin is to be 1 M, find the value that RG what are the corresponding amplitudes of vb , vsig ,
must have. and vo ?

+15 V

RB1 RC
C2
vo
C
Rsig = 10 k⍀ C1
RL
+ 10 k⍀

RB2 RE1
+ vsig vb
–
–
RE2 CE

Rin Rib

Figure 6.5.1

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 6-3

[40 minutes] 6.6 voltage divider of IE /10. What values are required
[32 points] for RB1 , RB2 , RE , and RC ?
VCC = +12 V (b) If the transistor has β = 100, find the actual [6 points]
values obtained for IE , IC , VB , and VC .
(c) What are the values of gm , re , and rπ at the dc [3 points]
RB1 RC bias point.
CC2 (d) Assuming very large coupling and bypass [4 points]
vo capacitors, find the values of RE1 and RE2 that
Rsig CC1 result in Rin = 10 k.
RL (e) Find the overall voltage gain Gv = vo /vsig . [6 points]
(f) For vo , a sine wave with a 1-V peak ampli- [7 points]
tude, what is the peak amplitude required of the
RB2 RE1 sine wave vbe ? If this value is greater than 5 mV,
+ vsig
reduce vsig to limit the peak amplitude of vbe to
– 5 mV. What is the resulting output voltage in this
case?
RE2 CE

Rin
6.7 [25 minutes]
RE = RE1 + RE2 Rsig = 10 k⍀ RL = 10 k⍀ The transistor in the emitter follower of Fig. 6.7.1 [21 points]
(refer to Figure below) has β = 100. Assume
Figure 6.6.1 VBE = 0.7 V and neglect the Early effect.
(a) Find the dc emitter current IE . [4 points]
[6 points] (a) Perform a dc bias design for the amplifier in (b) Find the value of the emitter resistance re . [1 point]
Fig. 6.6.1. For this purpose, assume β is very (c) Find the input resistance Rin . [5 points]
high and VBE = 0.7 V and neglect the Early (d) Find the voltage gain from signal source to the [2 points]
effect. Design to obtain a dc base voltage of transistor base, vb /vsig .
VCC/3, a dc emitter current of 1 mA, and a dc (e) Find the voltage gain from transistor base to [3 points]
voltage at the collector that allows for ±1-V the output, vo /vb .
signal swing at the collector with the minimum (f) Find the overall voltage gain, vo /vsig . [1 point]
collector voltage no lower than VB. Use (g) Find the output resistance Rout . [5 points]
a dc current in the base

+5 V

Rsig = 10 k⍀ ` vb

`
vo
+ vsig
–
RB = 10 k⍀ RE = 1 k⍀ RL = 1 k⍀

Rin –5 V Rout

Figure 6.7.1

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 6-4

[40 minutes] 6.8 The transistors in the amplifier shown in Fig. 6.8.1
[35 points] have β = 100, VBE = 0.7 V, and negligible Early
VCC = +15 V
effect.
(a) Design the circuit to obtain the following dc [10 points]
operating parameters: VB1 = +3 V, IE1 = 1 mA,
I R1 R3 VE2 = +4 V, and IE2 = 4 mA. Use I = 0.1 mA.
Find the values of R1 , R2 , R3 , (R4 + R5 ), and R6 .
vc1
Q2 (b) Find the value of R4 (and hence R5 ) that results [4 points]
` VB1
in Rin = 10 k.
vi Q1 (c) Find Ri2 . [2 points]
Ri2 (d) Find the voltage gain vc1 /vi . [3 points]
` (e) Find the voltage gain vo /vc1 . [3 points]
R4 vo (f) Find the overall voltage gain vo /vi . [1 point]
(g) Find the output resistance Rout . [4 points]
(h) In order to minimize nonlinear distortion, it is [8 points]
required to keep the maximum signal across the
R2 R5 ` R6 base-emitter junction of each of Q1 and Q2 to
5 mV. Under this constraint, what is the maximum
Rin Rout peak-to-peak sine wave signal that can be obtained
at the output?
Figure 6.8.1

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 6 Transistor Amplifiers

6.1 (d)
(a)
+1.5 V Avo = −gm (RD ro )
= −1.42(1050)
iD RD = −11.8 V/V

+ (e) At the edge of saturation,

+ vD
vGmax − vDmin = Vt
vGS
– –
Here,
Figure 6.1.1
vGmax = VGS +V̂i = 0.541 +V̂i
vDmin = VD − |Avo |V̂i
ID = 12 (μn Cox )(W/L)(VGS − Vt )2
= 0.5 − 11.8V̂i
0.1 = 12 × 0.4 × 25(VGS − 0.4)2
⇒ VGS = 0.541 V Thus,

(b) 0.541 +V̂i − 0.5 + 11.8V̂i = 0.4

1.5 − VD 1.5 − 0.5 ⇒V̂i = 28 mV

RD = = = 10 k
ID 0.1

(c)
2ID 6.2
gm =
VOV (a) Saturation with VOV = 0.2 V,
where
ID = 12 (μn Cox )(W/L)V2OV (1)
VOV = VGS − Vt = 0.541 − 0.4 = 0.141 V
2 × 0.1 = 12 × 0.4 × (10.8/0.54) × 0.22
gm = = 1.42 mA/V
0.141 = 0.16 mA
V 5
ro = A = = 50 k VGS = Vtn + VOV = 0.5 + 0.2 = 0.7 V
ID 0.1

6-5
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 6-6

2ID 2 × 0.16
gm = = = 1.6 mA/V For a matched PMOS transistor,
VOV 0.2
V VA L 5 × 0.54 k
ro = A = = = 16.9 k (W/L)P = (W/L)N × n
ID ID 0.16 kp

(b) If W is doubled while VOV is maintained, we 387

= 34.5 × = 155
see from Eq. (1) that ID doubles to 86

ID = 0.32 mA Thus,

From L = 2L min = 2 × 0.18 = 0.36 µm

2ID WN = 34.5 × 0.36 = 12.4 µm
gm =
VOV WP = 155 × 0.36 = 55.8 µm
we see that gm doubles to
(c)
gm = 3.2 mA/V
IDP = IDN = 12 kn (W/L)N |VOV |2
Finally, from
= 12 × 387 × 34.5 × 0.22
V
ro = A = 267 µA
ID

we see that ro is halved to For the NMOS transistor,

ro = 8.45 k VG = VGS = Vtn + VOV = 0.5 + 0.2 = 0.7 V

For the PMOS transistor,

6.3
(a) VG = −VSG = −(|Vtp | + |VOV |)

kn = μn Cox = −(0.5 + 0.2)

= −0.7 V
cm2 F
= 450 × 8.6 × 10−15
V·s µm2
µm2 F
= 450 × 108 × 8.6 × 10−15 VD
V·s µm2
F +0.7 V –0.7 V
= 387 × 10−6
V·s
VD
= 387 µA/V2
μp 100
kp = kn × = 387 × (a) (b)
μn 450
Figure 6.3.1
= 86 µA/V2
From Fig. 6.3.1, we see that for the NMOS tran-
(b) For an NMOS transistor operating in a triode sistor to operate in saturation,
region,

1 VD ≥ VOV
rDS = 
kn (W/L)N VOV
1 that is,
250 =
387 × 10−6 × (W/L)N × 0.3
⇒ (W/L)N = 34.5 VD ≥ 0.2 V

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 6-7

For the PMOS transistor to operate in saturation, (g)

VD ≤ −|VOV | VA = VA × L

= 10 × 0.36 = 3.6 V
that is,
V 3.6
ro = A = = 13.5 k
ID 0.267
VD ≤ −0.2 V
Av = −gm (RD ro )
(d) Since ID is proportional to |VOV |2 , the drain = −2.67(513.5)
current can be reduced by a factor of 4 by reducing
|VOV | by a factor of 2, that is, to 0.1 V. Alterna- = −9.74 V/V
tively, |VOV | can be kept constant and W reduced
by a factor of 4, resulting in

34.5 6.4
WN = = 8.63 µm
4
VDD = +5 V

and
RD
155
WP = = 38.8 µm `
4 vo
Rsig `
(e)
RL
`
2ID 2 × 0.267
gm = = = 2.67 mA/V
|VOV | 0.2 CS
+ vsig RG
– I
(f)
Rin –VSS
VDD = 1.8 V
Figure 6.4.1

ID RD
5 k⍀ (a)

VD
I = ID = 12 kn V2OV

= 12 × 4 × 0.252
= 0.125 mA

(b)
Figure 6.3.2
VD = VDD − ID RD
0 = 5 − 0.125 × RD
Refer to Fig. 6.3.2.
⇒ RD = 40 k

VD = VDD − ID RD (c)
= 1.8 − 0.267 × 5 = 0.465 V
2ID 2 × 0.125
Av = −gm RD = −2.67 × 5 = −13.35 V/V gm = = = 1 mA/V
VOV 0.25

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 (d) 6.5 Refer to Figure 6.5.1 at the bottom of this page.

+15 V
V 25
ro = A = = 200 k
ID 0.125
RB1 RC
(e)
0.99 mA
0.11 mA +6 V
Rin = RG
0.01 mA
+5 V
Thus,
0.1 mA +4.3 V
RG = 1 M 1 mA

RB2 RE1
(f)

vo vg vo RE2
= ×
vsig vsig vg

Rin
= × −gm (RD ro RL )
Rin + Rsig Figure 6.5.2
1 (a) Refer to Fig. 6.5.2 above.
= × −1(4020040)
1+1
5 − 0.7
RE1 + RE2 = = 4.3 k
= −9.1 V/V 1 mA
(b)
Rib = (β + 1)(re + RE1 )
(g) If CS is removed, the resistance in the where
source lead becomes infinite and the voltage gain
VT 25 mV
becomes zero. re = = = 25 
IE 1 mA

+15 V

RB1 RC
C2
vo
C
Rsig = 10 k⍀ C1
RL
+ 10 k⍀

RB2 RE1
+ vsig vb
–
–
RE2 CE

Rin Rib

Figure 6.5.1

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 6-9

vb
For Rib = 10 k, = 0.43
vsig
20
10 = (99 + 1)(0.025 + RE1 ) ⇒ vsig = = 46.5 mV
0.43
⇒ RE1 = 0.075 k = 75  vo
= 20.3
RE2 = 4.3 − 0.075 = 4.225 k vsig
⇒ vo = 20.3 × 46.5 mV
(c) Refer to Fig. 6.5.2. = 0.944 V

5V
RB2 = = 50 k
0.1 mA 6.6
15 − 5
RB1 = = 90.9 k VCC = +12 V
0.11

(d) Refer to Fig. 6.5.2.

RB1 RC
CC2
15 − 6 vo
RC = = 9.1 k
0.99 Rsig CC1
RL
(e) Refer to Fig. 6.5.1.

RB2 RE1
Rin = RB1 RB2 Rib + vsig
–
= 90.95010
= 7.63 k RE2 CE
vb Rin 7.63
= = = 0.43 V/V
vsig Rin + Rsig 7.63 + 10 Rin
RE = RE1 + RE2 Rsig = 10 k⍀ RL = 10 k⍀
(f )
Figure 6.6.1
vo R RL
= −α C
vb re + RE1 VCC = +12 V
9.110
= −0.99 ×
0.025 + 0.075
RB1 1 mA RC
= −47.2 V/V

0.1 mA VC = +5 V
(g)
0 mA
vo v vo VB = +4 V
= b × = 0.43 × −47.2
vsig vsig vb
= −20.3 V/V 0.1 mA +3.3 V

(h) Refer to Fig. 6.5.1. RB2 1 mA RE1

RE
vπ v re
= be = RE2
vb vb re + RE1
5 mV 25
=
vb 25 + 75
⇒ vb = 20 mV Figure 6.6.2

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 6-10

(a) Refer to Fig. 6.6.2 on the previous page. (c)

I 0.917
gm = C = = 36.7 mA/V
12 − 4 VT 0.025
RB1 = = 80 k
0.1 VT 25
re = = = 27 
4 IE 0.926
RB2 = = 40 k
0.1 β 100
rπ = = = 2.72 k
RE =
3.3
= 3.3 k gm 36.7
1
12 − 5 (d) Refer to Fig. 6.6.1 on the previous page.
RC = = 7 k
1
Rin = RB1 RB2  [(β + 1)(re + RE1 )]
10 = 8040 [101(0.027 + RE1 )]
(b)
⇒ RE1 = 0.131 k
RE2 = RE − RE1 = 3.3 − 0.131 = 3.169 k
VCC = +12 V
(e)

RC
vb Rin
=
vsig Rin + Rsig
VC
10
VBB RBB = = 0.5 V/V
10 + 10
VB vo R RL
IE /(b + 1) = −α C
IE vb re + RE1
RE 710
= −0.99 ×
0.027 + 0.131
= −25.8 V/V
vo
Figure 6.6.3 = 0.5 × −25.8 = −12.9 V/V
vsig

(f )
Refer to Fig. 6.6.3.
1V
vb = = 38.8 mV
25.8
RB2 vbe re
VBB = VCC =
RB2 + RB1 vb re + RE1
40 0.027
= 12 × =4V vbe = 38.8 ×
40 + 80 0.027 + 0.131
RBB = RB1 RB2 = 8040 = 26.7 k = 6.63 mV
VBB − VBE
IE = RBB
RE + β+1 To reduce vbe to 5 mV, we must reduce vsig by a
4 − 0.7 factor of
= = 0.926 mA
3.3 + 26.7
101 5
= 0.75
IC = αIE = 0.99 × 0.926 = 0.917 mA 6.63
VB = VBE + IE RE
This reduces vo by the same factor, thus
= 0.7 + 0.926 × 3.3 = 3.76 V
VC = VCC − IC RC = 12 − 0.917 × 7 = 5.58 V vo = 1 × 0.75 = 0.75 V

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 6.7

+5 V

Rsig = 10 k⍀ ` vb

`
vo
+ vsig
–
RB = 10 k⍀ RE = 1 k⍀ RL = 1 k⍀

Rin –5 V Rout

Figure 6.7.1

+5 V (e)
IE
IB = vo RE RL
b+1 =
vb (RE RL ) + re
11
= = 0.987 V/V
IE (11) + 0.00639
(f )
RB = 10 k⍀ RE = 1 k⍀ vo
= 0.455 × 0.987 = 0.449 V/V
vsig

–5 V
(g)
 
RB Rsig
Figure 6.7.2 Rout = RE  re +
β +1
 
1010
= 1 0.00639 +
(a) Refer to Fig. 6.7.2. 101
= 52.9 
5 − 0.7
IE = 10
= 3.91 mA
1 + 101
6.8

(b)
VCC = +15 V
VT 25
re = = = 6.39 
IE 3.91
I R1 R3

(c) Refer to Fig. 6.7.1. vc1

Q2
` VB1
Rin = RB (β + 1) [re + (RE RL )] vi Q1
Ri2
= 10101 [0.00639 + (11)]
`
= 8.36 k R4 vo

(d)
R2 R5 ` R6
vb Rin
=
vsig Rin + Rsig Rin Rout
8.36
= = 0.455 V/V Figure 6.8.1
8.36 + 10

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 6-12

VCC = +15 V (d)

1.03 mA

0.1 mA R1 R3 vc1 R3 Ri2

0.04 mA = −α
vi re1 + R4
Q2
0.99 mA 10101.6
= −0.99
0.01 mA +4.7 V 0.025 + 0.136
+3 V Q1 = −56 V/V

+2.3 V
0.09 mA +4 V (e)
1 mA R4 4 mA

vo R6 1
= = = 0.994 V/V
R2 R5 R6 vc1 R6 + re2 1 + 0.00625

(f )
Figure 6.8.2 vo
= −56 × 0.994 = −55.6 V/V
vi

(a) Refer to Fig. 6.8.2. (g)

15 − 3  
R1 = = 120 k R3
0.1 Rout = R6  re2 +
3 β +1
R2 = = 33.3 k  
0.09 10
= 1 0.00625 +
15 − 4.7 101
R3 = = 10 k
1.03 = 95.2 
2.3
R4 + R 5 = = 2.3 k
1
4 (h) For vbe1 = 5 mV,
R6 = = 1 k
4
R4 + re1
(b) Refer to Fig. 6.8.1 on the previous page. vb1 = 5 ×
re1
 
0.136
Rin = R1 R2  [(β + 1)(re1 + R4 )] = 5 1+ = 32.2 mV
0.025
where
Thus,
VT 25 mV
re1 = = = 25  = 0.025 k
IE1 1 mA vi = 32.2 mV
10 = 12033.3 [101(0.025 + R4 )]
and
⇒ R4 = 0.136 k
vo = 32.2 × 55.6 = 1.79 V
R5 = 2.3 − 0.136 = 2.164 k
Thus,
(c)
Ri2 = (β + 1)(re2 + R6 )
1790
where vbe2 = × re2
R6
25 0.00625
re2 = = 6.25  = 1790 ×
4 1
Ri2 = 101(0.00625 + 1) = 101.6 k = 11.2 mV

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 6-13

re1
which violates the constraint given. Thus, we must vbe1 = vi ×
re1 + R4
impose the constraint first on Q2 :
0.025
= 14 ×
0.025 + 0.136
vbe2 = 5 mV
= 2.2 mV
R6
⇒ vo = vbe2 ×
re2
which meets the constraint. Thus, the maximum
1 sine-wave signal available at the output is 0.8 V
= 5×
0.00625 peak or 1.6 V peak-to-peak.
= 800 mV = 0.8 V
800
vi = = 14 mV
55.6

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