Bảng mạch và công thức BJT

TABLE 4.1
BJT Bias Configurations

Type Configuration Pertinent Equations

Fixed-bias VCC

VCC - VBE
RC IB =
RB RB
IC = bIB, IE = (b + 1)IB
VCE = VCC - IC RC

Emitter-bias VCC

RC VCC - VBE
RB IB =
RB + (b + 1)RE
IC = bIB, IE = (b + 1)IB
Ri = (b + 1)RE
VCE = VCC - IC (RC + RE)
RE

Voltage-divider VCC
bias
RC R2VCC APPROXIMATE: bRE Ú 10R2
R1 EXACT: RTh = R1||R2, ETh =
R1 + R2 R2VCC
VB = , VE = VB - VBE
ETh - VBE R1 + R2
IB =
RTh + (b + 1)RE VE IE
IE = , IB =
IC = bIB, IE = (b + 1)IB RE b + 1
R2
RE VCE = VCC - IC (RC + RE) VCE = VCC - IC (RC + RE)

Collector-feedback VCC

RC
RF
VCC - VBE
IB =
RF + b(RC + RE)
IC = bIB, IE = (b + 1)IB
VCE = VCC - IC (RC + RE)
RE

Emitter-follower

VEE - VBE
IB =
RB + (b + 1)RE
IC = bIB, IE = (b + 1)IB
RB
RE VCE = VEE - IE RE

–VEE
Common-base VEE - VBE
IE =
RE
RE RC IE
IB = , IC = bIB
– + b + 1
VEE VCC VCE = VEE + VCC - IE (RC + RE)
+ –
VCB = VCC - ICRC
193
 TABLE 5.1
Unloaded BJT Transistor Amplifiers

Configuration Zi Zo Av Ai
Fixed-bias: Medium (1 k ) Medium (2 k ) High (-200) High (100)

RB 7 bre RC 7 ro (RC 7 ro)

VCC
Io = = bRBro
RC = - =
RB re (ro + RC)(RB + bre)
Ii bre RC
+
Vo RC b
+ Zo
– (RB Ú 10bre) (ro Ú 10RC) -
Vi re
Zi (ro Ú 10RC,
–
(ro Ú 10RC) RB Ú 10bre)

Voltage-divider Medium (1 k ) Medium (2 k ) High (-200) High (50)

R1 7 R2 7 bre RC 7 ro R C 7 ro b(R1 7 R2)ro

bias: VCC
Io = =
(ro + RC)(R1 7 R2 + bre)
RC
R1 = - =
Ii
re

b(R1 7 R2)
+ RC

R1 7 R2 + bre
+ Zo RC
Vo (ro Ú 10RC) -
Vi Zi R2 re
RE CE
– – (ro Ú 10RC) (ro Ú 10RC)

Unbypassed High (100 k ) Medium (2 k ) Low (- 5) High (50)

RB 7 Zb
emitter bias: VCC
= = RC RC bRB
Io RC = - -
RB re + RE R B + Zb
Ii Zb b(re + RE) (any level of ro)

RB 7 bRE
+
RC
+ Zo -
Vo RE
Vi
Zi RE (RE W re)
(RE W re)
– –

Emitter- High (100 k ) Low (20 ) Low ( 1) High (-50)

RB 7 Zb = RE 7 re
follower: VCC
= RE bRB
Ii RB = -
RE + re RB + Zb
Zb b(re + RE)

RB 7 bRE
+ re
1
Vi Io RE + (RE W re)
Zi Vo
– Zo (RE W re)
–
Common-base: Low (20 ) Medium (2 k ) High (200) Low (-1)

R E 7 re
Ii
= = RC RC -1
+ Io RC + re
RE re
Vi Zi Zo Vo
VEE VCC
– – (RE W re)

Collector Medium (1 k ) Medium (2 k ) High (-200) High (50)

RC 7 RF
feedback: VCC
Io re RC bRF
RC
RF = - =
1 RC re RF + bRC
+ (ro Ú 10RC)
Ii + b RF
(ro Ú 10RC) RF
+ Zo Vo (ro Ú 10RC) (RF W RC) RC
Vi Z
o
– –

293
 TABLE 5.2
BJT Transistor Amplifiers Including the Effect of Rs and RL

Configuration AvL Vo >Vi Zi Zo

-(RL RC) RB 7 bre RC

re

Including ro:

(RL 7 RC 7 ro)
- RB 7 bre R C 7 ro
re

- (RL 7 RC) R1 7 R2 7 bre RC

re

Including ro:

- (RL 7 RC 7 ro)
R1 7 R2 7 bre R C 7 ro
re

R E = RL 7 RE R s = Rs 7 R1 7 R2

R1 7 R2 7 b(re + R E) RE a + re b
Rs
1
b

R1 7 R2 7 b(re + R E)
Including ro:
RE a + re b
Rs
1
b

-(RL 7 RC) RE 7 re RC
re

Including ro:

-(RL 7 RC 7 ro)
RE 7 re R C 7 ro
re

VCC

- (RL 7 RC)
R1 7 R2 7 b(re + RE) RC
RC RE
R1
Vo
Rs Vi Including ro:

- (RL 7 RC)
R1 7 R2 7 b(re + Re)
Zo
+ RL RC
Vs Zi R2 RE
RE
–

294
 TABLE 5.2 (Continued)
BJT Transistor Amplifiers Including the Effect of Rs and RL

Configuration AvL Vo >Vi Zi Zo

VCC

-(RL 7 RC)
RC RB 7 b(re + RE1) RC
RB RE1
Vo
Rs Vi

Zo Including ro:

-(RL 7 RC)
RB 7 b(re + RE)
+ RE 1 RL
Zi
Vs RC
– REt
RE 2 CE

VCC

-(RL 7 RC) RF
RC bre RC
re Av
RF
Vo

Rs Vi Including ro:

-(RL 7 RC 7 ro)
Zo

RC 7 RF 7 ro
+ RL

0 Av 0
Vs
RF
Zi
bre
– re

VCC

-(RL 7 RC)
RC 7 RF
0 Av 0
RF
RC bRE
RE
RF
Vo

Rs Vi
Zo Including ro:

-(RL 7 RC)
RC 7 RF
0 Av 0
+ RL RF
Vs
bRE
RE RE
Zi L
–

packaged system relates to the actual amplifier or network. The system of Fig. 5.61 is
called a two-port system because there are two sets of terminals—one at the input and the
other at the output. At this point it is particularly important to realize that
the data surrounding a packaged system is the no-load data.
This should be fairly obvious because the load has not been applied, nor does it come with
the load attached to the package.

Ii Io

+ +
Zi Zo
Vi AvNL Vo

– –

Thévenin

FIG. 5.61
Two-port system.
295
Equations SUMMARY 351

26 mV
re =
IE
Hybrid parameters:
hie = bre, hfe = bac, hib = re, hfb = -a -1
CE fixed bias:
Zi bre, Zo RC
RC Zi
Av = - , Ai = -Av b
re RC

Zi = R1 7 R2 7 bre,
Voltage-divider bias:
Zo RC
RC Zi
Av = - , Ai = -Av b
re RC

RB 7 bRE,
CE emitter-bias:
Zi Zo RC
RC bRB
Av - , Ai
RE RB + bRE

RB 7 bRE,
Emitter-follower:
Zi Zo re
Zi
Av 1, Ai = -Av
RE
Common-base:
Zi RE re, Zo RC
RC
Av , Ai -1
re
Collector feedback:
RC 7 RF
re
Zi , Zo
1 RC
+
b RF
RC RF
Av = - , Ai
re RC

RF1 7 bre, RC 7 RF2

Collector dc feedback:

RF2 7 RC
Zi Zo
Zi
Av = - , Ai = -Av
re RC
Effect of load impedance:
Vo RL Io Zi
AvL = = AvNL, AiL = = -AvL
Vi RL + Ro Ii RL
Effect of source impedance:
RiVs Vo Ri
Vi = , Avs = = A
Ri + Rs Vs Ri + Rs vNL
Vs
Is =
Rs + Ri
Combined effect of load and source impedance:

AvL =
Vo
=
RL
AvNL, Avs =
Vo
=
Ri # RL AvNL
Vi RL + Ro Vs Ri + Rs RL + Ro
Io Ri Io Rs + Ri
AiL = = -AvL , Ais = = -Avs
Ii RL Is RL
352 BJT AC ANALYSIS Cascode connection:
Av = Av1Av2
Darlington connection (with RE):
bD = b1b2,

Zi = RB 7 (b1b2RE),
b1b2RB
Ai =
(RB + b1b2RE)
re1 Vo
Zo = + re2 Av = 1
b2 Vi

b1b2(R1 7 R2)
Darlington connection (without RE):

R1 7 R2 + Zi
Zi = R1 R2 b1(re1 + b1b2re2) Ai =

where Zi = b1(re1 + b2re2)

RC 7 ro2
Vo b1b2RC
Zo Av = =
Vi Zi
Feedback pair:

Zi = RB 7 b1b2RC
-b1b2RB
Ai =
RB + b1b2RC
re1
Zo Av 1
b2

5.27 COMPUTER ANALYSIS

●
PSpice Windows
BJT Voltage-Divider Configuration The last few chapters have been limited to the dc anal-
ysis of electronic networks using PSpice and Multisim. This section will consider the applica-
tion of an ac source to a BJT network and describe how the results are obtained and interpreted.
Most of the construction of the network of Fig. 5.139 can be accomplished using the
procedures introduced in earlier chapters. The ac source can be found in the SOURCE
library as VSIN. You can scroll down the list of options or simply type in VSIN at the head
of the listing. Once this is selected and placed, a number of labels will appear that define

FIG. 5.139
Using PSpice Windows to analyze the network of Fig. 5.28
(Example 5.2).
 Bảng mạch và công thức của FET
TABLE 6.3
Field Effect Transistors

Symbol and Input Resistance

Type Basic Relationships Transfer Curve and Capacitance
JFET
(n-channel)

Ri 7 100 M
Ci: (1 - 10) pF

MOSFET
depletion type
(n-channel)

Ri 7 1010
Ci: (1 - 10) pF

MOSFET
enhancement type
(n-channel)

Ri 7 1010
Ci: (1 - 10) pF

MESFET
depletion type
(n-channel)

Ri 7 1012
Ci: (1 - 5) pF

MESFET
enhancement type
(n-channel)

Ri 7 1012
Ci: (1 - 5) pF
416 FIELD-EFFECT 6. The transfer characteristics (ID versus VGS) are characteristics of the device itself and

7. When VGS = VP>2, ID = IDSS >4; and at a point where ID = IDSS >2, VGS
TRANSISTORS are not sensitive to the network in which the JFET is employed.
0.3 V.
8. Maximum operating conditions are determined by the product of the drain-to-source
voltage and the drain current.
9. MOSFETs are available in one of two types: depletion and enhancement.
10. The depletion-type MOSFET has the same transfer characteristics as a JFET for drain
currents up to the IDSS level. At this point the characteristics of a depletion-type MOSFET
continue to levels above IDSS, whereas those of the JFET will end.
11. The arrow in the symbol of n-channel JFETs or MOSFETs will always point in to the
center of the symbol, whereas those of a p-channel device will always point out of
the center of the symbol.
12. The transfer characteristics of an enhancement-type MOSFET are not defined by
Shockley’s equation but rather by a nonlinear equation controlled by the gate-to-source
voltage, the threshold voltage, and a constant k defined by the device employed. The
resulting plot of ID versus VGS rises exponentially with incrseasing values of VGS.
13. Always handle MOSFETs with additional care due to the static electricity that exists
in places we might least suspect. Do not remove any shorting mechanism between the
leads of the device until it is installed.
14. A CMOS (complementary MOSFET) device employs a unique combination of a p-
channel and an n-channel MOSFET with a single set of external leads. It has the
advantages of a very high input impedance, fast switching speeds, and low operating
power levels, all of which make it very useful in logic circuits.
15. A depletion-type MESFET includes a metal–semiconductor junction, resulting in char-
acteristics that match those of an n-channel depletion-type JFET. Enhancement-
type MESFETs have the same characteristics as enhancement-type MOSFETs. The
result of this similarity is that the same type of dc and ac analysis techniques can be
applied to MESFETs as was applied to JFETs.

Equations
JFET:

ID = IDSS a 1 - b
VGS 2
VP

ID = IDSS 0 VGS = 0 V, ID = 0 mA 0 VGS = VP, ID = ` 0.3VP 0 ID = IDSS>2

IDSS
, VGS
4 VGS = VP>2

VGS = VP a 1 - b
A IDSS
ID

PD = VDSID
ro
(1 - VGS >VP)2
rd =

MOSFET (enhancement):
ID = k(VGS - VT)2
ID(on)
k =
(VGS(on) - VT)2

6.15 COMPUTER ANALYSIS

●
PSpice Windows
The characteristics of an n-channel JFET can be displayed using the same procedure
employed for the transistor in Section 3.13. The series of curves across the characteristics
plotted against various values of voltage requires a nested sweep within the sweep for the
drain-to-source voltage. The required configuration of Fig. 6.51 is constructed using pro-
cedures described in the previous chapters. In particular, note the complete absence of
resistors since the input impedance is assumed to be infinite, resulting in a gate current of 0 A.
 TABLE 7.1
FET Bias Configurations

Type Configuration Pertinent Equations Graphical Solution

VDD ID
RD IDSS
JFET VGSQ = - VGG
Fixed-bias RG VDS = VDD - IDRS Q-point
VGG –
+ VP VGG 0 VGS

ID
VDD
IDSS
RD
JFET VGS = -IDRS
I'D
Self-bias VDS = VDD - ID(RD + RS) Q-point
RG RS
VP V' 0 VGS
GS

VDD ID
RD
R2VDD IDSS
JFET R1 VG =
R1 + R2 VG
Voltage-divider
VGS = VG - IDRS Q-point RS
bias R2 RS
VDS = VDD - ID(RD + RS)
VP 0 VG VGS

VDD ID
RD IDSS
JFET VGS = VSS - IDRS VSS
Q-point
Common-gate VDS = VDD + VSS - ID(RD + RS) RS
RS
–VSS VP 0 VSS VGS

ID
VDD VGS = -IDRS IDSS
RD
JFET VD = VDD
(RD = 0 ) VS = IDRS I'D
Q-point
VDS = VDD - ISRS
VP V'GS 0 VGS

VDD ID
RD Q-point IDSS
JFET
VGSQ = 0 V
Special case VGS = 0 V
IDQ = IDSS Q
(VGSQ = 0 V) RG
VGG
VP 0 VGS

ID
VDD
Depletion-type Q-point
MOSFET VGSQ = + VGG IDSS
Fixed-bias RG VDS = VDD - IDRS
RS
(and MESFETs)
VP 0 VGG VGS

ID
Depletion-type VDD R2VDD
VG
VG = RS
MOSFET R1 RD Q-point
R1 + R2 IDSS
Voltage-divider
VGS = VG - ISRS
bias R2 RS
VDS = VDD - ID(RD + RS)
(and MESFETs) VP 0 VG VGS

VDD ID
Enhancement VDD
RD
type MOSFET RG RD ID(on)
VGS = VDS
Feedback Q-point
VGS = VDD - IDRD
configuration
(and MESFETs) 0 VGS(Th)
VGS(on)
VDD VGS

Enhancement VDD VG ID
RS
type MOSFET RD R2VDD
R1 VG =
Voltage-divider R1 + R2 Q-point
bias R2 RS VGS = VG - IDRS
(and MESFETs) 0 VGS(Th) VG VGS

450
 6. The method of analysis applied to depletion-type MOSFETs is the same as applied to COMPUTER ANALYSIS 471
JFETs, with the only difference being a possible operating point with an ID level
above the IDSS value.
7. The characteristics and method of analysis applied to enhancement-type MOSFETs
are entirely different from those of JFETs and depletion-type MOSFETs. For values
of VGS less than the threshold value, the drain current is 0 A.
8. When analyzing networks with a variety of devices, first work with the region of the
network that will provide a voltage or current level using the basic relationships asso-
ciated with those devices. Then use that level and the appropriate equations to find other
voltage or current levels of the network in the surrounding region of the system.
9. The design process often requires finding a resistance level to establish the desired volt-
age or current level. With this in mind, remember that a resistance level is defined by the
voltage across the resistor divided by the current through the resistor. In the design
process, both of these quantities are often available for a particular resistive element.
10. The ability to troubleshoot a network requires a clear, firm understanding of the termi-
nal behavior of each of the devices in the network. That knowledge will provide an
estimate of the working voltage levels of specific points of the network, which can be
checked with a voltmeter. The ohmmeter section of a multimeter is particularly helpful
in ensuring that there is a true connection between all the elements of the network.
11. The analysis of p-channel FETs is the same as that applied to n-channel FETs except
for the fact that all the voltages will have the opposite polarity and the currents the
opposite direction.

Equations
JFETs/depletion-type MOSFETs:
Fixed@bias configuration: VGS = -VGG = VG
Self@bias configuration: VGS = -ID RS
R2VDD
Voltage@divider biasing: VG =
R1 + R2
VGS = VG - ID RS
Enhancement-type MOSFETs:
Feedback biasing: VDS = VGS
VGS = VDD - ID RD
R2VDD
Voltage@divider biasing: VG =
R1 + R2
VGS = VG - ID RS

7.17 COMPUTER ANALYSIS

●
PSpice Windows
JFET Voltage-Divider Configuration The results of Example 7.19 will now be verified
using PSpice Windows. The network of Fig. 7.72 is constructed using computer methods
described in the previous chapters. The J2N3819 JFET is obtained from the EVAL library,
and Edit-PSpice model is used to set Beta to 0.222 mA/V2 and Vto to -6 V. The Beta
value is determined using beta = IDSS > VP2 Eq. (6.17) and the provided IDSS and VP. The
results of the Simulation appear in Fig. 7.73 with the dc bias voltage and current levels.
The resulting drain current is 4.225 mA, compared to the calculated level of 4.24 mA—an
excellent match. The voltage VGS is 3.504 V - 5.070 V = -1.57 V versus the calculated
level of -1.56 V in Example 7.19—another excellent match.

Combination Network Next, the result of Example 7.12 with both a transistor and JFET
will be verified. For the transistor Bf is set to 180, whereas for the JFET, Beta is set to
0.333 mA/V2 and Vto to -6 V as called for in the example. The results for all the dc levels
appear in Fig. 7.73. Note again the excellent comparison with the calculator solution, with
VD at 11.44 V compared to 11.07 V, VS = VC at 7.138 V compared to 7.32 V, and VGS at
3.380 V - 7.138 V = 3.76 V compared to -3.7 V.
 TABLE 8.1
Zi, Zo, and Av for various FET configurations

Configuration Zi Zo Vo
Av =
Vi
Fixed-bias
[JFET or D-MOSFET]
Fixed-bias +VDD
[JFET or D-MOSFET] Medium (2 k ) Medium (-10)
RD
C2 High (10 M )
C1
Vo = RD rd = - gm(rd RD)
Vi = RG
Zo RD -gmRD (rd Ú 10 RD)
RG (rd Ú 10 RD)
Zi
–V
GG
+
Self-bias
bypassed RS
[JFET or D-MOSFET]
Self-bias +VDD
bypassed RS Medium (2 k ) Medium (- 10)
[JFET or D-MOSFET] RD
C2
High (10 M )
Vo = R D rd = -gm(rd RD)
C1 = RG
Vi
Zo RD -gmRD
(rd Ú 10 RD) (rd Ú 10 RD)

Zi
RG
RS CS

Self-bias
unbypassed RS
[JFET or D-MOSFET]
Low (-2)
c 1 + gmRS + dR
Self-bias +VDD RS
unbypassed RS rd D gmRD
[JFET or D-MOSFET] High (10 M ) =
c 1 + gmRS + d
RD =
C2 RS RD RD + RS
Vo + 1 + gmRS +
C1 = RG rd rd rd
Vi
Zo
= RD gmRD
Zi rd Ú 10 RD or rd = -
RG 1 + gmRS 3 rd Ú 10 (RD + RS) 4
RS

Voltage-divider bias
[JFET or D-MOSFET]
Voltage-divider bias +VDD
[JFET or D-MOSFET]
Medium (2 k ) Medium (-10)
RD
C2 High (10 M )
R1
Vo = RD rd = -gm(rd RD)
C1
Vi = R1 R2
Zo RD - gmRD (rd Ú 10 RD)
(rd Ú 10 RD)
Zi
R2
RS CS

514
 TABLE 8.1
(Continued)

Configuration Zi Zo Vo
Av =
Vi
Common-gate
[JFET or D-MOSFET]
Medium (+10)
Common-gate +VDD Low (1 k )
[JFET or D-MOSFET] Medium (2 k ) RD
RD rd + RD gmRD +
c d rd
Q1
C1 C2 = RS = RD rd =
Vi Vo 1 + gmrd RD
1 +
RD rd
1 (Rd Ú 10 RD)
Zi RS Zo RS
RG CS gm gmRD
(rd Ú 10 RD) (rd Ú 10 RD)

Source-follower
[JFET or D-MOSFET]
Low ( 6 1)
Source-follower Low (100 k )
[JFET or D-MOSFET] +VDD
High (10 M ) gm(rd RS)
C1 = rd RS 1>gm =
Vi 1 + gm(rd RS)
C2 = RG
Zi RG
Vo RS 1>gm gmRS
(rd Ú 10 RS)
RS
Zo
1 + gmRS
(rd Ú 10 RS)

Drain-feedback bias
E-MOSFET
Drain-Feedback bias +VDD Medium (1 M )
E-MOSFET Medium (2 k ) Medium (-10)
RD RF + rd RD
RF C2 = = R F rd R D = -gm(RF rd RD)
Vo 1 + gm(rd RD)
C1
Vi RF RD -gmRD
(RF, rd Ú 10RD) (RF, rd Ú 10RD)
Zo
1 + gmRD
Zi (rd Ú 10 RD)

Voltage-divider bias
E-MOSFET
Voltage-divider bias +VDD
E-MOSFET
Medium (2 k ) Medium (−10)
RD
C2 Medium (1 M )
R1 D Vo
= RD rd = - gm(rd RD)
C1
G = R1 R2
Vi
Zo RD -gmRD
S (rd Ú 10 RD) (rd Ú 10 RD)
Zi R2 RS

515
 7. The voltage gain for the fixed-bias and self-bias JFET configurations (with a bypassed COMPUTER ANALYSIS 531
source capacitance) is the same.
8. The ac analysis of JFETs and depletion-type MOSFETs is the same.
9. The ac equivalent network for an enhancement-type MOSFET is the same as that
employed for JFETs and depletion-type MOSFETs. The only difference is the equa-
tion for gm.
10. The magnitude of the gain of FET networks is typically between 2 and 20. The self-
bias configuration (without a bypass source capacitance) and the source-follower
are low-gain configurations.
11. There is no phase shift between input and output for the source-follower and common-
gate configurations. Most others have a 180° phase shift.
12. The output impedance for most FET configurations is determined primarily by RD.
For the source-follower configuration it is determined by RS and gm.
13. The input impedance for most FET configurations is quite high. However, it is quite
low for the common-gate configuration.
14. When troubleshooting any electronic or mechanical system, always check the
most obvious causes first.

Equations
ID
gm = yfs =
VGS

0 VP 0
2IDSS
gm0 =

gm = gm0 c 1 - d
VGS
VP

A IDSS
ID
gm = gm0

`
1 VDS
rd = =
yos ID VGS = constant
For JFET and depletion-type MOSFET configurations, see Tables 8.1 and 8.2.

8.19 COMPUTER ANALYSIS

●
PSpice Windows
JFET Fixed-Bias Configuration The first JFET configuration to be analyzed in the ac
domain will be the fixed-bias configuration of Fig. 8.61, using a JFET with VP 4V
and IDSS 10 mA. The 10-M resistor was added to act as a path to ground for the
capacitor but is essentially an open circuit for the ac analysis. The J2N3819 n-channel
JFET from the EVAL library was used, and the ac voltage is to be determined at four dif-
ferent points for comparison and review.
The constant Beta is determined by

0 VP 0
IDSS 10 mA
Beta = 2
= = 0.625 mA>V2
42V2
and is inserted in the Edit Model dialog box obtained by the sequence EDIT-PROPERTIES.
Vto is also changed to 4 V. The remaining elements of the network are set as described
for the transistor in Chapter 5.
An analysis of the network results in the printout of Fig. 8.62. The CIRCUIT
DESCRIPTION includes all the elements of the network along with their assigned nodes.
In particular, note that Vi is set at 10 mV at a frequency of 10 kHz and a phase angle of 0