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experiment 8 //design of FSM - Vending Machine

The document describes a finite state machine (FSM) implementation of a vending machine using Verilog code. It includes the code for the FSM module, testbench module, and code for a mealy state machine implementation and corresponding testbench.

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Rishab
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20 views

experiment 8 //design of FSM - Vending Machine

The document describes a finite state machine (FSM) implementation of a vending machine using Verilog code. It includes the code for the FSM module, testbench module, and code for a mealy state machine implementation and corresponding testbench.

Uploaded by

Rishab
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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//EXPERIMENT 8

//Design of FSM – Vending Machine

CODE
module fsm_(nw_pa,clk,coin,rst);
output reg nw_pa;

input [1:0] coin;


input clk,rst;
reg [1:0] state;
reg [1:0] next_state;

parameter [1:0] s0=2'b00;


parameter [1:0] s5=2'b01;
parameter [1:0] s10=2'b10;
parameter [1:0] s15=2'b11;
always@(posedge clk)

begin
if(rst)
state=s0;
else

state=next_state;
end
always@(state,coin)
begin

case(state)
s0:
begin
if(coin==2'b00)

next_state=s0;
else
if(coin==2'b01)
next_state=s10;

else
if(coin==2'b10)
next_state=s10;
end

s5:
begin
if(coin==2'b00)
next_state=s5;

else
if(coin==2'b01)
next_state=s10;
else
if(coin==2'b10)

next_state=s15;
end
s10:
begin

if(coin==2'b00)
next_state=s10;
else
if(coin==2'b01)

next_state=s15;
else
if(coin==2'b10)
next_state=s15;

end
s15:
begin
next_state=s0;

end
default:next_state=s0;
endcase
end

always@(state)
begin
case(state)
s0:nw_pa<=1'b0;

s5:nw_pa<=1'b0;
s10:nw_pa<=1'b0;
s15:nw_pa<=1'b1;
default:nw_pa<=1'b0;
endcase

end
endmodule

TESTBENCH

module fsm_TBv;
// Inputs
reg clk;
reg [1:0] coin;

reg rst;
// Outputs
wire nw_pa;
// Instantiate the Unit Under Test (UUT)

fsm_uut (
.nw_pa(nw_pa),
.clk(clk),
.coin(coin),

.rst(rst)
);
initial begin
clk= 0;coin= 2'b00; rst=1; #100;

coin = 2'b01;rst = 0;#100;


coin = 2'b01;rst = 0;#100;
coin = 2'b01;rst = 0;#100;
coin = 2'b10;rst = 0;#100;

coin = 2'b01;rst = 0;#100;


coin = 2'b11;rst = 0;#100;
// Add stimulus here
end
always #25 clk=~clk;

endmodule
//POSTLAB
CODE
module mealy_(

input wire clk,

input wire reset,

input wire data_in,

output reg detected

);

// Define states

parameter S0 = 2'b00;

parameter S1 = 2'b01;

parameter S2 = 2'b10;

parameter S3 = 2'b11;

// Define outputs

reg [1:0] state, next_state;

// Initialize state

always @ (posedge clk or posedge reset) begin

if (reset)

state <= S0;

else

state <= next_state;

end

// State transition logic

always @* begin
case(state)

S0: begin

if (data_in)

next_state = S1;

else

next_state = S0;

end

S1: begin

if (data_in)

next_state = S1;

else

next_state = S2;

end

S2: begin

if (data_in)

next_state = S3;

else

next_state = S0;

end

S3: begin

if (data_in)

next_state = S1;

else

next_state = S0;

end

default: next_state = S0;

endcase

end
// Output logic

always @ (posedge clk) begin

case(state)

S3: detected <= 1;

default: detected <= 0;

endcase

end

endmodule

TESTBENCH

module mealy_TB_v;

// Inputs

reg clk;

reg reset;

reg data_in;

// Outputs

wire detected;

// Instantiate the Unit Under Test (UUT)

mealy_ uut (

.clk(clk),

.reset(reset),

.data_in(data_in),

.detected(detected)

);

initial begin

// Initialize Inputs

clk = 0;

reset = 1;

data_in = 0;
// Wait 100 ns for global reset to finish

#100; reset = 0;

#100; data_in = 1;

#100; data_in = 1;

#100; data_in = 0;

#100; data_in = 1;

#100; data_in = 0;

#100; data_in = 1;

#100; data_in = 0;

#100; data_in = 1;

// Add stimulus here

end

always #25 clk=~clk;

endmodule

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