Future University

Faculty of Computers and Information Technology

Mini Calculator

Nour eldin Hossam Mahmoud Aly Fahmy 20232773

Mohamed Sherif Mohamed Ibrahim Mohamed 20233901

Ehab Abdelaziz Mohamed Abdelaziz Elshazly 20233068

Salma Ahmed Mohmed Ahmed 20234395

Nada Abdulhamid Aiad Gharghuti 20234848

May 2024
 Future University
Faculty of Computers and Information Technology
Logic design (CS111) Spring 2024

Abstract:

This report outlines the creation of a 4-bit mini calculator using logic design principles. Capable of handling
basic arithmetic operations like addition, subtraction, multiplication, and division, this calculator employs
fundamental logic gates and components for efficiency. Users input binary numbers and select operations via
a user interface, with results displayed on an output screen. Primarily an educational tool, it aids in
understanding digital logic and binary arithmetic. Additionally, it holds potential for prototype development
and embedded systems. Future iterations may focus on efficiency improvements and additional features.

Introduction:

This report discusses the creation of a 4-bit mini calculator using basic logic design principles. This calculator
can handle simple arithmetic tasks like addition, subtraction, multiplication, and division with 4-bit binary
numbers. By combining fundamental logic gates and components, we've developed separate modules for
each arithmetic operation. This mini calculator is not only useful for educational purposes, helping learners
understand digital logic and binary arithmetic, but it also has practical applications in prototype development
and embedded systems. Let's explore its design and functionality further .

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 Future University
Faculty of Computers and Information Technology
Logic design (CS111) Spring 2024

The Components:

Frist (Input Operation)

Turth Table for Input A :

EN A1 A0 a b c d e f g
0 X X 0 0 0 0 0 0 0
1 0 0 1 1 1 1 1 1 0
1 0 1 0 1 1 0 0 0 0
1 1 0 1 1 0 1 1 0 1
1 1 1 1 1 1 1 0 0 1

Turth table for Input B:

EN B1 B0 a b c d e f g
0 X X 0 0 0 0 0 0 0
1 0 0 1 1 1 1 1 1 0
1 0 1 0 1 1 0 0 0 0
1 1 0 1 1 0 1 1 0 1
1 1 1 1 1 1 1 0 0 1

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 Future University
Faculty of Computers and Information Technology
Logic design (CS111) Spring 2024

K-map for Input A:

a A0
a = ((A0)` + A1).EN
A1 0 1
0 1
7y 1
1 1

b A0
0
A1 1 b = 1.EN
0 1 1

1 1 1

d A0
c A0
A1 0 1
A1 01 1
0 d = c((A 0)`0 + A
= (A (A1 1).EN=
)`).ENa
1 1 11
01

1 1
e A0
A1 0 1 e = (A0)`.EN
0 1
1g 1 A0
Af 0 A0 1
1

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A01 0 1
0 1
1 1
1 f = ((A0)`.( A1 )`).EN
 Future University
Faculty of Computers and Information Technology
Logic design (CS111) Spring 2024

K-map for Input B:

a B0 b B0 c B0
B1 0 1 B1 0 1 0
B1 1
0 1 0 1 1 0 1 1
1 1 1 1 1 1 1 1

b = c1.EN
= (B0 + (B1)`).EN

d B0 e B0 f B0
B1 0 1 B1 0 1 B1 0 1
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0 1 0 1 0 1
1 1 1 1 1 1
 Future University
Faculty of Computers and Information Technology
Logic design (CS111) Spring 2024

+ B1).EN= a e = (B0)`.EN f = ((B0)`.( B1 )`).EN

Circuit design for the input:

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