Govt.

Postgraduate College of Science, Faisalabad BS-CS 3rd & 5th Semesters - ASM

&

M.Rizwan
Computer Lecturer

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Govt. Postgraduate College of Science, Faisalabad BS-CS 3rd & 5th Semesters - ASM

Computer Organization & Assembly Language

16-Bit
Processor
NASM
64-Bit
&
Processor
DOSBox
Assembly
Language
Programming
MASM
& AFD
VS 2017
32-Bit
Processor

Assembly Language gives you direct control of the system's

resources. The involves setting processor registers, accessing
memory locations, and interfacing with other hardware elements.
This requires a significantly deeper understanding of exactly how
the processor and memory work.

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Govt. Postgraduate College of Science, Faisalabad BS-CS 3rd & 5th Semesters - ASM

Interrupts
In a general sense, an interrupt is a pause or hold in the current flow. For example, if you are
talking on the phone and the door-bell rings, the phone conversation is placed on hold, and
the door answered. After the salesperson is sent away, the phone conversation is resumed
(where the conversation left off).
In computer programming an interrupt is also pause, or hold, of the currently executing
process. Typically, the current process is interrupted so that some other work can be
performed. An interrupt is usually defined as an event that alters the sequence of instructions
executed by a processor. Such events correspond to signals generated by software and/or
hardware. For example, most (I/O) devices generate an interrupt in order to transmit or
receive data. Software programs can also generate interrupts to initiate I/O as needed,
request OS services, or handle unexpected conditions.
Handling interrupts is a sensitive task. Interrupts can occur at any time, the kernel tries to get
the interrupt addressed as soon as possible. Additionally, an interrupt can be interrupted by
another interrupt.

Multi-user Operating System

A modern multi-user Operating System (OS) supports multiple programs executing, or to
appearing to be executing, simultaneously by sharing resources as necessary. The OS is
responsible for managing and sharing the resources. These resources include the CPU cores,
primary memory (i.e., RAM), secondary storage (i.e., disk or SSD), display screen, keyboard,
and mouse. For example, multiple programs must share the available CPU resources (core or
cores as applicable).
The interrupt mechanism is the primary means that the OS uses in order to provide the
resource sharing. Consequently, understanding how interrupts are processed by the
computer provides insight into how the operating system is able to provide multiprocessing
functions. When an interrupt occurs, the current process is interrupted (i.e., placed on hold),
the interrupt is handled (which depends on the specific reason for the interrupt), and then
eventually the process is resumed. The OS may choose to perform other tasks or processes
before the original processes is resumed. The interrupt is handled by a special software
routine called an Interrupt Service Routine (ISR) (also called Interrupt Handler, Device Driver,
etc.). By using interrupts and quickly switching between various processes, the OS is able to
provide the illusion that all processes are executing simultaneously.

Interrupt Timing
The timing of interrupts may occur synchronously or asynchronously. These terms are fairly
common terms in computer processing and are explained in the following sections.

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Govt. Postgraduate College of Science, Faisalabad BS-CS 3rd & 5th Semesters - ASM

Asynchronous Interrupts
Asynchronous means that the interrupts occur, independent of the working of the processor,
i.e. independent of the instruction currently executing.
Interrupts must be asynchronous as they are generated by the external world which is
unaware of the happenings inside the processor. True interrupts that occur in real time are
asynchronous with the execution.
In the context of computer interrupts, an asynchronously occurring interrupt means that the
interrupt may occur at an arbitrary time with respect to program execution. Asynchronous
interrupts are unpredictable relative any specific location within the executing process.
For example, an external hardware device might interrupt the currently executing process at
an unpredictable location.

Synchronous Interrupts
Synchronous events are those that occur side by side with another activity.
Synchronously occurring interrupts typically occur while under CPU control and are caused by
or on behalf of the currently executing process. The synchronous nature is related to where
the interrupt occurs and not a specific clock time or CPU cycle time. Synchronous interrupts
typically reoccur at the same location (assuming nothing has changed to resolve the original
cause).

Interrupt Categories
Interrupts are typically categorized as hardware or software.

Hardware Interrupt
Hardware interrupts are typically generated by hardware. Hardware interrupts can be issued
by
▪ I/O devices (keyboard, network adapter, etc.)
▪ Interval timers
▪ Other CPUs (on multiprocessor systems)
Hardware interrupts are asynchronously occurring. An example of a hardware interrupt is
when a key is typed on the keyboard. The OS cannot know ahead of time when, or even if,
the key will be pressed. To handle this situation, the keyboard support hardware will generate
an interrupt. If the OS is executing an unrelated program, that program is temporarily
interrupted while the key is processed. In this example, that specific processing consists of
storing the key in a buffer and returning to the interrupted process. Ideally, this brief
interruption will have little impact in the interrupted process.
Hardware interrupts are generated by devices, these devices can be chips on the system
board or they can be chips on cards plugged into the computers external I/O bus slots.

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Govt. Postgraduate College of Science, Faisalabad BS-CS 3rd & 5th Semesters - ASM

Software Interrupt
A software interrupt is a call to an operating system procedure. Most of these procedures,
called interrupt handlers, provide input–output capability to application programs. They are
used for such tasks as the following:
▪ Displaying characters and strings
▪ Reading characters and strings from the keyboard
▪ Displaying text in color
▪ Opening and closing files
▪ Reading data from files
▪ Writing data to files
▪ Setting and retrieving the system time and date
A software interrupt is produced by the CPU while processing instructions. This is typically a
programmed exception explicitly requested by the programmer. Such interrupts are typically
synchronously occurring and often used to request system services from the OS. For example,
requesting system services such I/O.
Software interrupts are generated by machine code instructions within programs.

Types of Hardware Interrupt

▪ Maskable interrupts
▪ Non-maskable interrupts

Maskable Interrupt or Interrupt Request (IRQ)

Maskable interrupts are typically issued by I/O devices. As the name 'maskable' implies,
maskable interrupts can be ignored, or masked, for a short time period. This allows the
associated interrupt processing to be delayed.
The IRQ, an interrupt that can be delayed if the processor is busy with some more important
process.

Non-Maskable Interrupt (NMI)

Non-maskable interrupts (NMI's) must be handled immediately. This includes some OS
functions and critical malfunctions such as hardware failures. Non-maskable interrupts are
always processed by the CPU.
The Non Maskable Interrupt (NMI) an interrupt that must be processed when it occurs.

Interrupt Levels
Interrupt Levels refer to the privilege level at which the interrupt code executes. This may be
a higher privilege level than the interrupted code is executing. The processor executes code
in one of four privilege levels as follows:

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Govt. Postgraduate College of Science, Faisalabad BS-CS 3rd & 5th Semesters - ASM

Level Description
Level 0 Full access to all hardware resources (no restrictions). Used by only the
lowest level OS functions.
Level 1 Somewhat restricted access to hardware resources. Used by library
routines and software that interacts with hardware.
Level 2 More restricted access to hardware resources. Used by library routines
and software that has limited access to some hardware.
Level 3 No direct access to hardware resources. Application programs run at this
level.

Should an application program executing at level 3 be interrupted by a hardware interrupt for

the keyboard, the keyboard interrupt handler must execute at level 0. The following diagram
shows the relationship of the levels.
Level 3

Level 2

Level 1

Level 0

Privilege Level

Interrupt Processing
When an interrupt occurs, it must be handled or processed securely, quickly, and correctly.
The general idea is that when the currently executing process is interrupted it must be placed
on hold, the appropriate interrupt handing code found and executed. The specific interrupt
processing required depends on the cause or purpose of the interrupt. Once the interrupt is
serviced, the original process execution will eventually be resumed.
To generate an interrupt the INT instruction is used. The routine that executes in response to
an INT instruction is called the Interrupt Service Routine (ISR) or the interrupt handler.

INT Instruction
The INT (call to interrupt procedure) instruction calls a system subroutine also known as an
interrupt handler. Before the INT instruction executes, one or more parameters must be
inserted in registers. At the very least, a number identifying the particular procedure must be
moved to the AH register. Depending on the function, other values may have to be passed to
the interrupt in registers. The syntax is
INT number
where number is an integer in the range 0 to FF hexadecimal.

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Govt. Postgraduate College of Science, Faisalabad BS-CS 3rd & 5th Semesters - ASM

Interrupt Vectoring
The CPU processes the INT instruction using the interrupt vector table, which, as we’ve
mentioned, is a table of addresses in the lowest 1024 bytes of memory. Each entry in this
table is a 32-bit segment-offset address that points to an interrupt handler. The actual
addresses in this table vary from one machine to another. Figure illustrates the steps taken
by the CPU when the INT instruction is invoked by a program:
▪ Step 1: The operand of the INT instruction is multiplied by 4 to locate the matching
interrupt vector table entry.
▪ Step 2: The CPU pushes the flags and a 32-bit segment/offset return address on the
stack, disables hardware interrupts, and executes a far call to the address stored at
location (10h * 4) in the interrupt vector table (F000:F065).
▪ Step 3: The interrupt handler at F000:F065 executes until it reaches an IRET (interrupt
return) instruction.
▪ Step 4: The IRET instruction pops the flags and the return address off the stack, causing
the processor to resume execution immediately following the INT 10h instruction in
the calling program.
Interrupt Vectoring Process

Interrupt Vector Table (IVT)

The interrupt vector table points to the locations of the interrupt routines that carry out the
functions associated with the interrupts.

Common Interrupts
Interrupts introduce temporary breakage in the program flow, sometimes programmed
(software interrupts) and un-programmed at other times (hardware interrupts).
Interrupts call interrupt service routines (ISRs) either in the BIOS or in DOS. Some frequently
used interrupts are the following:

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Govt. Postgraduate College of Science, Faisalabad BS-CS 3rd & 5th Semesters - ASM

Interrupt No. Description

INT 0h CPU Divide by zero
INT 1h Debug single step
INT 2h Non-Maskable Interrupt
INT 3h Debug Breakpoints
INT 4h Arithmetic Overflow
INT 5h BIOS provided Print Screen routine
INT 8h IRQ0, Time of day hardware services
INT 9h IRQ1, Keyboard Interface
INT 10h Video services
INT 14h Serial port I/O routines
INT 16h Keyboard I/O services
INT 17h Printer I/O services
INT 1Ah Time of Day services
INT 1Ch User Timer Interrupt (Timer tick – provides 18.2 ticks per second)
INT 21h All MS-DOS services
INT 28h to 3Fh Reserved for DOS
INT 40h to 4Fh Reserved for BIOS
INT 70h IRQ8, ISA bus Real time clock
INT 76h IRQ14, ISA bus hard disk controller
INT 77h IRQ15, (available hardware interrupt)
INT 86h to F0h Used by basic
INT FFh Unused

Real-Time Hardware Interrupts

A hardware interrupt is generated by the Intel Programmable Interrupt Controller (PIC), which
signals the CPU to suspend execution of the current program and execute an interrupt service
routine. For example, a keyboard character waiting at the input port would be lost if not saved
by the CPU, or characters received from the serial port would be lost if not for an interrupt-
driven routine that stores them in a buffer.
Occasionally, programs must disable hardware interrupts when performing sensitive
operations on segment registers and the stack. The CLI (clear interrupt flag) instruction
disables interrupts, and the STI (set interrupt flag) instruction enables interrupts.

IRQ Levels

Interrupts can be triggered by a number of different devices on a PC, including those listed in
below Table. Each device has a priority, based on its interrupt request level (IRQ). Level 0 has
the highest priority, and level 15 has the lowest. A lower-level interrupt cannot interrupt a
higher-level one still in progress. For instance, if communications port 1 (COM1) tried to
interrupt the keyboard interrupt handler, it would have to wait until the latter was finished.
Also, two or more simultaneous interrupt requests are processed according to their priority
levels. The scheduling of interrupts is handled by the PIC.

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Govt. Postgraduate College of Science, Faisalabad BS-CS 3rd & 5th Semesters - ASM

Let’s use the keyboard as an example: When a key is pressed, the PIC sends an INTR signal to
the CPU, passing it the interrupt number; if external interrupts are not currently disabled, the
CPU does the following, in sequence:

1. Pushes the Flags register on the stack.

2. Clears the Interrupt flag, preventing any other hardware interrupts.
3. Pushes the current CS and IP on the stack.
4. Locates the interrupt vector table entry for INT 9 and places this address in CS and IP.

IRQ Assignments

IRQ Interrupt No. Description

0 8 System timer (18.2 times/second)
1 9 Keyboard
2 0Ah Programmable Interrupt Controller
3 0Bh COM2 (serial port 2)
4 0Ch COM1 (serial port 1)
5 0Dh LPT2 (parallel port 2)
6 0Eh Floppy disk controller
7 0Fh LPT1 (parallel port 1)
8 70h CMOS real-time clock
9 71h (Redirected to INT 0Ah)
10 72h (Available) sound card
11 73h (Available) SCSI card
12 74h PS/2 mouse
13 75h Math coprocessor
14 76h Hard disk controller
15 77h (Available)

Next, the BIOS routine for INT 9 executes, and it does the following in sequence:

1. Reenables hardware interrupts so the system timer is not affected.

2. Inputs a scan code from the keyboard port, attempts to convert it to an ASCII
character, or assigns an ASCII code equal to zero. It then stores the scan code and ASCII
code in the keyboard buffer, a 32-byte circular buffer in the BIOS data area.
3. Executes an IRET (interrupt return) instruction, which pops IP, CS, and the Flags
register off the stack. Control returns to the program that was executing when the
interrupt occurred.

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Govt. Postgraduate College of Science, Faisalabad BS-CS 3rd & 5th Semesters - ASM

16-Bit MS-DOS Programming

MS-DOS Function Calls (INT 21h)

16-Bit BIOS-Level Programming

Keyboard Input (INT 16h)

Expert MS-DOS Programming

Interrupt Handling

Best of Luck 😊

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