Exam Code 0921

Sub. Code: 6835

2622
BE (nformation Technology)
Third Semester
ESC-301 Digital Electronics
Max. Marks: 50
Time allowed: 3 Hours
NOTE Atempt fxe questions in all, incsding Question Na I which is compulsory
and selecting ho questions from each Unt
Answer the follewing
a) Priority encoder
b) Single output functions
e) EPROM
d) Weighted binary Codes
e) Enable circuit
n Shift register
g) Next state decoder
h) RAM
i) FPGA
j) ADC (LOxi)
UNIT-I

Design Multiplexer with the heip of diagrams. (10)

II. A
combinational circuit is defined by the functions:

Fi (A, B. C)- E(3.5.6,7)

F (A. B, C) - I (0.24,7)
Implement it with a PLA having three inputs, four product terms, and two outputs.
(10)
IV Design Modulo-N Ripple Counter. (10)

UNIT-I1
Explain Successive approximation A/D converter. (10)
P.IO.

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 Sub. Cle: 6835
()
VI Explain digital logie families. Also compare characteristics of TTL. ECL, MOS nd
CMOS logic circuits. (10)

VII.
a) Briefly explain the state reduction and assignment rules for synchronous sequential
circuit.

b) Explain various characteristics of digital circuits (2x5)

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 Exam. Code 0921
Sub. 6836
2012
BE. (hformation Technology):
Semestee
PC-IT-303: Database Management System
Time allowed: 3 Hoars Mx Murk s6
NOTE Aitenyr x questions in all, ineluding Questlon No whh s conpalsor
and selecting heo questions rom each Unit.

1
Answer the following
a) What is meant by redundancy of data? is it desirable in a database containing
private information?
b) What is the result of applying 'hot operator on a column containing nul
value?
) What is the purpose of a weak entity set? Why not model it together with the
strong entity set?
) Give an example of atrivial functional dependency.
e) Can relational algebra queries be executed over the DBMS directly?
Which Normal Form is the most desirable overa banking database that needs
to analyse data pertaining to individual entity sets?
g) State the database object that will be used if we want to maintain complex
integrity constraints in a database. Also give reason.
h) Which file organisation and index supports both sequential and random access
to file records?
) Which type of serializability of schedules: conflict or view, is more desirable?
) What is the difference in consisteney and integrity of a database? Can one
exist withou the other? (10x1)

UNIT-I
Explain the architecturc of a database management system with the hclp of a diagram.
What is the placement of these components with respect to the operating
system? (10)

Consider the relational database given below:

employee eid e name, street, city)
works e d compary_name, salary)
comparty (comany, name, city)
manages (e mgr id)
Write relational calculus qucries for the following
a) Find e id, e name and city of all employees who work
for ABC Corporation and have salary more
than 50,000.
b) Find all names of employees who live in sane city as
company for which they work
(2x5)
IV
Design an ER diagram for keeping track of activities of your favorite sports team.
Store the matches played, scores in each match, playersin each match, and individual
player statistics for each match. Summary statistics may be derived attributes.
(10)

P.TO.

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 Exam.Code:0921
Sub. Code: 6473
2122
B.E. (Information Technology)
Third Semester
ESC-301: Digital Electronics
Max, Marks: 50
Time allowed: 3 Hours
NOTE: Attempt ive questrions in all, including Question No. I which is compulsory
and selecting two questions from each Part.

1. a) Write down disadvantages of Analog Signals.

b) What are applications of Grey Codes?
c) Define following parameters:
i) Fan-in ii) Power Dissipation

d) Define redundant group in K-map.

e) Write various types of ROMs. (5*2=10)

Part-A
2 a) Apply Demorgan's theorem to the following expression:
AB (CD + EF).(AB +CD)
b) Using Boolean Algebra show that
(A+B) (A+C) (B+C) =AC +BA (2*5=10)

flip-flops in detail.
3. a) Explain the triggering methods of latches and it avoided? (2*5=10)
b) What is Race around Condition? How can be
flowing
Design a synchronous counter using J-K filp-flop to count the
states only: (10)
1,2,3, 1,2.
Part-B.
5 a) Write down the drawbacks of Binary Weighted Resistance D/A
converters.

b) What are the advantages of the R-2R ladder DACover the weighted (2*5=10)
resistor type DAC?

6 Explain the various characteristics of logic families in the

detail. (10)

7 Explain the classifications of memories and their characteristics in the

detail.
(10)

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 Exam.Code:0921
Sub. Code: 6835
2021
B.E. (Information Technology)
Third Semester
ITE-303: Digital Electronics
Time allowed: 3 Hours
Max. Marks: 50
NOTE: Atempt ive questions in all,
and selecting two questions from including Ouestion No. ! which is compulsory
each Unit.
-X-X
Answer the following:
a) Priority encoder
b) Single output functions
c) EPROM
d) Excitation Table
e) Enable circuit (5x2)
UNIT- 1I

II. Design master slave JK flip flop. (10)

Acombinational circuit is defined by the functions;

Fi(A. B. C) = (3.5,6.7)
Fz(A, B, C) =E(0,2,4,7)
Implement it with a PLA having three inputs four product terms, and two outputs.
(10)
IV. Design Modulo-N Ripple Counter. (10)

UNIT- II
V Explain Successive approximation A/D converter. (10)

VI Explain digital logic families. Also compare characteristics of TTL, ECL, MOS and
CMOS logic circuits. (10)

VIL. a) Explain recading and writing operation in RAM.

b) Explain various characteristics of digital circuits. (2x5)

X-X-X

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Exam. Code:0921
Sub. Code: 6954
 Exam.Code:0921
Sub. Code: 6835
1129
B.E. (Information Technology)
Third Semester
ITE-303: Digital Electronics
Time allowed: 3 Ilours Max. Marks: 50
NOTE:-Attempt ive questions in all, includ1ng Ouestion o. I which is compulsory
and selecting wo questionsfrom each Unit.
Y-1-Y

Answer the following:

a) Explain Demorgan's Law.
b) What do you mean by terms "Fan-in" and "Fan-out
c) What are the applications of Multiplexer?
d) What is Race round condition? What is its solution?
e) Compare PLA and PAL. (5x2)
UNIT -I
A process is defined by the logical expression, Z= AB + BC + CD BD + BC.
Reduce the above expression to minimum no. of literals using:
a) Boolean algebra
b) K-map (2x5)
What is a ring counter? What type of Flip-Flop is used in such counters? Write one
application of this counter. (10)

IV. Explain error correcting codes in detail. (10)

UNIT-II
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Write notes on following:
a) ECL and DTL logic families
b) Shift Registers (2x5)

VI.
What is a dual slope A/D converter? Draw its circuit and explain its working. (10)
What is the difference between ROM and RAM? Draw the basic structure of RAM
VIL.
cell. Compare static and dynamic RAM cells. (10)

X-X-X
 Exan. Code-0921
Sub. Code: 6835
1127
B.E. (Information Technology)
Third Semester
rTE-3Z4: Digital Electronics
Max. Marks: 50
Time allowed: 3 Hours
Atempt fie questions in all, Inchuding Quesrion No.I which is comptlsory
NOTE
and selecting wo questions from each Part.
X-X-X

L(a) Esplain state dingram for synchronous sequential machines.

(b) What type of codes are used in K-map designing and why?
communication systent.
() Differentiate between encoder and decoder on the basis of
(d) Whlch is the fastest logie family and wy?
(52-19)
(e) Exptain the role of shift registers.
Part A
implement the circuit using NAND gates only
I1. (a) Solve the following using K-map and (5)
F-Em(0,2.3,8,1 1,12)+ d(19,14)
Explain SR lip-flop. (5)
(b) What is the role of flip-flop in an electronic cireuit?
suitable diagram. (5)
IL. (a) Explain four bit PSO shift register with the help of
(5)
(b) Explain Hamming codes. Give its applications.
IV. ()Design a synchronous counter using JK flip-lops to count the following sequence

0,2,5,6,7 21/61
Avoid lockout condition.
(b) Whatsa digital comparator? Explain single bit digital comparator.

Part B
drawbacks. (5)
V. (a) Explain binary weighted resistance type DVA converter. Lst its
(b) Explain flash type A/D converter with the belp of un example. (5)
VL (a) Design and explain the circuit of ECL ORINOR gate. (5)
(b) Give eomparison of logie families. (5)

VIL. (a) Write slhort note on

) FPGA
(ü)PLA and PAL

(b) Design synch ronous sequential machine for the following state diagram

(5)
 anables
boolean alvehra luic eales k
n Dernonstrate the understunding of Number
systems, logic gates, flip flops, multiplerers,
Couten. acyuired knowledge to design
Rinal and sequential cincuits
IV. Analyze and examine the data converners,
digital logic families, mernories cmployed in
Stbesis and cunstruct digital circuits by
employing logic gates, flip flops, data
coverters, memorics.
VI hthe a l cinuits
irned: und tnterpret he output
SYLLABUS
Nole: The examiner shall set seven questians of 10 marks ench. Flnst questian has to be

atiempt at least twp uupstions rum cach section, All che coure outcomos mus be coerrd
by the queston paper.
SECTION-A COts)
Introduction
Representation of Logie, Logic Variables, Boolecan Algebra, Booleun Expressions and
minimization of Booleun expresion using K-Map, Review of Logic Gates & Fip-lops,
deign &Implementationt of Adde, Subtractux,
Nmomparators, Maltiplexer, DeMultipleer, Encodet
Code Coverters,
Decimal, Binary, Hexadecimal, Otal's complerment, 2' complenent, addition and
utratiom, weighted binary codes, Erux detecting codes, Errur corecting codes,
071
Alphanurnerc codes.
a Sain Registers
BE-INFORMATION TECHNOLOGY SCHEME & sYLLABUS Bach 2021-25 49 Pae

50/173

Ripple Counters, Design of Modulo-N nple counier, Up- Down counter, design f
synctrukUS CUUnters witth and without lockut cunditios, design ol' shift registers with
-efl, shift-righ1 & purallel load facilities, Univenul shit Registen
SECTION.B
Data Caserterns
swen. DA converter weghied type. R-2R Ladder type, AD
Slope Type. StKKessive approximution type.
ype: Specfications of ADC& DAc.
Digital Loge
lanise fan in. fan-ot
ae matuin Transislor-trunslstur LogicTILA
wer dissipat delay,
TT, NAND Gate with active pull up.
its input and output Charncteristics, MOS and CMOS, Comparison o> huracteristics of
TIL. ECL. MOS & CMOS lugie circuits

niconductor Memorles &Prugrammable Lagie

ROM, PROM. EPROM, EEPROM; RAM: Static RAM.
Reading. & Writing Operatiot in RAM. PLA
MeIMory Organizatin.
PAL & FPGA

hrg sequentlal logle

Sequential circuits. Stale Reductio and Asignnent. Design Procedure

RECOMMENDED BOKORS

S. No NAME AUTHORIS) |PURLISHER

Digital Electronics Ar Willharm H Gothmann Prentice Hall of Enda
introduction to theury and

TbmDrital Eletruni RPJain Tata McGraw -Hill

Digital Integrated Herben Taub& Donald Tata McGraw-Hill
Electronics, Schilling
Integrated Electrmics. MillmandHalkias Tata McGtraw-Hill
Digital SyMem Principles & RJ Tocri Prentice Hall of Inda
Applicatiuns.
Digital Logic Dexign. Mortis Mano
Educatiot

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