Admission No.

: __________________

TEMASEK POLYTECHNIC

SCHOOL OF ENGINEERING

AY 2023/2024 SEMESTRAL EXAMINATION

(October Semester)

DIGITAL FUNDAMENTALS 1 (EEE1003)

SUBJECT LEVEL : 1

TIME ALLOWED : 2 HOURS

INSTRUCTIONS TO CANDIDATES EXAMINER’S

QUESTION
USE ONLY
1. This paper consists of 12 pages (excluding cover page). ANSWERED
MARKS
2. It is divided into 2 sections: A and B. A1 / 15

3. Section A contains 4 questions. A2 / 15

4. Section B contains 3 questions. A3 / 15

5. Answer ALL the questions in this paper. A4 / 15

6. Write your answers for all sections directly on this paper. If there is B1 / 14
insufficient space, write your answer at the blank back pages. Label
your answer clearly and cross out whatever answer that is not B2 / 12
required for marking.
B3 / 14
7. Write your admission number on the space provided at the top right
corner of ALL pages.
TOTAL / 100
8. Do not tear out or remove any page from this question paper. It is
your responsibility to ensure that all the pages of this paper are intact during submission.

9. DO NOT REMOVE THIS SET OF QUESTION PAPER FROM THE EXAM ROOM.

10. Write your seat number, course of study, tutorial group and admission number in the space provided below:

Seat No. Course of Study Tutorial Group Admission No.

Do not
Digital Fundamentals 1 (EEE1003) Page 0 write
on this
margin
 Admission No.: __________________
Section A: Answer all 4 questions in this section.

A1. a. Draw the logic circuit for W =A . B . C+ A . C . D+ A . B . C . D+ A . B . C .Do

not simplify W. [5 marks]

b. Complete Table A1 for W =A . B . C+ A . C . D+ A . B . C . D+ A . B . C . [6 marks]

A B C D W
0 0 0 1
1 0 0 1
0 1 1 0
1
0
1
0
1
1
0
1
6
1 0 1 1
Table A1

Digital Fundamentals 1 (EEE1003) Page 1

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Do not
c. Simplify W =A . B . C+ A . C . D+ A . B . C . D+ A . B . C using a Karnaugh map write
shown in Figure A1. Show all your loop(s) and the simplified SOP of W. on this
[4 marks] margin
CD
AB

Figure A1
4
Simplified SOP of W = _____________________________

15
Digital Fundamentals 1 (EEE1003) Page 2
 Admission No.: __________________

Do not
A2. a. Table A2 shows the truth table of a digital system. Complete the write
Karnaugh map for Q output in Figure A2. Show all the loop(s) clearly on this
and write down the most simplified SOP of Q. [8 marks] margin
Inputs Output
A B C D Q
0 0 0 0 0
0 0 0 1 1 CD
0 0 1 0 x AB
0 0 1 1 x Fi
0 1 0 0 1 g u
0 1 0 1 x r e
0 1 1 0 1
0 1 1 1 1
1 0 0 0 1 A2
1 0 0 1 0
1 0 1 0 1
1 0 1 1 0
1 1 0 0 0
1 1 0 1 0
1 1 1 0 x
1 1 1 1 0

Table A2
8
Simplified SOP of Q = ____________________________________________

b. A periodic waveform has a period of 2ms and a pulse width of 0.4ms.

Calculate the frequency and the duty cycle of this waveform. Show your
workings clearly. [2 marks]

Digital Fundamentals 1 (EEE1003) Page 3

 Admission No.: __________________

Do not
c. Simplify T = AB(B+ AC + AB)+ A C B using Boolean Algebra rules and De write
Morgan’s theorems. Show all workings clearly and the most simplified on this
expression of T. Your answer should require the least number of logic margin
gate(s) to implement. You do not need to draw the simplified logic
circuit.

[5 marks]

Digital Fundamentals 1 (EEE1003) Page 4

15
 Admission No.: __________________

Do not
A3. a. Express -11710 as an 8-bit signed binary number in 2’s complement write
system. Show all workings and the base clearly. [2 marks] on this
margin

b. Convert 6FA16 to binary. Show the base clearly. [2 marks]

c. Perform binary addition of 11112 and 10012. Leave your answer in binary
and show all workings and the base. [2 marks]

Digital Fundamentals 1 (EEE1003) Page 5

 Admission No.: __________________

Do not
d. Figure A3-1 shows the block diagram of a BCD error detector circuit at a write
remote receiver. If the 4-bit code, A 3A2A1A0, received is an invalid BCD on this
code, the BCD error output E will output a logic ‘1’. Design a logic circuit margin
to perform this task using only ONE IC 7400 which comprises of four 2-
input NAND gates. Complete Table A3 and the Karnaugh map shown in
Figure A3-2. Show all the loop(s) and label your circuit clearly. [9 marks]

A3 MSB BCD error

A2 BCD Error Output
detector circuit
A1 at receiver E
A0
Figure A3-1

A3
Inputs
A2 A1 A0
Output
E
9
A1A0
0 0 0 0
A3A2
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0 Figure A3-2
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1
Table A3

Draw your circuit:

Digital Fundamentals 1 (EEE1003) Page 6

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Do not
A4. a. Refer to the device shown in Figure A4-1 and its input waveforms shown write
in Figure A4-2. Draw the output Q1 waveform in Figure A4-2. [3 marks] on this
margin
S
S Q1 R

Q1 Figure A4-2
Figure A4-1
R Q1
3
b. Refer to the device shown in Figure A4-3
and its input waveforms shown in
Figure A4-4. Draw the output Q2 waveform in Figure A4-4. Assume Q2
is SET initially. [4 marks]

Clock
J Q2
Clock KCLK Q2
4
J

Figure A4-3
K

Q2
Figure A4-4

c. Refer to the device shown in Figure A4-5 and its input waveforms shown
in Figure A4-6. Assume Q3 is RESET initially. Draw the output Q3
waveform in Figure A4-6. [3 marks]

EN
D Q3
EN
D
3
Q3

Q3

Figure A4-5 Figure A4-6

Digital Fundamentals 1 (EEE1003) Page 7
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Do not
d. Refer to the multiplexer circuit shown in Figure A4-7 to complete Table
write
A4. [5 marks]
on this
margin

1
0
1
D
1
0

A B C

Figure A4-7

Inputs Logic state at

IC74151 Output Z
E D A B C Z
1 0 1 0 0
0 1 1 1 0
1 0 0 1 1 Table A4
0 1 0 1 1 5
0 1 1 1 1

15

Do not
Section B: Answer all 3 questions in this section. write
on this
margin
Digital Fundamentals 1 (EEE1003) Page 8
 Admission No.: __________________
B1. a. Refer to the Priority Encoder IC 74147 circuit shown in Figure B1-1 to
complete Table B1-1. [10 marks]

Figure B1-1

IC74147 Inputs Outputs

1 2 3 4 5 6 7 8 9 D C B A X 10
1 0 0 1 0 0 1 0 1

1 1 1 0

Table B1-1

b. Refer to the demultiplexer circuit shown in Figure B1-2 to complete Table

B1-2. [4 marks]

Demultiplexer O0
D S1 S0 O0 O1 O2 O3
O1
D Data Input 0 0 1 4
O2 1 1 0

O3 Table B1-2
S1 S0

Figure B1-2 14
cc
Do not
Digital Fundamentals 1 (EEE1003) Page 9write
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margin
 Admission No.: __________________
B2. Refer to the sequential circuit shown in Figure B2-1 and complete the Q0, Q1
and Q2 waveforms in Figure B2-2. [12 marks]

5V 5V
B PRE PRE PRE

A J Q0 S Q1 5V J Q2
Clock Clock Clock
CLK CLK CLK
5V 5V
K Q0 R Q1 K Q2

CLR CLR CLR

C

Figure B2-1

Clock

Q0

Q1

Q2

Figure B2-2

12

Do not
write
Digital Fundamentals 1 (EEE1003) Page 10on this
margin
 Admission No.: __________________
B3. You are tasked to design an anti-burglary system to create the illusion of an
occupied home. When the input mode M is LOW, one appliance is turned on
between 12:00 Midnight to 7:00 AM in the following order:
12:00 Midnight TV set
1:00 AM Lamp 1 in the living room
2:00 AM Lamp 2 in the dining room
3:00 AM Lamp 3 in bedroom 1
4:00 AM Lamp 4 in bedroom 2
5:00 AM Lamp 5 in kitchen
6:00 AM Lamp 6 in study room
7:00 AM Radio

All the appliances will be switched OFF when the input mode M is HIGH.
Each appliance requires a logic ‘0’ to be activated and it will remain ON only
for one hour. Note: CBA=000 represents 12:00 Midnight; CBA=001 represents
1:00 AM; CBA=010 represents 2:00 AM; etc.

a. Complete Table B3 to satisfy the above conditions when the input mode
M is set to LOW. [4 marks]
Lamp 1

Lamp 2

Lamp 3

Lamp 4

Lamp 5

Lamp 6
TV set

C B A Radio
0 0 0
0 0 1
0
0
1
1
0
1
4
1 0 0
1 0 1
1 1 0
1 1 1
Table B3

b. You are provided with two 2-to-4 decoders and two IC 7400. A 2–to-4
decoder is shown in Figure B3. Each IC 7400 comprises of four 2-input
NAND gates. Complete the circuit design in Figure B3 using the
components provided only. Label all the inputs (M, C, B and A) and
outputs (TV set, Lamp 1 to Lamp 6 and Radio) clearly in Figure B3.
[10 marks]

Digital Fundamentals 1 (EEE1003) Page 11

 Admission No.: __________________

2-to-4 decoder
LSB A0 Y0
A1 Y1
Y2
E Y3

10

14
Figure B3

END OF PAPER
Digital Fundamentals 1 (EEE1003) Page 12