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C-CS316 - Lect09 - Memory Management - Part 2

The document discusses memory management techniques in operating systems including contiguous memory allocation, paging, swapping, demand paging, copy-on-write, page replacement, and allocation of frames. It covers addressing translation schemes, paging hardware, examples of paging logical and physical memory, and calculating internal fragmentation.

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9 views

C-CS316 - Lect09 - Memory Management - Part 2

The document discusses memory management techniques in operating systems including contiguous memory allocation, paging, swapping, demand paging, copy-on-write, page replacement, and allocation of frames. It covers addressing translation schemes, paging hardware, examples of paging logical and physical memory, and calculating internal fragmentation.

Uploaded by

omarelgohary800
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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Introduction to

Operating Systems
C-CS316 Spring 2024

LECTURE 09:
Memory Management
Dr. Basma Hassan Dr. Ahmed Salama
[email protected] [email protected]

Faculty of Computing and Information Sciences


1
Chapters 9,10: Memory Management
Contiguous Memory Allocation
Paging
Swapping
Demand Paging
Copy-on-Write
Page Replacement
Allocation of Frames
Thrashing
Memory-Mapped Files
Allocating Kernel Memory
Overview of Mass Storage Structure
HDD Scheduling
NVM Scheduling
Error Detection and Correction
Storage Device Management
Swap-Space Management
Storage Attachment
RAID Structure

Faculty of Computing and Information Sciences


2
Paging

• Physical address space of a process can be noncontiguous; process is allocated physical


memory whenever the latter is available
• Avoids external fragmentation
• Avoids problem of varying sized memory chunks
• Divide physical memory into fixed-sized blocks called frames
• Size is power of 2, between 512 bytes and 16 Mbytes
• Divide logical memory into blocks of same size called pages
• Keep track of all free frames
• To run a program of size N pages, need to find N free frames and load program
• Set up a page table to translate logical to physical addresses
• Still have Internal fragmentation

Faculty of Computing and Information Sciences


Address Translation Scheme
• Address generated by CPU is divided into:
• Page number (p) – used as an index into a page table which contains base
address of each page in physical memory
• Page offset (d) – combined with base address to define the physical memory
address that is sent to the memory unit

page number page offset


p d
m -n n

• For given logical address space 2m and page size 2n

Faculty of Computing and Information Sciences


Paging Hardware

Faculty of Computing and Information Sciences


Paging Model of Logical and Physical Memory

Faculty of Computing and Information Sciences


Paging Example
• Logical address: n = 2 and m = 4.
For given logical address space 2m and page size 2n

Using a page size of 4 bytes and a physical memory of


32 bytes (8 frames)

a Logical Address Physical Address


0 20

How ??

Faculty of Computing and Information Sciences


Paging Example
• Logical address: n = 2 and m = 4.
Using a page size of 4 bytes and a physical memory of 32 bytes (8 frames)
Page Number =Logical address / Page size Page offset =Logical address% Page size

P=0 D= 0

F=5 D=0

P=3 D= 1

F=2 D=1

Faculty of Computing and Information Sciences


Paging -- Calculating internal fragmentation

• Page size = 2,048 bytes


• Process size = 72,766 bytes
• 35 pages + 1,086 bytes
• Internal fragmentation of 2,048 - 1,086 = 962 bytes
• Worst case fragmentation = 1 frame – 1 byte
• On average fragmentation = 1 / 2 frame size
• So small frame sizes desirable?
• But each page table entry takes memory to track

Faculty of Computing and Information Sciences


Memory Protection
• Memory protection implemented by associating protection bit with
each frame to indicate if read-only or read-write access is allowed
• Can also add more bits to indicate page execute-only

• Valid-invalid bit attached to each entry in the page table:

• “valid” indicates that the associated page is in the process’


logical address space, and is thus a legal page

• “invalid” indicates that the page is not in the process’ logical


address space

Faculty of Computing and Information Sciences


Shared Pages
• Shared code
• One copy of read-only (reentrant) code shared among processes (i.e., text editors,
compilers, window systems)
• Similar to multiple threads sharing the same process space
• Also useful for interprocess communication if sharing of read-write pages is allowed

• Private code and data


• Each process keeps a separate copy of the code and data
• The pages for the private code and data can appear anywhere in the logical address space

Faculty of Computing and Information Sciences


Shared Pages Example

Faculty of Computing and Information Sciences


Structure of the Page Table

• Memory structures for paging can get huge using straight-forward methods

• One simple solution is to divide the page table into smaller units

• Hierarchical Paging

• Hashed Page Tables

• Inverted Page Tables

Faculty of Computing and Information Sciences


Hierarchical Page Tables
• Break up the logical address space into multiple page tables
• A simple technique is a two-level page table
• We then page the page table

Faculty of Computing and Information Sciences


Two-Level Paging Example
• A logical address (on 32-bit machine with 4K page size (212)) is divided into:
• a page number consisting of 20 bits 2 32 / 2 12 = 2 20
• a page offset consisting of 12 bits

• Since the page table is paged, the page number is further divided into:
• a 10-bit page number
• a 10-bit page offset

• Thus, a logical address is as follows:

where p1 is an index into the outer page table, and p2 is the displacement within the
page of the inner page table
• Known as forward-mapped page table

Faculty of Computing and Information Sciences


Hashed Page Tables
• Common in address spaces > 32 bits

• The virtual page number is hashed into a page table


• This page table contains a chain of elements hashing to the same location

• Each element contains (1) the virtual page number (2) the value of the mapped page frame
(3) a pointer to the next element

• Virtual page numbers are compared in this chain searching for a match
• If a match is found, the corresponding physical frame is extracted

• Variation for 64-bit addresses is clustered page tables


• Especially useful for sparse address spaces (where memory references are non-
contiguous and scattered)

Faculty of Computing and Information Sciences


Hashed Page Table

Faculty of Computing and Information Sciences


Inverted Page Table

• Rather than each process having a page table and keeping track of all possible logical pages,
track all physical pages

• Entry consists of the virtual address of the page stored in that real memory location, with
information about the process that owns that page

• Decreases memory needed to store each page table, but increases time needed to search the
table when a page reference occurs

Faculty of Computing and Information Sciences


Swapping
• A process can be swapped temporarily out of memory to a backing store, and then
brought back into memory for continued execution
• Total physical memory space of processes can exceed physical memory

• Backing store – fast disk large enough to accommodate copies of all memory images
for all users; must provide direct access to these memory images

• Roll out, roll in – swapping variant used for priority-based scheduling algorithms;
lower-priority process is swapped out so higher-priority process can be loaded and
executed
• Major part of swap time is transfer time; total transfer time is directly proportional to
the amount of memory swapped
• System maintains a ready queue of ready-to-run processes which have memory
images on disk
Faculty of Computing and Information Sciences
Schematic View of Swapping

Faculty of Computing and Information Sciences


End of Lecture!
Thanks for your Attention!

Faculty of Computing and Information Sciences


21

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