Application Note

Op-Amp/Comparator Application Note

Operational amplifier ,Comparator (Tutorial)

This application note explains the general terms and basic techniques that are necessary for configuring application circuits with
op-amps and comparators. Refer to this note for guidance when using op-amps and comparators. a

Contents
1 What Is Op-Amp/Comparator?.......................................................................................................................................................................... 2
1.1 What is op-amp? ......................................................................................................................................................................................... 2
1.2 What is comparator? .................................................................................................................................................................................. 3
1.3 Internal circuit configuration of op-amp/comparator ............................................................................................................................ 4
2 Absolute Maximum Rating ................................................................................................................................................................................ 5
2.1 Power supply voltage/operating range of power supply voltage ....................................................................................................... 5
2.2 Differential input voltage ............................................................................................................................................................................ 6
2.3 Input common-mode voltage .................................................................................................................................................................... 7
2.4 Input current ................................................................................................................................................................................................. 8
2.5 Operating temperature range.................................................................................................................................................................... 8
2.6 Maximum junction temperature, storage temperature range.............................................................................................................. 8
2.7 Power dissipation (total dissipation)........................................................................................................................................................ 9
3 Electrical Characteristics.................................................................................................................................................................................. 10
3.1 Supply current ........................................................................................................................................................................................... 10
3.2 Input offset voltage ................................................................................................................................................................................... 12
3.3 Input bias current and input offset current ........................................................................................................................................... 16
3.4 Input common-mode voltage range....................................................................................................................................................... 18
3.5 Maximum output voltage (High/Low level output voltage ................................................................................................................. 20
3.6 Large signal voltage gain (open loop gain) .......................................................................................................................................... 22
3.7 CMRR (Common Mode Rejection Ratio)............................................................................................................................................... 23
3.8 PSRR (Power Supply Rejection Ratio) .................................................................................................................................................. 27
3.9 SR (Slew Rate) ........................................................................................................................................................................................... 30
3.10 Frequency characteristics of op-amp.................................................................................................................................................... 31
3.11 Phase delay and oscillation..................................................................................................................................................................... 33
3.12 Cause of phase delay in op-amp ............................................................................................................................................................ 35
3.13 Stability confirmation method (amplifier circuit).................................................................................................................................. 36
3.14 Stability confirmation method (unity feedback circuit/voltage follower) ......................................................................................... 37
3.15 Summary of stability confirmation method .......................................................................................................................................... 38
3.16 Countermeasures against oscillation by load capacitance (output isolation resistor 1) ............................................................. 38
3.17 Countermeasures against oscillation by load capacitance (output isolation resistor 2) ............................................................. 39
3.18 THD+N (Total Harmonic Distortion + Noise) ......................................................................................................................................... 40
3.19 Input referred noise................................................................................................................................................................................... 44
3.20 Response time (rise/fall times and propagation delay time).............................................................................................................. 48
4 Reliability Items .................................................................................................................................................................................................. 50
4.1 Electrostatic Breakdown Voltage (ESD Breakdown Voltage) ............................................................................................................ 50
4.2 Latch Up Test ............................................................................................................................................................................................. 51

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1 What is Op-Amp/Comparator?
1.1 What is op-amp?

An op-amp (operational amplifier) is a differential amplifier As shown in Figure 1.1.2 and the equation (1.1.1), the signal
that has high input resistance, low output resistance, and high voltage VS is divided into resistance voltages by the signal
open loop gain. Its function is to amplify the differential source resistor RS and the input resistor Ri of the op-amp. As
voltage between the + input terminal (non-inverting terminal) a result, the input signal to the op-amp is attenuated.
and the - input terminal (inverting terminal). However, when the Ri is sufficiently larger than the RS (Ri =
∞), the first term in the equation (1.1.1) can be approximated
Each op-amp circuit is composed of five terminals: a power
by 1 and it can be considered that VS = Vi. Next, as for the
supply terminal on the positive side, a power supply terminal
second term, the amplified input voltage AVVi is divided by the
on the negative side, a + input terminal, a - input terminal, and
output resistor RO of the op-amp and the load resistor RL and
an output terminal. (There are no general terms for the
output in Figure 1.1.2.
terminals except classifications such as power source, input
Here, the signal can be output without being attenuated if the
and output.)
RO is sufficiently smaller than the RL (RO=0) because the
second term can be approximated by 1. Such an op-amp is
Power supply terminal on the
+ input terminal called an ideal op-amp. Usually, op-amps with high input
positive side (VCC)
(+IN) resistance and low output resistance are preferred. The
Output (OUT) circuit configuration is designed to achieve an ideal op-amp
as closely as possible.
- input terminal Power supply terminal on

(-IN) the negative side (VEE) RS Vi RO VO

Figure 1.1.1. Op-amp/comparator symbol

Table 1.1.1. Examples of names for op-amp VS Ri AV Vi RL

power supply terminals

Bipolar type CMOS type

Power supply
terminal on the VCC VDD Figure 1.1.2. Model of voltage controlled voltage source
positive side
amplifier
Power supply
terminal on the VEE VSS
negative side
Table 1.1.2. Ideal input and output resistances required
for op-amp
Providing high input resistance (impedance) and low output
Input Output
resistance is a function required for the op-amps.
resistance resistance
In Figure 1.1.2. Model of voltage controlled voltage source Ideal op-amp
amplifier (op-amp), VS is the input signal source, RS is the (Voltage controlled ∞ 0
voltage source)
signal source output resistor, Ri is the input resistor of the
op-amp, RO is the output resistor of the op-amp, RL is the load
resistor, and AV is the amplification factor of the op-amp. The
relation between the input and output voltages is described in
the equation (1.1.1).

Ri RL
VO  VS  AV
Ri  RS RO  RL (1.1.1)

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An op-amp amplifies a small differential voltage between the grounding. When configuring and using a negative feedback
+ input terminal and - input terminal and outputs the amplified circuit, this relation is realized and application circuits are
voltage. For this purpose, an op-amp with a large designed utilizing the characteristic of the virtual grounding.
amplification factor is preferred. The reason is explained
using the voltage follower circuit in Figure 1.1.3.
1.2 What is comparator?
A voltage follower circuit is a circuit in which the input and
output voltages are equal. It is mainly used as a voltage A comparator (voltage comparator) has the same terminal
buffer. structure as an op-amp composed of five terminals: the +
This circuit provides characteristics such as high input input terminal, the - input terminal, the positive side power
resistance and low output resistance, as mentioned above. supply terminal, the negative side power supply terminal, and
In Figure 1.1.3, the input voltage VS and the VOUT become the output terminal. When a comparator is used, the voltage

identical. is fixed at one of the input terminals as a reference terminal,

and the difference between the reference voltage and the
VIN+
output voltage to the other terminal is amplified. The output
VOUT
AV voltage is either higher or lower than the reference voltage.

VS When the + input terminal potential > the - input terminal

VIN- potential
→ High level output.
When the - input terminal potential > the + input terminal
Figure 1.1.3. Voltage follower circuit
potential
→ Low level output.
Since the op-amp amplifies the differential voltage between
The major difference between op-amps and comparators is
the terminals by the amplification factor of the op-amp, the
whether or not the phase compensation capacitance exists.
output voltage is expressed with the equation (1.1.2).
Since op-amps configure and utilize a negative feedback
circuit, they require phase compensation capacitance to
VOUT  AV  (VIN   VIN  )  AV  (VS  VOUT ) (1.1.2)
prevent oscillation inside the IC. On the other hand, since
comparators will not configure the negative feedback circuit,
The equation (1.1.2) is converted to the equation (1.1.3).
they do not include the phase compensation capacitance.
VOUT Since the phase compensation capacitance limits the
 VS  VOUT (1.1.3)
AV response time between the input and the output, a
comparator without the phase compensation capacitance
In the equation (1.1.3), when the open loop gain of the
provides a better responsiveness compared to an op-amp.
op-amp is sufficiently high, the left side can be approximated
In contrast, if an op-amp is used as a comparator, since the
by 0 and the equation gives VS = VOUT. When the gain is low,
phase compensation capacitance limits the response, it
the left side of the equation (1.1.3) cannot be approximated
provides a very poor responsiveness compared with a
by 0 and the output voltage will contain an error.
comparator.
An op-amp with a high open loop gain is desirable because
Therefore, care must be taken when using an op-amp as a
the error in the output voltage can be minimized by the high
comparator.
gain.
From another point of view, the high open loop gain means
that the difference in the potentials between the + input
terminal and the - input terminal is minimized. Namely, the
higher the open loop gain is, the better the relation VIN+ = VIN-
holds. This relation in which the potentials of the + input
terminal and the - input terminal become nearly equal is
called a virtual short-circuit, imaginary short-circuit, or virtual

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1.3 Internal circuit configuration of

op-amp/comparator

Figure 1.3.1 shows the internal circuit configuration of an The difference in the amount of drive current affects the
op-amp. Generally, an op-amp is composed of three stages: distortion factor generated in the output stage. In general, the
the input stage, the gain stage, and the output stage. Class A output circuit has the lowest distortion factor, followed
The input stage is configured with a differential amplification by Classes AB, B, and C.
stage that amplifies the differential voltage between the two Figure 1.3.2 shows the internal circuit configuration of a
terminals. In addition, it does not amplify the common-mode comparator. Although the circuit configuration is nearly
signal component (a condition where no difference in identical to that of an op-amp, the phase compensation
potential exists between the terminals and an equal voltage is capacitance for oscillation prevention is not included in the
input). comparator since it is not supposed to be used in a negative
Since the gain is insufficient with the differential amplification feedback configuration. Since the phase compensation
circuit alone, the gain stage further increases the open loop capacitance limits the operating speed between the input and
gain in the op-amp. the output, the response time is remarkably better compared
In general op-amps, the phase compensation capacitance for with op-amps.
oscillation prevention is connected over the gain stage. The type of output circuit for comparators is classified into the
The output stage is connected as a buffer so that the op-amp open collector (open drain) type or the push-pull type.
characteristics will not be affected by loads such as the Figure 1.3.2 (b) shows the internal equivalent circuit of the
resistance connected to the output terminal. The changes in BA2903. The BA2903 is an output circuit of the open collector
the output characteristics due to the loads (such as distortion type.
or voltage drop) mainly depend on the circuit configuration
and the current capability of the output stage. The type of
output stage, Class A and B, C, or AB push-pull output circuit,
is classified according to the amount of drive current flowing
in the output circuit (the difference in the bias voltage).
+ input terminal
+入力端子 +入力端子
+ input terminal
(+IN) Phase compensation capacitance (+IN)
(+IN) 位相補償容量 (+IN)

Output terminal Output terminal

出力端子 出力端子
(OUT)
(OUT)
Input Gain Output (OUT) Input Gain Output (OUT)
入力段
stage 利得段
stage 出力段
stage 入力段
stage 利得段
stage 出力段
stage

- input terminal - input terminal

-入力端子 -入力端子
(-IN)
(-IN)
(-IN) (-IN)
(a) Internal circuit configuration of general op-amp (a) Internal circuit configuration of general comparator
VCC VCC

Phase compensation
-IN
capacitance
位相補償容量
OUT +IN OUT

+IN -IN

VEE VEE

Output
Input
入力段 stage Gain
利得段 stage 出力段 Input
入力段 stage Gain
利得段 stage Output
出力段
stage stage

(b) BA4558 Internal equivalent (b) BA2903 Internal equivalent

Figure 1.3.1. Internal circuit configuration of op-amp Figure 1.3.2. Internal circuit configuration of comparator
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2 Absolute Maximum Rating

The absolute maximum rating is specified in the data sheet with the value of (VCC-VEE) never exceeding the absolute
for op-amps/comparators. The absolute maximum rating maximum rating for the power supply voltage. Therefore,
provides the condition that must not be exceeded even when 24 V and -12 V are applied to the VCC and VEE
instantaneously. The application of a voltage above the terminals, respectively, the difference in voltage between the
absolute maximum rating or use in a temperature terminals is 36 V and the deterioration of characteristics or
environment outside the environment specified by the destruction does not occur. It should be noted that the
absolute maximum rating may cause the deterioration of absolute maximum rating for the power supply voltage has a
characteristics or destruction of the internal circuit. The different meaning from the operating power supply voltage.
absolute maximum ratings for the following items are The absolute maximum rating for the power supply voltage
explained. indicates the maximum value of the power supply voltage that
2.1. Power supply voltage/operating range of power supply will not cause the characteristics deterioration or destruction
voltage of the IC. It does not provide the voltage range in which the
2.2. Differential input voltage specifications and characteristics that are described in the
2.3. Input common-mode voltage data sheet are maintained. To obtain the characteristics that
2.4. Input current are guaranteed in the specifications, the op-amp/comparator
2.5. Operating temperature range must be used with the voltage value within the operating
2.6. Maximum junction temperature, storage temperature range of the power supply voltage. However, the absolute
range maximum rating for the power supply voltage of some
2.7. Power dissipation (total dissipation) products may be identical to the maximum value of the
operating power supply voltage. Op-amps are sometimes
2.1 Power supply voltage/operating range of
called dual power supply or single power supply op-amps. In
power supply voltage
other words, an op-amp may be suited for the usage as a
For the power supply voltage, the absolute maximum rating dual power supply or single power supply. Dual power supply
refers to the maximum power supply voltage that can be op-amps have a voltage range in which either the input
applied between the positive side power supply terminal voltage or the output voltage cannot be output due to the
(VCC terminal) and the negative side power supply terminal circuit configuration on the positive power supply (VCC) side
(VEE terminal) of the op-amp without causing the and the negative power supply (VEE) side. Therefore, the
deterioration of characteristics or destruction of the internal dual power supply op-amps are often used while applying a
circuit. Figure 2.1.1 shows examples of the power supply positive power supply and a negative power supply with the
voltage that can be applied to an op-amp/comparator that has ground being the middle point. On the other hand, the single
an absolute maximum rating for the power supply voltage of power supply op-amps are used while applying the positive
36 V. The absolute maximum rating for the power supply power supply with reference to the ground and the
voltage specifies the difference in voltage between the VCC input/output can be performed nearly at the ground level.
and VEE terminals. The op-amp/comparator must be used

VCC=18V VCC=36V VCC=24V

VOUT VOUT VOUT

VEE=-18V VEE=GND VEE=-12V

VCC-VEE=18V-(18V)=36V VCC-VEE=36V-(0V)=36V VCC-VEE=24V-(-12V)=36V

Dual power supply, ±18 V applied Single power supply, 36 V applied Dual power supply, 24 V and -12 V applied

Figure 2.1.1. Examples of the power supply voltage that can be applied to an IC that has an
absolute maximum rating for the power supply voltage of 36 V
Note: Dual power supply refers to the application of a power supply voltage to op-amps using two voltage power supplies (positive and negative).
Single power supply refers to the application of a power supply voltage to op-amps with reference to the ground.

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2.2 Differential input voltage

Differential input voltage indicates the maximum value of the (ground) as in Figure 2.2.1(a), or the elements are connected
voltage that can be applied between the + input terminal between the input terminals and both the VCC and VEE
(non-inverting input terminal) and the - input terminal (ground) as in Figure 2.2.1(b).
(inverting input terminal) without causing the characteristic In the former, since there is no current path on the VCC side,
deterioration or destruction of the IC. This voltage is the the differential voltage does not depend on the VCC value
difference in voltage between the + input terminal and the - and is determined by factors such as the breakdown voltage
input terminal, and either of the terminals can be used as the of the transistors (e.g., NPN and PNP transistors) that are
reference. The polarity is not very important. connected to the input terminals. In the latter, since a
However, the potential of each input terminal is required to be protection element is located on the VCC side as well and the
higher than that of the VEE terminal. The reason for this potential of the input terminals must be lower than that of the
requirement is that the current may flow out of the input VCC, the differential input voltage is determined by VCC -
terminal via the electrostatic protection element when the VEE or VDD - VEE. Some op-amps use an NPN differential
potential of the input terminal is lower than that of the VEE input stage and the clamp diodes for the protection between
terminal, leading to deterioration or destruction. the base and emitter of these transistors are connected
Two types of protection element are available: the elements between the input terminals. The differential voltage in such
are connected between the input terminals and the VEE products may be specified to several volts (Figure 2.2.2).

VCC Protection element

VCC
against electrostatic
breakdown静電破壊保護素子
+入力端子
+ input terminal + input+入力端子
terminal
(+IN)
(+IN) (+IN) (+IN)

Output terminal Output terminal

出力端子 出力端子
Specific differential
差動入力電圧 Differential input voltage is (OUT)
Input Gain Output (OUT)
(OUT) 差動入力電圧 Input Gain Output (OUT)
input+36V、+7V
voltage such as 入力段 利得段 出力段 VCC - VEE or VCC-VEE
VDD – VSS. 入力段 利得段
stage
出力段
stage stage stage stage stage
+36 V or +7 V is
など具体的な数値が もしくは
indicated.
記載されている
VDD-VSS

- input terminal
-入力端子
- input-入力端子
terminal
(-IN)(-IN) (-IN) (-IN)
Protection element Protection element
against electrostatic
静電破壊保護素子
against electrostatic
静電破壊保護素子
breakdown breakdown
VEE VEE

(a) When the electrostatic protection element is located only on (b) When the electrostatic protection elements are located on both

the VEE (ground) side the VCC and VEE (ground)

(potential of input terminal must be higher than that of VEE) (potential of input terminal must be higher than that of VEE and
lower than that of VCC)
Figure 2.2.1. Differential input voltage

VCC
Protection element against
静電破壊保護素子
electrostatic breakdown
+入力端子
+ input
(+IN)terminal
(+IN)

Differential input Output

出力端子 terminal
voltage is差動入力電圧
the forward Input Gain Output (OUT)
(OUT)
入力段 利得段 出力段
voltage of端子間保護素子
the stage stage stage
protectiveの順方向電圧
element
between the terminals.

- input terminal
-入力端子
(-IN)
(-IN)

Protection element against

静電破壊保護素子
electrostatic breakdown
VEE

When the diodes for the overvoltage protection are connected between the + input terminal and the - input terminal
Figure 2.2.2. Differential input voltage (with the protection between the terminals)

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2.3 Input common-mode voltage

For the input common-mode voltage, the absolute maximum In summary, the input common-mode voltage is determined
rating indicates the maximum voltage that can be applied by the protection circuit configuration and the parasitic
without causing the characteristic deterioration or destruction element of the input terminals as well as the breakdown
of the IC when the potentials of the + input terminal and - voltage of the input transistors among other factors. Figure
input terminal are set to the same value. Unlike the input 2.3.1 shows the absolute maximum rating for the input
common-mode voltage range in the electrical characteristics common-mode voltage.
specifications, the absolute maximum rating for the input In addition, the value of 0.3 V indicated in “VEE-0.3V” or
common-mode voltage does not guarantee the normal “VCC+0.3V” represents the voltage range in which the
operation of the IC. electrostatic protection elements (diodes) are not activated
If normal operation of the IC is expected, the voltage must when the forward voltage is applied to the protective element.
follow the input common-mode voltage range in the electrical For the protection method when a voltage outside the input
characteristics items. Generally, the absolute maximum rating voltage range is applied, refer to the next section, 2.4 Input
for the input common-mode voltage is -0.3 V and +0.3 V for current.
the VEE and VCC, respectively. However, as mentioned in
section 2.2 Differential input voltage, the voltage can be
applied up to the absolute maximum rating for the power
supply voltage (e.g., +36 V for the VEE) in some products in
which the protection element is not present on the VCC side.

VCC VCC

VOUT VOUT

VCM VCM

VEE=GND VEE=GND

The absolute
Depends on the power supply voltage being used
maximum rating 使用している電源電圧に依存
絶対最大定格
for the power VCC+0.3V
の電源電圧VCC
supply voltage
例：36V, 7V VCC
VCC
e.g., 36 V, 7 V
The input The input
The absolute maximum
絶対最大定格の common-mode The absolute maximum
絶対最大定格の common-mode
rating
同相入力範囲of the input 電気的特性の
range in the rating
同相入力範囲of the input 電気的特性の
range in the
＝動作しない領域も含む
common-mode range 同相入力範囲
electrical ＝動作しない領域も含む
common-mode range 同相入力範囲
electrical
= includes non-operable ＝正常に動作 = includes non-operable ＝正常に動作
characteristics characteristics
area = normal operation area = normal operation

VEE=GND VEE=GND
VEE-0.3V VEE-0.3V

When the electrostatic protection element is located only on the VEE When the electrostatic protection elements are located on both the

(ground) side (VEE of -0.3 V to the absolute maximum rating for the VCC and VEE (ground) (VEE of -0.3 V to the working power supply

power supply voltage) voltage of +0.3 V)

Figure 2.3.1. Absolute maximum rating for the input common-mode voltage

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2.4 Input current 2.5 Operating temperature range

In sections 2.2 Differential input voltage and 2.3 Input Operation temperature range refers to the range in which the
common-mode voltage, it is explained that the current may IC maintains the expected functions and operates normally.
flow into or out of the input terminals if a voltage is input at a The IC characteristics vary with temperature. Therefore, the
value lower than the VEE of -0.3 V or higher than the VCC standard values specified for 25°C are not necessarily
+0.3 V, leading to the characteristics deterioration or guaranteed at other temperatures unless specified otherwise.
destruction. There are some specification items that are guaranteed for all
As countermeasures, a small forward voltage diode for temperatures within the operating temperature range. The
clamping can be provided on the input terminal, or the current values for such items are standard ones that take into
flowing through the input terminal can be limited by inserting a consideration the variation in IC characteristics within the
resistor. The former is a method to limit the voltage that is operating temperature range indicated in the specifications.
input to the IC, while the latter is a method to limit the current. The data sheet lists the temperature characteristics data for
Set the resistor value so that the input current is 10 mA or less. the specification items. Refer to the data for using the IC.
Set the forward voltage of the diode (VF in Figure 2.4.1) to
approximately 0.6 V.
2.6 Maximum junction temperature, storage
ESD protection temperature range
element
ESD保護素子 VCC
Maximum junction temperature is the maximum temperature
Current limiting resistor at which the semiconductor can operate. The junction refers
電流制限抵抗
VOUT to the part where the chip and the package join. If the chip
R
temperature exceeds the maximum junction temperature
Vin specified in the data sheet, a large number of electron-hole
pairs will be generated in the semiconductor crystal,
VEE=GND preventing the normal operation of the element. Therefore,
ESD protection
ESD保護素子
element the usage and thermal design should take into consideration
the heat generation due to the power consumption by the IC
VCC
and the ambient temperature. The maximum junction
VF VEE temperature is determined by the manufacturing process.
VF
The storage temperature range indicates the maximum
R temperature of the storage environment when the IC is not
R
Vin operating, i.e., without consumption power. Usually, this value
Vin is the same as the maximum junction temperature.

Figure 2.4.1. Connection of input current limiting resistor

ESD protection
IC内部 inside
element
ESD保護素子
the IC VCC
VCC
External diode for
外付けクランプ用
clamping
ダイオード

VOUT

Vin

ESD protection
IC内部
element
IC内部 inside
VEE=GND
ESD保護素子 VEE=GND
theESD保護素子
IC

Figure 2.4.2. Connection of input protection diode

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2.7 Power dissipation (total dissipation)

Power dissipation (total dissipation) or PD indicated in the Figure 2.5.2 shows examples of the thermal reduction curve
data sheet refers to the power that the IC can consume at the (derating curve). This curve shows how much power the IC
ambient temperature Ta = 25°C (ordinary temperature). The can consume at the ambient temperature. It indicates the
power consumption by the IC causes self-heating, increasing power that can be consumed without exceeding the
the chip temperature so it is higher than the ambient temperature that the IC chip can tolerate.
temperature. The temperature that the chip can tolerate is As an example, the chip temperature of the MSOP8 is
determined by the maximum junction temperature. Therefore, considered. Since the storage temperature range for this IC is
the consumable power is limited by the thermal reduction -55 [°C] to 150 [°C], the maximum allowable temperature is
curve (derating curve). The power dissipation at 25°C is 150 [°C]. The thermal resistance of the MSOP8 is θj-a ≈ 212.8
determined by the temperature that the IC chip inside the [°C/W]. Therefore, the junction temperature when this IC
package can tolerate (maximum junction temperature) and consumes the power of 0.58 [W] at Ta = 25 [°C] is calculated
the thermal resistance (heat radiation property) of the as follows.
package. In addition, the maximum value of the junction Tj = 25 [°C] + 212.8 [°C/W] × 0.58 [W] ≈ 150 [°C] (2.5.2)
temperature is determined by the manufacturing process. The result shows that the junction temperature will reach the
The heat generated by the IC power consumption is radiated maximum allowable temperature of the chip, suggesting the
through the mold resin or lead frame of the package. possibility of deterioration or destruction if the power
The parameter to describe this heat radiation property consumption is further increased.
(difficulty for the heat to escape) is called thermal resistance For the thermal reduction curve, the amount of reduction per
and is represented by the symbol θj-a [°C/W].The IC 1 [°C] is determined by the reciprocal of the thermal
temperature (Junction temperature :Tj) inside the package resistance. In the figure, the reduction rate is as follows:
can be estimated from the thermal resistance. Figure 2.5.1 5.5 [mW/°C] for the SOP8
shows the model for the thermal resistance of the package. 5.0 [mW/°C] for the SSOP-B8
θj-a is represented as the sum of the thermal resistance θj-c 4.7 [mW/°C] for the MSOP8
between the chip and the case (package) and the thermal Note: For calculation of the consumption power of op-amps,
resistance c-a between the case (package) and the outside. refer to the next section for the circuit current.
When the thermal resistance θj-a [°C/W], the ambient
0.8
temperature Ta [°C], and the consumption power P [W] are SOP8 ： 0.68 [W] SOP8
known, the junction temperature can be calculated with the 0.7 SSOP-B8 ： 0.62 [W] SSOP-B8
MSOP8
following equation. Consumable
25℃で消費可能な電力power at 25°C

(2.5.1) 0.6
Tj = Ta + θj–a × P
Reduction at the rate of
1/θja[mW/℃]で減少する
0.5 1/θj-a [W/°C]
dissipation [W]

Thermal resistance between the junction and the outside:

Power許容損失[W]

θj–a = θj–c + θc–a [ºC/W]

0.4 MSOP8 ： 0.58 [W]
Consumable power at 125°C
125℃で消費可能な電力
θj-c: Thermal resistance between the junction and the case [°C/W]

θc-a: Thermal resistance between the case and the outside [°C/W] 0.3

Ta: Ambient temperature [°C]

0.2
Tj: Junction temperature [°C]

The slope of the derating curve is the reciprocal of θj-a 0.1

Ta
0
ICICチップ
chip θc-a Tj
0 25 50 75 100 125 150
θj-c Ambient temperature Ta [°C]
周囲温度Ta[℃]
Figure 2.5.2. Examples of the thermal reduction curve
θj-c (When a 70 mm × 70 mm × 1.6 mm one-layer FR4 glass
θc-a epoxy substrate is mounted)
Lead frame
リードフレーム Ta

Figure 2.5.1. Thermal resistance of the package

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3 Electrical Characteristics
This technical note explains the electrical characteristics of Calculation of the power consumption of op-amps
op-amps and comparators as well as the precautions during When calculating the power consumption of an op-amp, it is
actual use. necessary to consider the output current as well as the supply
current.
3.1 Supply current
We explain the calculation of the power consumption step by
The supply current of an op-amp/comparator represents a step. There are two types of power consumption by op-amps:
current flowing through the IC alone in the no-load and steady the power consumption caused by the supply current or the
state as shown in Figure 3.1.1. Normally, the current flowing output current. First, we show the calculation of the power
from the VCC terminal to the VEE terminal is monitored. The consumption caused by the supply current. When PAMP is the
supply current is commonly called a no-signal supply current power consumed by an op-amp, Equation (3.1.1) becomes
or quiescent current as well. The input range and the the supply current × supply voltage based on P = current ×
operating voltage range vary with the products, resulting in voltage.
different measurement conditions. Normally, the This power consumption is always consumed as long as the
measurement is performed by applying a voltage in the center supply voltage is applied on the op-amp.
of the input common-mode voltage range or in the middle
between the supply voltages, VCC and VEE. In addition, the PAMP  I CC  (VCC  VEE ) (3.1.1)
supply current of a comparator takes a different value either
under the High or Low condition that is determined by the
circuit structure. The value is specified under the condition
that gives the higher supply current.

A
ICC
ＩCC
VCC

VCC
+
ICC Output: unconnected
Internal
出力：未接続
VOUT Output
内部回路 出力段
circuit stage
Input同相入力範囲/2
common mode
VCC/2
range/2 or VCC/2
もしくはVCC/2
-
VEE=GND

(a) Measurement circuit for the supply current of VEE=GND

op-amps Figure 3.1.2. Power consumption caused by

supply current

VCC
ICC
VOUT
Vin+

Vin-
VEE=GND

(b) Measurement circuit for the supply current of

comparators

Figure 3.1.1. Supply current of op-amp/comparator

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Next, we show the calculation of the power consumption The output source current flows when the output voltage (Vo)
caused by the output current. is higher than VCC/2, with which the load resistance (RL) is
The power is calculated for the case when an output sink connected. The calculation of the power caused by this
current flows, as shown in Figure 3.1.3 (a). source current is described by Equation (3.1.4). The power
The output sink current flows when Vo is lower than VCC/2, consumption is determined by the product of the current that
with which the load resistance (RL) is connected. The power flows from the inside of the IC and the difference in potentials
consumption caused by this sink current is described by between the VCC and OUT terminals.
Equation (3.1.2). The power consumption is determined by
the product of the current that flows into the inside of the IC PSOURCE  I SOURCE  (VCC  VO ) (3.1.4)
and the difference in potentials between the OUT and VEE
terminals. The total power consumption of the op-amp when the source
current exists is represented as Equation (3.1.5).
PSINK  I SINK  (VO  VEE ) (3.1.2)
P  PAMP  PSOURCE  I CC  (VCC  VEE )
(3.1.5)
The total power consumption of the op-amp when the sink
 I SOURCE  (VCC  VO )
current exists is represented as Equation (3.1.3).
When estimating the power consumption, the larger value of
the sink or source current is used.
P  PAMP  PSINK  I CC  (VCC  VEE )
(3.1.3)
 I SINK  (VO  V EE )

Next, the power is calculated for the case when an output

source current flows, as shown in Figure 3.1.3 (b).

A A
ＩCC ＩCC+ISOURCE
VCC VCC

+ + ISOURCE
ISINK
Internal Vo Internal Vo
Output Output
内部回路
circuit 出力段
stage
A 内部回路
circuit
出力段
stage
A
Vin Vin

- -
RRL RRL

ＩCC+ISINK ＩCC
VCC/2 VCC/2

VEE=GND
VEE=GND

(a) Output sink current (b) Output source current

Figure 3.1.3. Power consumption caused by output current

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3.2 Input offset voltage

The input offset voltage represents the error voltage of an The unit of the input offset voltage is usually [mV] or [μV]. The
op-amp or comparator. An ideal op-amp or comparator has ideal condition is approached when the value is closer to 0.
the input offset voltage of 0 V. When a common mode When the voltage is out of the input common-mode voltage
(identical) voltage is input to the input terminal of an op-amp range, the input offset voltage rapidly increases and the
or comparator, no output voltage is output in an ideal op-amp. circuit cannot be operated as an op-amp or comparator.
However, when the input offset voltage exists, an output When the frequency of appearance of the input offset voltage
voltage is output in response to the input offset voltage. is observed, the observed values follow a normal distribution
The difference in potential between the input terminals that is around 0 V. In other words, the values stochastically distribute
required to make this output voltage 0 V is referred to as the within the range specified in the data sheet. While the
input offset voltage. This value is the input conversion value. standard values are described as absolute values, the input
One advantage of expressing the value as the input offset voltages actually have both + and - polarities. The
conversion is as follows: since op-amps and comparators are specific effects of the input offset voltage are explained in the
utilized with various amplification factors and circuit next section.
configurations, the influence on the output voltage can be
easily estimated by using the input conversion.

VCC/VDD
±Vos

+ OUT

Input common-
-
mode voltage
同相入力電圧
VEE/VSS
Input offset voltage: can be
入力オフセット電圧：
expressed
端子間に存在する as the voltage
between the terminals.
電圧として表現できる。

Input同相入力範囲
common-mode range Op-amp
オペアンプ 1 1
（入力電圧範囲）
(Input voltage range)

++極性
polarity
入力オフセット電圧
Input offset voltage

仕様範囲 range
Specification
VOS1 Frequency

0 Input common-
同相入力電圧 VOS2
mode voltage Op-amp 2 2
オペアンプ

--極性
polarity
Input offset voltage

入力オフセット電圧
Input offset voltage

Change in the offset voltage

入力電圧範囲に対する Image of the offset voltage
for the input voltage range
オフセット電圧の変化 オフセット電圧の分布イメージ
distribution

Figure 3.2.1. Image of input offset voltage

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Effect of input offset voltage

Op-amp
This section explains the effect of the input offset voltage
Rf Rf
when an amplifier circuit is configured with an op-amp. VO   Vin  (1  )VOS (3.2.2)
For the non-inverting amplifier circuit in Figure 3.2.2 (a), the
RS RS
effect of the input offset voltage is calculated as in Equation As described in Equation (3.2.2), the input offset voltage is
(3.2.1). multiplied by the amplification factor seen from the + terminal
The input offset voltage is multiplied by the gain and the side (i.e., the amplification factor of the non-inverting amplifier
product is added to the output voltage. When the input offset circuit) and the product is added to the output of the inverting
voltage has the + polarity, the output voltage is higher than amplifier circuit. As in the previous case, the output voltage is
the expected value. Conversely, the - polarity results in a shifted from the expected value by the product of the input
lower output voltage than the expected value. offset voltage multiplied by the gain.
In Figure 3.2.3, the calculation is performed assuming that the
Rf Rf
VO  (1  )Vin  (1  )VOS (3.2.1) input offset voltage is ±5 mV. In either circuit, the center of the
RS RS
waveform is shifted by the product of the input offset voltage
Next, the effect of the input offset voltage is determined when multiplied by the amplification factor (5 mV × 16). It is
the inverting amplifier circuit is configured as in Figure 3.2.2 necessary to choose an op-amp with an appropriate value for
(b). the input offset voltage considering the desired circuit gain.

Rf
Vin ±Vos

Vo
Rs
Vin
- Vo
Rf
±Vos
+
Rs

(a) Non-inverting amplifier circuit (b) Inverting amplifier circuit

Figure 3.2.2. Amplifier Circuit with Op-Amp

30kΩ
VCC=2.5V
±Vos=±5mV
VCC=2.5V
Vo 2kΩ

Vin=0.2Vpp
- Vo
±Vos=±5mV
VEE=-2.5V +
Vin=0.2Vpp
VEE=-2.5V
30kΩ
2kΩ

GND
Voltage [V]

電圧[V][V]

電圧[V][V]
電圧[V] [V]
電圧[V]

Voltage

Voltage
Voltage

3.2Vpp
3.0Vpp

0.2Vpp +80mV 0.2Vpp +80mV

Time [t]
時間[t]
0 0 0 0
時間[t]
Time [t] Time
時間[t][t] Time
時間[t][t]
-80mV -80mV

(a) Non-inverting amplifier circuit (b) Inverting amplifier circuit

Figure 3.2.3. Example of effect of offset voltage

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Comparator
Effect of the input offset voltage on the overdrive voltage However, when the input offset voltage is 6 mV, the
The difference between the voltage to be compared and the comparator does not respond to the overdrive voltage of 5 mV.
reference voltage (Vref) is referred to as the overdrive voltage. In other words, the input offset voltage appears to be added
When the difference is smaller, the response time tends to be to the reference voltage Vref. When the specification for the
longer. The response time is generally specified at 5 mV, 10 input offset voltage is ±Vos, the individual circuits may output
mV, 50 mV, and 100 mV. As an example, consider a either High or Low outputs in the section between Vref + Vos
comparator with the input offset voltage of 6 mV. In an ideal and Vref - Vos. Datasheet graphs of response time vs
situation where no input offset voltage exists, the output overdrive voltage are measured with compensating for input
voltage is switched even when the applied input is only offset voltage.
slightly higher or lower than the reference voltage (Vref).

VDD
±Vos

OUT
Vin

Vref
VSS=GND

VDD VDD VDD

① ③
② Vref+Vos
Input
入力 Vref Vref Vref
Vref-Vos

GND GND GND

VDD VDD VDD

High High High

Output
出力 In the section between
Vref + Vos and Vref -
Low Vos, both the High and
GND GND GND
Low output may exist.
(This does not mean
Ideal situation when no input offset voltage exists When the input offset voltage (Vos) exists
that the output may

become unstable.)
Figure 3.2.4. Effect of input offset voltage on comparator

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Cause of the input offset voltage

Since the principle of generation is identical for the bipolar of the board since the stress is larger in the edges. In addition,
and CMOS types, the explanation is given for the bipolar since a larger package is less susceptible to the stress, it is
type. effective to choose a package with a larger size when
In Figure 3.2.5, the input offset voltage is generated by the precision is necessary.
difference in the characteristics between transistors Q1 and
Q2 as well as between Q3 and Q4. More precisely, variations Temperature drift of the input offset voltage
during the manufacturing process make the voltages between
The input offset voltage varies with temperature. This
the base and emitter different between Q1 and Q2 as well as
variation is referred to as the temperature drift. As with the
between Q3 and Q4. This causes the difference between
input offset voltage, the temperature drift value is not constant
collector currents Ic3 and Ic4, which flow through Q3 and Q4,
and follows a normal distribution. For some products, the
respectively. The difference between the collector currents
standard values may be described in the data sheet. It should
contributes to the generation of the input offset voltage. (The
be noted that the input offset voltage may be observed as if
base currents of Q3 and Q4 can also affect the input offset
drift has been caused by the piezo-resistance effect as
voltage through the variation in the center value. However,
mentioned above when the degree of bending of the mounted
this effect is usually minimized by design and can be
board changes with the temperature.
excluded from the consideration.)

Increase of the input offset voltage caused by the input

VCC bias current
I
When configuring an amplifier circuit with a bipolar op-amp, it
Vbe1 Vbe2
-IN is necessary to take a countermeasure against the input bias
current. The input offset voltage is increased by the product of

Q1 Q2 the input bias current and the parallel combined resistor value

+IN Ic1 of the resistors that constitute the amplifier circuit.

A countermeasure is to connect the same combined
2Ib Ic2=Ic4 resistance to the other input terminal. This will be explained in
Ic3=Ic1-2Ib
Q3 Q4 more detail in the section for the input bias current.

Vbe3 Vbe4
VEE=GND

Figure 3.2.5. Differential input stage of op-amp

In addition, the effect of the stress from the package and the
board is a cause of input offset voltage generation. This effect
generally becomes more significant in the smaller packages.
When the stress is received, the piezo-resistance effect is
generated by the semiconductor element surface being
pushed or the IC chip being bent. The piezoelectric effect
caused by this piezo-resistance effect changes the
characteristics of transistors.
In op-amps, mainly the differential input stage is subject to the
stress effect and the input offset voltage may be changed by
the stress from the board after the board is mounted. As a
countermeasure, the op-amp should be placed on the center

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3.3 Input bias current and input offset current

A current flowing from or into the input terminal of op-amps is In the case of the NPN input as shown in Figure 3.3.1 (b), the
referred to as the input bias current. In op-amps of the bipolar input bias current flows into the terminal. In the full swing
type, the base current of the transistor connected to the input op-amp of the bipolar type shown in Figure 3.3.1 (c), the
terminal is the input bias current. When the differential input direction of the input bias current changes depending on the
stage is configured with PNP transistors, the current flows out. operating range. In the range where only the PNP transistor
Conversely, when the differential input stage is configured operates, the input bias current flows from the terminal. In the
with NPN transistors, the current flows in. Many products are range where both types of transistors operate, the differential
designed so that the amount of current falls approximately in current flows, and the polarity becomes the larger one. When
the order of nA (10-9 [A]) while some high-speed type products only the NPN transistor operates, the input bias current flows
have a bias current in the order of μA (10-6 [A]). into the terminal. Therefore, the polarity of the bias current
Ideally, op-amps are easier to use when the bias current is changes within the input common-mode voltage range.
smaller. The CMOS type (FET input) op-amps are considered The input bias current in the CMOS op-amp shown in Figure
such op-amps. The bias current in the CMOS op-amp is very 3.3.1 (d) is the terminal leakage current. The main cause is
small and falls in the order of fA (10-15 [A]) to pA (10-12 [A]). the electrostatic protection element connected to the inside of
Therefore, the CMOS op-amps are used as the sensor the IC. This current is very small compared with the bipolar
amplifiers of sensor elements and other elements with high type, providing an advantage when connecting op-amps of
impedance. this type with high-impedance elements such as sensors. In
As shown in Figure 3.3.1 (a), the input bias current flows from addition, this type of op-amp has a characteristic in which the
the input terminal when the op-amp is configured with a PNP current tends to increase at a higher temperature since the
transistor as the input transistor. leakage current increases with temperature.

VCC VCC
ESD ESD
ESD ESD
protection
protection
保護素子 保護素子
element
element

バイアス電流
Bias current バイアス電流
Bias current

+IN +IN
ESD
ESD ESD
ESD
保護素子
protection 保護素子
protection
element element
ＧＮＤ ＧＮＤ

(a) Input ground sense (ground sense single/ (b) NPN input (VCC sense)
dual power supply)

ESD
VCC VCC
Leakage
protection
ESD リーク電流
current
element
保護素子
ESD
ESD
バイアス電流
Bias current バイアス電流 protection
保護素子
Bias current element

+IN +IN
ESD
ESD Leakage ESD
ESD リーク電流 protection
protection current 保護素子
保護素子 element
element

ＧＮＤ ＧＮＤ
(c) PNP/NPN input (full swing) (d) CMOS input (full swing)

Figure 3.3.1. Input bias current and input transistor

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Effect of input bias current Cancel of the input bias current

The difference in the input bias currents in the + and - input The effect of the input bias current in the inverting amplifier
terminals is referred to as the input offset current. Since the circuit in Figure 3.3.3 is described by Equation (3.3.3).
base current and the leakage current are affected by the
R2 R  RR 
performance variation in transistors, the values are not Vout   Vin  (1  2 )  1 2 Ib  R3 Ib  (3.3.3)
R1 R1  R1  R2 
necessarily the same.
Arranging Equation (3.3.3) with Equations (3.3.1) and (3.3.2)
The input bias current (Ib) and the input offset current (Iio) are
gives Equation (3.3.4), where Equation (3.3.1) defines the
defined by Equations (3.3.1) and (3.3.2), respectively.
input bias current and Equation (3.3.2) defines the input offset
Ib  Ib current.
Ib  (3.3.1)
2 In Equation (3.3.4), the effect of the input bias current can be
removed if R3 is set to the same value as the parallel
Iio  Ib  Ib (3.3.2)
combined impedance of R1 and R2 in order to nullify the Ib
term. Equation (3.3.4) also shows that the presence of the
input offset current affects the output voltage.

R2 R  RR RR I 
Vout   Vin  (1  2 ) ( 1 2  R3 ) I b  ( 1 2  R3 ) io 
R1 R1  R1  R2 R1  R2 2
(3.3.4)
VCC

-IN Ib-
VCC
Q1 Q2
+IN OUT
Ib+
Ib+

Q3 Q4 Ib-
VEE=GND

VEE=GND

(a) Differential input stage (b) Input bias current in op-amp

Figure 3.3.2. Input bias current

VCC
R3

OUT
Ib+

R1 Ib-
Vin VEE=GND

R2

Figure 3.3.3. Input bias current in inverting

amplifier circuit

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3.4 Input common-mode voltage range

The input common-mode voltage range (VICM) refers to the Equation (3.4.2) shows that the 4558 series op-amp has both
range of input voltage within which an op-amp operates upper and lower limits between which the transistors can
normally. When a signal outside the input common-mode operate. The op-amps of this type are referred to as dual
voltage range is input, the input offset voltage is increased power supply op-amps. Normally, positive and negative
rapidly and the output voltage is saturated, disrupting the power supplies are used with the ground being the middle
normal operation. point potential. However, this type of op-amp can also be
The input common-mode voltage range is determined by the used with a single supply if the bias voltage is appropriately
circuit configuration of the differential amplifier circuit that is adjusted.
the input circuit of the op-amp. Next, the input common-mode voltage range of the 358/2904
Figures 3.4.1 and 3.4.2 show the differential input stages of series op-amp shown in Figure 3.4.2 is described by Equation
the 4558 and 358/2904 series op-amps, respectively. (3.4.3). In the 358/2904 series op-amps, level shift circuits Q1
Consider the input common-mode voltage ranges for these and Q2 are employed so that the input voltage at the ground
two types of op-amp. (VEE) level can be handled. In addition, this type of op-amp is
The input common-mode voltage range of the 4558 series designed so that the collector potentials at Q3 and Q4 can be
op-amp is described by Equation (3.4.1), where VICM is the made nearly equal due to the arrangement of the circuit
input common-mode voltage. The lower limit of the input configuration. This makes Q3 and Q4 saturated at nearly the
common-mode voltage range is the voltage that is required same voltage.
for transistors Q1 and Q2 to operate without being saturated. Equation (3.4.4) shows that the lower limit of the input
Conversely, the upper limit of the input common-mode common-mode voltage is determined by Vsat and Vbe. Since
voltage range is the voltage that is required for transistor Q0 Vsat is generally lower than Vbe, the input common-mode
to operate without being saturated. voltage range of the 358/2904 series op-amp can include
VEE, allowing the signal input at the ground level.

VEE  Vbe 6  Vbe5  Vsat 2  Vbe 2  VICMR  VCC  Vsat 0  Vbe 2 (3.4.1)

If we assume that all Vbe and Vsat values are equal in Equation (3.4.1),

VEE  (Vbe  Vsat )  VICMR  VCC  (Vsat  Vbe ) (3.4.2)

VEE  Vbe5  VVsat 3  Vbe3  Vbe1  VICMR  VCC  Vsat 0  Vbe3  Vbe1 (3.4.3)

If we assume that all Vbe and Vsat values are equal in Equation (3.4.3),

VEE  (VVsat  Vbe )  VICMR  VCC  (Vsat  2Vbe ) (3.4.4)

VCC VCC

Vsat0 Vsat0
Q0 Q0
Vbe1 Vbe2 Vbe3 Vbe4
-IN Vbe1
Vsat2 Vsat3 Vbe2
Q1 Q2 -IN
Q3 Q4
Q1
Q2
+IN
+IN
Q8
Q5
Q9
Q3 Q4 Q5 Q6 Q7
Vbe5
Q6
Vbe5
Vbe6
VEE VEE

Figure 3.4.1. Differential input stage of 4558 series op-amp Figure 3.4.2. Differential input stage of 358/2904 series op-amp

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Next, we explain examples of the characteristics and the As in Figures 3.4.4 and 3.4.5, the input common-mode
measurement method of the input common-mode voltage. voltage range limits the input voltage. Therefore, it is
Figure 3.4.3 (a) shows the measurement circuit for the input necessary to choose an op-amp with an input range adequate
common-mode voltage. The input voltage is varied with the for the application to be used. So far, we have explained that
input terminal of the differential amplifier circuit being used as the input common-mode voltage range and the input offset
the common terminal. voltage are closely related. Regardless of whether the
Since the common-mode voltage is input, the output voltage op-amp type is the CMOS (FET input) type or the bipolar type,
should ideally be 0. However, since the input offset voltage there are commercially available op-amps of the full swing
actually exists, the output offset voltage is output with the input type in which the input common-mode voltage range is
input offset voltage multiplied by the amplification factor as extended from VEE to VCC. Since such op-amps can secure
shown in Figure 3.4.3 (b). the input dynamic range even with a low supply voltage, they
Next, we present images of the input common-mode voltage are ideal for applications operated at a low voltage, such as
ranges for the 358/2904 and 4558 series op-amps, which we mobile devices.
considered in the previous section for the input
common-mode voltage range.

VCC
R3
出力電圧 voltage

OUT
Output

R1
R4 VEE
Vin Output offset voltage
出力オフセット電圧

0 Input common-mode
同相入力電圧 voltage
R2

(a) Measurement circuit diagram (b) Input common-mode voltage vs. output voltage

Figure 3.4.3. Measurement circuit for input common-mode voltage

VEE+(Vbe+Vsat) VCC-(Vbe+Vsat) Vbe+Vsat

VEE VCC
Input common-mode voltage [V]

Outside the input common- Outside the input common- VCC VICM(Max)
mode voltage range mode voltage range Vbe+Vsat is

Input common-mode constant for

voltage Range(VICM) all operating
VCC (VEE)[V] range of
input common-mode voltage range power supply

VEE VICM(Min) voltage.

0 input common-mode voltage Vbe+Vsat

Figure 3.4.4. Input common-mode voltage range of 4558 series op-amp

Input common-mode voltage [V]

VCC
2Vbe+Vsat

VICM(Max)
Output Voltage

Input common-mode
voltage Range(VICM)

VICM(Min)=0V

VCC[V]

Figure 3.4.5. Input common-mode voltage range of 358/2904 series op-amp

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Op-Amp/Comparator Tutorial Application Note

3.5 Maximum output voltage (High/Low level

output voltage

The maximum output voltage (output voltage range) refers to The maximum output voltage High is described by the
the voltage range within which an op-amp can output. The following equation.
voltage values can be separated into the maximum output Maximum output voltage High
voltage High (High level output voltage) and the maximum = VCC - Vce1 - Vbe2 - (R1 × Isource) (3.5.1)
output voltage Low (Low level output voltage). Next, we consider the maximum output voltage Low. There
The output voltage range is limited by the output circuit are transistors Q3 and Q4 and short circuit protection resistor
configuration, the supply voltage, and the load condition (the R2 along the path from the output terminal to the VEE
amount of output current). terminal. As in the case for the maximum output voltage High,
Next, we explain the output voltage range of the 4558 series the maximum output voltage Low is determined by the
low noise op-amp, which is the most standard dual power voltage between the collector and emitter of transistor Q4
supply op-amp. (Vce4), the voltage between the base and emitter of Q3
As we mentioned, the output voltage range depends on the (Vbe3), and when the output sink current (Isink) flows, the
output circuit configuration. The limit is imposed because a voltage drop caused by protection resistor R2.
certain voltage is required for the elements that constitute the The maximum output voltage Low is described by the
circuit, such as transistors, to operate normally. following equation.
Figure 3.5.1 shows the output equivalent circuit diagram for Maximum output voltage Low
the 4558 series op-amp. First, we consider the maximum = VEE + Vce4 + Vbe3 + (R2 × Isink) (3.5.2)
output voltage High. There are transistors Q1 and Q2 and Figure 3.5.2 shows an example of the maximum output
output protection resistor R1 along the path from the output voltages for the 4558 series op-amp.
terminal to the VCC terminal. The voltage necessary for the As shown in Figure 3.5.2, there exists dead zones on both the
normal operation is determined by the voltage between the positive power supply (VCC) side and the negative power
collector and emitter of Q1 (Vce1), the voltage between the supply (VEE) side where the op-amp cannot operate.
base and emitter of Q2 (Vbe2), and when the output source
current (Isource) flows, the voltage drop from the Q2 emitter
by R1 × Isource. The output voltage range is reduced when
the load (RL) is higher (the resistor value is smaller) and a
larger source current flows.
15
VCC 最大出力電圧High
Maximum output voltage High

10
Vce1
V be 2 + Vc e 1
Q2
Q1 + R1 ×I so u r c e
Output voltage [V]

5
Vbe2
R1 Isource Maximum
最大出力
output 0
電圧範囲
voltage range
R2 Isink
Vbe3 RL -5

Q4 Vbe 3 + Vc e 4
Q3 -10
+ R1 ×I sin k
Maximum 最大出力電圧Low
output voltage Low
Vce4

VEE
-15
0.1 1 10 100
Load resistance [kΩ]
VCC/VEE = +15 V/-15 V, Ta = 25°C, VRL = VCC/2
Figure 3.5.1. Output equivalent circuit diagram Figure 3.5.2. Example of maximum output voltage
for 4558 series op-amp for 4558 series op-amp

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Op-Amp/Comparator Tutorial Application Note

Next, we consider the output voltage range of the 358/2904 Since this Low level output voltage is very small (around 10
series op-amp, which is the most standard single supply mV), the output voltage can be output nearly at the ground
op-amp. level. When the output sink current becomes larger than 40
Figure 3.5.3 shows the output equivalent circuit diagram for μA, the output sink current begins to flow into Q4. The voltage
the 358/2904 series op-amp. As for the maximum output necessary for Q4 to operate is determined by the voltage
voltage High, there are transistors Q1, Q2, and Q3, and between the collector and emitter of Q5 and the voltage
current limit resistor R1 along the path from the output between the base and emitter of Q4.
terminal to the VCC terminal. The voltage necessary for this The maximum output voltage Low is described by the
circuit to operate is determined by the voltage between the following equation.
collector and emitter of Q1 (Vce1), the voltages between the Maximum output voltage Low
base and emitter of Q2 (Vbe2) and Q3 (Vbe3), and the = VEE + Vce6 (Isink < 40 μA) (3.5.4)
voltage drop due to the output source current (Isource) by R1 Maximum output voltage Low
× Isource. The output voltage range is reduced when the load = VEE + Vce5 + Vbe4 (Isink > 40 μA) (3.5.5)
(RL) is higher (the resistor value is smaller) and a larger In this way, the different circuits operate in the 358/2904
source current flows. series op-amps depending on the amount of the output sink
The maximum output voltage High is described by the current. Therefore, when the 358/2904 series op-amps are
following equation. used with the load current value being near the Low level sink
Maximum output voltage High current of 40 μA, the Low level voltage varies as the output
= VCC - Vce1 - Vbe2 - Vbe3 - (R1 × Isource) (3.5.3) circuits are switched, causing a distortion in the waveform.
Next, we consider the maximum output voltage Low. The This distortion is referred to as the crossover distortion. We
358/2904 series op-amps feature two routes from the output explain this distortion in detail later.
terminal to the VEE terminal. One is the path through Figure 3.5.4 shows an example of the maximum output
transistors Q4 and Q5. The other is the path through Q6. The voltages for the 358/2904 series op-amp. As shown in Figure
Q6 path has a structure in which a constant current of 40 μA 3.5.4, there exists a dead zone on the positive power supply
from the output terminal is always supplied by Q6 while the (VCC) side where the op-amp cannot operate. On the
output voltage is Low. This constant current is referred to as negative power supply (VEE) side, the figure demonstrates
the Low level sink current. When the output current is that a voltage near VEE (ground) can be output in some
sufficiently smaller than 40 μA, the output voltage Low is conditions.
determined by the voltage between the collector and emitter
of Q6 (Vce6).

VCC 5.0
4.5
Vce1
Vbe 2 + Vbe 3 + Vc e 1 Maximum output voltage High
最大出力電圧High
Q2 4.0
Q1 + R 1 ×I so u r c e
Q3
voltage [V]

3.5
Vbe2
Isource Maximum
出力電圧[V]

Vbe3
3.0
output
最大出力
voltage
電圧範囲 range 2.5
Output

R1 2.0

Vbe4 Vc e 6 1.5
Isink Isink (I sin k < < 4 0 μA)
RL Maximum output voltage Low
最大出力電圧Low
1.0
Q5 Vbe 4 + Vc e 5
Q4 (I sin k > 4 0 μA) 0.5
Vce6 VRL
Q6 0.0
Vce5 VEE 0.1 1 10 100
Constant current source: 40 μA
定電流源：40μA
Load resistance [kΩ]
負荷抵抗[kΩ]
VCC/VEE = 5V/0V, Ta = 25°C, VRL = VCC/2

Figure 3.5.3. Output equivalent circuit for Figure 3.5.4. Example of maximum output voltage for
358/2904 series op-amp 358/2904 series op-amp

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 Application Note

3.6 Large signal voltage gain (open loop gain)

This refers to a gain with respect to the voltage difference When R1 = 1 [kΩ], R2 = 10 [kΩ], Av = 80 dB (10,000 times),
between + and - input terminals of op-amps/comparators. the amplification factor is 11 in an ideal situation.
The standard values specified in the data sheet are the
1 11
voltage gains with respect to a DC current. To minimize the VOUT  11   VIN   10.988 (3.6.3)
1 1.0011
1  11 
gain error that is generated when a feedback circuit is 10000
configured, a high voltage gain (high open loop gain) is VOUT is given by Equation (3.6.3), resulting in an amplification
generally considered ideal. When the output voltage is VOUT factor less than 11. The difference from the ideal situation is
and the difference in input potentials is VIN_d, the voltage gain referred to as the gain error. Figure 3.6.2 shows the relation
(Av) is given by the following equation. between the output voltage and the amplification factor of a

VOUT large signal voltage gain.

Av  (3.6.1)
VIN _ d

Take a non-inverting amplifier circuit shown in Figure 3.6.1 as

an example to consider the gain error.

Output voltage [V]

VCC

VOUT
Av
VIN

R1
VEE

R2
Figure 3.6.1. Non-inverting amplifier circuit Large signal voltage gain [dB]

Figure 3.6.2. Relation between output voltage and large

signal voltage gain
The output voltage (VOUT) is given by the following equation.

 R  1 The voltage gain depends on the frequency. It is attenuated

VOUT  1  2    VIN
 R1   R 2  1 (3.6.2) as the input signal frequency is increased. Therefore, the gain
1  1  
 R1  Av error increases at a higher frequency. Figure 3.6.3 shows an
In Equation (3.6.2), if we assume that Av is ∞, the gain of the example of the frequency characteristic of the voltage gain in
circuit is determined by 1 + R2/R1. Therefore, a gain error the circuit shown in Figure 3.6.1 (using a BA2904 op-amp).
occurs when the open loop gain (Av) has a finite value.

40

30

20

10
Gain [dB]

-10

-20

-30

-40
10
10 1002
10 10 3
1000 10 4
10000 10 5
100000 10 6
1000000 10 7
10000000

Frequency [Hz]

Figure 3.6.3. Frequency characteristic of the voltage gain

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 Application Note

3.7 CMRR (Common Mode Rejection Ratio)

The common mode rejection ratio (CMRRAMP) is the ratio of G is the gain (R2/R1) of the amplifier circuit. Suppose that
variation in the output voltage when the input common-mode CMRRRES = GDIFF/GCM, where GDIFF is the amplification factor
voltage is varied, expressed in dB. Generally, the CMRR for the differential voltage and GCM is the amplification factor
specified in the data sheet represents the ratio of the DC input for the common-mode voltage (the derivation is omitted).
common-mode voltage and the variation in the input offset
1 G
voltage (ΔVIO) when the DC input common-mode voltage is CMRRRES 
RR
varied. This ratio expresses the value of the CMRR for the 1 2 3 (3.7.2)
R1 R4
op-amp itself. We will explain the details in the next section.
In Figure 3.7.1 (a), the CMRR of the whole circuit (CMRRALL)
 V 
CMRR AMP  20 log ICM  (3.7.1) is described by Equation (3.7.3).
 VIO 
1 G
Next, we explain a view about the common mode rejection CMRR ALL 
1 G  R R 
ratio when an amplifier circuit is configured.  1  2 3 
CMRR AMP  R1 R4 
When an amplifier circuit is configured with external resistors, (3.7.3)
an error in resistance (pair mismatch) causes an offset Therefore, a resistance mismatch affects the common mode
voltage in the amplifier circuit. This offset voltage due to the rejection ratio of an associated amplifier circuit. It can be seen
resistance error affects the common mode rejection ratio in that CMRRALL is limited even when an op-amp with a large
the same way that the input offset voltage of op-amps does. CMRR (CMRRAMP) is used.
The CMRRRES due to the resistance error in the amplifier In the next section, we further consider the meaning of the
circuit can be calculated with the following equation. Here, we common mode rejection ratio of op-amps.
suppose that the CMRR of the op-amp is ideal (CMRRAMP =
∞). The error mentioned here is a mismatch between R1 and
R3 as well as between R2 and R4.

ΔVICM
VCC
R3

OUT
ΔVIO

Vin R1
0
出力電圧
voltage

R4 VEE Input common-mode

同相入力電圧 voltage
The同相入力信号レベルに対する
offset voltage variation is small
relative to the input common-mode
オフセット電圧変動が小さい
Output

R2 signal level
=CMRRが大きい(良い)
= CMRR is large (good)

(a) Measurement circuit diagram (b) Variation in the input offset voltage

Figure 3.7.1. Relation between input offset voltage and CMRR

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 Application Note

Common mode rejection ratio of op-amps

Introductory books on circuit design define the CMRR of an the input offset voltage as mentioned above.
op-amp itself as CMRR = Ad/Ac expressed in dB, where Ad
(the differential voltage gain) is the gain with respect to the As an example, we use Equation (3.7.7) to calculate the effect
difference in input voltages of the op-amp and Ac (the of a variation in the input common-mode voltage on the
common-mode voltage gain) is the gain with respect to the output.
input common-mode voltage. This definition corresponds to We calculate VIO_10 when VIO_0 = 1 [mV] and CMRR = 80 [dB]
Equation (3.7.1). = 10,000 [times], where VIO_10 is the input offset voltage when
Ideally, an op-amp should amplify the difference in voltages VIC = 10 [V], VIO_0 is the offset voltage when VIC = 0 [V], and
between its + and - input terminals by the gain of the amplifier. VIC is the input common-mode voltage.
However, the differential voltage gain and the common-mode
VIC _ 10 _ VIC _ 0
voltage gain are altered in an actual op-amp due to changes CMRR  (3.7.8)
VIO _ 10 _ VIO _ 0
in the DC operating points (current and voltage) inside the
circuit that are caused by a variation in the input
10[V ]
common-mode voltage. As a result, the input offset voltage is VIO _ 10   1[mV ]  2[mV ] (3.7.9)
CMRR[times]
varied and a variation in the output voltage is observed.
When the gain with respect to the difference in the input Therefore, when CMRR = 80 [dB], a variation of 10 [V] in the
voltages is Ad (the differential voltage gain), the gain with input common-mode voltage increases the input offset
respect to the input common-mode voltage is Ac voltage by 1 [mV].
(common-mode voltage gain), the potential of the + input The next section explains the mechanism by which the input
terminal is Vin_p, and the potential of the - input terminal is offset voltage is varied due to a variation in the input
Vin_n, the output voltage of the op-amp can be described by common-mode voltage.
the following equations.

VOUT  Ad  (Vin _ p  Vin _ n )  Ac  VICM (3.7.4)

 Ac 
VOUT  Ad   (Vin _ p  Vin _ n )   VICM  (3.7.5)
 Ad 
VICM is the input common-mode voltage and equal to (Vin_p +
Vin_n)/2.
In Equation (3.7.5), the term, (Ac/Ad) × VIC, represents an
error term due to the input common-mode voltage and can be
considered the input offset voltage.

Ac
VIO   VICM (3.7.6)
Ad

From Equation (3.7.6), a variation in the input offset voltage

due to a variation in the input common-mode voltage is
provided as follows.

VICM Ad
  CMRR (3.7.7)
VIO Ac

Equation (3.7.7) shows that the ratio of the variations is

equivalent to the ratio of the input common-mode voltage and

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 Application Note

Mechanism of the variation in the input offset voltage due to For the calculation of common-mode voltage gain, gm is the
the input common-mode voltage (reference) transconductance of transistors, rd is the drain impedance, gd
Figure 3.7.2 shows the equivalent circuit for a differential is the drain conductance, VICM is the input common-mode
input stage. We explain the mechanism by which the input voltage, and V is the drain voltage of M5.
offset voltage is increased by a variation in the input In addition, 1/rd = gd. Form an equation for nodes VO and V.
common-mode voltage. First, we assume that the Arranging Equation (3.7.10) and using an approximation that
characteristics are identical between transistors M1 and M2 gm4, gm2 >> gd4, gd2, Equation (3.7.11) is obtained (the
as well as between M3 and M4. This means that no input derivation is omitted).
offset voltage is generated by the differential input stage or Equation (3.7.11) shows that the common-mode voltage gain
the active loads. Since the characteristics are identical, the (AC) is determined by the impedance of transistor M5 and gm
voltages between the gate and source are equal and the of the active load. Next, the differential voltage gain can be
currents flowing through differential input transistors M1 and described by Equation (3.7.12) (the derivation is omitted).
M2 are equal. Next, since the characteristics of active loads When the input offset voltage is VIO, CMRR is calculated from
M3 and M4 are identical, the currents flowing through the Equations (3.7.11) and (3.7.12), resulting in Equation
loads are equal. The identical currents and characteristics (3.7.13).
result in identical drain voltages between active loads M3 and Thus, to obtain a smaller common-mode voltage gain (AC), rd5
M4. Therefore, we can consider that Vx and Vo is virtually or gm4 needs to be larger. A larger rd5 means that the current
short-circuited in small signal equivalent circuit 1 in Figure flowing through transistor M5 is less likely to be affected by
3.7.2 (b). Based on this point, the small signal equivalent the input common-mode voltage. However, actual values of
circuit is described as small signal equivalent circuit 2 in rd5 and gm4 are finite and CMRR is therefore limited. In other
Figure 3.7.2 (c). Since we can consider that the transistor words, since CMRR is finite, the input offset voltage is varied
elements are connected in parallel to each other, it is possible due to the variation in the input common-mode voltage.
to combine the circuits for simplification. The common-mode
voltage gain is calculated with this circuit.

g d 5V  2 g m 2 (V ICM  V )  2 g d 2 (V  V O )  0
2 g m 4V O  2 g d 4V O  2 g m 2 (V ICM  V )  2 g d 1 (V  V O )  0 (3.7.10)

VO 1
Ac   (3.7.11)
V ICM 2 g m 4 rd 5

VO
Ad   g m1 ( rd 2 // rd 4 ) (3.7.12)
Vind
Ad V ICM V ICM
CMRR     2 g m 4 g m1 rd 5 ( rd 2 // rd 4 ) (3.7.13)
Ac Vind V IO

VDD

M5 rd5 rd5
gm1(VICM-V) gm2(VICM-V)
V V
rd1 rd2 2gm2(VICM-V) 2rd2
M1 M2
Vo Vo
Vx Vo
rd3 rd4 2gm4VO 2rd4
VICM gm3VO gm4VO
M3 M4

VSS=GND

(a) Equivalent circuit for differential input circuit (b) Small signal equivalent circuit 1 (c) Small signal equivalent circuit 2

Figure 3.7.2. Equivalent circuit diagram for op-amp differential input stage

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 Application Note

Next, we explain the frequency characteristic of the CMRR. This causes a simultaneous reduction in the CMRR. Figure
The differential voltage gain shown in Equation (3.7.13) is the 3.7.3 shows the frequency characteristic of the CMRR.
gain with respect to a given DC voltage. This gain actually It is important to consider the frequency characteristic of the
has a frequency characteristic. As shown in Equation (3.7.13), CMRR when actually using op-amps.
the differential voltage gain of op-amps is closely related to
the CMRR. The differential voltage gain of the op-amp is
reduced at the rate of -6 dB/oct (= -20 dB/dec) as the
frequency increases, due to the first pole of the differential
input stage.

100

90

80

70

60
CMRR[dB]

50

40

30

20

10

0 2
10
10 10
100 10 3
1000 10 4
10000 10 5
100000
Frequency [Hz]

Figure 3.7.3. CMRR frequency characteristic

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 Application Note

3.8 PSRR (Power Supply Rejection Ratio)

The power supply rejection ratio (PSRR) is the amount of equivalent to the ratio of the variation in the input offset
variation in the input offset voltage when the power supply voltage with respect to the power supply voltage variation
voltage is varied, expressed as a ratio. Generally, the mentioned above.
standard values described in the data sheet are the ratio of
VCC Ad
variation in the input offset voltage when a DC voltage supply   PSRR (3.8.5)
VIO Ap
is varied.
As an example, we use Equation (3.8.5) to calculate Vio_20
 VCC 
PSRR  20 log  (3.8.1) when Vio_10 = 1 [mV], where Vio_20 and Vio_10 are the input
 VIO  offset voltages when Vcc = 20 [V] and 10 [V], respectively.
PSRR is generally defined by PSRR = Ad/Ap, where Ad is the Suppose that PSRR = 80 [dB] (= 10,000 times).
gain with respect to the difference in the input voltages of the
VCC _ 20 _ VCC _ 10
amplifier (differential voltage gain) and Ap is the gain with PSRR   10000[times] (3.8.6)
VIO _ 20 _ VIO _ 10
respect to the power supply voltage. This definition has the
same meaning as Equation (3.8.1).
10[V ]
Ideally, an op-amp should increase the difference in voltages VIO _10   1[mV ]  2[mV ] (3.8.7)
10000[times]
between its + and - input terminals by the gain of the amplifier.
However, the differential voltage gain and the power supply Therefore, when PSRR = 80 [dB], a variation of 10 [V] in the
variation gain are altered in an actual op-amp due to changes power supply voltage increases the input offset voltage by 1
in the DC operating points (current and voltage) inside the [mV].
circuit that are caused by changing the power supply voltage. When an amplifier circuit is configured, the error voltage that
As a result, the input offset voltage varies and a variation in is multiplied by the gain of the amplifier circuit is output as an
the output voltage is observed. error in the output voltage.
When the gain with respect to the difference in the input When a non-inverting amplifier circuit with a gain of 100
voltages is Ad (the differential voltage gain), the gain with [times] is configured, a variation of 10 [V] in the power supply
respect to the power supply voltage is Ap (power supply voltage causes a variation of 100 [mV] in the output voltage.
voltage gain), the potential of the + input terminal is Vin_p,
and the potential of the - input terminal is Vin_n, the output
voltage of the op-amp can be expressed by the following
equations.

VOUT  Ad  (Vin _ p  Vin _ n )  Ap  VCC (3.8.2)

 Ap 
VOUT  Ad   (Vin _ p  Vin _ n )   VCC  (3.8.3)
 Ad 

In Equation (3.8.3), the term, (Ap/Ad) × Vcc, represents an

error term due to the power supply voltage and can be
considered the input offset voltage.

Ap
V IO   VCC (3.8.4)
Ad

From this relational expression, the variation in the input

offset voltage with respect to the variation in the power supply
voltage is described by Equation (3.8.5). Therefore, PSRR is

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 Application Note

Mechanism of the variation in the input offset voltage due to Since we can consider that the transistor elements are
the power supply voltage (reference) connected in parallel to each other, it is possible to combine
Figure 3.8.1 shows the equivalent circuit for a differential the circuits for simplification. The power supply voltage gain is
input stage. Now we will explain the mechanism by which the calculated with this circuit. For the calculation of power supply
input offset voltage is increased by a variation in the power voltage gain, gm is the transconductance of transistors, rd is
supply voltage. First, we assume that the characteristics are the drain impedance, gd is the drain conductance, VICM is the
identical between transistors M1 and M2 as well as between input common-mode voltage, and V is the drain voltage of M5.
M3 and M4. This means that no input offset voltage is In addition, 1/rd = gd. Form Equation (3.8.8) for nodes VO and
generated by the differential input stage or the active loads. V.
Since the characteristics are identical, the voltages between Arranging Equation (3.8.8) and using approximations that
the gate and source are equal and the currents flowing V-Vps=Vds and gm4, gm2 >> gd4, gd2, Equation (3.8.9) is
through differential input transistors M1 and M2 are equal. obtained (the process is omitted).
However, when considering the power supply voltage Equation (3.8.9) shows that the power supply voltage gain
variation, the variation in the power supply also alters the (AP) is determined by the impedance of transistor M5 and gm
input common-mode voltage range. Therefore, the input of the active load. Next, the differential voltage gain can be
voltage level should always be adjusted to a value in the described by Equation (3.8.10). (The derivation is omitted.)
middle of the input common-mode voltage range. When the input offset voltage is VIO, PSRR is calculated from
Next, since the characteristics of active loads M3 and M4 are Equations (3.8.9) and (3.8.10), resulting in Equation (3.8.11).
identical, the currents flowing through the loads are equal. Thus, to obtain a smaller power supply voltage gain (Ap), rd5
The identical currents and characteristics result in identical or gm4 needs to be larger. A larger rd5 means that the current
drain voltages between active loads M3 and M4. Therefore, flowing through transistor M5 is less likely to be affected by
we can consider that Vx and Vo is virtually short-circuited in the input common-mode voltage. However, actual values of
small signal equivalent circuit 1 in Figure 3.8.1 (b). Based on rd5 and gm4 are finite and PSRR is therefore limited. In other
this point, the small signal equivalent circuit is described as words, since the PSRR is finite, the input offset voltage is
small signal equivalent circuit 2 in Figure 3.8.1 (c). varied due to the variation in the input common-mode voltage.

g d 5 (V  V ps )  2 g m1 (VICM  V )  2 g d 1 (V  VO )  0
(3.8.8)
2 g m 4VO  2 g d 4VO  2 g m1 (VICM  V )  2 g d 1 (V  VO )  0
VO g 1
AP   e5  (3.8.9)
V ds 2 g m 4 2 g m 4 r5
VO
Ad   g m1 ( rd 2 // rd 4 ) (3.8.10)
Vind
Ad Vds Vds
PSRR    2 g m 4 r5 g m1 (rd 2 // rd 4 ) (3.8.11)
AP Vind VIO

VPS Vps
M5
rd5 rd5 Vps
gmd1(VICM-V) gmd2(VICM-V)
V V V
M2 rd1 rd1 2gmd1(VICM-V)
M1 2rd1

Vo Vo
VICM
Vx
Vo rd3 rd4
gmd3Vo 2gmd4Vo 2rd4
M3 M4 gmd4Vo

VSS=GND

(a) Equivalent circuit for differential input circuit (b) Small signal equivalent circuit 1 (c) Small signal equivalent circuit 2

Figure 3.8.1. Equivalent circuit diagram for op-amp differential input stage

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 Application Note

As with the CMRR, the value of the PSRR is reduced as the Therefore, any ripple noise with a high frequency on the
input signal frequency increases. As shown in Equation power supply line will alter the output voltage significantly,
(3.8.11), the differential voltage gain of op-amps is closely causing output noise. As a countermeasure against power
related to the PSRR. The differential voltage gain of the supply noise, you can connect a bypass capacitor near the
op-amp is reduced at the rate of -6 dB/oct (= -20 dB/dec) as power supply terminal of op-amps. Figure 3.8.2 shows an
the frequency increases, due to the first pole of the differential example of the frequency characteristic of the power supply
input stage. This causes a simultaneous reduction in the rejection ratio.
PSRR.

120
110
100
90
80
70
PSRR[dB]

60
50
40
30
20
10
0 2
10
10 10
100 10 3
1000 10 4
10000 10 5
100000
Frequency
周波数[Hz][Hz]

Figure 3.8.2. PSRR frequency characteristic

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 Application Note

3.9 SR (Slew Rate)

The slew rate is a parameter that represents the operating

A
speed of op-amps. This parameter describes the rate of
Amplitude
振幅[V][V]
variation that the output voltage can undertake per specified y = Asinωt

unit time. For example, 1 [V/μs] means that the voltage can
Time [sec]
時間[sec]
be varied by 1 [V] in 1 [μs].
An ideal op-amp can exactly follow any input signal and
-A
output the output signal. However, the slew rate sets limits on Vpp = 2A

the output in practice. The slew rate describes how much the Figure 3.9.2 Waveform of a sine wave
output voltage can change per unit time when a rectangular
wave pulse with a steep rise and fall is input. Equation (3.9.1)
y  A sin t (3.9.2)
Since the slew rate is the slope of the tangent to the sine
shows the definition of slew rate.
wave, we differentiate Equation (3.9.2).
The slew rates for the rise and fall are calculated with
dy
Equation (3.9.1).  A cos t t  0 (3.9.3)
V V dt
SR r  SR f  (3.9.1)
Tr T f From Equation (3.9.3), the slew rate is described by

The slew rate specified in the data sheet is based on the rate SR  A   2f (3.9.4)
for either “rise” or “fall”, whichever is the slower. The slew rate In addition, since the amplitude of the sine wave is given by
represents the maximum slope of the op-amp output signal. Vpp = 2A (peak-to-peak), Equation (3.9.4) can be rearranged
When the signal has a steeper change, the output waveform as follows.
cannot follow the signal and will be distorted. Since the slew SR SR SR
f   [ Hz ] V pp  [V ] (3.9.5)
rate is the rate of output change, it is not affected when an 2  A V pp f
amplifier circuit is configured. This frequency f is referred to as the full power bandwidth.
Consider the meaning of the slew rate when an op-amp is These are the relations between the frequency and the
actually used. Op-amps are used for the amplification of both amplitude that an op-amp can output (within the output
DC and AC signals. As mentioned above, since op-amps voltage range) when no amplification factor is set for the
have a limit on their response speed, there are signals that op-amp—in other words, when the op-amp is operated as a
op-amps cannot handle. We explain a voltage follower voltage follower.
configuration shown in Figure 3.9.1. For a given DC voltage Example: Calculate the frequency at which an op-amp with
input, limits are set by the input and output voltage ranges. SR = 1 V/μs can output a signal of 1 Vpp.
For an AC signal with a frequency, additional limits are set by SR 1 1
f     318.4kHz (3.9.6)
the gain bandwidth product and the slew rate. Here, we V pp 10  6   1
consider the relation between the amplitude and frequency, When the frequency increases such that it is higher than the
namely the slew rate. frequency calculated with Equation (3.9.6) while the
We calculate the maximum frequency that an op-amp can amplitude is kept constant, the slew rate restricts the
output. To determine the maximum frequency, we calculate waveform, distorting the sine wave into a triangular wave.
the slew rate that is required to output a waveform as shown
in Figure 3.9.2.
VCC

90%
VOUT
Vin Output
Input ΔV
入力波形 t waveform
出力波形 t
waveform

VEE=GND 10%

ΔTr ΔTf
Figure 3.9.1. Example of slew rate measurement circuit and waveforms

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 Application Note

3.10 Frequency characteristics of op-amp

Term descriptions
• Gain frequency characteristic: where the -6 dB/oct attenuation occurs is referred to as the
The gain of an amplifier circuit has a frequency gain bandwidth product. This product represents the
characteristic. frequency bandwidth within which the op-amp can be used
This characteristic is determined by the phase for small signals.
compensation capacitance and terminal capacitance of the Gain bandwidth product [Hz] = Frequency [Hz] × Gain
inside of the op-amp, the parasitic capacitance of the circuit [times]
board, and the circuit constant.
• Phase frequency characteristic: •First pole:
This characteristic represents the difference in phase This is the first of several poles. The amplitude is
between the input and output waveforms of the op-amp. attenuated at the rate of -6 dB/oct per single pole. Phase
Similarly to the gain, it is affected by the characteristics, the delay begins to increase when the frequency reaches 1/10
circuit constant, and the parasitic capacitance of the of the first pole frequency. The delay increases by 45deg at
op-amp. the first pole frequency and by 90deg when the frequency
• Open loop gain (Av): reaches 10 times that of the first pole frequency.
The open loop gain represents the voltage gain for direct • Second pole:
current. This is the second of several poles. The attenuation rate
• Unity gain frequency (fT): increases to -12 dB/oct. In addition to the phase delay from
The frequency at which the gain is 0 dB (1times) is referred the first pole, the phase delay further increases by 45deg at
to as the unity gain frequency. the second pole frequency and by 90deg when the
• Gain bandwidth product (GBW): frequency reaches 10 times that of the second pole
The frequency characteristic of an amplifier circuit shows frequency.
an attenuation at the rate of -6 dB/oct per pole. The product Note: -6 dB/oct = attenuation by -6 dB when the frequency
of the gain and frequency at an arbitrary point in the range is doubled. (oct = octave)

180 180

Open loop gain

135 First pole 135

90 90
Gain frequency Unity gain frequency
characteristic VDD
45 45 +IN
OUT
位相[deg]
[deg]
利得[dB]
[dB]

0 0 Vin
-IN
Phase
Gain

VSS
-45 Second pole -45 Vref

Phase frequency
-90 characteristic -90 Figure 3.10.2. Measurement circuit
Gain bandwidth product θ (schematic diagram)
-135 Product of the frequency and gain in the -135
range where the gain is attenuated at
the rate of -6 dB/oct
-180 -180
10
-1
1.E-01 1.E+00
1 1.E+01
10 10
2
1.E+02 10
3
1.E+03 4
1.E+04
10
5
1.E+05
10
6
1.E+06
10
7
1.E+07
10 10 8
1.E+08

Frequency
周波数[Hz] [Hz]

Figure 3.10.1. Example of open loop frequency characteristics of op-amp

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 Application Note

• Phase margin:
180 180
The difference in phase between the input and output
160 160

signals at the frequency where the gain is 0 dB (1times) is 140 140

120 Phase characteristic of 120
referred to as the phase margin. The phase margin is an 100 non-inverting amplifier circuit 100
Gain margin
80 80
indicator of the margin level and is designed to have a 60 Phase margin: θ1 60
40 40
value between 40deg and 60deg.

[deg]
θ1

[dB]

位相[deg]
20 20

利得[dB]
In an inverting amplifier circuit, the difference in phase 0 0

Phase
Gain
-20 -20
between the input and output θ1 is the gain margin. The -40 -40
-60 θ2 -60
phase of an inverting amplifier circuit begins at 180deg. -80 Phase characteristic of Phase margin: -80
-100 inverting amplifier circuit 180deg + θ2 -100
Since the phase of a non-inverting amplifier circuit begins
-120 -120

at 0deg, the gain margin is the margin level from 180deg, -140 -140
-160 -160
namely 180deg + θ2 -180
2 3 4 5 6 7 8
-180
10
1.E+02 10
1.E+03 10
1.E+04 10
1.E+05 10
1.E+06 10
1.E+07 10
1.E+08 109
1.E+09

Phase margin of inverting amplifier circuit: θ1 Frequency

周波数[Hz]
[Hz]

Phase margin of non-inverting amplifier circuit: 180deg Figure 3.10.3. Example of frequency characteristics of inverting
+ θ2 (non-inverting) amplifier circuit 40 dB* (100 times)
• Gain margin:
The gain margin is the margin level for the gain to 0 dB at * The open loop gain of an op-amp is very large near a
the frequency where the phase delay reaches 180deg. direct current (100 dB or larger). Applying a DC
Typically, the gain margin is designed to be 7 dB or larger. feedback from the output with a resistor stabilizes the
The gain margin is used as an indicator of the margin level output DC voltage.
similarly to the phase margin. When measuring the gain frequency characteristics, the
gain of the inverting or non-inverting amplifier circuit is
set to about 40 dB in order to perform the measurement
stably. Since the characteristics at frequencies higher
than the first pole frequency range are equivalent, the
phase and gain margins can be read from this graph.

R2 R2

VDD VDD

R1 -IN R1 -IN
OUT OUT
Vref
Vin
+IN Vout V +IN Vout V
Vref
Vin
VSS VSS
Vref

Figure 3.10.4. Inverting amplifier circuit Figure 3.10.5. Non-inverting amplifier circuit

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 Application Note

3.11 Phase delay and oscillation

This section describes one of the most general concepts for We focus on the denominator of the transfer function, 1 +
oscillations caused by Phase delay, the Barkhausen stability βA(s).
criterion. When β•A(s) = -1, the denominator is zero and the gain
The transfer function of a negative feedback circuit is becomes infinity. This means that the transfer function
determined in Figure 6. diverges when β•A(s) = -1.
In other words, β•A(s) = -1 implies that the signal returned via
A( s )(Vin  Vin  )  Vout a negative feedback is inverted (phase delay of 180deg),
Vin    Vout equivalent to the condition when a positive feedback is
applied. Therefore, the circuit becomes unstable, causing an
From the two equations above, the transfer function is oscillation.
determined as follows.
Vout A( s ) The following are a summary of oscillation conditions when

Vin 1   A( s ) the loop gain is 1times. (The loop gain of 1times represents
an unity feedback.)

β | βA(s) | ＝ 1
βA(s)  -180deg
VDD

Vin-
Here ∠βA(s) is the phase delay. When s = jω1 and the loop
A(s)
A(S) gain βA(ω1) = 1, a phase delay of 180deg causes an
Vout oscillation with the angular frequency of ω1.
Vin
Vin
A(s): transfer function of op-amp
VSS
s = jω, ω = 2πf, •There are two indicators of stability: the phase and
f: frequency, β: loop gain gain margins. The phase margin indicates how
much margin remains from the phase delay of
Figure 3.11.1. Negative feedback circuit
180deg when the gain is unity (0 dB). The gain
margin indicates how much the gain is attenuated
• When the phase is delayed by 180deg, the from unity when the phase delay is 180deg (phase
condition becomes identical to the state margin of 0deg).
when a positive feedback is applied,
causing an oscillation.

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 Application Note

The phase delay is caused by the presence of the poles. We

explain the reasoning using the frequency characteristics of Vin R Vout
an RC filter as an example.

C
Consider the transfer function of an RC filter as shown in
Figure 3.11.2. Figure 3.11.3. shows that a pole is caused by
capacitance in the transfer function (the first characteristic).
This pole produces a phase delay of 45deg at the pole Figure 3.11.2. RC filter circuit

frequency fc, and a phase delay of about 90deg when the

frequency is about 10times that of the pole frequency.

• One pole produces a phase delay of 90deg.

• The pole frequency depends on the capacitance value.
• Even with a high pole frequency, the phase begins to
delay when the frequency reaches 1/10 of the pole
frequency.

Transfer function of RC filter

Cutoff frequency fc = 1,592 Hz
Phase delay 45deg Vout ( j ) 1

Vin ( j ) 1  jRC
Signal amplitude
Phase [deg]

Attenuation at 6 dB/oct per pole 1

Gain [dB]

H ( ) 
1  (RC ) 2
Phase delay begins around Phase
a frequency of 1/10 of fc

   ArcTanRC 

From the transfer function of the

RC filter, the pole and cutoff
Frequency [Hz] Phase delay of 90deg around a
frequencies are described as
frequency 10 times higher than fc.
follows.
1 1
Figure 3.11.3. Frequency characteristics of RC filter 0  fc 
R = 1kΩ, 0.1 µF, fc = 1,592 Hz RC 2RC

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 Application Note

3.12 Cause of phase delay in op-amp

We consider the causes of phase delay in op-amps, including

the load capacitance.

From the transfer function of the circuit in Figure 9, we explain VCC

the cause of phase delay for an unity feedback circuit (voltage
IC inside
follower), which is most susceptible to oscillations.
ro Vo1 rd Vout
A( s )(Vin  Vo1 )  Vo Cp A(s) + Vo
-

1 Cp Load
Vin Cp capacitance CL
sC p 1
Vo1   Vo
1 1  r C s
ro  o p VEE
sC p
Figure 3.12.1. Unity feedback circuit

From the equations above, the transfer function is described A(s): transfer function of op-amp, s = jω, ω = 2πf

as follows when the output impedance (ro) and the terminal f: frequency, ro: output impedance,

capacitance are taken into account (Cp represents the total of Cp: parasitic capacitance of terminal, CL: load capacitance

parasitic capacitances).

• Pole caused by the output impedance and the

Vo1 A( s) 1 parasitic capacitance of the terminals
 
Vin 1  roC p s  A( s ) 1  C p ro s • Pole caused by the output impedance and the
1
A( s) load capacitance
(intentionally provided)
A pole is formed by Cp and ro.
• Pole caused by the feedback resistor and the
This effect is considered in the op-amp design. parasitic capacitance of the input terminal when
an amplifier circuit is configured
In the equation above, assuming Cp = Cp + CL gives the
transfer function when the load capacitance is connected.

Vo1 A( s) 1
 
Vin 1  ro (C p  C L ) s  A( s) 1  (C p  C L )ro s
1
A( s)
A pole is formed by Cp + CL and ro.
Cp varies little since it is the parasitic capacitance inside the
IC. However, the frequency where the pole occurs is reduced
if the load capacitance CL is large.

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 Application Note

3.13 Stability confirmation method (amplifier

circuit)
As an actual example, we show the variations in the phase
and frequency characteristics according to the value of the
load capacitance CL for the BA2904.
60 180 60 180
位相 160
50 Phase 位相
Phase 160
140 50
140
40 120 40 120
利得
Gain 100 利得
Gain 100
30 30
80 80
20 60 20 60
Phase margin 40 Phase margin 40

位相[deg]
位相[deg]

[deg]
[deg]
10 10

[dB]
[dB]
利得[dB]

20

利得[dB]
20
0 0 0 0

Gain

Phase
Phase
Gain

Gain margin -20 -20

-10 -10
-40 -40
Gain margin
-20 -60 -20 -60
-80 -80
-30 -30
-100 -100
-40 -120 -40 -120
-140 -140
-50 -50
-160 -160
-60 -180 -60 -180
10 2
1.E+02 10 3
1.E+03 10 4
1.E+04 10 5
1.E+05 10 6
1.E+06 10 7
1.E+07 10 2
1.E+02 3
1.E+03
10
4
1.E+04
10 10 5
1.E+05 10 6
1.E+06 7
1.E+07
10
Frequency
周波数[Hz] [Hz] Frequency
周波数[Hz][Hz]

Figure 3.13.1. Frequency characteristics of Figure 3.13.2. Frequency characteristics of

BA2904 (CL = 25 pF) BA2904 (CL = 0.01 µF)

• When CL = 25 pF • When CL = 0.01 µF

Phase margin: 55deg → the phase when the gain is 0 dB Phase margin: 7deg → the phase when the gain is 0 dB
Gain margin: -10 dB → the gain when the phase is 0deg Gain margin: -5 dB → the gain when the phase is 0deg
Although the phase margin is small, no oscillation occurs.

100kΩ

VDD

1kΩ -IN
OUT

Vin
+IN Load
負荷容量C
負荷容量CL L V Vout
Vref capacitance CL

VSS

Figure 3.13.3. Inverting amplifier circuit of 40 dB (100 times)

• The oscillation stability of op-amps is confirmed with the phase and gain margins.
• In an inverting amplifier circuit, the phase margin is the phase when the gain is 0 dB since the phase
begins from 180deg.
• In a non-inverting amplifier circuit, the phase margin is the difference between 180deg and the phase
value when the gain is 0 dB since the phase begins from 0deg.
• Considering factors such as variations or temperature change, the phase margin is designed to be
35deg or larger, and the gain margin -7 dB or smaller.

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 Application Note

3.14 Stability confirmation method (unity feedback

circuit/voltage follower)
1 1
We review the idea of phase margin. exp( j )
(cos   j sin  )
Vout  
( j )  
Vin 1 1
 exp( j )  cos   j sin 
VCC  
Vout Figure 3.14.3. shows the result of the calculation when the
A(jω)
following values are substituted in the above equations.
Vin θ(ω1) = -175deg (5deg), θ(ω2) = -135deg (45deg), θ(ω3) =
-120deg (60deg), β=1.
VEE

As the result shows in Figure 3.14.3, the phase margin of

Figure 3.14.1. Overall feedback circuit
60deg corresponds to a peak of 0 dB, giving an ideal
condition

40

35 The standard value of a phase

0dB 30 margin is between 60deg and 45deg
Frequency [Hz] 25 for an op-amp without CL, and about
20 35deg for an op-amp with a load
Peak [dB]

15 capacitance.
10
Figure 3.14.2. Measurement result
5

0
• The phase margin indicates how much margin -5
remains from the phase delay of 180deg when
-10
the gain is unity (0 dB). 0 20 40 60 80 100 120 140 160 180
Phase margin [deg]
• The gain margin indicates how much the gain is
attenuated from unity when the phase delay is Figure 3.14.3. Result of gain peak calculation
180deg (phase margin of 0deg).
Phase margin Result of
calculation [times] Peak [dB]

5deg 11.5 21
45deg 1.3 2
The methods that we have explained so far cannot confirm 60deg 1 0
the phase margin in an unity feedback circuit (gain of 0 dB).
When the circuit becomes less stable, a peak gain appears in
• By measuring the frequency characteristics of a voltage
the frequency characteristic as shown in Figure 14. The
follower, the phase margin can be calculated from the
phase margin is calculated from the size of the produced
gain peak.
peak using the transfer function.
• This method is applicable to any types of general
Transfer function of a voltage follower (unity feedback circuit)
op-amps.
Vout A( j ) • When the phase margin is small, the occurrence of
( j ) 
Vin 1   A( j ) oscillation is actually confirmed using an oscilloscope or
other instruments.
A(jω) is expressed in complex form and substituted in the
transfer function.

A( j )  exp( j )

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 Application Note

3.15 Summary of stability confirmation method

When an amplifier circuit is configured When an unity feedback circuit (voltage follower) is

• Oscillation in an amplifier circuit is confirmed by measuring configured

the phase frequency characteristic and checking the phase • By measuring the frequency characteristics between the
and gain margins. input and output and checking the gain peak, the phase

• In an inverting amplifier circuit, the reading of the phase margin can be estimated from Figure 15 of this document.

margin is the phase when the gain is 0 dB since the phase • Figure 15 is applicable to any types of general op-amps.
begins from 180deg. • When the phase margin is small, the occurrence of
• In a non-inverting amplifier circuit, the phase margin is the oscillation should actually be confirmed.
difference between the phase when the gain is 0 dB and • Considering factors such as variations or temperature
180deg since the phase begins from 0deg. change, the phase margin is designed to be 35deg or
• Considering factors such as variations or temperature larger as a standard.
change, the phase margin is designed to be 35deg or Since the confirmation of oscillation with the calculations
larger as a standard, and the gain margin -7 dB or smaller. above is complicated, it is generally confirmed by experiment.
(Generally, the phase margin is designed to be between
60deg and 40deg for an op-amp alone.)

3.16 Countermeasures against oscillation by load

capacitance (output isolation resistor 1)

Basically, it is possible to prevent oscillation by satisfying the Vout A( s ) 1

conditions to avoid oscillation as described in the previous 
Vin (1  ro C p s  A( s)) (1  rd C L s)
sections. In this section, however, we explain
While the transfer function without the isolation resistance
countermeasures against oscillation when a capacitor with a
calculated in Figure 3.12.1 is
large capacitance is connected to the output terminal. Vo1 A( s)

Vin 1  ro (C p  C L ) s  A( s)
We calculate the transfer function in Figure 3.16.1.
When these two transfer functions are compared, it can be
seen that the capacitance CL that is connected to the output
A( s )(Vin  Vo1 )  Vo is separated into another transfer function with the dividing
1 resistance rd.
sC p 1 VCC
Vo1   Vo
1 1  ro C p s IC inside
ro 
sC p ro rd
Vo1 Vout
A(s)
A(s) + Vo
Cp -
Vo1 A( s) 1
  Cp
Vin 1  roC p s  A( s ) 1  C p ro s Vin Cp
Load
1 capacitance CL
A( s)
VEE
Vout 1
 Figure 3.16.1. Example of output isolation resistor connection 1
Vo1 1  rd C L s
• The value of the isolation resistor is set to between
Vo1 Vout A( s) 1 50Ω to several hundred ohms, according to the

Vin Vol 1  ro C p s  A( s) (1  rd C L s) capacitance and the required frequency bandwidth.
• Since a low pass filter is configured with rd and CL,
the circuit bandwidth is reduced if the load
capacitance is large.

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 Application Note

3.17 Countermeasures against oscillation by load

capacitance (output isolation resistor 2)

When using the method to insert an output isolation resistor Vout 1


as described in the previous section, the configuration of a
Vin C L  C p ( sC L  1)
low pass filter may be disadvantageous in some applications. A( s )  ro s 1
sC L Rd  1
The peak gain is reduced by inserting a resistor in series to
the capacitance. While the transfer function without the isolation resistance

We calculate the transfer function in Figure 3.17.1. calculated in Figure 3.12.1. is

A( s)(Vin  Vout )  Vo Vo1 A( s)


Vin 1  ro (C p  C L ) s  A( s)
Vo  A( s)Vin  A( s)Vout
Z This part of the transfer functions is different.
Vout  Vo
ro  Z We analyze the frequency characteristic of the underlined
part in equation A. Suppose that s = jω = j2πf.

ro C L  C p ( sC L  1)
(1  )Vout  A( s)Vin  A( s)Vout X
Z sC L Rd  1
r
( A( s)  1  o )Vout  A( s )Vin When f → 0: s → 0 and X → CL + Cp
Z
When f → ∞: s → ∞, sCLRd >> 1, CL << Cp (sCL + 1),
and sCL >> 1. Therefore, X is converged to Cp/Rd.
Vout A( s)
 This result shows that the effect of the load capacitance CL is
Vin 1
A( s)  ro  1 removed.
Z
Vout 1
 • The value of the isolation resistor is set to between 50Ω
Vin 1
1  sC p ( Rd  ) to several hundred ohms, according to the capacitance
sC L
A( s )  ro  1 and the required frequency bandwidth.
1
Rd 
sC L

1
IC inside Z
1
sC p 
Z 1
Rd 
Vo Vout sCL
A(s)
1
Cp Rd Rd 
sCL
Z
Load 1
capacitance CL 1  sC p ( Rd  )
sCL

Figure 3.17.1. Example of output dividing resistor connection 2

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 Application Note

3.18 THD+N (Total Harmonic Distortion + Noise)

The value of THD+N (total harmonic distortion + noise) These components are mixed in the output signal of an
describes the percentage of the harmonic and noise op-amp, distorting the waveform.
components included in the output signal. We explain effects of the amplification factor and noise when
When the harmonic component or noise is included, the an amplifier circuit is configured with an op-amp. An amplifier
waveform of the output signal is not an exact reproduction of circuit amplifies not only the input signal but also the noise
that of the input signal. In other words, the waveform of the component. When you configure a circuit with a larger
output signal is distorted. amplification factor to amplify the signal and the same
THD+N = (Sum of harmonic and noise components)/(Output magnitude of the output amplitude is obtained, the noise
voltage) voltage is amplified by the gain and the distortion rate of the
The harmonic component arises from the non-linearity of output signal becomes larger as the circuit gain increases
op-amp circuits. For example, bipolar transistors have static (Figure 3.18.1).
current-voltage characteristics described by an exponential When the amplification factor is constant, a smaller output
function. Therefore, the amplification factor is a non-linear amplitude results in a larger percentage of the noise voltage,
function for the input voltage, causing the harmonic exacerbating the distortion rate.
component. As we mentioned in the section for the slew rate, the
We explain details of the noise in section 3.13 Input Referred amplitude that can be output becomes smaller as the signal
Noise. Noise also arises from semiconductor elements inside frequency increases. Therefore, the slew rate limits the
the IC or from peripheral parts such as resistors. waveform and increases the distortion rate.
VCC
VCC

Vout
Vout

Vin 1kHz
Vin 1kHz VEE=GND
VEE=GND
R1 R2

Fundamental
基本波 wave Fundamental
基本波 wave
1kHz 1kHz
Output voltage

出力電圧 voltage
出力電圧

Output

Second
2次高調波 order harmonics Second
2次高調波order harmonics

Third
3次高調波 order harmonics Third
3次高調波order harmonics

Frequency
周波数(None(None Scaled)
Scaled) Frequency
周波数(None(None Scaled)
Scaled)

(a) Noise frequency spectrum of voltage follower (b) Noise frequency spectrum of amplifier circuit
Figure 3.18.1. Noise frequency spectrum of THD+N
Next, Figure 3.18.2 shows examples of THD+N vs. the output voltage
characteristics.
10 1
[%][%]

Total Harmonic Distortion [%]

1
Total Harmonic Distortion [%]
Distortion

20dB 0.1
Harmonic Distortion

40dB 20Hz
0.1
1kHz
0.01
TotalHarmonic

0.01
20kHz
0.001
Total

0dB
0.001

0.0001 0.0001
0.01 0.1 1 10 0.01 0.1 1 10
Output Voltage[Vrms]
Output Voltage [Vrms] Output
OutputVoltage [Vrms]
Voltage [Vrms]

(a) THD+N when the gain is varied (b) THD+N when the frequency is varied

Figure 3.18.2. Examples of THD+N vs. output voltage characteristics

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 Application Note

Next, we explain a cause of distortion in the output waveform

of op-amps.
Input crossover distortion
Input full swing op-amps, especially op-amps equipped with Output
出力電圧 voltage

two types (PMOS/NMOS or PNP/NPN) of differential input

stage, have independent input offset voltages in the operating
region of each differential input stage. Therefore, the input
t:t:時間
Time
offset voltage varies within the input common-mode voltage
range as shown in the figure. When the input signal passes
over the step (crossover), a distortion is generated in the
output signal. Figure 3.18.4. Output crossover distortion

Input同相入力範囲
common-mode range Class A output circuit
入力オフセット電圧
Input offset voltage

A Class A output stage is an output stage through which a

Offset voltage varies within
the input common-mode
同相入力範囲内で drive current flows at all times from a constant current source.
rangeオフセット電圧が変化する
One advantage of a constant current is that no crossover
distortion is generated, since Q1 is always in the operating
0 Input 同相入力電圧
common-mode range
region. However, since the drive current keeps flowing even
when there is no signal, power consumption increases. Since
Figure 3.18.3. Offset voltage variation in input the output is driven by a constant current source, the capacity
common mode range of the constant current source limits the source current, which
Output crossover distortion and output circuit of op-amp flows from the amplifier, and a heavy load cannot be driven.
Output crossover distortion is generated as a result of the (A heavy load distorts the waveform.)
op-amp’s output circuit configuration. It is also referred to as
switching distortion. As we described in section 3.11 for the VCC

negative feedback system effect, you can restrain distortion

generated in the output with a negative feedback effect. The
Vo
distortion is restrained by the feedback amount when the
Vin
open loop gain, A(s), of the op-amp is large at lower Q1
RL
frequencies, as shown in Equation (3.11.5). As A(s) is
Vsat2

decreased at higher frequencies, the restraining effect Vbe1

diminishes and the distortion gradually increases. However, GND

as described in the next section for Class C operation, the
output stage of 358/2904 series op-amps switches between
Figure 3.18.5. Class A output circuit
Classes A and C operations according to the amount of the
output sink current. Therefore, such distortions cannot be
restrained by feedback.
The following sections explain how crossover distortion is
generated as well as Classes A, B, C, and AB push-pull
circuits for the types of op-amp output stages. Figure 3.18.4
shows an image of crossover distortion.

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 Application Note

Class B push-pull output circuit

In Figure 3.18.6 (a) for Class B push-pull circuit, the vertical When the inflow current exceeds 40 [μA], transistor Q2 starts
and horizontal axes are the output and input voltages, to operate and the operation of the output stage transitions to
respectively. Since the operating regions for Q1 and Q2 are Class C, causing discontinuous operation of the transistor.
discontinuous, a distortion is generated in the output This discontinuity contributes to crossover distortion. To
waveform. An output stage that has a discontinuous output reduce this distortion, you can decrease the amount of
characteristic with a gap of two Vbe is called a Class B output current flowing into the op-amp’s output to the value of the
stage. It features low current consumption, since no idling current from the constant current source or below. It should
current flows in the output stage. also be noted that the feedback resistance serves as a load in
addition to the load resistance that is connected with the
Class C push-pull output circuit output.
The Class C push-pull circuit shown in Figure 3.18.6 (b) is
used for general single power supply op-amps, including Class AB push-pull output circuit
2904 and 358. When operating an op-amp with a single The Class AB push-pull circuit shown in Figure 3.18.6 (c) is
power supply, a bias voltage is applied to set the DC used for dual power supply low-noise op-amps, including
operating point of the circuit. In addition, when a load 4558/4560. Class AB push-pull circuits are output stages that
resistance is connected with the output of the op-amp—and are modified so that a drive current flows in the output stage.
especially if the voltage with which the load is connected is The bias voltage is set so that transistors Q1 and Q2 are
close to the bias voltage—no current flows into the output always ON by connecting two diode-connected transistors
stage of the amplifier, since there is no potential difference with a Class B push-pull circuit. Since the NPN and PNP
between both ends of resistance RL. When the output voltage transistors on the output stage are always operated by the
amplitude of the op-amp is varied from this condition, a drive current, switching operations are performed smoothly
potential difference between both ends of the resistance and crossover distortion is less likely to be generated.
arises and a current flow into the amplifier. When this inflow However, when a heavy load is connected—one that the
current is 40 [μA] (value of the current from the constant current capacity of the output stage cannot drive—distortion
current source) or less, the output stage operates as Class A. may be generated even in a Class AB output stage.
VCC ダイオード接続トランジスタ
VCC Biased by the forward VCC
の順方向電圧
voltage of diode-connected
によりバイアスされ
transistors,出力段には
a current keeps
Q3 Q1
Q1 flowing in the output stage
電流が流れ続ける
Vsat1 Vsat1
Q1 Constant
Vsat1 current source
Vbe1 Vbe1
Vbe3 Vbe1 40μA
Vo Vbe
Vo Vo
Vbe2 Vbe2 Vbe2
Vin Vin Vin
Vbe
RL 定電流源 RL RL
Vsat2 Q2
Vsat2 40μ A Q2
Vsat2
Q2 Intermediate Intermediate
中間電位 Intermediate
中間電位 中間電位
potential potential
(VCC-VEE)/2 potential
(VCC-VEE)/2
(VCC-VEE)/2
(VCC-VEE)/2 (VCC-VEE)/2 (VCC-VEE)/2
GND GND
GND
Output range Vo
出力範囲 VCC+Vbe1 +Vbe3 -Vsat1
Output range Vo
出力範囲 VCC+Vbe1 -Vsat1 Vo VCC+Vbe1 -Vsat1 -2Vbe

VCC-Vsat1 VCC-Vsat1 VCC-Vsat1

Q2の動作領域
Operating region of Q2
-Vbe2 入力範囲 Operating region of Q2 -Vbe2
Q2の動作領域 入力範囲 Operating region of Q2 -Vbe2 Q1の動作領域
0 Vin 0 Vin Vin
Vbe1 Vbe1 +Vbe3 Q2の動作領域 0
Q1の動作領域
Operating region of Q1 Operating region of Q1
Operating
Q1の動作領域 region of Q1
電流が増加し
Biased by the forward Operating with a constant
Q2がONすると 40μAの定電流により
voltage of diode-connected
動作領域が遷移し current of 40 μA. (358/2904)
動作をしている。(358/2904)
transistors,不感帯が生じる
a current keeps このときQ2はOFFしている。
Q2 is turned OFF.
flowing in the output stage GND+Vsat2
GND+Vsat2 GND+Vsat2

GND-Vbe2 +Vsat2 GND-Vbe2 +Vsat2 GND-Vbe2 +Vsat2

(a) Class B push-pull circuit (b) Class C push-pull circuit (c) Class AB push-pull circuit

Figure 3.18.6. Op-amp output equivalent circuit

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 Application Note

Output distortion with a heavy load

Connecting a load resistance or load capacitance with the The initial current that flows into the capacitor is given by
output terminal of an op-amp may cause distortion, Equation (3.18.1).
depending on the values of these variables. Here, we explain
V 1
distortion generated when an RC filter is connected with the I (t )  exp( t) (3.18.1)
R CR
output. When a charge/discharge current to the capacitance
exceeds the source and sink current capacities of the op-amp, The above equation shows that the initial charge current is
distortion is generated. Figure 3.18.7 shows an RC filter determined only by the resistance and current. Therefore, it is
circuit. possible to check whether the maximum value of the charge
current will exceed the output current capacity of the op-amp.
VR(t)
The effect on the output voltage when an excessive current
flows is also explained in section 3.5 for the maximum output
R voltage.
I(t)
V For example, consider the output current for 2904. When you
CL VC(t)
configure a filter with R = 100Ω, a current of 50 mA is required
for outputting an amplitude of 5 Vpp. Since this current value
Figure 3.18.7. RC filter exceeds the standard current capacity of 20 mA for 2904, it is
expected that the output voltage range will be reduced and a
Based on Figure 3.18.7, we calculate the initial value distortion will be generated in the waveform. When R = 10kΩ,
(maximum value) of the current that is charged in the the current value is 0.5 mA, which causes no distortion in the
capacitor. We assume that the capacitor has no electric waveform. Discharge current can be viewed similarly. Figure
charge initially. 3.18.8 shows the relation between the output current and
distortion. Figure 3.18.9 shows an example of waveform
distortion.

VCC
Output
出力電圧 voltage Vo
ソース電流 Load RL is light
負荷RL軽い
Source current

Sink
シンク電流current Load RL is heavy
負荷RL重い
R Vo
A Vo Output range is reduced as
出力電流が大きくなると
output current increases
出力範囲が狭くなる
Vin R1
VEE=GND CL t: Time t: Time
t:時間 t:時間

R2

Figure 3.18.8. Relation between output current and distortion

Figure 3.18.9. Example of waveform distortion for BA2904

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 Application Note

3.19 Input referred noise

Thermal noise
There are two types of noise: external and internal noise.
This noise arises from a random thermal motion of free
Input referred noise in an op-amp—for example, thermal
electrons. Free electrons in a conductor move around
noise, 1/f noise, shot noise, and partition noise—is generated
randomly due to Brownian motion. This motion produces a
inside the electronic circuit and observed as noise at the
tiny fluctuation in voltage, resulting in thermal noise. Thermal
op-amp’s output stage. Output noise that is referred to input
noise is distributed over a wide range of frequencies; it is also
noise is termed input referred noise. Typically, the input
referred to as “white noise”. The amount of this noise
referred noise voltage is described in a unit such as VRMS,
depends not on the amount of current flowing through a
representing the magnitude of noise in the specified
conductor, but on variations in temperature.
frequency bandwidth. The input referred noise voltage density
Thermal noise VnT generated with resistance R [Ω] is
is described in the unit of nV/√Hz, representing the noise
described by the following equation.
voltage density per frequency. The product of the noise
When k is the Boltzmann constant (1.38 × 10-23 [J/K]), T is the
density multiplied by the noise bandwidth is the noise voltage.
absolute temperature [K], and Δf is the bandwidth to estimate
Op-amps are used in various circuit configurations with
the noise [Hz],
various amplification factors. Therefore, it is convenient to
express the noise voltage as an input referred value in the VnT2  4kTRf (3.19.1)
same way as the input offset voltage.

Type of noise
Noise arises from the random motion of electrons, which is
discontinuous in time. Primary noise generated from resistors
and semiconductor elements includes thermal noise, shot
noise, and 1/f noise (flicker noise). Primary mechanisms of
noise generation are as follows:

External noise
外来ノイズ power
Commercial
商用電源
supply
Electromagnetic
電子機器からの電磁波 waves Input referred noise voltage
from electronic devices 入力換算雑音電圧

in+ Vn VCC

Signal source OUT

resistance: Rs
信号源抵抗：Rs A

Signal 信号源：Vs
source: Vs

in- VEE

R1 R2
Input referred noise current
入力換算雑音電流

Figure 3.19.1. Op-amp noise

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 Application Note

Shot noise
When a current flow inside a semiconductor, each carrier This current is referred to as flicker noise. Since it is more
(electron or hole) passes through a depletion layer (PN frequently generated as the frequency decreases, it is also
junction) while moving randomly, causing a fluctuation in the referred to as 1/f noise in the sense that the noise is inversely
current like waves on a river surface. The magnitude of the proportional to the frequency. In principle, this noise is said to
generated noise depends on the average current value arise from the presence of uncombined bonds referred to as
flowing through the junction. It is also related to the traveling dangling bonds on the interface between SiO2 and silicon
time of the carriers and is nearly constant in regions where crystals. Since atomic bonds with which silicon molecules
the traveling time can be ignored. (It cannot be ignored at form covalent bonds are discontinuous at the SiO2 interface,
higher frequencies.) trapping and releasing occur as the carriers travel on the
This noise is distributed over a wide range of frequencies silicon interface. As a result, a fluctuation occurs in the current,
(white noise). When ID is the current flowing through the generating noise.
junction, q is the elementary charge (1.6 × 10-19 [C]), and Δf is When Kf is a constant determined by the manufacturing
the bandwidth for estimating noise [Hz], ins (noise current of process, I is the DC current, f is the frequency, and Δf is the
the generated shot noise) is described by Equation (3.19.2). bandwidth for estimating noise [Hz],

I
2
inS  2qI D f (3.19.2) inf2  K f f (3.19.3)
f
1/f noise (flicker noise) There are other types of noise generated in semiconductors.
When carriers are trapped by and released from uncombined For example, partition noise is generated when a current is
bonds that are generated on a semiconductor interface, a split into different routes. Burst noise (popcorn noise) occurs
current occurs that is different from the normal carrier travel. in a low frequency region near the audio bandwidth.

1/f region
1/f領域 白色雑音領域 分配雑音領域
Partition noise region
voltage/current density

White noise region

雑音電圧/電流密度

Flicker noise
フリッカノイズ
分配雑音
Partition noise
fc
Corner frequency
コーナー周波数 Thermal
熱雑音noise
ショット雑音
Shot noise
Noise

Frequency (None Scaled)

周波数(None Scaled)

Figure 3.19.2. Image of frequency spectrum for input referred noise voltage

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 Application Note

As mentioned above, various types of noise are generated in There is no correlation between the noise currents in the
op-amps and appear as a noise in the output. Using a inverting terminal (i-) and non-inverting terminal (i+). Each
non-inverting amplifier circuit shown in Figure 3.19.3, we noise current is generated at random. Therefore, they will not
consider how the input referred noise of an op-amp affects an cancel each other out.
application circuit.
Thermal noise from external resistor and signal source
Input referred noise voltage/noise voltage density of op-amps resistance
When the input circuit is short-circuited, noise generated External resistors and signal source can be sources of
inside an op-amp (primarily the differential amplification thermal noise. Thermal noise voltage is described as a noise
stage) is amplified and appears as noise in the output. voltage source connected in series to each resistance source.
Dividing this output noise by the amplification factor of the
circuit provides the input referred noise voltage (Vn). Since it The input referred noise voltage density is calculated based
appears as if noise is input to the amplifier and amplified, it is on these considerations. The thermal noise voltage density
termed input referred. However, the noise is actually for the resistance is calculated by Equation (3.19.1). The
generated inside the op-amp and no noise voltage is noise voltage generated at each resistance source is
generated on the input terminal, as shown in Figure 3.19.3. calculated. The input referred noise current is converted into
noise voltage at the external resistors. Since the noise is
Input referred noise current/noise current density of op-amps handled as power, its mean square is provided. In addition, it
As mentioned above, the input referred noise current arises is assumed in Figure 3.19.3 that in+ = in- = in. Since the noise
from a fluctuation in the transistor current or from noise is generated at random, each term has no polarity. When Vn
caused by a split in the current. is the input referred noise voltage density of the op-amp and
This current is actually output from the input terminal to the “in” is the input referred noise current density of the op-amp,
outside. It is converted into voltage by external resistors or by the input referred noise voltage density is described by
signal source resistance, and it acts as a part of the input Equation (3.19.4). This equation corresponds to a situation
referred noise voltage. Its effect depends on factors in the where all sources of noise are combined together and
external environment such as the circuit constant and circuit connected with a non-inverting input terminal, as shown in
configuration. In Figure 3.19.3, a noise current is converted Figure 3.19.4.
into a noise voltage by R1, R2, and Rs.
 
Vna2  Vn2  RS2  ( R1 // R2 ) 2 i n2  4kT RS  ( R1 // R2 )
(3.19.4)

VCC VCC

in+
Vn Vna

Op-amp
雑音の無い
VOUT Op-amp VOUT
Signal source resistance:
信号源抵抗：Rs Rs 雑音の無い
in- in+ without
オペアンプ without
オペアンプ
noise noise
Signal source: Vs
信号源：Vs Signal source:
信号源：Vs Vs
in-

VEE VEE

R1 R2 R1 R2

Figure 3.19.3. Equivalent circuit for non-inverting Figure 3.19.4. Equivalent circuit for non-inverting
amplifier circuit noise amplifier circuit noise
(Noise sources are combined together into IN+)

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 Application Note

Next, we determine the output noise voltage of a The noise gain is the gain from the location of the noise
non-inverting amplifier circuit. source to the output. If you divide each term in Equation
Equation (3.19.5) shows the output noise voltage due to (3.19.7) by the square of the noise gain, it is equivalent to
resistance. Equation (3.19.4) determined above for the input referred
Equation (3.19.6) shows the output noise voltage due to the noise voltage.
input referred noise voltage of an op-amp. As a measure to reduce noise in application circuits, you can
Equation (3.19.7) shows the output noise voltage caused by use metal film resistors that do not generate flicker noise,
the input referred noise current of an op-amp. avoid increasing the circuit constant (resistance value)
Suppose that the noise gain of a non-inverting amplifier circuit excessively, or use low-noise op-amps. Products referred to
(1 + R2/R1) is G1 and (R2/R1) is G2 and assume in+ = in- = in. as low-noise op-amps are designed so that the input referred
The total output noise voltage is described by Equation noise voltage of the op-amp itself is small. They are mainly
(3.19.8). used for high-precision amplification applications, such as
sensors, and audio applications.

R2 R2
Vn 2  4kTR2 Vn1  4kTR1 ( ) Vns  4kTRS (1  ) (3.19.5)
R1 R1

R2
VnOP  Vn (1  ) (3.19.6)
R1

R2
Vni   in ( R1 // R2 ) Vni   in RS (1  ) (3.19.7)
R1

Vno2  Vn G1   in RS G1   in R1 // R2   4kTR2 

2 2 2
 4kTR1 G 2  
2
4kTR S G1 
2
(3.19.8)

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 Application Note

Items unique to comparators

3.20 Response time (rise/fall times and propagation delay time)

The response time of comparators is specified in terms of the There are two types of comparator: open-collector type (open
rise time, fall time, rise propagation delay time, and fall drain CMOS) and push-pull type (CMOS).
propagation delay time. As a feature of the open-collector (drain) type, the output
The rise time refers to the time during which a signal is varied stage of the comparator has no circuit for outputting at the
from 10% to 90% of the output signal amplitude. The fall time High setting and external resistors are required to pull-up the
refers to the time during which a signal is varied from 90% to output. By varying the value of the pull-up voltage (VRL), you
10% of the output signal amplitude. The propagation delay can adjust the High setting of the output voltage to a value
time is specified in terms of the time during which the voltage different from that of the power supply of the comparator. It
is varied from the reference voltage to 50% of the output should also be noted that the rise time of an open-collector
voltage amplitude. The propagation delay time is evaluated type comparator is affected by a time constant resulting from
by varying the potential difference between the reference the external pull-up resistor and the load or from parasitic
voltage and the signal level (overdrive voltage) as shown in capacitance.
Figure 3.20.1. The propagation delay time becomes longer as
the overdrive voltage is reduced. In addition, an input signal
at the TTL level (3.5 [Vpp]) may be supplied for evaluation.
Figure 3.20.1 shows the input and output waveforms of a
comparator.

Vref
Overdrive
オーバードライブ電圧voltage

Input入力波形
waveform Overdrive
オーバードライブ電圧voltage
Input waveform
入力波形
Vref

t t

Propagation
伝搬遅延時間：t delay time: tPLH
Propagation
伝搬遅延時間：t delay time: tPLH
PLH PＨＬ

90%
90%
Output waveform Output 出力波形
waveform 50%
出力波形
50% H→L
L→H
10%
10%

t t
Rise time: tR F
立下り時間：t
Rise time: tRR
立上り時間：t
Figure 3.20.1. Response time of comparator

VRL
VRL
VCC VDD
R
RL
L

Vin VOUT Vin

VOUT

Vref Vref
VEE=GND VSS=GND

(a) Open-collector (drain) (b) Push-pull

Figure 3.20.2. Measurement circuit for response time of

comparator

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 Application Note

Notes for using an op-amp as a comparator

In the output waveform of an op-amp in which phase Since the propagation delay time is not specified, the use of
compensation capacitance has been installed, the rise and comparators is also recommended when a high-speed
fall times are limited by the slew rate. The slew rate is response is required or when variations are of concern.
determined by the time for charging and discharging the As we explained in section 2.2 for the differential breakdown
phase compensation capacitance. Since comparators have voltage of the terminal structure, the protection diodes for
no phase compensation capacitance, they can respond with clamping are connected between the terminals in some
faster rise and fall times compared with op-amps. In addition, op-amps. Such op-amps cannot be used as comparators,
some op-amps are not appropriate to use as comparators since a current flow between the terminals. Equivalently,
due to their inside circuit configuration. when a model whose differential input breakdown voltage is
In general, rise times and propagation delay times are not lower than the maximum rating for the power supply voltage
specified for op-amps. However, you can estimate rise and is used as a comparator, care must be taken not to exceed
fall times based on the slew rate (SR = [V/μs]) if the output the maximum rating.
amplitude is known.

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 Application Note

4 Reliability Items
4.1 Electrostatic Breakdown Voltage (ESD
Breakdown Voltage)

The breakdown resistance to static electricity is one of the • MM (Machine Model)

reliability test items. The machine model describes the discharge phenomenon
The following phenomena are examples of the breakdown that occurs when an electrically charged machine made of
when static electricity is applied to the IC. metal contacts the semiconductor products. The
• Dielectric breakdown of the oxide film capacitance is larger while the resistance is lower than those
When the transistor has a MOS structure, this type of used for the human body model.
breakdown occurs when a high electric field is applied to the CESD = 200 [pF], RESD = 0 [Ω]
gate oxide film. This is an old standard and is currently slipping out of
• Thermal breakdown of the PN junction mainstream use.
Static electricity causes an overcurrent through the PN • CDM (Charged Device Model)
junction inside the IC, resulting in thermal breakdown of the This is a method to evaluate the resistance to the
junction. electrostatic discharge that occurs when the semiconductor
• Fusing in the wiring itself is electrically charged and contacts metals or other
Thermal breakdown in the wiring occurs if an overcurrent materials.
that exceeds the allowable current flows through the wiring. Figure 4.1.1 shows a simple test circuit for the human body
and machine models.
The following are models for the electrostatic stresses that The capacitance of CESD is charged with a high voltage
may be applied during the handling of semiconductor source, the charge is discharged through the resistance of
products. RESD, and then the occurrence of destruction is checked.
• HBM (Human Body Model) The test is performed for both the positive and negative
The human body model describes the discharge polarities. Generally, the common terminal for applying static
phenomenon that occurs when the electrically charged electricity is the VEE terminal (ground terminal) or the VCC
human body contacts semiconductor products. The values terminal. Usually, the IC is provided with a protection circuit
of capacitance and resistance are used for the modeling. against static electricity and a countermeasure is taken so
CESD = 100 [pF], RESD = 1.5 [kΩ] that an overcurrent will not flow inside the circuit. The role of
the protection circuit is to release the surge due to static
electricity to the common terminal and a current path with low
R RESD
R EDS
impedance is secured. Moreover, a resistor may be
connected in series to the terminal in order to prevent the
charging of hot carriers to the gate of the CMOS device.
保護回路で静電気サージに対する
Figure 4.1.2 shows an example低インピーダンスの電流経路を確保する。
of a protection circuit.
High voltage Measurement VCC
高電圧源 測定デバイス
source CESD
EDS device
A Current path with low
impedance is secured
Protection by the protection circuit
保護回路
circuit against the
electrostatic surge.
HBM : CEDS=100pF、R =1.5kΩ Application Internal
HBM: CESD = 100 pF, EDS
RESD = 1.5kΩ 印加端子 内部回路
circuit
MM : CEDS=200pF、REDS=0Ω terminal
MM: CESD = 200 pF, RESD = 0Ω
Protection
保護回路
circuit
Figure 4.1.1. Simple test circuit for HBM and MM

VEE Current flows inside

内部に電流が流れる
= destruction or deterioration
=破壊・劣化する

Figure 4.1.2. Example of an electrostatic protection circuit of an IC

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 Application Note

Figure 4.1.3 shows the equivalent circuit diagram for the CDM
test.

Measurement device
測定デバイス

High voltage
高電圧源
source

Figure 4.1.3. Equivalent circuit for the CDM test

4.2 Latch Up Test

The Latch up phenomenon occurs in an IC that is configured The following methods are available for evaluation of the IC
mainly with CMOS devices. The parasitic bipolar transistor resistance to the latch up.
that occurs between the elements is operated by the pulse • Current latch up test
current or voltage created by electrical noise or the A trigger by the current pulse is supplied to the IC and the
electrostatic testing, causing abnormal operations. occurrence of the latch up is checked.
This phenomenon shows various symptoms such as A current with both negative and positive polarities is
breakdown caused by a continued flow of overcurrent, or a applied.
fixed output voltage due to an increase of the circuit current. It • Voltage latch up test
also has a feature that enables the normal operation to be A trigger by the overvoltage pulse is supplied to the IC and
recovered by turning the power OFF and then ON again if a the occurrence of the latch up is checked.
breakdown has not occurred. The occurrence of the latch up
can be judged by monitoring the circuit current since the In both tests, the latch up is judged by monitoring the circuit
circuit current increases in all cases. current.
Usually, the latch up phenomenon is addressed using layout Figure 4.2.1 shows the latch up test circuit.
techniques during the design phase of the IC so that the
capability of the parasitic element is restrained.

VDD
Power supply
電源

VSS
Measurement
測定デバイス
device

Figure 4.2.1. Latch up test circuit

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 Notice

Notes
1) The information contained herein is subject to change without notice.

2) Before you use our Products, please contact our sales representative and verify the latest specifica-
tions :

3) Although ROHM is continuously working to improve product reliability and quality, semicon-
ductors can break down and malfunction due to various factors.
Therefore, in order to prevent personal injury or fire arising from failure, please take safety
measures such as complying with the derating characteristics, implementing redundant and
fire prevention designs, and utilizing backups and fail-safe procedures. ROHM shall have no
responsibility for any damages arising out of the use of our Poducts beyond the rating specified by
ROHM.

4) Examples of application circuits, circuit constants and any other information contained herein are
provided only to illustrate the standard usage and operations of the Products. The peripheral
conditions must be taken into account when designing circuits for mass production.

5) The technical information specified herein is intended only to show the typical functions of and
examples of application circuits for the Products. ROHM does not grant you, explicitly or implicitly,
any license to use or exercise intellectual property or other rights held by ROHM or any other
parties. ROHM shall have no responsibility whatsoever for any dispute arising out of the use of
such technical information.

6) The Products specified in this document are not designed to be radiation tolerant.

7) For use of our Products in applications requiring a high degree of reliability (as exemplified
below), please contact and consult with a ROHM representative : transportation equipment (i.e.
cars, ships, trains), primary communication equipment, traffic lights, fire/crime prevention, safety
equipment, medical systems, servers, solar cells, and power transmission systems.

8) Do not use our Products in applications requiring extremely high reliability, such as aerospace
equipment, nuclear power control systems, and submarine repeaters.

9) ROHM shall have no responsibility for any damages or injury arising from non-compliance with
the recommended usage conditions and specifications contained herein.

10) ROHM has used reasonable care to ensure the accuracy of the information contained in this
document. However, ROHM does not warrants that such information is error-free, and ROHM
shall have no responsibility for any damages arising from any inaccuracy or misprint of such
information.

11) Please use the Products in accordance with any applicable environmental laws and regulations,
such as the RoHS Directive. For more details, including RoHS compatibility, please contact a
ROHM sales office. ROHM shall have no responsibility for any damages or losses resulting
non-compliance with any applicable laws or regulations.

12) When providing our Products and technologies contained in this document to other countries,
you must abide by the procedures and provisions stipulated in all applicable export laws and
regulations, including without limitation the US Export Administration Regulations and the Foreign
Exchange and Foreign Trade Act.

13) This document, in part or in whole, may not be reprinted or reproduced without prior consent of
ROHM.

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