Q1) Difference Between Maximum Mode & Minimum Mode

Feature Maximum Mode Minimum Mode

Bus Control 8086 acts as bus controller and manages the 8086 does not act as a bus controller
gadget bus. and relies on an external bus controller.

Bus Requires an external bus controller Requires an external bus controller

Controller (e.G.8288) for bus arbitration and manipulate (e.G., 8284) for bus manage signal era
sign generation. and coordination.

Address Lines Utilizes all 20 address traces for extended Utilizes handiest sixteen cope with
reminiscence addressing. traces for limited reminiscence
addressing.

Data Lines Uses all 16 records strains for statistics Uses the handiest 16 data traces for
switch. facts switch.

Processor Supports a couple of processors for Designed for unmarried-processor

multiprocessor structures. systems.

System Full control over the device bus and gadgets Share management of the device bus
Control linked to it. with other gadgets.

System More complicated device design because of Simple gadget layout as bus manager is
Complexity bus manipulation obligations and support treated by means of an external bus
chips. controller.

Memory and Can get right of entry to a larger memory Limited reminiscence addressing and
I/O space and accommodate extra good sized I/O options.
I/O abilities.

System Cost Generally higher gadget value because of Lower machine fee due to reduced
extra support chips. complexity and less aid chips.

Typical Use Suitable for larger systems with more Preferred for simpler systems with an
than one processor and sizable unmarried processor and restricted
memory/I/O requirements. resource desire
Q2) Architecture of 8086 Microprocessor Diagram

Architecture Of 8086
It is clear from the diagram that only the BIU has a direct link with the memory.
This memory can be directly accessed either by the segment registers, the
Instruction Pointer (IP) or the Instruction Queue for fetching up the instructions.

These instructions are sent in the Control Unit for execution. The control unit takes the
help of General Purpose registers, Index registers and Pointers, operands, flags and the
most important, the Arithmetic Logic Unit (ALU). All these are part of the Execution
Unit.
1.1. Bus Interface Unit (BIU)
The Instruction Queue contains the set of instruction which is to be executed. To make the
processing faster, the 8086 pre-fetches up to 6 instructions in advance and stores them in the
Instruction queue. So, whenever one instruction completes its execution, the control unit need
not wait for the next instruction to be fetched and then brought for execution because this job is
already done and the next instruction that is to be executed is ready in the Instruction queue.

1.2. Segment Registers

Each Segment register can work with 16 bits of binary data

There are 4 types of segment registers:

i. CS: Code Segment Register

ii. DS: Data Segment Register
iii. SS: Stack Segment Register
iv. ES: Extra Segment Register

1.3. Instruction Pointer

The Instruction pointer contains the address of the next instruction that is to be executed.

2. Execution Unit (EU).

2.1. Control Unit (CU)
All the Instructions are executed inside the Control Unit. It is the main component which is
responsible for the processing of any processor.

2.2. Arithmetic Logic Unit (ALU)

All the Mathematical and Logical Operations are performed inside the ALU. So, if any instruction
needs to perform such operation, the Control Unit handovers it to the ALU.

2.3. Flag Register

The flag Register is of 16-bit length which consists of 9 flags, and the rest 7 bits are of don't care
cases.
2.4. General Purpose Registers
The General Purpose Registers are just as containers for storing the values which may be
required for executing the instructions. Each General Purpose Register consists of 16 bits. There
are 4 types of General Purpose Registers:

i. AX = [AH:AL]
ii. BX = [BH:BL]
iii. CX = [CH:CL]
iv. DX = [DH:DL]

2.5. Pointers and Index Registers

The 8086 contains following Pointers and Index Registers. (Here, IP is not mentioned because it
is a part of the BIU)

i. BP: Base Pointer

ii. SP: Stack Pointer
iii. SI: Source Index
iv. DI: Destination Index

2.6. Operands
These may be used within the instructions.

Conclusion
In this tutorial, we explained everything about the Architecture of 8086 Microprocessor, including
its internal architecture, i.e., the diagram of 8086 Microprocessor, parts of the execution units. If
you have any questions, you can leave a comment below.
Q3) Explain the Interrupt structure of 8086 processor

An interrupt is a special condition that arises during the working of a microprocessor. The
microprocessor services it by executing a subroutine called Interrupt Service Routine (ISR).There are
three sources of interrupts for 8086:

1. Hardware interrupt
These interrupts occur as signals on the external pins of the microprocessor. 8086 has two pins to
accept hardware interrupts, NMI and INTR.
2. Software interrupt
These interrupts are caused by writing the software interrupt instruction INT n where ‘n’ can be
any value from 0 to 255 (00H to FFH). Hence all 256 interrupts can be invoked by software.
3. Error conditions (Exception or types)
8086 is interrupted when some special conditions occur while executing certain instructions in the
program. Example: An error in division automatically causes the INT 0 interrupt.
Interrupt Vector Table (IVT):
 1. The interrupt vector (or interrupt pointer) table is the link between an interrupt type code and the
procedure that has been designated to service interrupts associated with that code. 8086 supports
total 256 types i.e. 00H to FFH.
2. For each type it has to reserve four bytes i.e. double word. This double word pointer contains the
address of the procedure that is to service interrupts of that type.
3. The higher addressed word of the pointer contains the base address of the segment containing the
procedure. This base address of the segment is normally referred as NEW CS.
4. The lower addressed word contains the procedure’s offset from the beginning of the segment.
This offset is normally referred as NEW IP.
5. Thus NEW CS: NEW IP provides NEW physical address from where user ISR routine will start.
6. As for each type, four bytes (2 for NEW CS and 2 for NEW IP) are required; therefore interrupt
pointer table occupies up to the first 1k bytes (i.e. 256 x 4 = 1024 bytes) of low memory.
7. The total interrupt vector table is divided into three groups namely,
A. Dedicated interrupts (INT 0…..INT 4)
B. Reserved interrupts (INT 5…..INT 31)
C. Available interrupts (INT 32…..INT 225)
A. Dedicated interrupts (INT 0…..INT 4):
1. INT 0 (Divide Error)
o This interrupt occurs whenever there is division error i.e. when the result of a division is
too large to be stored. This condition normally occurs when the divisor is very small as
compared to the dividend or the divisor is zero.
o Its ISR address is stored at location 0 x 4 = 00000H in the IVT.
2. INT 1 (Single Step)
o The microprocessor executes this interrupt after every instruction if the TF is set.
o It puts microprocessor in single stepping mode i.e. the microprocessor pauses after
executing every instruction. This is very useful during debugging.
o Its ISR generally displays contents of all registers. Its ISR address is stored at location 1 x 4
= 00004H in the IVT.
3. INT 2 (Non mask-able Interrupt)
o The microprocessor executes this ISR in response to an interrupt on the NMI (Non mask-
able Interrupt) line.
o Its ISR address is stored at location 2 x 4 = 00008H in the IVT.
4. INT 3 (Breakpoint Interrupt)
o This interrupt is used to cause breakpoints in the program. It is caused by writing the
instruction INT 03H or simply INT.
o It is useful in debugging large programs where single stepping is efficient.
o Its ISR is used to display the contents of all registers on the screen. Its ISR address is stored
at location 3 x 4 = 0000CH in the IVT.
5. INT 4 (Overflow Interrupt)
o This interrupt occurs if the overflow flag is set and the microprocessor executes the INTO
(Interrupt on Overflow) instruction.
o It is used to detect overflow error in signed arithmetic operations.
o Its ISR address is stored at location 4 x 4 = 00010H in the IVT.
B. Reserved interrupts (INT 5…..INT 31):

1. These levels are reserved by Intel to be used in higher processors like 80386, Pentium etc. They
are not available to the user.

C. Available interrupts (INT 32…..INT 225):

1. These are user defined, software interrupts.

2. ISRs for these interrupts are written by the users to service various user defined conditions.
3. These interrupts are invoked by writing the instruction INT n. Its ISR address is obtained by the
microprocessor from location n x 4 in the IVT.

Hardware Interrupts:
1. NMI (Non mask-able interrupt)-
o This is a non-mask-able, edge triggered, high priority interrupt.
o On receiving an interrupt on NMI line, the microprocessor executes INT
o Microprocessor obtains the ISR address from location 2 x 4 = 00008H from the IVT.
o It reads 4 locations starting from this address to get the values for IP and CS to execute the
ISR.
2. INTR-

1. This is a mask-able, level triggered, low priority interrupt.

2. On receiving an interrupt on INTR line, the microprocessor executes
2 INTA¯¯¯¯¯¯¯¯¯¯¯¯¯¯𝐼𝑁𝑇𝐴¯ pulses.
3. 1st INTA¯¯¯¯¯¯¯¯¯¯¯¯¯¯𝐼𝑁𝑇𝐴¯ pulse – The interrupting device calculates (prepares to send) the vector
number.
a. 2nd INTA¯¯¯¯¯¯¯¯¯¯¯¯¯¯𝐼𝑁𝑇𝐴¯ pulse – The interrupting device sends the vector number ‘N’ to
the microprocessor.
4. Now microprocessor multiplies N x 4 and goes to the corresponding location in the IVT to obtain
the ISR address. INTR is a mask-able interrupt.
5. It is masked by making IF = 0 by software through CLI instruction.
6. It is unmasked by making IF = 1 by software through STI instruction.

Q4) Control signals for all operations are generated by decoding M/IO’, RD’, WR’.
They are decoded by 74138 3:8 decoder.
 INTR and INTA :
When INTR = 1,then there is an interrupt to 8086 by other devices for their service.
When INTA’= 0,then it indicates that the processor is ready to service them.

• The
bus request is made by other devices using the HOLD signal and the
processor acknowledges them using the HLDA output signal

Timing diagram :
The working of min mode can be easily understood by timing diagrams.

1. All processors bus cycle is of at least 4 T-states(T1,T2,T3,T4) .The address is given by

processor in the T1 state. It is available on the bus for one T-state.
2. In T2, the bus is tristated for changing the direction of the bus( in the case of a data read
cycle.)
3. The data transfer takes place between T3 and T4.
4. If the addressed device is slower, then the wait state is inserted between T 3 and T4.

Opcode fetch or read timing diagram

1. At T1 state ALE =1 ,this indicates that a valid address is latched on the address bus and
also M / IO’= 1, which indicates the memory operation is in progress.
2. In T2, the address is removed from the local bus and is sent to the addressed device.
Then the bus is tristated.
3. When RD’ = 0 , the valid data is present on the data bus.
 4. During T2 DEN’ =0, which enables transceivers and DT/R’ = 0 ,which indicates that the
data is received.
5. During T3, data is put on the data bus and the processor reads it.
6. The output device makes the READY line high. This means the output device has
performed the data transfer process. When the processor makes the read signal to 1,
then the output device will again tristate its bus drivers.

Write memory cycle

1. At T1 state ALE =1 ,this indicates that a valid address is latched on the address bus
and also M / IO’= 1, which indicates the memory operation is in progress.
2. In T2, the processor sends the data to be written to the addressed location.
3. The data is buffered on the bus until the middle of T4 state.
4. The WR’=0 becomes at the beginning of T2.
5. The BHE’ and A0 signals are used to select the byte or bytes of memory or I/O
word.
6. During T2 DEN’ =0, which enables, transceivers and DT/R’ =
 Q5) Memory Banking in Microprocessor
The 8086 processor provides a 16-bit data bus. So It is capable of transferring 16 bits in
one cycle but each memory location is only of a byte(8 bits), therefore we need two
cycles to access 16 bits(8 bit each) from two different memory locations. The solution to
this problem is Memory Banking. Through Memory banking, our goal is to access two
consecutive memory locations in one cycle(transfer 16 bits).

The memory chip is equally divided into two parts(banks). One of the banks contains
even addresses called Even bank and the other contains odd addresses called Odd
bank. Even bank always gives lower byte So Even bank is also called Lower bank(LB)
and Odd bank is also called Higher bank(HB). This banking scheme allows to access
two aligned memory locations from both banks simultaneously and process 16-bit data
transfer. Memory banking doesn’t make it compulsory to transfer 16 bits, it facilitates the
16-bit data transfer.
The choice between 8 bit and 16-bit transfer depends on the instructions given by the
programmer.

Example:
Memory Banking:
Here we shall consider an 8086 processor which can hold 1MB of memory due to its 20 address lines (
220 = 1MB ) So this 1MB memory is divided into two parts ( two banks ), where one bank consists of all
even addresses and the other bank consists of odd addresses.

The Least Significant bit of address (A0 is not used for byte selection) is reserved for bank
selection. Therefore A0=0 will select Even bank. The BHE signal is used for the selection
of odd banks. The processor will use a combination of these two signals to decide the
type of data transfer.

BHE A0 types of Transfer

0 0 16-0bit data transfer from both HB and LB

0 1 8-bit data transfer from HB

1 0 8-bit data transfer from LB

1 1 None(Idle)

In this case, the first machine cycle generates an odd address (A 0=1) transfer lower order
8 data bits on a higher-order data bus. In the second machine cycle, the higher-order data
bus will be transferred to the lower-order data bus.
 Advantages:

Improved Performance: Memory banking allows the microprocessor to access multiple

banks of memory simultaneously. This can improve the performance of memory-
intensive applications by reducing memory access times and increasing overall memory
bandwidth.arax

Flexibility: Memory banking provides a flexible way to allocate and manage memory
resources. It allows the processor to allocate memory as needed, which can help reduce
memory wastage and improve overall system efficiency.

Cost-Effective: Memory banking can be a cost-effective way to increase the memory

capacity of a microprocessor. Instead of using expensive, high-density memory modules,
memory banking allows the use of multiple, smaller memory modules.

Disadvantages:

Increased Complexity: Memory banking adds complexity to the microprocessor

design, which can make it more difficult to implement and debug. Memory banking
requires additional hardware components, such as memory address decoders and control
logic, which can increase the cost and complexity of the microprocessor.

Latency: Although memory banking can improve memory performance, it can also
introduce latency. Memory banking requires additional memory address decoding and
control logic, which can increase memory access times and reduce overall system
performance.

Limited Applications: Memory banking is not suitable for all types of microprocessor
applications. It is primarily used in systems that require large amounts of memory, such
as high-performance computing and data center applications. In other applications, the
added complexity and cost of memory banking may not be worth the benefits.
Q6) What is purpose of maximum mode df-8086? Give suitable example

As the 16-bit data is stored in 2 locations, lower byte in lower address and upper byte in next consecutive
address location.
The data stored here is 1345H. This is representation of data in hexadecimal form. So whenever the processor
needs to fetch this , it first gives the address to the address bus and fetches 45H and then it gives the next
address, then it fetches 13H. So overall a 16-bit processor needs 2 cycles to perform a 16-bit operation, which
is completely a wrong concept. This thing led to memory banking.

If the memory can be divided into two parts, with some algorithm, two 8-bit datas can be fetched in one cycle.

As Even bank starts from 00000H and goes up to FFFFEH , it stores the lower byte so also known as lower
bank. Odd bank locations start from 00001H and go upto FFFFFH , this stores higher byte , thus also known
as Higher bank in 8086.

Q7) What is segmentation? OR Write short note ate the Advantage on

Advantages of memory OR Segmentation, OR Explain mentation

Types Of Segmentation
1. Overlapping Segment – A segment starts at a particular address and its
maximum size can go up to 64kilobytes. But if another segment starts along with
this 64kilobytes location of the first segment, then the two are said to
be Overlapping Segment.
 2. Non-Overlapped Segment – A segment starts at a particular address and its
maximum size can go up to 64kilobytes. But if another segment starts before this
64kilobytes location of the first segment, then the two segments are said to be Non-
Overlapped Segment.

Rules of Segmentation Segmentation process follows some rules as follows:

• The starting address of a segment should be such that it can be evenly divided by 16.
• Minimum size of a segment can be 16 bytes and the maximum can be 64 kB.

Advantages of the Segmentation The main advantages of segmentation are as

follows:

1. It provides a powerful memory management mechanism.

2. Data related or stack related operations can be performed in different segments.
3. Code related operation can be done in separate code segments.
4. It allows to processes to easily share data.
5. It allows to extend the address ability of the processor, i.e. segmentation allows
the use of 16 bit registers to give an addressing capability of 1 Megabytes.
Without segmentation, it would require 20 bit registers.

6. It is possible to enhance the memory size of code data or stack segments beyond
64 KB by allotting more than one segment for each area

1001H 00H

1002H 80H
Timing Diagram of STA Instructions

Timing Diagram of INR M Instructions

• C500H INR M 34H

• D050 as memory address

• E1H and E2H as opcode

Timing Diagram of INR Instructions

Applications 0f 8085

1. System charts keep track of all changes occurring in the system.

2. Timelines provide a more accurate representation of physical activity.
3. The timing table of 8085 instructions graphically represents the time required to
execute each instruction.
4. Timing Diagram is a special form of sequence diagram.
5. Timing Diagram keep track of every change that occur in the system.
6. The timing diagram is important for planning the clock frequency of the
microprocessor.
7. The timing diagram helps design memory circuits that meet the required set and hold
times during read and write operations.

Conclusion
The timing diagram of the 8085 microprocessor looks like a brief overview of how the
microprocessor works during operation. It helps engineers solve problems, create good
memories and interactions between devices, make quick decisions, and do good, on-time work.
For students, it simplifies the learning process by providing a visual representation of the inner
workings of a microprocessor. Essentially, it serves as a guide for understanding,
troubleshooting and optimizing the performance of the 8085 microprocessor.