ESP32-C3

Hardware Design Guidelines

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Espressif Systems
Feb 21, 2024
Table of contents

Table of contents i

1 About This Document 3

1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.2 Latest Version of This Document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

2 Product Overview 5

3 Schematic Checklist 7
3.1 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.1.1 Digital Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.1.2 Analog Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.1.3 RTC Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.2 Chip Power-up and Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.3 Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.4 Clock Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.4.1 External Crystal Clock Source (Compulsory) . . . . . . . . . . . . . . . . . . . . . . . . 11
3.4.2 RTC Clock Source (Optional) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.5 RF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.5.1 RF Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.5.2 RF Tuning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.6 UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.7 Strapping Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.8 GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.9 ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.10 USB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

4 PCB Layout Design 19

4.1 General Principles of PCB Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.2 Positioning a Module on a Base Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.3 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.3.1 General Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.3.2 3.3 V Power Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.3.3 Analog Power Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.4 Crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.5 RF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.6 Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4.7 UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4.8 USB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
4.9 Typical Layout Problems and Solutions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
4.9.1 1. The voltage ripple is not large, but the TX performance of RF is rather poor. . . . . . . 27
4.9.2 2. When ESP32-C3 sends data packages, the voltage ripple is small, but RF TX perfor-
mance is poor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
4.9.3 3. When ESP32-C3 sends data packages, the power value is much higher or lower than the
target power value, and the EVM is relatively poor. . . . . . . . . . . . . . . . . . . . . . 27
4.9.4 4. TX performance is not bad, but the RX sensitivity is low. . . . . . . . . . . . . . . . . 28

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5 Hardware Development 29
5.1 ESP32-C3 Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5.2 ESP32-C3 Development Boards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5.3 Download Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

6 Related Documentation and Resources 31

7 Glossary 33

8 Revision History 35
8.1 ESP Hardware Design Guidelines v1.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

9 Disclaimer and Copyright Notice 37

ii
Table of contents

This document provides guidelines for the ESP32-C3 SoC.

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Table of contents

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Chapter 1

About This Document

1.1 Introduction
The hardware design guidelines advise on how to integrate ESP32-C3 into a product. These guidelines will help to
achieve optimal performance of your product, ensuring technical accuracy and adherence to Espressif’s standards.
The guidelines are intended for hardware and application engineers.
The document assumes that you possess a certain level of familiarity with the ESP32-C3 SoC. In case you lack prior
knowledge, we recommend utilizing this document in conjunction with the ESP32-C3 Series Datasheet.

1.2 Latest Version of This Document

Check the link to make sure that you use the latest version of this document: https://docs.espressif.com/projects/
esp-hardware-design-guidelines/en/latest/esp32c3/index.html

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Chapter 1. About This Document

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Chapter 2

Product Overview

ESP32-C3 is a system on a chip that integrates the following features:

• Wi-Fi (2.4 GHz band)
• Bluetooth® 5 (LE)
• High performance 32-bit RISC-V single-core processor
• Multiple peripherals
• Built-in security hardware
Powered by 40 nm technology, ESP32-C3 provides a robust, highly-integrated platform, which helps meet the con-
tinuous demands for efficient power usage, compact design, security, high performance, and reliability. Typical
application scenarios for ESP32-C3 include:

• Smart Home
• Industrial Automation
• Health Care
• Consumer Electronics
• Smart Agriculture
• POS Machines
• Service Robot
• Audio Devices
• Generic Low-power IoT Sensor Hubs
• Generic Low-power IoT Data Loggers
For more information about ESP32-C3, please refer to ESP32-C3 Series Datasheet.

Note: Unless otherwise specified, “ESP32-C3”used in this document refers to the series of chips, instead of a
specific chip variant.

5
Chapter 2. Product Overview

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Chapter 3

Schematic Checklist

The integrated circuitry of ESP32-C3 requires only 20 electrical components (resistors, capacitors, and inductors)
and a crystal, as well as an SPI flash. The high integration of ESP32-C3 allows for simple peripheral circuit design.
This chapter details the schematic design of ESP32-C3.
The following figure shows a reference schematic design of ESP32-C3. It can be used as the basis of your schematic
design.

Fig. 1: ESP32-C3 Reference Schematic

Any basic ESP32-C3 circuit design may be broken down into the following major building blocks:

• Power supply
• Chip power-up and reset timing
• Flash
• Clock source

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Chapter 3. Schematic Checklist

• RF
• UART
• Strapping pins
• GPIO
• ADC
• USB
The rest of this chapter details the specifics of circuit design for each of these sections.

3.1 Power Supply

The general recommendations for power supply design are:
• When using a single power supply, the recommended power supply voltage is 3.3 V and the output current is
no less than 500 mA.
• It is suggested to add an ESD protection diode at the power entrance.
More information about power supply pins can be found in ESP32-C3 Series Datasheet > Section Power Supply.

3.1.1 Digital Power Supply

ESP32-C3 has pin17 VDD3P3_CPU as the digital power supply pin(s) working in a voltage range of 3.0 V ~ 3.6 V.
It is recommended to add an extra 0.1 μF decoupling capacitor close to the pin(s).
Pin VDD_SPI can serve as the power supply for the external device at 3.3 V (typical value), provided by
VDD3P3_CPU via RSPI . Therefore, there will be some voltage drop from VDD3P3_CPU. When the VDD_SPI
outputs 3.3 V, it is recommended that users add a 1 μF capacitor close to VDD_SPI.
VDD_SPI can be connected to and powered by an external power supply.
When not serving as a power supply pin, VDD_SPI can be used as a regular GPIO.

Attention: When using VDD_SPI as the power supply pin for the in-package flash or external 3.3 V flash, the
supply voltage should be 3.0 V or above, so as to meet the requirements of flash’s working voltage. In such
cases, VDD_SPI cannot be used as a regular GPIO.

The schematic for the digital power supply pins is shown in Figure ESP32-C3 Schematic for Digital Power Supply
Pins.

3.1.2 Analog Power Supply

ESP32-C3’s VDDA and VDD3P3 pins are the analog power supply pins, working at 3.0 V ~ 3.6 V.
For VDD3P3, when ESP32-C3 is transmitting signals, there may be a sudden increase in the current draw, causing
power rail collapse. Therefore, it is highly recommended to add a 10 μF capacitor to the power rail, which can work
in conjunction with the 0.1 μF capacitor(s).
Add a LC circuit on the VDD3P3 power rail to suppress high-frequency harmonics. The inductor’s rated current is
preferably 500 mA and above.
Place appropriate decoupling capacitors near the other analog power pins according to Figure ESP32-C3 Schematic
for Analog Power Supply Pins.

3.1.3 RTC Power Supply

ESP32-C3’s VDD3P3_RTC pin is the RTC and analog power pin. It is recommended to place a 0.1 μF decoupling
capacitor near this power pin in the circuit.

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Chapter 3. Schematic Checklist

Fig. 2: ESP32-C3 Schematic for Digital Power Supply Pins

Fig. 3: ESP32-C3 Schematic for Analog Power Supply Pins

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Chapter 3. Schematic Checklist

Note that this power supply cannot be used as a single backup power supply.
The schematic for the RTC power supply pin is shown in Figure ESP32-C3 Schematic for RTC Power Supply Pin.

Fig. 4: ESP32-C3 Schematic for RTC Power Supply Pin

3.2 Chip Power-up and Reset Timing

ESP32-C3’s CHIP_EN pin can enable the chip when it is high and reset the chip when it is low.
When ESP32-C3 uses a 3.3 V system power supply, the power rails need some time to stabilize before CHIP_EN
is pulled up and the chip is enabled. Therefore, CHIP_EN needs to be asserted high after the 3.3 V rails have been
brought up.
To reset the chip, keep the reset voltage VIL_nRST in the range of (–0.3 ~ 0.25 × VDD) V. To avoid reboots caused
by external interferences, make the CHIP_EN trace as short as possible.
Figure ESP32-C3 Power-up and Reset Timing shows the power-up and reset timing of ESP32-C3.

Fig. 5: ESP32-C3 Power-up and Reset Timing

Table Description of Timing Parameters for Power-up and Reset provides the specific timing requirements.

Table 1: Description of Timing Parameters for Power-up and Reset

Parameter Description Minimum (µs)
tSTBL Time reserved for the power rails to stabilize before the CHIP_EN 50
pin is pulled high to activate the chip
tRST Time reserved for CHIP_EN to stay below VIL_nRST to reset the 50
chip

Attention:
• CHIP_EN must not be left floating.

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Chapter 3. Schematic Checklist

• To ensure the correct power-up and reset timing, it is advised to add an RC delay circuit at the CHIP_EN
pin. The recommended setting for the RC delay circuit is usually R = 10 kΩ and C = 1 μF. However, specific
parameters should be adjusted based on the characteristics of the actual power supply and the power-up
and reset timing of the chip.
• If the user application has one of the following scenarios:
– Slow power rise or fall, such as during battery charging.
– Frequent power on/off operations.
– Unstable power supply, such as in photovoltaic power generation.
Then, the RC circuit itself may not meet the timing requirements, resulting in the chip being
unable to boot correctly. In this case, additional designs need to be added, such as:
– Adding an external reset chip or a watchdog chip, typically with a threshold of around 3.0
V.
– Implementing reset functionality through a button or the main controller.

3.3 Flash
ESP32-C3 can support up to 16 MB external flash, powered by VDD_SPI. It is recommended to add a zero-ohm
series resistor on the SPI lines as shown in Figure ESP32-C3 Schematic for External Flash, to lower the driving current,
reduce interference to RF, adjust timing, and better shield from interference.
For the ESP32-C3 variants with in-package SPI flash, the pins for flash communication cannot be used externally for
other purposes.

Fig. 6: ESP32-C3 Schematic for External Flash

3.4 Clock Source

ESP32-C3 supports two external clock sources:
• External crystal clock source (Compulsory)
• RTC clock source (Optional)

3.4.1 External Crystal Clock Source (Compulsory)

The ESP32-C3 firmware only supports 40 MHz crystal.

The circuit for the crystal is shown in Figure ESP32-C3 Schematic for External Crystal. Note that the accuracy of the
selected crystal should be within ±10 ppm.

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Fig. 7: ESP32-C3 Schematic for External Crystal

Please add a series component (resistor or inductor) on the XTAL_P clock trace. Initially, it is suggested to use an
inductor of 24 nH to reduce the impact of high-frequency crystal harmonics on RF performance, and the value should
be adjusted after an overall test.
The initial values of external capacitors C1 and C2 can be determined according to the formula:

C1 × C2
CL = + Cstray
C1 + C2
where the value of CL (load capacitance) can be found in the crystal’s datasheet, and the value of Cstray refers to the
PCB’s stray capacitance. The values of C1 and C2 need to be further adjusted after an overall test as below:
1. Select TX tone mode using the Certification and Test Tool.
2. Observe the 2.4 GHz signal with a radio communication analyzer or a spectrum analyzer and demodulate it to
obtain the actual frequency offset.
3. Adjust the frequency offset to be within ±10 ppm (recommended) by adjusting the external load capacitance.
• When the center frequency offset is positive, it means that the equivalent load capacitance is small, and the
external load capacitance needs to be increased.
• When the center frequency offset is negative, it means the equivalent load capacitance is large, and the external
load capacitance needs to be reduced.
• External load capacitance at the two sides are usually equal, but in special cases, they may have slightly different
values.

Note:
• Defects in the manufacturing of crystal (for example, large frequency deviation of more than ±10 ppm, unstable
performance within the operating temperature range, etc) may lead to the malfunction of ESP32-C3, resulting
in a decrease of the RF performance.
• It is recommended that the amplitude of the crystal is greater than 500 mV.
• When Wi-Fi or Bluetooth connection fails, after ruling out software problems, you may follow the steps men-
tioned above to ensure that the frequency offset meets the requirements by adjusting capacitors at the two sides
of the crystal.

3.4.2 RTC Clock Source (Optional)

ESP32-C3 supports an external 32.768 kHz crystal or an external signal (e.g., an oscillator) to act as the RTC clock.
The external RTC clock source enhances timing accuracy and consequently decreases average power consumption,
without impacting functionality.
Figure ESP32-C3 Schematic for 32.768 kHz Crystal shows the schematic for the external 32.768 kHz crystal.
Please note the requirements for the 32.768 kHz crystal:

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Fig. 8: ESP32-C3 Schematic for 32.768 kHz Crystal

• Equivalent series resistance (ESR) ≤ 70 kΩ.

• Load capacitance at both ends should be configured according to the crystal’s specification.
The parallel resistor R is used for biasing the crystal circuit (5 MΩ < R ≤ 10 MΩ). In general, you do not need to
populate the resistor.
If the RTC clock source is not required, then the pins for the 32.768 kHz crystal can be used as GPIOs.
The external signal can be input to the XTAL’s P end through a DC blocking capacitor (about 20 pF). The XTAL’s
N end can be floating. Figure ESP32-C3 Schematic for External Oscillator shows the schematic of the external signal.

Fig. 9: ESP32-C3 Schematic for External Oscillator

The signal should meet the following requirements:

External signal Amplitude (Vpp, unit: V)

Sine wave or square wave 0.6 < Vpp < VDD

3.5 RF

3.5.1 RF Circuit

ESP32-C3’s RF circuit is mainly composed of three parts, the RF traces on the PCB board, the chip matching
circuit, the antenna and the antenna matching circuit. Each part should meet the following requirements:
• For the RF traces on the PCB board, 50 Ω impedance control is required.
• For the chip matching circuit, it must be placed close to the chip. A CLC structure is preferred.

– The CLC structure is mainly used to adjust the impedance point and suppress harmonics, and
a set of LC can be added if space permits.
– The RF matching circuit is shown in Figure ESP32-C3 Schematic for RF Matching.
• For the antenna and the antenna matching circuit, to ensure radiation performance, the antenna’s characteristic
impedance must be around 50 Ω. Adding a CLC matching circuit near the antenna is recommended to adjust
the antenna. However, if the available space is limited and the antenna impedance point can be guaranteed to
be 50 Ω by simulation, then there is no need to add a matching circuit near the antenna.

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Chapter 3. Schematic Checklist

Fig. 10: ESP32-C3 Schematic for RF Matching

3.5.2 RF Tuning

The RF matching parameters vary with the board, so the ones used in Espressif modules could not be applied directly.
Follow the instructions below to do RF tuning.
Figure ESP32-C3 RF Tuning Diagram shows the general process of RF tuning.

Fig. 11: ESP32-C3 RF Tuning Diagram

In the matching circuit, define the port near the chip as Port 1 and the port near the antenna as Port 2. S11 describes
the ratio of the signal power reflected back from Port 1 to the input signal power, the transmission performance is
best if the matching impedance is conjugate to the chip impedance. S21 is used to describe the transmission loss of
signal from Port 1 to Port 2. If S11 is close to the chip conjugate point (35+j0) and S21 is less than -35 dB at 4.8
GHz and 7.2 GHz, the matching circuit can satisfy transmission requirements.
Connect the two ends of the matching circuit to the network analyzer, and test its signal reflection parameter S11
and transmission parameter S21. Adjust the values of the components in the circuit until S11 and S21 meet the
requirements. If your PCB design of the chip strictly follows the PCB design stated in Chapter PCB Layout Design,
you can refer to the value ranges in Table Recommended Value Ranges for Components to debug the matching circuit.

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Table 2: Recommended Value Ranges for Components

Reference Desig- Recommended Value Range Serial No.
nator
C11 1.2 ~ 1.8 pF GRM0335C1H1RXBA01D
L2 2.4 ~ 3.0 nH LQP03TN2NXB02D
C12 1.8 ~ 1.2 pF GRM0335C1H1RXBA01D

If the components are in the 0201 SMD package size, please use a stub in the PCB design of the RF matching circuit
near the chip. If the antenna input impedance is not 50 ohm, an additional set of RF matching is recommended for
antenna tuning.
If the usage or production environment is sensitive to electrostatic discharge, it is recommended to reserve ESD
protection devices near the antenna.

Note: If RF function is not required, then the RF pin can be left floating.

3.6 UART
It is recommended to connect a 499 Ω series resistor to the U0TXD line to suppress the 80 MHz harmonics.
Usually, UART0 is used as the serial port for download and log printing. For instructions on download over UART0,
please refer to Section Download Guidelines.
Other UART interfaces can be used as serial ports for communication, which could be mapped to any available
GPIO by software configurations. For these interfaces, it is also recommended to add a series resistor to the TX line
to suppress harmonics.
When using the AT firmware, please note that the UART GPIO is already configured (refer to AT Firmware Down-
load). It is recommended to use the default configuration.

3.7 Strapping Pins

At each startup or reset, a chip requires some initial configuration parameters, such as in which boot mode to load
the chip, etc. These parameters are passed over via the strapping pins. After reset, the strapping pins work as normal
function pins.
All the information about strapping pins is covered in ESP32-C3 Series Datasheet > Section Strapping Pins. In this
document, we will mainly cover the strapping pins related to boot mode.
After chip reset is released, the combination of GPIO2, GPIO8, and GPIO9 controls the boot mode. See Table Boot
Mode Control.

Table 3: Boot Mode Control

Boot Mode GPIO21 GPIO8 GPIO9
Default Config –(Floating) –(Floating) 1 (Pull-up)
SPI Boot (default) 1 Any value 1
Joint Download Boot2 1 1 0

Signals applied to the strapping pins should have specific setup time and hold time. For more information, see Figure
Setup and Hold Times for Strapping Pins and Table Description of Timing Parameters for Strapping Pins.
1 GPIO2 actually does not determine SPI Boot and Joint Download Boot mode, but it is recommended to pull this pin up due to glitches.
2 Joint Download Boot mode supports the following download methods:
• USB-Serial-JTAG Download Boot
• UART Download Boot

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Fig. 12: Setup and Hold Times for Strapping Pins

Table 4: Description of Timing Parameters for Strapping Pins

Parameter Description Minimum (ms)
tSU Time reserved for the power rails to stabilize before the chip enable 0
pin (CHIP_EN) is pulled high to activate the chip.
tH Time reserved for the chip to read the strapping pin values after 3
CHIP_EN is already high and before these pins start operating as
regular IO pins.

Attention: Do not add high-value capacitors at GPIO9, otherwise, the chip may not boot successfully.

3.8 GPIO
The pins of ESP32-C3 can be configured via IO MUX or GPIO matrix. IO MUX provides the default pin configura-
tions, whereas the GPIO matrix is used to route signals from peripherals to GPIO pins. For more information about
IO MUX and GPIO matrix, please refer to ESP32-C3 Technical Reference Manual > Chapter IO MUX and GPIO
Matrix.
Some peripheral signals have already been routed to certain GPIO pins, while some can be routed to any available
GPIO pins. For details, please refer to ESP32-C3 Series Datasheet > Section Peripheral Pin Configurations.
When using GPIOs, please:

• Pay attention to the states of strapping pins during power-up.

• Pay attention to the default configurations of the GPIOs after reset. The default configurations can be found
in Table IO MUX Pin Functions. It is recommended to add a pull-up or pull-down resistor to pins in the
high-impedance state or enable the pull-up and pull-down during software initialization to avoid extra power
consumption.
• Avoid using the pins already occupied by flash.
• Some pins will have glitches during power-up. Refer to Table Power-Up Glitches on Pins for details.

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Table 5: IO MUX Pin Functions

Name No. Function 0 Function 1 Function 2 Reset Notes
XTAL_32K_P 4 GPIO0 GPIO0 — 0 R
XTAL_32K_N 5 GPIO1 GPIO1 — 0 R
GPIO2 6 GPIO2 GPIO2 FSPIQ 1 R
GPIO3 8 GPIO3 GPIO3 — 1 R
MTMS 9 MTMS GPIO4 FSPIHD 1 R
MTDI 10 MTDI GPIO5 FSPIWP 1 R
MTCK 12 MTCK GPIO6 FSPICLK 1* G
MTDO 13 MTDO GPIO7 FSPID 1 G
GPIO8 14 GPIO8 GPIO8 — 1 —
GPIO9 15 GPIO9 GPIO9 — 3 —
GPIO10 16 GPIO10 GPIO10 FSPICS0 1 G
VDD_SPI 18 GPIO11 GPIO11 — 0 —
SPIHD 19 SPIHD GPIO12 — 3 —
SPIWP 20 SPIWP GPIO13 — 3 —
SPICS0 21 SPICS0 GPIO14 — 3 —
SPICLK 22 SPICLK GPIO15 — 3 —
SPID 23 SPID GPIO16 — 3 —
SPIQ 24 SPIQ GPIO17 — 3 —
GPIO18 25 GPIO18 GPIO18 — 0 USB, G
GPIO19 26 GPIO19 GPIO19 — 0* USB
U0RXD 27 U0RXD GPIO20 — 3 G
U0TXD 28 U0TXD GPIO21 — 4 —

Reset
The default configuration of each pin after reset:
• 0 –input disabled, in high impedance state (IE = 0)
• 1 –input enabled, in high impedance state (IE = 1)
• 2 –input enabled, pull-down resistor enabled (IE = 1, WPD = 1)
• 3 –input enabled, pull-up resistor enabled (IE = 1, WPU = 1)
• 4 –output enabled, pull-up resistor enabled (OE = 1, WPU = 1)
• 0* –input disabled, pull-up resistor enabled (IE = 0, WPU = 0, USB_WPU = 1). See details in Notes
• 1* –When the value of eFuse bit EFUSE_DIS_PAD_JTAG is
– 0, input enabled, pull-up resistor enabled (IE = 1, WPU = 1)
– 1, input enabled, in high impedance state (IE = 1)
Notes

• R –These pins have analog functions.

• USB –GPIO18 and GPIO19 are USB pins.
– By default, the USB function is enabled for USB pins (i.e., GPIO18 and GPIO19), and
the pin pull-up is decided by the USB pull-up resistor. The USB pull-up resistor is
controlled by USB_SERIAL_JTAG_DP/DM_PULLUP and the pull-up value is controlled by
USB_SERIAL_JTAG_PULLUP_VALUE. For details, see ESP32-C3 Technical Reference Manual >
Chapter USB Serial/JTAG Controller.
– When the USB function is disabled, USB pins are used as regular GPIOs and the pin’s internal weak
pull-up and pull-down resistors are disabled by default (configurable by IO_MUX_FUN_WPU/WPD).
• G –These pins have glitches during power-up. See details in Table Power-Up Glitches on Pins.

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Table 6: Power-Up Glitches on Pins

Pin GlitchPage 18, 3 Typical Time (ns)
MTCK Low-level glitch 5
MTDO Low-level glitch 5
GPIO10 Low-level glitch 5
U0RXD Low-level glitch 5
GPIO18 High-level glitch 50,000

3.9 ADC
Please add a 0.1 μF filter capacitor between ESP pins and ground when using the ADC function to improve accuracy.
It is recommend to use ADC1, given that ADC2 is not factory-calibrated, and ADC2 of some chip revisions is not
operable. For details, please refer to ESP32-C3 Series SoC Errata.
The calibrated ADC results after hardware calibration and software calibration are shown in the list below. For higher
accuracy, you may implement your own calibration methods.

• When ATTEN=0 and the effective measurement range is 0 ~ 750 mV, the total error is ±10 mV.
• When ATTEN=1 and the effective measurement range is 0 ~ 1050 mV, the total error is ±10 mV.
• When ATTEN=2 and the effective measurement range is 0 ~ 1300 mV, the total error is ±10 mV.
• When ATTEN=3 and the effective measurement range is 0 ~ 2500 mV, the total error is ±35 mV.

3.10 USB
ESP32-C3 integrates a USB Serial/JTAG controller that supports USB 2.0 full-speed device.
GPIO18 and GPIO19 can be used as D- and D + of USB respectively. It is recommended to populate zero-ohm series
resistors between the mentioned pins and the USB connector. Also, reserve a footprint for a capacitor to ground on
each trace. Note that both components should be placed close to the chip.
Note that USB_D+ will have level output, so please add a pull-up resistor to determine the initial high-level output
voltage.
ESP32-C3 also supports download functions and log message printing via USB. For details please refer to Section
Download Guidelines.

• Low-level glitch: the pin is at a low level output status during the time period;
• High-level glitch: the pin is at a high level output status during the time period.

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Chapter 4

PCB Layout Design

This chapter introduces the key points of how to design an ESP32-C3 PCB layout using an ESP32-C3 module (see
Figure ESP32-C3 Reference PCB Layout) as an example.

Fig. 1: ESP32-C3 Reference PCB Layout

4.1 General Principles of PCB Layout

It is recommended to use a four-layer PCB design:
• Layer 1 (TOP): Signal traces and components.
• Layer 2 (GND): No signal traces here to ensure a complete GND plane.
• Layer 3 (POWER): GND plane should be applied to better isolate the RF and crystal. Route power traces and
a few signal traces on this layer, provided that there is a complete GND plane under the RF and crystal.
• Layer 4 (BOTTOM): Route a few signal traces here. It is not recommended to place any components on this
layer.
A two-layer PCB design can also be used:
• Layer 1 (TOP): Signal traces and components.
• Layer 2 (BOTTOM): Do not place any components on this layer and keep traces to a minimum. Please make
sure there is a complete GND plane for the chip, RF, and crystal.

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Chapter 4. PCB Layout Design

4.2 Positioning a Module on a Base Board

If module-on-board design is adopted, attention should be paid while positioning the module on the base board. The
interference of the baseboard on the module’s antenna performance should be minimized.
It is suggested to place the module’s on-board PCB antenna outside the base board, and the feed point of the
antenna closest to the board. In the following example figures, positions with mark ✓ are strongly recommended,
while positions without a mark are not recommended.

Fig. 2: Placement of ESP32-C3 Modules on Base Board (antenna feed point on the right)

If the PCB antenna cannot be placed outside the board, please ensure a clearance of at least 15 mm around the antenna
area (no copper, routing, or components on it), and place the feed point of the antenna closest to the board. If there
is a base board under the antenna area, it is recommended to cut it off to minimize its impact on the antenna. Figure
Keepout Zone for ESP32-C3 Module’s Antenna on the Base Board shows the suggested clearance for modules whose
antenna feed point is on the right.
When designing an end product, attention should be paid to the interference caused by the housing of the antenna
and it is recommended to carry out RF verification. It is necessary to test the throughput and communication signal
range of the whole product to ensure the product’s actual RF performance.

4.3 Power Supply

Figure ESP32-C3 Power Traces in a Four-layer PCB Design shows the overview of the power traces in a four-layer
PCB design.

4.3.1 General Guidelines

• Four-layer PCB design is preferred.

• The power traces should be routed on the inner third layer whenever possible.
• Vias are required for the power traces to go through the layers and get connected to the pins on the top layer.
There should be at least two vias if the main power traces need to cross layers. The drill diameter on other
power traces should be no smaller than the width of the power traces.

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Fig. 3: Placement of ESP32-C3 Modules on Base Board (antenna feed point on the left)

Fig. 4: Keepout Zone for ESP32-C3 Module’s Antenna on the Base Board

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Chapter 4. PCB Layout Design

Fig. 5: ESP32-C3 Power Traces in a Four-layer PCB Design

• The ground pad at the bottom of the chip should be connected to the ground plane through at least nine ground
vias.
• If you need to add a thermal pad EPAD under the chip on the bottom of the module, it is recommended to
employ a square grid on the EPAD, cover the gaps with solder paste, and place ground vias in the gaps, as shown
in Figure ESP32-C3 Power Traces in a Four-layer PCB Design. This can avoid chip displacement caused by
tin leakage and bubbles when soldering the module EPAD to the substrate.

4.3.2 3.3 V Power Layout

The 3.3 V power traces, highlighted in yellow, are routed as shown in Figure ESP32-C3 Power Traces in a Four-layer
PCB Design.
The 3.3 V power layout should meet the following guidelines:
• The ESD protection diode is placed next to the power port (circled in red in Figure ESP32-C3 Power Traces in
a Four-layer PCB Design). The power trace should have a 10 µF capacitor on its way before entering into the
chip, and a 0.1 or 1 µF capacitor could also be used in conjunction. After that, the power traces are divided
into several branches using a star-shaped topology, which reduces the coupling between different power pins.
Note that all decoupling capacitors should be placed close to the corresponding power pin, and ground vias
should be added close to the capacitor’s ground pad to ensure a short return path.
• In Figure ESP32-C3 Power Traces in a Four-layer PCB Design, the 10 µF capacitor is shared by the analog
power supply VDD3P3, and the power entrance since the analog power is close to the chip power entrance.
If the chip power entrance is not near VDD3P3, it is recommended to add a 10 µF capacitor to both the chip
power entrance and VDD3P3. Also, reserve two 1 µF capacitors if space permits.
• The width of the main power traces should be no less than 20 mil. The width of VDD3P3 power traces should
be no less than 15 mil. The recommended width of other power traces is 10 mil.

4.3.3 Analog Power Layout

Figure ESP32-C3 Analog Power Traces in a Four-layer PCB Design shows the analog power layout in a four-layer
PCB design.
The analog power layout should meet the following guidelines:

• As shown in Figure ESP32-C3 Analog Power Traces in a Four-layer PCB Design, it is recommended to connect
the capacitor to ground in the LC filter circuit near VDD3P3 to the fourth layer through a via, and maintain a
keep-out area on other layers. The purpose is to further reduce harmonic interference.

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Fig. 6: ESP32-C3 Analog Power Traces in a Four-layer PCB Design

• VDD3P3 analog power supply should be surrounded by ground copper. It is required to add GND isolation
between VDD3P3, power trace and the surrounding GPIO and RF traces, and place vias whenever possible.

4.4 Crystal
Figure ESP32-C3 Crystal Layout (without Keep-out Area on Top Layer) shows the layout for the crystal that is con-
nected to the ground through vias but there is no keep-out area on the top layer for ground isolation.

Fig. 7: ESP32-C3 Crystal Layout (without Keep-out Area on Top Layer)

The layout of the crystal should follow the guidelines below:

• Ensure a complete GND plane for the RF, crystal, and chip.
• The crystal should be placed far from the clock pin to avoid interference on the chip. The gap should be at least
2.0 mm. It is good practice to add high-density ground vias stitching around the clock trace for better isolation.

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Chapter 4. PCB Layout Design

• There should be no vias for the clock input and output traces, which means the traces cannot cross layers. The
clock traces should not intersect with each other.
• Components in series to the crystal trace should be placed close to the chip side.
• The external matching capacitors should be placed on the two sides of the crystal, preferably at the end of the
clock trace, but not connected directly to the series components. This is to make sure the ground pad of the
capacitor is close to that of the crystal.
• Do not route high-frequency digital signal traces under the crystal. It is best not to route any signal trace under
the crystal. The vias on the power traces on both sides of the crystal clock trace should be placed as far away
from the clock trace as possible, and the two sides of the clock trace should be surrounded by grounding copper.
• As the crystal is a sensitive component, do not place any magnetic components nearby that may cause interfer-
ence, for example large inductance component, and ensure that there is a clean large-area ground plane around
the crystal.

4.5 RF
The RF trace is routed as shown highlighted in pink in Figure ESP32-C3 RF Layout in a Four-layer PCB Design.

Fig. 8: ESP32-C3 RF Layout in a Four-layer PCB Design

The RF layout should meet the following guidelines:

• A π-type matching circuit should be added to the RF trace and placed close to the chip, in a zigzag.
• The RF trace should have a 50 Ω characteristic impedance. The reference plane is the second layer. For
designing the RF trace at 50 Ω impedance, you could refer to the PCB stack-up design shown below.
• Add a stub to the ground at the ground pad of the first matching capacitor to suppress the second harmonics.
It is preferable to keep the stub length 15 mil, and determine the stub width according to the PCB stack-up
so that the characteristic impedance of the stub is 100 Ω ± 10%. In addition, please connect the stub via to
the third layer, and maintain a keep-out area on the first and second layers. The trace highlighted in Figure
ESP32-C3 Stub in a Four-layer PCB Design is the stub. Note that a stub is not required for package types above
0201.
• The RF trace should have a consistent width and not branch out. It should be as short as possible with dense
ground vias around for interference shielding.
• The RF trace should be routed on the outer layer without vias, i.e., should not cross layers. The RF trace should
be routed at a 135° angle, or with circular arcs if trace bends are required.
• The ground plane on the adjacent layer needs to be complete. Do not route any traces under the RF trace
whenever possible.
• There should be no high-frequency signal traces routed close to the RF trace. The RF antenna should be
placed away from high-frequency components, such as crystals, DDR SDRAM, high-frequency clocks, etc. In
addition, the USB port, USB-to-serial chip, UART signal lines (including traces, vias, test points, header pins,
etc.) must be as far away from the antenna as possible. The UART signal line should be surrounded by ground
copper and ground vias.

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Chapter 4. PCB Layout Design

Fig. 9: ESP32-C3 PCB Stack-up Design

Fig. 10: ESP32-C3 Stub in a Four-layer PCB Design

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Chapter 4. PCB Layout Design

4.6 Flash
The layout for flash should follow the guidelines below:

• Place the zero-ohm series resistors on the SPI lines close to the chip.
• Route the SPI traces on the inner layer (e.g., the third layer) whenever possible, and add ground copper and
ground vias around the clock and data traces of SPI separately.
• Place the 0.1 μF capacitor to ground at the VDD_SPI close to corresponding flash power pins.
Figure ESP32-C3 Quad SPI Flash Layout shows the quad SPI flash layout.

Fig. 11: ESP32-C3 Quad SPI Flash Layout

4.7 UART
Figure ESP32-C3 UART Layout shows the UART layout.

Fig. 12: ESP32-C3 UART Layout

The UART layout should meet the following guidelines:

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Chapter 4. PCB Layout Design

• The series resistor on the U0TXD trace needs to be placed close to the chip side and away from the crystal.
• The U0TXD and U0RXD traces on the top layer should be as short as possible.
• The UART trace should be surrounded by ground copper and ground vias stitching.

4.8 USB
The USB layout should meet the following guidelines:
• Place the RC circuit on the USB traces close to the chip side.
• Use differential pairs and route them in parallel at equal lengths.
• Make sure there is a complete reference ground plane and surround the USB traces with ground copper.

4.9 Typical Layout Problems and Solutions

4.9.1 1. The voltage ripple is not large, but the TX performance of RF is rather poor.

Analysis: The voltage ripple has a strong impact on the RF TX performance. It should be noted that the ripple
must be tested when ESP32-C3 is in the normal working mode. The ripple increases when the power gets high in a
different mode.
Generally, the peak-to-peak value of the ripple should be <80 mV when ESP32-C3 sends MCS7@11n packets, and
<120 mV when ESP32-C3 sends 11 MHz@11b packets.
Solution: Add a 10 μF filter capacitor to the branch of the power trace (the branch powering the chip’s analog
power pin). The 10 μF capacitor should be as close to the analog power pin as possible for small and stable voltage
ripples.

4.9.2 2. When ESP32-C3 sends data packages, the voltage ripple is small, but RF TX
performance is poor.

Analysis: The RF TX performance can be affected not only by voltage ripples, but also by the crystal itself. Poor
quality and big frequency offsets of the crystal decrease the RF TX performance. The crystal clock may be corrupted
by other interfering signals, such as high-speed output or input signals. In addition, high-frequency signal traces,
such as the SDIO traces and UART traces under the crystal, could also result in the malfunction of the crystal.
Besides, sensitive components or radiating components, such as inductors and antennas, may also decrease the RF
performance.
Solution: This problem is caused by improper layout for the crystal and can be solved by re-layout. Please refer to
Section Crystal for details.

4.9.3 3. When ESP32-C3 sends data packages, the power value is much higher or lower
than the target power value, and the EVM is relatively poor.

Analysis: The disparity between the tested value and the target value may be due to signal reflection caused by
the impedance mismatch on the transmission line connecting the RF pin and the antenna. Besides, the impedance
mismatch will affect the working state of the internal PA, making the PA prematurely access the saturated region in
an abnormal way. The EVM becomes poor as the signal distortion happens.
Solution: Match the antenna’s impedance with the π-type circuit on the RF trace, so that the impedance of the
antenna as seen from the RF pin matches closely with that of the chip. This reduces reflections to the minimum.

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Chapter 4. PCB Layout Design

4.9.4 4. TX performance is not bad, but the RX sensitivity is low.

Analysis: Good TX performance indicates proper RF impedance matching. Poor RX sensitivity may result from
external coupling to the antenna. For instance, the crystal signal harmonics could couple to the antenna. If the TX
and RX traces of UART cross over with RF trace, they will affect the RX performance, as well. If there are many
high-frequency interference sources on the board, signal integrity should be considered.
Solution: Keep the antenna away from crystals. Do not route high-frequency signal traces close to the RF trace.
Please refer to Section RF for details.

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Chapter 5

Hardware Development

5.1 ESP32-C3 Modules

For a list of ESP32-C3 modules please check the Modules section on Espressif’s official website.
To review module reference designs please check the Documentation section on Espressif’s official website.

5.2 ESP32-C3 Development Boards

For a list of the latest designs of ESP32-C3 boards please check the Development Boards section on Espressif’s
official website.

5.3 Download Guidelines

You can download firmware to ESP32-C3 via UART and USB.
To download via UART:
1. Before the download, make sure to set the chip or module to Joint Download Boot mode, according to Table
Boot Mode Control.
2. Power up the chip or module and check the log via the UART0 serial port. If the log shows “waiting for
download”, the chip or module has entered Joint Download Boot mode.
3. Download your firmware into flash via UART using the Flash Download Tool.
4. After the firmware has been downloaded, pull GPIO9 high or leave it floating to make sure that the chip or
module enters SPI Boot mode.
5. Power up the chip or module again. The chip will read and execute the new firmware during initialization.
To download via USB:
1. If the flash is empty, set the chip or module to Joint Download Boot mode, according to Table Boot Mode
Control.
2. Power up the chip or module and check the log via USB serial port. If the log shows “waiting for download”
, the chip or module has entered Joint Download Boot mode.
3. Download your firmware into flash via USB using Flash Download Tool.
4. After the firmware has been downloaded, pull GPIO9 high or leave it floating to make sure that the chip or
module enters SPI Boot mode.
5. Power up the chip or module again. The chip will read and execute the new firmware during initialization.
6. If the flash is not empty, start directly from Step 3.

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Chapter 5. Hardware Development

Note:
• It is advised to download the firmware only after the “waiting for download”log shows via serial ports.
• Serial tools cannot be used simultaneously with the Flash Download Tool on one com port.
• The USB auto-download will be disabled if the following conditions occur in the application, where it will be
necessary to set the chip or module to Joint Download Boot mode first by configuring the strapping pin.
– USB PHY is disabled by the application;
– USB is secondary developed for other USB functions, e.g., USB host, USB standard device;
– USB IOs are configured to other peripherals, such as UART and LEDC.
• It is recommended that the user retains control of the strapping pins to avoid the USB download function not
being available in case of the above scenario.

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Chapter 6

Related Documentation and Resources

• Chip Datasheet (PDF)

• Technical Reference Manual (PDF)
• Chip Errata (PDF)
• Chip Variants
• Modules
• Development Boards
• Espressif KiCad Library
• ESP Product Selector
• Regulatory Certificates
• User Forum (Hardware)
• Technical Support

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Chapter 6. Related Documentation and Resources

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Chapter 7

Glossary

The glossary contains terms and acronyms that are used in this document.

Term Description
CLC Capacitor-Inductor-Capacitor
DDR SDRAM Double Data Rate Synchronous Dynamic Random-Access Memory
ESD Electrostatic Discharge
LC Inductor-Capacitor
PA Power Amplifier
RC Resistor-Capacitor
RTC Real-Time Clock
Zero-ohm resistor A zero-ohm resistor is a placeholder on the circuit so that another higher ohm resistor can
replace it, depending on design cases.

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Chapter 7. Glossary

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Chapter 8

Revision History

8.1 ESP Hardware Design Guidelines v1.0

This is the first version of the ESP Hardware Design Guidelines in HTML format. During the migration from PDF
to HTML format, minor updates, improvements, and clarifications were made throughout the documentation.
If you would like to check previous versions of the document, please submit documentation feedback.

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Chapter 8. Revision History

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Chapter 9

Disclaimer and Copyright Notice

Information in this document, including URL references, is subject to change without notice.
All third party’s information in this document is provided as is with no warranties to its authenticity and accuracy.
No warranty is provided to this document for its merchantability, non-infringement, fitness for any particular purpose,
nor does any warranty otherwise arising out of any proposal, specification or sample.
All liability, including liability for infringement of any proprietary rights, relating to use of information in this doc-
ument is disclaimed. No licenses express or implied, by estoppel or otherwise, to any intellectual property rights are
granted herein.
The Wi-Fi Alliance Member logo is a trademark of the Wi-Fi Alliance. The Bluetooth logo is a registered trademark
of Bluetooth SIG.
All trade names, trademarks and registered trademarks mentioned in this document are property of their respective
owners, and are hereby acknowledged.

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