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Lab 1 DLD

This document discusses an experiment on basic logic gates using a digital logic trainer and Proteus simulation software. The objective is to understand logic gate characteristics and functionality. The document describes logic gate ICs, experimental procedures for analyzing gates, Proteus simulation procedures, and post-lab questions about logic gate families and fan-in/fan-out.

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hammadkhan22343
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5 views

Lab 1 DLD

This document discusses an experiment on basic logic gates using a digital logic trainer and Proteus simulation software. The objective is to understand logic gate characteristics and functionality. The document describes logic gate ICs, experimental procedures for analyzing gates, Proteus simulation procedures, and post-lab questions about logic gate families and fan-in/fan-out.

Uploaded by

hammadkhan22343
Copyright
© © All Rights Reserved
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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Lab#01: Introduction to Basic Logic Gate ICs on Digital

Logic Trainer and Proteus Simulation

Objective
Part 1
To know about the basic logic gates, their truth table, input-
output characteristics and analyzing their functionality.
Introduction to logic gate ICs, integrated circuit pin
configuration and their use.
Part 2
Learn to use Proteus Software for Simulation of Digital Logic
Circuits.

In Lab:
Part 1: Basic Logic Gate Integrated Circuits (ICs)
Equipment Required
 KL-31001 Digital Logic Lab
 Logic gates ICs
o 4001 quad 2-input NOR
o 4011 quad 2-input NAND
o 4070 quad 2-input XOR
o 4071 quad 2-input OR
o 4077 quad 2-input XNOR
o 4081 quad 2-input AND
o 4069 Six Inverting Buffer NOT

Procedure
1. Collect the necessary materials, including basic logic
gate ICs (such as AND, OR, NOT, gates), breadboard,
jumper wires and logic trainer.
2. Set up your breadboard and begin placing the ICs
other components according to your circuit
diagram. Ensure proper placement and orientation
of the ICs.
3. Use jumper wires to connect the power supply,
connect it to be appropriate power rails on the
breadboard. Ensure the voltage levels are
compatible with the ICs begin used.
4. Apply input signals to the logic gate and observe the
output behavior. Use switches to control the input
signals. Verify that the output match the expected
truth table values for each gate
5. Record your observation, circuit diagrams, and any
modifications made during the experiment.
INPUTS OUTPUTS

A B
AND OR XOR NAND NOR XNOR
0 0 0 0 0 1 1 1

0 1 0 1 1 1 0 0

1 0 0 1 1 1 0 0

1 1 1 1 0 0 0 1

In Lab Task 1:

INPUT OUTPUT

A B

0 1

1 0
Part 2: Proteus (Simulation Software)
Procedure
1.Launch Proteus and start a new project. Give it a
suitable name and save it in your desired location.
2.Use the schematic capture tool to design your
circuit. Place components from the components
library onto the workspace and connect them
using wires.
3. Ensure all components are correctly wired
according to your circuit design.
4.Click on the play icon to run the simulation.
Proteus will analyze the circuit and provide
simulation results based on the selected sitting.
5.Once you are done, save your project and close
Proteus.
Simulation for AND Gate
Simulation for OR Gate
Simulation for XOR Gate
Simulation for NAND Gate
Simulation for NOR Gate
Simulation for XNOR Gate
Post Lab Task
Q1: Make a list of logic gate ICs of TTL family and CMOS family along
with the ICs names.

7400 Series 4000 Series


1 7400 - Quad 2-input 4001-Quad 2-input NOR
NAND Gate Gate
2 7402 – Quad 2-input 4002-Dual 4-input NOR
NOR Gate Gate
3 7404 – Hex inverter 4006-18-bit Static Shift
Register
4 7408-Quad 2-input AND 4007-Dual Complementary
Gate Pair Plus inverter
5 7410 Triple 3-input 4011-Quad 2-input NAND
NAND Gate Gate
6 7411 Triple 3-input AND 4013-Dual D-type Flip-Flop
Gate
7 7420-Dual 4-input 4017-Decade
NAND Gate Counter/divider
8 7421-Dual 4-input AND 4023-Triple 3-input NAND
Gate Gate
9 7432-Quad 2-input OR 4028-BCD-to-Decimal
Gate Decoder
10 7442-BCD to Decimal 4030-Quad Exclusive-OR
Decoder Gate
11 7447-BCD to 7-segment 4046-Phase-locked
Decoder Loop(PLL)
12 7474 Dual D-type Flip- 4049-Hex Inverting Buffer
Flop
13 7486-Quad 2-input XOR 4050-Hex Non-Inverting
Gate Buffer
14 7490-Decade Counter 4066-Quad Bilateral Switch
15 7493-4-bit Binary 4070- Quad 2-input XOR
Counter Gate

Q2: What is Fan-In and Fan-Out?


Fan-in refers to the maximum number of input signals
that a logic gate can accept.
Fan-out refers to the maximum number of standard
input loads that a logic gate's output can drive while
maintaining proper operation.
Critical Analysis/Conclusion
The experiment on basic logic gate ICs using a digital
logic trainer and Proteus simulation was instrumental in
enhancing our understanding of digital logic principles.
By combining theoretical knowledge with practical
experimentation, we gained valuable insights into the
functionality, applications, and troubleshooting of logic
gates in digital circuits. This foundational knowledge is
essential for anyone pursuing a career in fields related to
electronics, computer science, or engineering.

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